Display substrate and display device

Abstract

A display substrate (1A) comprises a display area (01) and a peripheral area (03) surrounding the display area (01), wherein the display area (01) comprises a first display area (012); the display substrate (1A) comprises: a base substrate (1), a first light shielding layer (31), a plurality of first sub-pixels (41) and a first power supply line (5); the first light shielding layer (31) is arranged on one side of the base substrate (1), the first light shielding layer (31) is located in the first display area (012), and the first light shielding layer (31) has a plurality of array-arranged openings. The invention relates to a display device comprising a first light shielding layer (31) and a first light shielding layer (31). The first light shielding layer (31) is provided with a plurality of first sub-pixels (41) on a side away from the substrate (1). The plurality of first sub-pixels (41) are located in a first display area (012). The orthographic projections of the plurality of first sub-pixels (41) on the substrate (1) do not overlap with the orthographic projections of the opening (31a) on the substrate (1). The first power supply line (5) comprises a first power supply bus (51) and a plurality of first power supply lines (52). The first light shielding layer (31) is electrically connected to the first power supply line (5).

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] In the structural design of display devices (such as mobile phones, tablet computers, wearable display products and other terminal products), the screen-to-body ratio, that is, the ratio of the display area to the front of the entire display device, is an important design parameter.

[0003] With the development of display technology, display devices are increasingly moving towards ultra-large screen-to-body ratios, or even full-screen displays (i.e., the area of ​​the display area is equal to or very close to the area of ​​the front of the entire display device). Therefore, how to improve the screen-to-body ratio of display devices has become a research hotspot for technicians in this field.

[0004] To ensure that some components in a display device, such as a front camera unit, light sensor, distance sensor, and biometric sensor, function properly, they must be positioned toward the front of the display device. For example, the lens of the front camera unit must be positioned toward the front of the display device, and the sensing surface of the sensor must be positioned toward the front of the display device. This allows the component to capture information from the environment and perform corresponding operations, such as capturing images of people or objects in front of the display device or capturing light in front of the display device. Summary of the Invention

[0005] The present disclosure provides a display substrate and a display device, which are applied in the field of display technology to improve the screen-to-body ratio of the display device and solve the problem that a conductive film layer in the display device generates an uncontrollable potential signal, thereby affecting normal display.

[0006] In order to achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0007] In one aspect, a display substrate is provided, comprising a display area and a peripheral area surrounding the display area, wherein the display area includes a first display area. The display substrate comprises: a base substrate, a first light shielding layer, a plurality of first sub-pixels, and a first power line.

[0008] A first light-shielding layer is provided on one side of the substrate, the first light-shielding layer is located in the first display area, and the first light-shielding layer has a plurality of openings arranged in an array. A plurality of first sub-pixels are provided on the side of the first light-shielding layer away from the substrate, the plurality of first sub-pixels are located in the first display area, and the orthographic projections of the plurality of first sub-pixels on the substrate do not overlap with the orthographic projections of the openings on the substrate. A first power line includes a first power bus and a plurality of first power sub-lines; at least a portion of the first power bus is located in an area of ​​the peripheral area close to the first display area; the plurality of first power sub-lines are located in the first display area and are electrically connected to the first power bus, the plurality of first power sub-lines are configured to provide a first power signal to the plurality of first sub-pixels, and the orthographic projections of the plurality of first power sub-lines on the substrate do not overlap with the orthographic projections of the openings on the substrate. The first light-shielding layer is electrically connected to the first power line.

[0009] In some embodiments, the display substrate further includes: at least one insulating film disposed between the first power line and the first light shielding layer, the at least one insulating film having a plurality of via holes extending therethrough, wherein the first power line is electrically connected to the first light shielding layer through the plurality of via holes.

[0010] In some embodiments, the first light shielding layer is further located in the peripheral area, the plurality of vias include a plurality of first vias located in the peripheral area, and the first light shielding layer is electrically connected to the first power bus through the plurality of first vias.

[0011] In some embodiments, the plurality of first via holes include at least two types of first via holes having different hole depths.

[0012] In some embodiments, the plurality of first via holes include at least one first via hole group, each first via hole group includes at least one first via hole column, and each first via hole in each first via hole column has a different hole depth.

[0013] In some embodiments, there are multiple first via hole groups; each first via hole group includes multiple first via hole columns; the multiple first via hole groups are arranged along a first direction; the multiple first via hole columns in each first via hole group are arranged along the first direction, and the first via holes of the same hole depth in each first via hole column are arranged in a row along the first direction.

[0014] In some embodiments, the plurality of via holes further include a plurality of second via holes located in the first display area, and the first light shielding layer is electrically connected to the plurality of first power sub-lines through the plurality of second via holes.

[0015] In some embodiments, the plurality of second via holes are evenly distributed in the first display area.

[0016] In some embodiments, a pixel is provided between every four openings of the first light shielding layer, the pixel includes three first sub-pixels, and the position of the pixel corresponds to at least one second via hole.

[0017] In some embodiments, the display substrate further comprises: a first insulating layer located between the first light shielding layer and the plurality of sub-pixels. At least one first sub-pixel among the plurality of first sub-pixels comprises a thin film transistor and a storage capacitor.

[0018] The thin film transistor includes: an active layer located on the first insulating layer; a first gate insulating layer located on the side of the active layer away from the base substrate; a gate located on the side of the first gate insulating layer away from the base substrate; a second gate insulating layer located on the side of the gate away from the base substrate; an interlayer insulating layer located on the side of the second gate insulating layer away from the base substrate; and a source and a drain located on the side of the interlayer insulating layer away from the base substrate.

[0019] The storage capacitor includes a first plate and a second plate. The first plate and the gate are located in the same layer, and the second plate is located between the second gate insulating layer and the interlayer insulating layer.

[0020] In some embodiments, the at least one insulating thin film includes at least one of the first insulating layer, the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer.

[0021] In some embodiments, the first power bus includes a first sub-layer and a second sub-layer, and the first sub-layer and the second sub-layer are electrically connected through a third via.

[0022] In some embodiments, at least one first power sub-line of the plurality of first power sub-lines includes a third sub-layer and a fourth sub-layer, and the third sub-layer and the fourth sub-layer are electrically connected through a fourth via.

[0023] In some embodiments, the display area further includes a second display area; the second display area is located on a side of the first display area away from the first power line. The display substrate further includes: a plurality of second sub-pixels and a second power line. The plurality of second sub-pixels are located in the second display area. The second power line includes a second power bus and a plurality of second power sub-lines; at least a portion of the second power bus is located in an area of ​​the peripheral area proximal to the second display area. The plurality of second power sub-lines are located in the second display area and electrically connected to the second power bus. The plurality of second power sub-lines are configured to provide a second power signal to the plurality of second sub-pixels.

[0024] In some embodiments, the first power signal is the same as the second power signal, or the first power signal is different from the second power signal.

[0025] In some embodiments, when the first power signal is different from the second power signal, the first power signal is smaller than the second power signal.

[0026] In some embodiments, a distribution density of the plurality of second sub-pixels is greater than a distribution density of the plurality of first sub-pixels.

[0027] In some embodiments, the display substrate further includes a second light shielding layer disposed on one side of the base substrate, the second light shielding layer being located in the second display area, the second light shielding layer being located in the same layer as the first light shielding layer, and the second light shielding layer being electrically connected to the second power line.

[0028] In another aspect, a display device is provided. The display device comprises: the display substrate described above, and a front optical component disposed on a side of the display substrate away from the display surface thereof. The front optical component has an orthographic projection on the display substrate located within the first display area.

[0029] In some embodiments, the front optical component includes: an infrared detection unit.

[0030] The display substrate and display device provided by the embodiments of the present disclosure are such that, in the display substrate, at the multiple openings provided in the first light-shielding layer, ambient light can enter from one side of the display substrate, pass through the display substrate, and be emitted from the other side of the display substrate. In this way, the front optical component can be set on the side of the display substrate away from its display surface, and the positive projection of the front optical component on the display substrate is located in the first display area. In this way, the front optical component can also receive ambient light and realize the detection function. There is no need to set up a non-display area for placing the front optical component, so that the area of ​​the non-display area of ​​the display device is reduced, the area of ​​the display area is increased, and the screen-to-body ratio of the display area is improved.

[0031] At the same time, the first light-shielding layer included in the display substrate provided by the embodiment of the present disclosure can block the ambient light from the side of the base substrate away from the display layer, preventing the ambient light from being emitted to the display layer (the display layer includes the first sub-pixel and signal wiring, etc.) facing the first light-shielding layer. In this way, the first light-shielding layer can prevent the infrared light signal emitted by the above-mentioned infrared detection unit from irradiating the display layer, thereby avoiding the adverse effects of the infrared light signal on the display layer. The first light-shielding layer can also block a portion of the screen light reflected by the detected object, thereby reducing the screen light passing through the first display area, and thereby reducing the adverse effects of the screen light on the front optical components.

[0032] Moreover, in the display substrate, the first light shielding layer is electrically connected to the first power line, thereby connecting the first light shielding layer to a constant electrical signal to avoid induced charges on the first light shielding layer, thereby avoiding the influence of the induced charges generated on the first light shielding layer on the multiple first sub-pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0034] Figure 1 The following are structural diagrams of two display devices provided according to the relevant technology;

[0035] Figure 2 A structural diagram of a display substrate provided according to some embodiments of the present disclosure;

[0036] Figure 3A Based on Figure 2 A cross-sectional view taken along section line CC' of a display substrate is provided;

[0037] Figure 3B Based on Figure 2 A cross-sectional view taken along section line DD' in the display substrate is provided;

[0038] Figure 4 A wiring diagram of a display substrate provided according to some embodiments of the present disclosure;

[0039] Figures 5A to 5G for Figure 2 A film layer image of region G in a display substrate is provided;

[0040] Figure 5H Based on Figure 5G A film layer diagram of a sub-pixel in the film layer diagram shown;

[0041] Figure 6A A structural diagram of a display device provided according to some embodiments of the present disclosure;

[0042] Figure 6B Another structural diagram of a display device according to some embodiments of the present disclosure;

[0043] Figure 7 A schematic diagram of the operation of a display device according to some embodiments of the present disclosure;

[0044] Figure 8 A circuit diagram of a pixel driving circuit in a display substrate according to some embodiments of the present disclosure;

[0045] Figure 9A Another cross-sectional view of a display substrate provided according to some embodiments of the present disclosure;

[0046] Figure 9B is another cross-sectional view of a display substrate provided according to some embodiments of the present disclosure;

[0047] Figure 10 A cross-sectional view of a plurality of via holes in a display substrate according to some embodiments of the present disclosure;

[0048] Figure 11A Another cross-sectional view of a plurality of via holes in a display substrate according to some embodiments of the present disclosure;

[0049] Figure 11B is another cross-sectional view of a plurality of via holes in a display substrate according to some embodiments of the present disclosure;

[0050] Figure 11C is another cross-sectional view of a plurality of via holes in a display substrate according to some embodiments of the present disclosure;

[0051] Figure 12 A schematic diagram of a sub-pixel arrangement according to some embodiments of the present disclosure;

[0052] Figure 13 A schematic diagram of a sub-pixel opening arrangement provided according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0053] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0054] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0055] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0056] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the terms "connected" and "connected in series" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0057] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0058] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0059] Terms indicating orientation or positional relationships such as “up / above,” “down / below,” “row / row direction,” and “column / column direction” are based on the orientation or positional relationships shown in the accompanying drawings and are merely simplified descriptions for the convenience of illustrating the technical solutions of the present disclosure. They do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limitations on the present disclosure.

[0060] For example, in some cases, embodiments involving "row direction" can be implemented in "column direction", etc., and vice versa. Rotating or mirroring the embodiments described in this disclosure by 90 degrees also falls within the scope of the rights claimed in this disclosure.

[0061] In related technologies, such as Figure 1 As shown in part (a), taking a mobile phone as an example of a display device, the front of the mobile phone (i.e., the side displaying the image) includes: a display area 01 and a non-display area 02 located outside the display area 01. Devices 02a (such as one or more of a front camera unit, a light sensor, a distance sensor, and a biosensor) are provided in some areas of the non-display area 02, but devices 02a are not provided in the remaining areas, and these areas cannot be displayed, resulting in a low screen-to-body ratio.

[0062] With the emergence of technologies such as special-shaped cutting, related technologies have proposed transforming the display area from a traditional rectangle into a rectangle with a concave (i.e., notch), and increasing the proportion of the display area to the front of the entire display device by placing the device in the non-display area outside the concave.

[0063] Please continue reading Figure 1 ,like Figure 1 As shown in part (b), still taking the display device as a mobile phone as an example, the special-shaped cutting technology is used to "punch a hole" on the display panel, that is, a concave is formed in part of the area on one side of the display area 01, so that the area on the front of the mobile phone where the above-mentioned device 02a needs to be set is the non-display area 02, and the other areas are all display areas 01, thereby improving the screen-to-body ratio of the display area 01 to a certain extent.

[0064] However, the area outside the concave portion is still a non-display area, which still occupies a certain screen ratio, so that there is still a non-display area 02 on the front of the display device, affecting the screen ratio of the display device.

[0065] In one aspect, the present disclosure provides a display substrate 1A. Figures 2 to 4 As shown, the display substrate 1A has a display area 01 and a peripheral area 03 surrounding the display area 01 . The display area 01 includes a first display area 012 and a second display area 011 .

[0066] For example, Figure 2As shown, the first display area 012 is disposed near the edge of the display substrate 1A and has a shape that matches the edge.

[0067] Please continue reading Figure 2 and Figure 3A 、 Figure 3B The display substrate 1A includes a base substrate 1, a first light shielding layer 31, a plurality of first sub-pixels 41 and a first power supply line 5. Figure 3A and Figure 3B In the figure, for ease of understanding, the cross-sectional patterns of multiple first sub-pixels 41 and their corresponding signal lines (including the first power line 5) and other structures arranged on the side of the first light-shielding layer 31 away from the base substrate 1 are combined into one and illustrated as the display layer 2.

[0068] The first light shielding layer 31 is disposed on one side of the base substrate 1 . The first light shielding layer 31 is located in the first display area 012 . The first light shielding layer 31 has a plurality of openings 31 a arranged in an array.

[0069] A plurality of first sub-pixels 41 are arranged on a side of the first light-shielding layer 31 away from the base substrate 1, and the plurality of first sub-pixels 41 are located in the first display area 012. The orthographic projections of the plurality of first sub-pixels 41 on the base substrate do not overlap with the orthographic projection of the opening 31a on the base substrate, that is, the orthographic projections of the plurality of first sub-pixels 41 on the base substrate 1 are within the orthographic projection of the first light-shielding layer 31 on the base substrate 1.

[0070] Please continue reading Figures 2 to 3B In the above-mentioned display substrate 1A, the first light shielding layer 31 is configured to block ambient light, preventing ambient light from penetrating the display substrate 1A in areas other than the multiple openings 31a of the first light shielding layer 31. At the multiple openings 31a of the first light shielding layer 31, ambient light can enter from one side of the display substrate 1A, pass through the display substrate 1A, and exit from the other side of the display substrate 1A. The ambient light signal includes an invisible light signal, such as an infrared light signal. For example, the transmission path of the ambient light is as follows: Figure 3A Here, the two sides of the display substrate 1A refer to two opposite sides of the display substrate 1A along a direction perpendicular to the base substrate 1 .

[0071] In addition, the first light-shielding layer 31 is also configured to block the light emitted by the light-emitting device of the display substrate 1A (i.e., screen light), that is, the light emitted by the light-emitting device can be emitted toward the side of the first light-shielding layer 31 away from the base substrate 1, but cannot be emitted toward the side of the first light-shielding layer 31 close to the base substrate 1.

[0072] like Figure 2As shown, the first power line 5 includes a first power bus 51 and a plurality of first power sub-lines 52. At least a portion of the first power bus 51 is located in an area of ​​the peripheral area 03 near the first display area 012. The plurality of first power sub-lines 52 are located in the first display area 012 and are electrically connected to the first power bus 51. The plurality of first power sub-lines 52 are configured to provide first power signals to the plurality of first sub-pixels 41. The orthographic projections of the plurality of first power sub-lines 52 on the base substrate 1 do not overlap with the orthographic projections of the openings 31a of the first light-shielding layer 31 on the base substrate 1.

[0073] The first light shielding layer 31 is electrically connected to the first power line 5. Thus, the first power line 5 provides a first power signal to the first light shielding layer 31, so that the first light shielding layer 31 is connected to a stable electrical signal to prevent an uncontrollable potential signal from occurring in the first light shielding layer 31 and affecting the normal operation of other structures in the display substrate 1A.

[0074] For example, the disclosed embodiments do not limit the material of the first light shielding layer 31, so long as it can achieve the light shielding function. For example, the material of the first light shielding layer 31 can be black resin or metal. If the first light shielding layer 31 is made of metal, induced charges are easily generated on the first light shielding layer 31, which may affect the multiple first sub-pixels 41, such as causing voltage instability in the multiple first sub-pixels 41.

[0075] Therefore, in some embodiments of the present disclosure, when the material of the first light-shielding layer 31 is a metal material, the first light-shielding layer 31 is electrically connected to the first power line 5, so that the first light-shielding layer 31 is connected to a constant electrical signal to avoid the generation of induced charges on the first light-shielding layer 31, and further avoid the influence of the induced charges generated on the first light-shielding layer 31 on the multiple first sub-pixels 41.

[0076] The display substrate 1A provided in the embodiment of the present disclosure can be used to manufacture a display device 3A. Figure 6A and 6B As shown, in some embodiments, some embodiments of the present disclosure further provide a display device 3A, which includes a display substrate 1A and a front optical component 300. The front optical component 300 is disposed on a side of the display substrate 1A away from its display surface, and the orthographic projection of the front optical component 300 on the display substrate 1A is located within the first display area 012.

[0077] like Figure 6A and Figure 7 As shown, the display device 3A is a mobile phone 3A', and the front optical component 300 provided in the mobile phone 3A' is an infrared detection unit 300'.

[0078] Since the display substrate 1A has multiple openings 31a in the first light shielding layer 31, ambient light can enter from one side of the display substrate 1A, pass through the display substrate 1A, and exit from the other side of the display substrate 1A, the infrared detection unit 300' is set on the non-display surface of the mobile phone 3A', and there is no need to set up a separate area for placing the infrared detection unit 300' in the display area 01. Figure 7 As shown, in the detection mode (i.e., the infrared detection unit is turned on), the infrared light signal emitted by the infrared detection unit 300' can pass through the area corresponding to the multiple openings 31a of the first light-shielding layer 31 in the display substrate 1A, and then be emitted to the detected object (such as a person) in the front (i.e., opposite to the display surface of the mobile phone 3A'), so that the infrared light signal emitted by the infrared detection unit 300' is reflected by the detected object, and then the reflected infrared light signal passes through the area corresponding to the multiple openings 31a of the first light-shielding layer 31 in the display substrate 1A, and then is emitted to the infrared detection unit 300', thereby realizing the detection function.

[0079] In other words, even if the infrared detection unit 300' is located on the non-display surface of the mobile phone 3A', its front detection function can still be realized. In addition, because the first display area 012 and the second display area 011 included in the display area 01 of the display substrate 1A are both capable of displaying, that is, the entire display surface of the mobile phone 3A' can display normally, there is no need to set up a non-display area for accommodating the infrared detection unit 300'. As a result, the area of ​​the non-display area of ​​the mobile phone 3A' (i.e., the peripheral area 03) is reduced, the area of ​​the display area 01 is increased, and the screen-to-body ratio of the display area 01 is improved.

[0080] It can be seen from the above that the display substrate 1A provided in the embodiment of the present disclosure can improve the screen-to-body ratio of the display device.

[0081] See also Figure 2 The first light-shielding layer 31 included in the display substrate 1A provided in the embodiment of the present disclosure can block ambient light from the side of the base substrate 1 away from the display layer 2, preventing the ambient light from being emitted toward the display layer 2 (the display layer 2 includes the first sub-pixel 41 and signal wiring, etc.) directly facing the first light-shielding layer 31. The ambient light includes invisible light signals, such as the infrared light signal emitted by the infrared detection unit 300'. In this way, the first light-shielding layer 31 can prevent the infrared light signal emitted by the infrared detection unit 300' from reaching the display layer 2, thereby avoiding the infrared light signal from causing adverse effects on the display layer 2.

[0082] Exemplarily, at least one of the plurality of first sub-pixels 41 includes a thin film transistor and a storage capacitor, and the thin film transistor and the storage capacitor constitute a pixel driving circuit, for example. The pixel driving circuit 21 is as follows Figure 8In the 7T1C structure shown, the pixel driver circuit 21 is electrically connected to the light-emitting device 22, driving the light-emitting device 22 to emit light. Because the polysilicon channel of the thin-film transistor (i.e., the region between the source and drain of the thin-film transistor when it is in the on state) is sensitive to energy, when an infrared light signal illuminates the thin-film transistor, the polysilicon channel of the thin-film transistor is prone to generating photocurrent, which can easily cause current instability in the pixel driver circuit 21, resulting in unstable light emission from the light-emitting device 22, and thus affecting display quality. However, due to the action of the first light-shielding layer 31, the infrared light signal emitted by the infrared detection unit 300' cannot illuminate the thin-film transistor in the first sub-pixel 41, thereby preventing the infrared light signal from adversely affecting the thin-film transistor.

[0083] In addition, the first light shielding layer 31 can also block a portion of the screen light reflected by the detected object, thereby reducing the screen light that passes through the first display area 012 and further reducing the adverse effects of the screen light on the front optical component 300. For example, the screen light can reduce the impact on the information collection function of the infrared detection unit 300'.

[0084] In some embodiments, as Figures 9A to 10 As shown, the display substrate 1A further includes: at least one insulating film 20b disposed between the first power line 5 and the first light shielding layer 31. The at least one insulating film 20b is provided with a plurality of via holes P extending through the at least one insulating film 20b. The first power line 5 is electrically connected to the first light shielding layer 31 through the plurality of via holes P.

[0085] In some embodiments, as Figures 10 to 11C As shown, the plurality of via holes P include at least two types of via holes P ( Figure 10 (The three types of via holes P are used as examples for illustration.) In this way, the contact yield between the first power line 5 and the first light shielding layer 31 can be improved.

[0086] It needs to be explained that, from the above description, there is a multi-layer insulating film 20b between the first power line 5 and the first light-shielding layer 31. In order to achieve electrical connection between the first power line 5 and the first light-shielding layer 31, it is necessary to make at least one via P in the multi-layer insulating film 20b, wherein each via P penetrates the multi-layer insulating film 20b, and the hole depth h of the via P is relatively large. Therefore, in the process of making the via P, over-etching or under-etching problems are prone to occur.

[0087] The above embodiments, such as Figures 10 to 11C As shown, the plurality of via holes P include three types of via holes P with different hole depths h.

[0088] For example, see Figure 10 and Figure 11AThe hole depth h of each via hole P in the multiple via holes P is greater than or equal to the distance d1 between the first power line 5 and the first light shielding layer 31 in the direction perpendicular to the base substrate 1, and is less than the distance d2 between the first power line 5 and the base substrate 1 in the direction perpendicular to the base substrate 1.

[0089] So, if something like Figure 11B The over-etching condition shown in the figure, or the Figure 11C The insufficient etching shown can at least ensure that the first power line 5 passes through one of the via holes P and is electrically connected to the first light shielding layer 31 , thereby improving the contact yield between the first power line 5 and the first light shielding layer 31 .

[0090] For example, Figure 11A As shown, in some embodiments, three types of first via holes P with different hole depths h are manufactured:

[0091] like Figure 11A As shown, the hole depth h of the first type of via hole P is equal to the distance d1 between the first power line 5 and the first light shielding layer 31 in the direction perpendicular to the base substrate 1. That is, the first type of via hole P exposes the upper surface of the first light shielding layer 31 (i.e., the surface of the first light shielding layer 31 away from the base substrate). The hole depth h of the second and third types of first via holes P is greater than the distance d1 between the first power line 5 and the first light shielding layer 31 in the direction perpendicular to the base substrate 1, and less than the distance d2 between the first power line 5 and the base substrate 1 in the direction perpendicular to the base substrate 1. In addition, the hole depth h of the second type of via hole P is less than the hole depth h of the third type of via hole P.

[0092] See also Figure 12 When insufficient etching occurs, the via hole P with the smallest hole depth h may not expose the first light shielding layer 31, and the first power line 5 cannot be electrically connected to the first light shielding layer 31 through this via hole P. The other two via holes P with a larger hole depth h expose the first light shielding layer 31, and the first power line 5 can be electrically connected to the first light shielding layer 31 through these two via holes P.

[0093] Referring to FIG. 11 , when over-etching occurs, the via hole P having the largest hole depth h may cause etching damage to the first light shielding layer 31, potentially resulting in poor contact between the first power line 5 and the first light shielding layer 31. The first conductive layer 210 can be electrically connected to the first light shielding layer 31 through the other two via holes P having smaller hole depths h.

[0094] Based on this, the display substrate 1A provided in the present embodiment, by forming via holes P with different hole depths h, can effectively avoid poor contact between the first power line 5 and the first light shielding layer 31 caused by etching fluctuations (under-etching or over-etching) during the formation of the via holes P, which would result in waste of materials and an inability to effectively connect the first light shielding layer 31 to a stable electrical signal. By providing at least two types of via holes P with different hole depths h in the multiple insulating films 20b of the display substrate 1A, the contact yield between the first power line 5 and the first light shielding layer 31 is improved, thereby improving the reliability of the electrical connection between the first power line 5 and the first light shielding layer 31.

[0095] In some embodiments, as Figure 11A As shown, the plurality of via holes P include at least two types of via holes P with different apertures d ( Figure 10 In the figure, three types are used as examples for illustration), which can improve the contact yield between the first power line 5 and the first light shielding layer 31.

[0096] In some embodiments, see Figure 11A The plurality of via holes P include at least two types of via holes P with different hole depths h and different hole diameters d ( Figure 10 (Three examples are used for illustration.) This can improve the contact yield between the first conductive layer 20 and the light shielding layer 3.

[0097] In the following embodiments, the arrangement and positions of the plurality of vias P have the following situations:

[0098] In some embodiments, as Figure 2 As shown, the first light-shielding layer 31 is also located in the peripheral area 03, and the multiple vias P include multiple first vias P1 located in the peripheral area 03. The first light-shielding layer 31 is electrically connected to the first power bus 51 through the multiple first vias P1, thereby realizing the electrical connection between the first light-shielding layer 31 and the first power line 5.

[0099] In the peripheral area 03 , the arrangement of the plurality of first via holes P1 includes but is not limited to the following:

[0100] like Figure 2 As shown, the plurality of first via holes P1 include at least one first via hole group M ( Figure 13 5 first via hole groups M are used as an example for illustration). Each first via hole group M includes at least one first via hole column m ( Figure 13 In the figure, five first via hole rows m are used as an example. The hole depth h of each first via hole P1 in each first via hole row m is different. It should be noted that, Figure 13 The larger black dot in the figure represents the first via hole P1 with a larger hole depth h. Figure 2The smaller black dots represent the first via holes P1 with a smaller hole depth h, and the larger black dots represent the first via holes P1 with a larger hole depth h.

[0101] In this way, in the peripheral area 03, the first power bus 51 and the first light shading layer 31 can contact each other through at least one first via group M, thereby increasing the contact area between the first power bus 51 and the first light shading layer 31, thereby improving the contact yield between the first power bus 51 and the first light shading layer 31.

[0102] like Figure 2 As shown, in some embodiments, the first via holes P1 in each first via hole group M are arranged in an array.

[0103] Here, the array arrangement may be arranged in multiple rows and columns, for example, Figure 2 3 rows and 5 columns are used as an illustration. The row direction of the first vias P1 in each first via group M is assumed to be the first direction D1, and the column direction is assumed to be the second direction D2. It is understood that the row direction and column direction of the first vias P1 intersect with each other, that is, the first direction D1 and the second direction D2 intersect with each other, for example, the first direction D1 and the second direction D2 are perpendicular to each other.

[0104] In some embodiments, the plurality of first via holes P1 include three types of via holes with different hole depths h, and the number of first via hole columns m in each first via hole group M is multiple, such as 3, 4, 5, 6, 7, etc.

[0105] The following describes in detail the arrangement of the first via holes P1 in each first via hole group M, taking the multiple via holes P in these embodiments as an example. That is, the multiple via holes P include three types of via holes P with different hole depths h, and there are multiple first via hole columns m in each first via hole group M. It is understood that the arrangement of the first via holes P1 in each first via hole group M includes, but is not limited to, the following arrangements:

[0106] like Figure 2 As shown, each first via hole row m includes three via holes P with different hole depths h, and the three via holes P are arranged along the second direction D2. Each first via hole row m is arranged along the first direction D1, and the first via holes P1 with the same hole depth h in each first via hole row m are arranged in a row along the first direction D1.

[0107] In some examples, the arrangement of the first via holes P1 in each first via hole group M adopts the arrangement described above, and there are multiple first via hole groups M, for example, 3, 4, 5, 6, 7, etc. The multiple first via hole groups M are arranged along the first direction D1. The multiple first via hole columns m in each first via hole group M are arranged along the first direction D1, and the first via holes P1 with the same hole depth h in each first via hole column m are arranged in a row along the first direction D1.

[0108] In some embodiments, the plurality of first via holes P1 include at least one first via hole group M ( Figure 13 5 first via hole groups M are used as an example), each first via hole group M includes at least one first via hole column m ( Figure 13 (The five first via arrays m are used as an example for illustration); the aperture d of each first via P1 in each first via array m is different. Thus, within the peripheral area O3, the first power bus 51 can contact the first light shielding layer 31 via at least one first via array M, increasing the contact area between the first power bus 51 and the first light shielding layer 31 and thereby improving the contact yield between the first power bus 51 and the first light shielding layer 31.

[0109] Exemplarily, the number of the first via hole groups M is multiple, for example, 3, 4, 5, 6, 7, etc. The number of the first via hole columns m in each first via hole group M is multiple, for example, 3, 4, 5, 6, 7, etc. The multiple first via hole groups M are arranged along the first direction D1, wherein the multiple first via hole columns m in each first via hole group M are arranged along the first direction D1, and the first via holes P1 with the same aperture d in each first via hole column m are arranged in a row along the first direction D1.

[0110] In some embodiments, as Figure 2 As shown, the multiple vias include multiple first vias P1 arranged in the peripheral area 03, and also include multiple second vias P2 located in the first display area 012. The first light-shielding layer 31 is electrically connected to the multiple first power sub-lines 52 through the multiple second vias P2, thereby realizing the electrical connection between the first light-shielding layer 31 and the first power line 5.

[0111] A plurality of second via holes P2 are provided in the first display area 012, and the first light shielding layer 31 is electrically connected to the plurality of first power sub-lines 52 through the plurality of second via holes P2. In this way, the first light shielding layer 31 can not only access the first power signal through the first power bus 51 in the peripheral area 03, but also access the first power signal through the plurality of first power sub-lines 52 in the first display area 012, thereby ensuring that the first light shielding layer 31 can access the first power signal more evenly, thereby more effectively avoiding the occurrence of uncontrollable induced charges in the first light shielding layer 31 and ensuring the normal operation of the plurality of first sub-pixels 41.

[0112] In some examples, the multiple second vias P2 are evenly distributed in the first display area. Thus, in the first display area 012, the multiple first power sub-lines 52 can be more evenly electrically connected to the first light-shielding layer 31 through the multiple second vias P2, thereby ensuring that the first light-shielding layer 31 can be more evenly connected to the first power signal.

[0113] In some embodiments, as Figure 2 As shown, three first sub-pixels 41 are provided between every four openings of the first light shielding layer 31 . The three first sub-pixels 41 form a pixel 4 a , and the position of a pixel 4 a corresponds to at least one second via hole P2 .

[0114] For example, Figure 2 As shown, the first light-shielding layer 31 has a plurality of openings 31a arranged in an array, and a plurality of first sub-pixels 41 are grouped into three first sub-pixels 41 to form a plurality of pixels 4a arranged in an array. A pixel 4a is set between every four openings 31a, and the position of each pixel 4a corresponds to a second via hole P2.

[0115] Based on the arrangement of the above-mentioned multiple first sub-pixels 41, the multiple first power sub-lines 52 are grouped into three first power sub-lines 52, and the first power sub-lines 52 extend along the second direction D2. The row direction of the multiple array-arranged pixels 4a is the same as the first direction D1, and the column direction of the multiple pixels 4a is the same as the second direction D2. Each group of first power sub-lines 52 corresponds to a column of pixels 4a, and each first power sub-line 52 corresponds to a column of first sub-pixels 41.

[0116] In the display substrate 1A described above, each column of pixels 4a arranged along the second direction D2 corresponds to a first via group M, that is, each group of first power sub-lines 52 corresponds to a first via group M. This prevents the multiple first via groups M from being locally concentrated within the peripheral area 03. That is, the multiple first via groups M can be evenly distributed along the first direction D1 within the peripheral area 03, thereby improving the uniformity of the distribution of the contact positions between the first power bus 51 and the first light shielding layer 31, and further improving the uniformity of the signal received by the first light shielding layer 31.

[0117] In other embodiments, the multiple vias P include multiple second vias P2 located in the first display area 012, and the first light-shielding layer 31 is electrically connected to the multiple first power sub-lines 52 through the multiple second vias P2, thereby realizing the electrical connection between the first light-shielding layer 31 and the first power line 5.

[0118] A plurality of second via holes P2 are provided in the first display area 012, and the first light shielding layer 31 is electrically connected to the plurality of first power sub-lines 52 through the plurality of second via holes P2. In this way, the first light shielding layer 31 can be electrically connected to the plurality of first power sub-lines 52 through the plurality of second via holes P2, so that the first power signal can be accessed more evenly, thereby more effectively avoiding the occurrence of uncontrollable induced charges in the first light shielding layer 31 and ensuring the normal operation of the plurality of first sub-pixels 41.

[0119] In some examples, the multiple second vias P2 are evenly distributed in the first display area 012. Thus, in the first display area 012, the multiple first power sub-lines 52 can be more evenly electrically connected to the first light-shielding layer 31 through the multiple second vias P2, thereby ensuring that the first light-shielding layer 31 can be more evenly connected to the first power signal.

[0120] In some embodiments, as Figure 2 As shown, three first sub-pixels 41 are provided between every four openings 31 a of the first light shielding layer 31 . The three first sub-pixels 41 form a pixel 4 a , and the position of a pixel 4 a corresponds to at least one second via hole P2 .

[0121] For example, Figure 2 As shown, the first light-shielding layer 31 has a plurality of openings 31a arranged in an array, and a plurality of first sub-pixels 41 are grouped into three first sub-pixels 41 to form a plurality of pixels 4a arranged in an array. A pixel 4a is set between every four openings, and the position of each pixel 4a corresponds to a second via hole P2, thereby ensuring that the plurality of second via holes P2 are evenly distributed in the first display area 012.

[0122] In some embodiments, the first light-shielding layer 31 is also located in the peripheral area 03. On the basis that the multiple vias P include multiple second vias P2 located in the first display area 012, it also includes multiple first vias P1 arranged in the peripheral area 03. The first light-shielding layer 31 is electrically connected to the first power bus 51 through the multiple first vias P1, thereby realizing the electrical connection between the first light-shielding layer 31 and the first power line 5.

[0123] In the peripheral area 03 , the arrangement of the plurality of first via holes P1 can refer to the above description and will not be repeated here.

[0124] Please refer again Figures 2 to 4 The second display area 011 of the display substrate 1A is introduced below. In some examples, the second display area 011 is located on a side of the first display area 012 away from the first power line 5 .

[0125] like Figure 2 、 Figure 3A and Figure 3BAs shown, the display substrate 1A further includes: a second light shielding layer 32, a plurality of second sub-pixels 42 and a second power supply line 6. It should be noted that, in Figure 3A and Figure 3B In the figure, for ease of understanding, the cross-sectional patterns of multiple second sub-pixels 42 and their corresponding signal lines (including the second power line 6) and other structures arranged on the side of the second shading layer 32 away from the base substrate 1 are combined into one and illustrated as the display layer 2.

[0126] The second light shielding layer 32 is disposed on one side of the base substrate 1 . The second light shielding layer 32 is located in the second display area 011 . The second light shielding layer 32 and the first light shielding layer 31 are located in the same layer.

[0127] The plurality of second sub-pixels 42 are disposed on a side of the second light shielding layer 31 away from the base substrate 1 , and the plurality of second sub-pixels 42 are located in the second display area 011 .

[0128] The second power lines 6 include a second power bus 61 and a plurality of second power sub-lines 62. At least a portion of the second power bus 61 is located in an area of ​​the peripheral region 03 close to the second display region 011. The plurality of second power sub-lines 62 are located in the second display region 011 and are electrically connected to the second power bus 61. The plurality of second power sub-lines 62 are configured to provide a second power signal to the plurality of second sub-pixels 42.

[0129] In the aforementioned display substrate 1A, the second light-shielding layer 32 is configured to block ambient light, preventing it from passing through the display substrate 1A in the second display area 011. Furthermore, the second light-shielding layer 32 is configured to block light emitted by the light-emitting devices of the display substrate 1A (i.e., screen light). In other words, light emitted by the light-emitting devices can be emitted toward the side of the second light-shielding layer 32 away from the base substrate 1, but cannot be emitted toward the side of the second light-shielding layer 32 closer to the base substrate 1.

[0130] At the same time, a second light shielding layer 32 is provided, and the second light shielding layer 32 and the first light shielding layer 31 are located in the same layer, which can reduce the film thickness difference between the first display area 012 and the second display area 011 of the display substrate 1A and improve the flatness of the display substrate 1A.

[0131] In some embodiments, the second light shielding layer 32 is electrically connected to the second power line 6. Thus, the second power line 6 provides a second power signal to the second light shielding layer 32, thereby connecting the second light shielding layer 32 to a stable electrical signal. This prevents the second light shielding layer 32 from experiencing an uncontrollable potential signal that could affect the normal operation of other structures in the display substrate 1A, such as preventing the induced charges generated on the second light shielding layer 32 from affecting the plurality of second sub-pixels 42.

[0132] In some embodiments, the display substrate 1A also includes at least one insulating film arranged between the second power line 6 and the second light-shielding layer 32, and the at least one insulating film is provided with a plurality of vias passing through the at least one insulating film, and the second power line 6 is electrically connected to the second light-shielding layer 32 through the plurality of vias.

[0133] Regarding the specific arrangement of the above-mentioned multiple vias and the structure of the multiple second sub-pixels 42, please refer to the description of the specific arrangement of the multiple vias and the structure of the multiple second sub-pixels 42 in the first display area 012 of the display substrate 1A mentioned above, which will not be repeated here.

[0134] In some embodiments, as Figure 2 As shown, the distribution density of the plurality of second sub-pixels 42 is greater than the distribution density of the plurality of first sub-pixels 41. For example, the pixel distribution density of the first display area 012 is 300 PPI (Pixels Per Inch), and the pixel distribution density of the second display area 011 is 400 PPI.

[0135] like Figure 2 As shown, in the first display area 012, multiple first sub-pixels 41 are arranged in groups of three to form a plurality of pixels 4a arranged in an array, with one pixel 4a disposed between every four openings 31a. The distribution density of the multiple first sub-pixels 41 is relatively low. In the second display area 0121, multiple second sub-pixels 42 are arranged in an array, with a relatively high distribution density. Given the same area, the number of the multiple first sub-pixels 41 in the first display area 012 is less than the number of the multiple second sub-pixels 42 in the second display area 011.

[0136] Through such an arrangement, under the premise that the display area 01 of the display substrate 1A can display, the distribution density of the plurality of second sub-pixels 42 is greater than the distribution density of the plurality of first sub-pixels 41, that is, the number of first sub-pixels 41 in the first display area 012 is reduced relative to the second display area 011, so that in the first display area 012, the space occupied by the first sub-pixels 41 is reduced, and by setting a plurality of openings 31a in the first shading layer 31, space can be reserved for light to pass through, so that the first display area 012 has a higher light transmittance.

[0137] Thus, the display substrate 1A is applied to a display device 3A. Figure 6BAs shown, the front optical component 300 is disposed on a side of the display substrate 1A away from its display surface, and the orthographic projection of the front optical component 300 on the display substrate 1A is located within the first display area 012. In this way, the light (ambient light) emitted by the front optical component 300 can pass through the first display area 012 of the display substrate 1A, which has a relatively high light transmittance. At the same time, light from outside the display device can also pass through the first display area 012 of the display substrate 1A, which has a relatively high light transmittance, and be sensed by the front optical component 300, thereby enabling the front optical component 300 to perform the corresponding sensing function.

[0138] In some embodiments, the first power signal transmitted by the first power line 5 is the same as the second power signal transmitted by the second power line 6 , or the first power signal transmitted by the first power line 5 is different from the second power signal transmitted by the second power line 6 .

[0139] Exemplarily, when the first power signal is different from the second power signal, the first power signal is smaller than the second power signal.

[0140] Since the distribution density of the multiple second sub-pixels 42 is greater than the distribution density of the multiple first sub-pixels 41, and the first light-shielding layer 31 has multiple openings 31a, the area of ​​the first light-shielding layer 31 is smaller than that of the second light-shielding layer 32. Therefore, the first power signal required by the multiple first sub-pixels 41 and the first light-shielding layer 31 is smaller. Therefore, the size relationship between the first power signal and the second power signal is set so that the first power signal is smaller than the second power signal, so as to reasonably distribute the first power signal and the second power signal.

[0141] It is understood that in the display substrate 1A, an insulating film layer for insulation is provided between different conductive layers. In some embodiments, such as Figure 9A and Figure 9B As shown, the display substrate 1A also includes a first insulating layer 23 located between the first light-shielding layer 31 and the multiple first sub-pixels 41. The first insulating layer 23 insulates the first light-shielding layer 31 and the multiple first sub-pixels 41 from each other, thereby preventing crosstalk between the signals of the first light-shielding layer 31 and the multiple sub-pixels.

[0142] When the display substrate 1A further includes a second light-shielding layer 32, the first insulating layer 23 is disposed between the second light-shielding layer 32 and the plurality of second sub-pixels 42. For example, the first insulating layer 23 is an entire layer located in both the first display area 012 and the second display area 011. The first insulating layer 23 insulates the second light-shielding layer 32 from the plurality of first sub-pixels 41, thereby preventing crosstalk between the signals of the second light-shielding layer 32 and the plurality of sub-pixels.

[0143] At least one of the plurality of first sub-pixels 41 includes a thin film transistor and a storage capacitor. The thin film transistor and storage capacitor constitute a pixel driving circuit. The first sub-pixel 41 also includes a light-emitting device, which is electrically connected to the pixel driving circuit and is driven by the pixel driving circuit to emit light. Similarly, at least one of the plurality of second sub-pixels 42 includes a thin film transistor and a storage capacitor.

[0144] like Figure 9A and Figure 9B As shown, the thin film transistor TFT includes: an active layer 211 located on a side of the first insulating layer 23 away from the substrate 1, a first gate insulating layer 213 located on a side of the active layer 211 away from the substrate 1, a gate electrode 212 located on a side of the first gate insulating layer 213 away from the substrate 1, a second gate insulating layer 214 located on a side of the gate electrode 212 away from the substrate 1, an interlayer insulating layer 215 located on a side of the second gate insulating layer 214 away from the substrate 1, and a source electrode 216 and a drain electrode 217 located on a side of the interlayer insulating layer 215 away from the substrate 1.

[0145] The storage capacitor Cst includes a first plate c1 and a second plate c2 . The first plate c1 and the gate electrode 212 are located in the same layer, and the second plate c2 is located between the second gate insulating layer 214 and the interlayer insulating layer 215 .

[0146] like Figure 9A and Figure 9B As shown, the at least one insulating film 20 b mentioned above includes at least one of a first insulating layer 23 , a first gate insulating layer 213 , a second gate insulating layer 214 and an interlayer insulating layer 215 .

[0147] For example, Figure 9A As shown, in the first display area 012 of the display substrate 1A, the first power sub-line 52 is disposed in the same layer as the source electrode 216 and the drain electrode 217 of the thin-film transistor TFT. For example, the first power sub-line 52 is electrically connected to the drain electrode 217 of the thin-film transistor TFT, thereby providing a first power signal to the first sub-pixel 41. When the at least one insulating film 20b between the first power sub-line 52 and the first light-shielding layer 31 includes a first insulating layer 23, a first gate insulating layer 213, a second gate insulating layer 214, and an interlayer insulating layer 215, the second via hole P2 penetrates the first insulating layer 23, the first gate insulating layer 213, the second gate insulating layer 214, and the interlayer insulating layer 215, thereby electrically connecting the first power sub-line 52 to the first light-shielding layer 31.

[0148] In some embodiments, as Figure 9BAs shown, at least one first power sub-line 52 among the plurality of first power sub-lines 52 includes a third sub-layer 52a and a fourth sub-layer 52b, and the third sub-layer 52a and the fourth sub-layer 52b are electrically connected through a fourth via P4.

[0149] In the above embodiment, at least one first power sub-line 52 includes two layers, an insulating layer is provided between the third sub-layer 52a and the fourth sub-layer 52b, and the fourth via P4 penetrates the insulating layer to electrically connect the third sub-layer 52a and the fourth sub-layer 52b of the first power sub-line 52, so that the third sub-layer 52a and the fourth sub-layer 52b are connected in parallel. By such a configuration, the resistance of the first power sub-line 52 can be reduced, thereby reducing the loss of the first power signal during transmission, which is beneficial to the transmission of the first power signal in the first power sub-line 52. For example, as Figure 9B As shown, when at least one first power sub-line 52 includes a third sub-layer 52a and a fourth sub-layer 52b, the first light-shielding layer 31 is electrically connected to the third sub-layer 52a of the first power sub-line 52 through the second via P2, thereby achieving electrical connection with the first power sub-line 52.

[0150] In some embodiments, the first power bus 51 includes a first sublayer and a second sublayer, which are electrically connected via a third via. The first power bus 51 includes two layers, with an insulating layer disposed between the first sublayer and the second sublayer. The third via penetrates the insulating layer, electrically connecting the first sublayer and the second sublayer of the first power bus 51, thereby connecting the first sublayer and the second sublayer in parallel. This arrangement can reduce the resistance of the first power bus 51, thereby reducing the loss of the first power signal during transmission, and facilitating the transmission of the first power signal.

[0151] like Figures 5A to 5G The structure of the display substrate 1A is described in detail below with reference to a layout diagram (layout diagram) of the light shielding layer (including the first light shielding layer 31 and the second light shielding layer 32), the plurality of first sub-pixels 41, the plurality of second sub-pixels 42, and the plurality of signal lines in the display substrate 1A. The plurality of signal lines include a first power sub-line 52, a second power sub-line 62, a data line, a gate line (i.e., a scanning signal line), a common electrode line, an initial signal line, and the like.

[0152] like Figures 5A to 5FAs shown, without considering the insulating film, in a direction perpendicular to the base substrate 1 and from close to the base substrate 1 to away from the base substrate 1, the film layers included in the display substrate 1A are, in order: a light shielding layer (including a first light shielding layer 31 and a second light shielding layer 32), an active semiconductor layer 41a (i.e., a film layer where the active layer 211 of the thin film transistor TFT is located), a first conductive layer 81 (i.e., a film layer where the gate electrode 212 of the thin film transistor TFT and the first electrode c1 of the storage capacitor Cst are located), a second conductive layer 82 (i.e., a film layer where the second electrode c2 of the storage capacitor Cst is located), a connecting via K, and a third conductive layer 83 (i.e., a film layer where the source electrode 216 and the drain electrode 217 of the thin film transistor are located, that is, a third sublayer 52a of the first power sub-line 52). The above film layers are stacked in order to obtain Figure 5G The general layout diagram is shown.

[0153] In some embodiments, the active semiconductor layer 41a can be formed by patterning a semiconductor material. The active semiconductor layer 41a can be used to make the active layer of multiple transistors of the pixel driving circuit 21 in the first sub-pixel 41 or the second sub-pixel 42, such as Figure 8 As shown, the pixel driving circuit 21 includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, and a second reset transistor T7. Each active layer may include a source region, a drain region, and a channel region between the source region and the drain region. For example, the active layers of each transistor are integrally provided.

[0154] For example, the active semiconductor layer 41a may be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the source region and the drain region may be regions doped with n-type impurities or p-type impurities.

[0155] In some embodiments, as Figure 2 、 Figure 5C and Figure 5D As shown, the first conductive layer 81 includes a plurality of first signal lines extending along a first direction D1. For example, the plurality of signal lines include a reset control signal line 81a (reset), a scan signal line 81b (gate), and an emission control signal line 81c (EM). In some examples, the first conductive layer 81 also includes a first plate c1 of a storage capacitor Cst. The second conductive layer 82 includes a plurality of second signal lines extending along the first direction D1. For example, the plurality of signal lines include an initialization signal line 82a (vinit) and a voltage signal line 82b (VD). In some examples, the second conductive layer 82 also includes a second plate c2 of the storage capacitor Cst.

[0156] In the first display area 012, the portions of the first and second signal lines located between two adjacent pixels 4a (including three first sub-pixels 41) are converged relative to the portions located in the area where the pixels 4a are located. This design helps increase the area of ​​the opening 31a and improve the ambient light transmittance of the display substrate 1A provided in the embodiment of the present disclosure. In the second display area 011, the first signal lines 81a and the second signal lines 82a extend along the first direction D1 and are spaced uniformly in the first direction D1. The multiple first signal lines 81a are parallel to each other, and the multiple second signal lines 82a are parallel to each other, without a convergence design.

[0157] It should be noted that, in the first conductive layer 81, the number of each group of first signal lines (for example, 4) located in the first display area 012 is greater than the number of each group of first signal lines (for example, 3) located in the second display area 011. In the second conductive layer 82, the number of each group of second signal lines (for example, 3) located in the first display area 012 is greater than the number of each group of second signal lines (for example, 2) located in the second display area 011. This is because the distribution density of the first sub-pixels 41 is greater than the distribution density of the second sub-pixels 42, and the active semiconductor layers 41a of two adjacent second sub-pixels 42 located in the same column are connected to each other (see FIG. 1 ). Figure 5B Thus, in the second display area 011, the reset control signal line 81a (reset) in a group of first signal lines and the initialization signal line 82a (vinit) in a group of second signal lines can be shared by two adjacent second sub-pixels 42 located in the same column. However, in the first display area 012, the first signal lines and the second signal lines are clustered together, the distribution density of the first sub-pixels 41 is low, and the spacing is far apart. Therefore, the reset control signal line 81a (reset) and the initialization signal line 82a (vinit) cannot be shared by two adjacent first sub-pixels 41 located in the same column. Therefore, the number of first signal lines and second signal lines located in the first display area 012 is relatively large.

[0158] In some embodiments, as Figure 2 and Figure 5FAs shown, the third conductive layer 83 includes third signal lines extending along the second direction D2. Exemplarily, the third signal lines include multiple first power sub-lines 52 (VDD1) located in the first display area 012, multiple second power sub-lines 62 (VDD2) located in the second display area 011, and second data lines 72 (data2). The third signal lines extend along the first and second display areas 012 and 011, respectively. At the junction of the first and second display areas 012 and 011, the first data line 71 (data1) has a corner. In the first display area 012, the portions of the multiple third signal lines located between two adjacent pixels 4a (including three first sub-pixels 41) are converged relative to the portions located within the pixels 4a. This design helps increase the area of ​​the opening 31 and improve the ambient light transmittance of the display substrate 1A provided by the present embodiment. In the second display area 011, the multiple third signal lines extend along the first direction D1 and are parallel to each other, without a convergence design.

[0159] like Figure 5H As shown, Figure 5H Schematic diagram of the stacking position relationship of the active semiconductor layer 41a, the first conductive layer 81, the second conductive layer 82 and the third conductive layer 83. Figure 5H The schematic diagram shows the structure of the pixel driving circuit in a sub-pixel 42 in the second display area 011 (for example, corresponding to Figure 5G Area G) in the Figure 8 .

[0160] In some embodiments, the second data line 72 (data) is connected to the source region of the data write transistor T2 in the active semiconductor layer 41a through at least one via K in the insulating layer. The second power sub-line 62 (VDD2) is connected to the source region of the corresponding first light emission control transistor T4 in the active semiconductor layer 41a through at least one via K in the insulating layer. The second power sub-line 62 (VDD2) is connected to the first plate c1 of the storage capacitor Cst in the second conductive layer 82 through at least one via K in the insulating layer. The second power sub-line 62 (VDD2) is also connected to the voltage signal line 82b (VD) in the second conductive layer 82 through at least one via K in the insulating layer.

[0161] In some embodiments, as Figure 5HAs shown, the third conductive layer 83 further includes a first connecting portion 83a, a second connecting portion 83b, and a third connecting portion 83c. One end of the first connecting portion 83a is connected to the drain region of the corresponding threshold compensation transistor T3 in the active semiconductor layer 41a through at least one via K in the insulating layer. The other end of the first connecting portion 83a is connected to the gate of the drive transistor T1 in the first conductive layer 81 (i.e., the first plate c1 of the storage capacitor Cst) through at least one via K in the insulating layer. One end of the second connecting portion 83b is connected to the initialization signal line 82a (vinit) through a via K in the insulating layer. The other end of the second connecting portion 83b is connected to the drain region of the second reset transistor T7 in the active semiconductor layer 41a through at least one via K in the insulating layer. The third connecting portion 83c is connected to the drain region of the second emission control transistor T5 in the active semiconductor layer 41a through at least one via K in the insulating layer.

[0162] It should be noted that the present disclosure does not limit the structure of the pixel driving circuit 21 in the first sub-pixel 41 and the second sub-pixel 42. The above is only an example of the connection relationship between the transistors and the storage capacitors of the pixel driving circuit 21 in the second sub-pixel 42. The connection relationship between the transistors and the storage capacitors of the pixel driving circuit 21 in the first sub-pixel 41 can refer to the above description, but is not limited to this.

[0163] In some embodiments, in the first display area 012, each first sub-pixel 41 includes a light emitting device 22, illustratively, as shown in FIG. Figure 2 As shown, the first light-shielding layer 31 has a plurality of openings 31a arranged in an array, and a plurality of first sub-pixels 41 are grouped into three first sub-pixels 41 to form a plurality of array-arranged pixels 4a. When one pixel 4a is set between every four openings 31a, the light-emitting devices 22 in the three sub-pixels 41 included in one pixel 4a are configured to emit blue light, red light and green light, respectively.

[0164] In the second display area 011 , each second sub-pixel 42 includes a light-emitting device, and the plurality of light-emitting devices in the second display area 011 are configured to emit blue light, red light, or green light.

[0165] In some embodiments, as Figure 9AAs shown, when the first power sub-line 52 is a single layer, the film layer where the first power sub-line 52 and the source and drain of the thin film transistor are located is called the first source-drain layer (SD1 layer); when the first power sub-line 52 is a double layer (including the third sub-layer and the fourth sub-layer), the film layer where the third sub-layer of the first power sub-line 52 and the source and drain of the thin film transistor are located is called the first source-drain layer (SD1 layer), and the film layer where the fourth sub-layer of the first power sub-line 52 is located is called the second source-drain layer (SD2 layer). The display substrate 1A also includes a planar layer 24 disposed between the thin film transistor TFT and the light-emitting device 22, and a pixel defining layer 25 disposed on the side of the planar layer 24 away from the base substrate 1. Specifically, as shown in FIG. Figure 9A As shown, the planar layer 24 is disposed on the side of the first source and drain layer away from the base substrate 1. The planar layer 24 has a via hole extending therethrough to electrically connect the thin film transistor to the light-emitting device 22. The pixel defining layer 25 defines a plurality of openings for arranging the plurality of light-emitting devices 22 to define the size of the light-emitting area.

[0166] Exemplarily, the light emitting device 22 includes an anode 221, a cathode 223, and a light emitting layer 222 disposed between the anode 221 and the cathode 223. The relative positional relationship between the anode 221 and the cathode 223 in the embodiment of the present disclosure includes but is not limited to the following two situations:

[0167] One is, such as Figure 9A and Figure 9B As shown, cathode 223 is further away from substrate 1 than anode 221. That is, when substrate 1 is placed horizontally, in a direction perpendicular to substrate 1 and pointing from closer to substrate 1 to farther away from substrate 1, cathode 223 is on the upper layer and anode 221 is on the lower layer. The source electrode 216 of the thin-film transistor TFT is electrically connected to anode 221 via a via hole penetrating the planar layer 24.

[0168] Another is that the cathode is closer to the substrate than the anode. That is, when the substrate is placed horizontally, in a direction perpendicular to the substrate 1 and pointing from close to the substrate to away from the substrate, the cathode is at the bottom and the anode is at the top.

[0169] In some examples, such as Figure 9A and Figure 9B As shown, the display substrate 1A further includes an encapsulation layer 26 disposed on a side of the light-emitting device 22 away from the base substrate 1. For example, the encapsulation layer 26 includes a first inorganic encapsulation layer 261, an organic encapsulation layer 262, and a second inorganic encapsulation layer 263. The first inorganic encapsulation layer 261 is disposed on a side of the cathode 223 away from the base substrate 1, the organic encapsulation layer 262 is disposed on a side of the first inorganic encapsulation layer 261 away from the base substrate 1, and the second inorganic encapsulation layer 263 is disposed on a side of the organic encapsulation layer 262 away from the base substrate 1.

[0170] In some embodiments, see Figure 12 and Figure 13 The top view of the display substrate 1A is simplified, and only the arrangement of the plurality of first sub-pixels 41 and the plurality of second sub-pixels 42 is shown. It can be understood that Figure 2 The arrangement of the plurality of first sub-pixels 41 and the plurality of second sub-pixels 42 in the display substrate 1A is illustrated based on the layout of the pixel driving circuit 21 included in the sub-pixels. Figure 12 and Figure 13 The arrangement of the plurality of first sub-pixels 41 and the plurality of second sub-pixels 42 in the display substrate 1A is illustrated by the arrangement of the light-emitting devices (light-emitting areas of the light-emitting devices) included in the sub-pixels. Figure 2 and Figure 12 、 Figure 13 Can be compared.

[0171] like Figure 12 As shown, among some sub-pixels emitting the same color light, the area of ​​each first sub-pixel 41 located in the first display area 012 is larger than the area of ​​each second sub-pixel 42 located in the second display area 011. It should be noted that the area of ​​each first sub-pixel 41 and the area of ​​each second sub-pixel 42 described herein refer to the area of ​​the light-emitting area of ​​the light-emitting device 22 included in the sub-pixel. The orthographic projection areas of the pixel driving circuit 21 in the first sub-pixel 41 and the pixel driving circuit 21 in each second sub-pixel 42 on the substrate 1 are equal.

[0172] For example, in some sub-pixels for emitting red light, the area of ​​each first sub-pixel 41 located in the first display area 012 is larger than the area of ​​each second sub-pixel 42 located in the second display area 011. In some sub-pixels for emitting green light, the area of ​​each first sub-pixel 41 located in the first display area 012 is larger than the area of ​​each second sub-pixel 42 located in the second display area 011. In some sub-pixels for emitting blue light, the area of ​​each first sub-pixel 41 located in the first display area 012 is larger than the area of ​​each second sub-pixel 42 located in the second display area 011.

[0173] In the array substrate 1A provided by the embodiment of the present disclosure, since the distribution density of the first sub-pixels 41 in the first display area 012 is less than the distribution density of the second sub-pixels 42 in the second display area 011, the first display area 012 not only provides space for the aforementioned multiple first sub-pixels 41 and signal wiring (e.g., multiple first power sub-lines 52 and multiple first data lines 71, multiple gate lines, etc.), but also reserves a large amount of space. This reserved space corresponds to the multiple openings 31a of the first light-shielding layer 31. This reserved space can be used to transmit ambient light (e.g., infrared light), allowing the first display area 012 to both display images normally and transmit ambient light. This avoids the need to provide a hole in the array substrate 1A for mounting the front optical component 300, thus achieving full-screen display. At the same time, since the area of ​​the first sub-pixel 41 located in the first display area 012 of some sub-pixels used to emit the same color light is larger than the area of ​​the second sub-pixel 42 located in the second display area 011, the lower luminous intensity caused by the reduced pixel distribution density of the first sub-pixel 41 in the first display area 012 can be compensated, thereby reducing the brightness difference between the first display area 012 and the second display area 011.

[0174] In some embodiments, the shape of each of the plurality of sub-pixels may be a rectangle, a diamond, or other polygons. Of course, the shape may also be other regular shapes, which are not listed here one by one.

[0175] It is understandable that if Figure 13 As shown, each subpixel has at least one subpixel opening 200b. For example, the second subpixel 42 and the first subpixel 41 emitting red and blue light have one subpixel opening 200b, and the second subpixel 42 emitting green light has two subpixel openings 200b.

[0176] In some embodiments, the interval d3 between the sub-pixel openings 200 b of any two adjacent sub-pixels emitting the same color light along the first direction D1 is equal.

[0177] See also Figure 13 Taking the sub-pixel opening 200b of the first sub-pixel 41 emitting blue light and the sub-pixel opening 200b of the second sub-pixel 42 as examples, the meaning of "the interval d3 between any two adjacent sub-pixel openings along the first direction D1 emitting the same color light is equal" is explained. Its meaning includes three levels:

[0178] 1. The interval d3 between the sub-pixel openings 200 b of any two adjacent first sub-pixels 41 emitting blue light B along the first direction D1 is equal.

[0179] 2. The interval d3 between the sub-pixel openings 200 b of any two adjacent second sub-pixels 42 emitting blue light B along the first direction D1 is equal.

[0180] 3. The interval d3 between the sub-pixel openings 200b of any two adjacent second sub-pixels 42 emitting blue light B along the first direction D1 is equal to the interval d3 between the sub-pixel openings 200b of any two adjacent first sub-pixels 41 emitting blue light along the first direction D1.

[0181] In this way, when an organic electroluminescent material for emitting a certain color light (such as blue) is formed on the pixel definition layer 25 of the pixel display substrate 1A to form the light-emitting functional layer 222, the organic electroluminescent material is not easily formed in the wrong sub-pixel opening, thereby improving the color mixing problem.

[0182] It should be explained that, as can be seen from the above description of the light-emitting device 22, the light-emitting device 22 includes an anode 221, a light-emitting layer 222, and a cathode 223. The pixel defining layer 25 is disposed on the side of the anode 221 away from the base substrate 1 and has a sub-pixel opening that overlaps with the anode 221. Organic electroluminescent material is formed in the sub-pixel opening of the pixel display substrate 1A to form the light-emitting functional layer 222. Since the interval d3 between any two adjacent sub-pixel openings along the second direction D2 that emit the same color light is equal, when forming the light-emitting functional layer 222, the organic electroluminescent material is not easily formed in the wrong pixel opening, thereby improving the color mixing problem.

[0183] See also Figure 12 and Figure 13 It can be understood that the second display area 011 and the first display area 012 have a first boundary A (dashed line A).

[0184] In the first display area 012 , each first sub-pixel 41 closest to the first boundary A is configured to emit first color light, such as green light.

[0185] In the second display area 011, the number of sub-pixel openings 200b of each second sub-pixel 42 for emitting the first color light (e.g., green light) closest to the first junction A is smaller than the number of sub-pixel openings 200b of each second sub-pixel 42 for emitting the first color light (e.g., green light) in other areas of the second display area 011. This helps reduce the color difference of light near the first junction A.

[0186] For example, Figure 13 As shown, in the first display area 012, each first sub-pixel 41 closest to the first junction A is configured to emit green light. In the second display area 011, each sub-pixel 200 configured to emit green light closest to the first junction A has one sub-pixel opening 200b. However, in the second display area 011, each second sub-pixel 42 configured to emit green light has two sub-pixel openings 200b. This helps reduce light color differences near the first junction A.

[0187] like Figure 6B As shown, a display device 3A provided in an embodiment of the present disclosure further includes a cover plate 9 disposed on a side of the display layer 2 of the display substrate 1A away from the base substrate 1 .

[0188] The front optical component 300 is arranged on a side of the display panel 2A away from its display surface 01 a (ie, the back of the display panel 1A), and the orthographic projection of the front optical component 300 on the display substrate 2A is located within the first display area 012 .

[0189] It should be explained here that, although the front optical component 300 is arranged on the back side of the display substrate 1A, its corresponding receiving surface is facing the display surface 01a of the display substrate 1A to realize its front function.

[0190] The above-mentioned receiving surface means that when the front optical component 300 includes a front camera unit, the receiving surface is the lens of the front camera unit; when the front optical component 300 includes an infrared sensor unit, the receiving surface is the sensing surface of the infrared sensor unit.

[0191] The front optical component 300 may include a front camera unit, and of course, may also include an infrared detection unit 300 ′.

[0192] The display device 3A provided in the embodiment of the present disclosure can achieve the same beneficial effects as those achieved by the display substrate 1A provided in the embodiment of the present disclosure, and will not be described in detail here.

[0193] The display device 3A provided in the embodiments of the present disclosure can be any device that displays an image, whether in motion (e.g., video) or fixed (e.g., still image), and whether textual or pictorial. More specifically, it is expected that the embodiments can be implemented in or associated with a variety of electronic devices, including but not limited to mobile phones, wireless devices, personal data assistants (Portable Android Devices, abbreviated as PADs), handheld or portable computers, GPS (Global Positioning System) receivers / navigators, cameras, MP4 (full name MPEG-4 Part 14) video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays for displaying an image of a piece of jewelry), etc.

[0194] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate comprising a display area and a peripheral area surrounding the display area, wherein the display area includes a first display area; The display substrate comprises: substrate; a first light shielding layer provided on one side of the base substrate, the first light shielding layer being located in the first display area, and having a plurality of openings arranged in an array; a plurality of first sub-pixels disposed on a side of the first light-shielding layer away from the base substrate, the plurality of first sub-pixels being located in the first display area, and an orthographic projection of the plurality of first sub-pixels on the base substrate not overlapping with an orthographic projection of the opening on the base substrate; A first power line, comprising a first power bus and a plurality of first power sub-lines; At least a portion of the first power bus is located in a region of the peripheral area close to one side of the first display area; The plurality of first power sub-lines are located in the first display area and are electrically connected to the first power bus. The plurality of first power sub-lines are configured to provide a first power signal to the plurality of first sub-pixels. The orthographic projections of the plurality of first power sub-lines on the base substrate do not overlap with the orthographic projection of the opening on the base substrate. At least one insulating film is provided between the first power line and the first light shielding layer, wherein the at least one insulating film is provided with a plurality of via holes penetrating the at least one insulating film; The first light-shielding layer is also located in the peripheral area, and the multiple vias include multiple first vias located in the peripheral area. The first light-shielding layer is electrically connected to the first power bus through the multiple first vias, and the multiple first vias include at least two first vias with different hole depths.

2. The display substrate according to claim 1, wherein The plurality of first via holes include at least one first via hole group, each first via hole group includes at least one first via hole column; and the first via holes in each first via hole column have different hole depths.

3. The display substrate according to claim 2, wherein: There are multiple first via hole groups; each first via hole group includes multiple first via hole columns; The at least one first via hole group is arranged along a first direction; The plurality of first via hole columns in each first via hole group are arranged along the first direction, and the first via holes with the same hole depth in each first via hole column are arranged in a row along the first direction.

4. The display substrate according to claim 1, wherein: The plurality of via holes further include a plurality of second via holes located in the first display area, and the first light shielding layer is electrically connected to the plurality of first power sub-lines through the plurality of second via holes.

5. The display substrate according to claim 4, wherein: The plurality of second via holes are evenly distributed in the first display area. The display substrate according to claim 5 , wherein: Three first sub-pixels are arranged between every four openings of the first light shielding layer. The three first sub-pixels form a pixel, and the position of one pixel corresponds to at least one second via hole.

7. The display substrate according to any one of claims 1 to 6, further comprising: a first insulating layer located between the first light-shielding layer and the plurality of first sub-pixels; At least one first sub-pixel among the plurality of first sub-pixels comprises a thin film transistor and a storage capacitor; The thin film transistor includes: an active layer located on a side of the first insulating layer away from the substrate; a first gate insulating layer located on a side of the active layer away from the substrate; a gate located on a side of the first gate insulating layer away from the substrate; a second gate insulating layer located on a side of the gate away from the substrate; an interlayer insulating layer located on a side of the second gate insulating layer away from the base substrate; a source electrode and a drain electrode located on a side of the interlayer insulating layer away from the substrate; The storage capacitor includes a first plate and a second plate. The first plate and the gate are located in the same layer, and the second plate is located between the second gate insulating layer and the interlayer insulating layer.

8. The display substrate according to claim 7, wherein: The at least one insulating film includes at least one of the first insulating layer, the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer.

9. The display substrate according to claim 7, wherein: The first power bus includes a first sub-layer and a second sub-layer, and the first sub-layer and the second sub-layer are electrically connected through a third via.

10. The display substrate according to claim 7, wherein: At least one first power sub-line among the plurality of first power sub-lines includes a third sub-layer and a fourth sub-layer, and the third sub-layer and the fourth sub-layer are electrically connected through a fourth via.

11. The display substrate according to claim 1, wherein: The display area further includes a second display area; the second display area is located on a side of the first display area away from the first power line; The display substrate further includes: a plurality of second sub-pixels, located in the second display area; The second power line includes a second power bus and a plurality of second power sub-lines; at least a portion of the second power bus is located in an area of ​​the peripheral area close to one side of the second display area, the plurality of second power sub-lines are located in the second display area and are electrically connected to the second power bus, and the plurality of second power sub-lines are configured to provide a second power signal to the plurality of second sub-pixels.

12. The display substrate according to claim 11, wherein: A distribution density of the plurality of second sub-pixels is greater than a distribution density of the plurality of first sub-pixels.

13. The display substrate according to claim 11, wherein: The first power signal is the same as the second power signal, or the first power signal is different from the second power signal.

14. The display substrate according to claim 13, wherein: In a case where the first power signal is different from the second power signal, the first power signal is smaller than the second power signal.

15. The display substrate according to any one of claims 11 to 14, further comprising a second light shielding layer provided on one side of the base substrate, the second light shielding layer being located in the second display area, and the second light shielding layer and the first light shielding layer being located in the same layer; The second light shielding layer is electrically connected to the second power line.

16. A display device, wherein: include: The display substrate according to any one of claims 1 to 15; A front optical component is provided on a side of the display substrate away from the display surface thereof, and an orthographic projection of the front optical component on the display substrate is located within the first display area.

17. The display device according to claim 16, wherein: The front optical component includes: an infrared detection unit.

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