Single substrate multiplexer

Abstract

At least three acoustic filter circuits FC are arranged on a single chip CH. At least two of them have been electrically connected on the chip for multiplexing. This reduces space consumption and results in a smaller device size.

Description

[0001] At least three acoustic filters are arranged on a single chip. At least two of them have been electrically connected on the chip for multiplexing. This reduces space consumption and results in a smaller device size. Background Art

[0002] Devices In current mobile communication devices, multiplexers are used to allow filter operation in multiple frequency bands while using the same antenna connected to the multiplexer.

[0003] Discrete electroacoustic components with more than two filter functions or multiplexers consist of a carrier board (e.g. a laminate and individual filter chips). The respective filter function is embodied on a respective separate chip. This has the advantage that a separately optimized layer stack can be used for each filter function and different filter technologies can be used. In addition, the chip size for the individual filters remains small, which offers some advantages, for example in terms of mechanical stability or with regard to malfunctions of the individual filters during production, or when trimming the individual chips to the target frequency.

[0004] However, the carrier must be large enough to keep the distance between the chip edge and the electro-acoustic chip to a minimum. Moreover, heat dissipation is not optimal, cutting small chips from the wafer reduces the acoustically available area and results in greater material losses when dicing the wafer.

[0005] Using larger chips with more than two filter functions on a single chip is more sensitive to cracks and failures during operation due to thermal mismatches in the package or between the carrier and the chip. Further, it is difficult to simultaneously meet optimizations for different filter functions on the same chip. Summary of the invention

[0006] One object of the present invention is to provide a multiplexer as a chip solution which is thermally matched and fully meets the specifications of different filter functions. Another object is to provide a multiplexer with improved heat dissipation characteristics.

[0007] At least one of these objects is met by a multiplexer according to independent claim 1. Advantageous features and embodiments can be obtained from the dependent claims.

[0008] A multiplexer is formed by a single monolithic stack, the single monolithic stack comprising a carrier substrate comprising Si; a thin film piezoelectric layer located above the substrate and having a major surface; and at least one dielectric layer, the at least one dielectric layer being arranged between the piezoelectric layer and the substrate. On top of the major surface, the structured metal comprises an antenna terminal for connection to an antenna, three signal pads, and three SAW filter circuits. The filter circuits are connected in parallel between the antenna terminals and their respective corresponding signal pads. Each of the filter circuits comprises a series signal line and a plurality of SAW resonators connected in series or in parallel with the series signal line. The package provides a cavity on top of the stack, in which the SAW resonator is enclosed. The cavity is formed between the major surface of the piezoelectric layer and the lid and / or cover.

[0009] The multiplexer uses a single stack to implement all filter functions operated by the multiplexer. With a suitable combination of bands, that is, a suitable combination of filter functions for these bands, all bands can be operated using the same antenna with sufficient isolation between the band channels without any crosstalk.

[0010] The stack uses a thin film piezoelectric layer that does not generate parasitic modes in either of the filter circuits combined at the antenna terminals. Therefore, when the multiplexer operates in one frequency band, adjacent frequency bands do not interfere.

[0011] Each filter circuit includes all resonators required for the filter function. The multiplexer includes a separate filter circuit for each frequency band that can be operated by the multiplexer. This provides various technical advantages:

[0012] Wafer material can be saved. Instead of cutting each small chip from the wafer individually, only a single larger chip can be sawed. This greatly reduces the area loss of the wafer caused by cutting (for example, three square individual chips are reduced by one third or four square individual chips are reduced by half).

[0013] Depending on the process, the acoustic resonators must always maintain a minimum distance from the chip edge. Using a single chip instead of several smaller chips leads to a reduction in the overall chip edge area, which cannot be used acoustically and must remain free of any filter elements. In addition, the acoustic resonators can be placed more freely, since they do not have to be aligned on a straight edge in the area between the individual filter functions, but can be positioned in a variable manner. This provides more degrees of freedom for the design of existing acoustic surfaces, resulting in a more efficient use of space.

[0014] In addition, the single-chip variant offers the advantage that any heat loss energy generated can be dissipated more efficiently. The resulting heat is distributed over a larger chip, radiated better, and can be dissipated via a greater number of bumps. This has a positive impact on the performance compatibility and service life of the component.

[0015] Since usually only one filter circuit of the multiplexer is in operation, only the corresponding filter circuit generates heat. The other inactive filter circuits and the corresponding areas they occupy provide enough space in the stack to dissipate heat sufficiently to avoid excessive temperature rise.

[0016] It is preferred to use a substrate material for stacking that has a thermal conductivity that is at least ten times higher than the corresponding thermal conductivity of the piezoelectric layer. This relationship can be achieved by a single crystal Si carrier substrate and a piezoelectric layer consisting of lithium tantalate LT or lithium niobate LN. The thermal conductivity of silicon is about 40 times better than the usual SAW materials LiTaO3 or LiNbO3. The piezoelectric layer with poor thermal conductivity is relatively thin, the thermal resistance generated is correspondingly low, and heat can pass through the layer effectively. Therefore, most of the heat dissipation occurs in the Si substrate material with good conductivity, which is an improvement over SAW devices or filter chips implemented on well-known thick piezoelectric substrates.

[0017] According to a preferred embodiment, the piezoelectric layer is a single crystal thin film layer of lithium tantalate or lithium niobate and has a thickness in the range of 400nm to 2000nm. This layer thickness is conducive to TFSAW filter circuits operating in low frequency bands, medium frequency bands and high frequency bands. In order to minimize acoustic losses and achieve wafer bonding, the piezoelectric layer preferably has a smooth upper surface and lower surface. In this context, a smooth surface must be understood as having a roughness value Rq≤0.5nm, where Rq is the corresponding root mean square value. The root mean square (RMS or rms) is defined as the square root of the mean square (the arithmetic mean of the squares of the set of deviations from the mean line). The exact definition of the roughness parameter can be found in https: / / en.wikipedia.org / wiki / Surface_roughness.

[0018] The dielectric layer below the piezoelectric layer is preferably a silicon oxide layer with a thickness of 300nm to 2000nm and a smooth top surface with a roughness value of Ra≤0.5μm, where Ra is the arithmetic mean deviation from a constant mean line of the profile being evaluated. Such a dielectric layer can play a role in reducing the TCF (thermal coefficient of frequency) of the multiplexer and compensate or reduce the temperature drift of the filter circuit due to the relatively high TCF of the piezoelectric.

[0019] Fixed positive charges appear between the direct junction of the Si substrate and the silicon oxide layer, which attract mobile electrons, causing the conductive layer to suffer ohmic losses. In order to avoid such losses, it is advantageous to insert a trap-rich layer between the Si and SiO2 layers. The trap-rich layer can be composed of polysilicon with a thickness ranging from 100nm to 2000nm, for example.

[0020] A multilayer board with contact pads on the bottom surface and integrated wiring within its multilayer structure can be used for wiring and packaging. The contact pads of the board are connected to corresponding external contacts on the top surface opposite to the bottom surface to allow connection to external circuit systems of electronic devices such as mobile phones.

[0021] The multilayer board is mounted and electrically connected to the stack by connection technology. The contact pads are connected to the corresponding signal pads and antenna terminals on the main surface, for example, by bumps. A sealing device can be provided to seal the cavity formed between the multilayer board and the main surface.

[0022] Alternatively, the SAW resonator can be enclosed in a corresponding cavity formed as a thin film acoustic package TFAP. Such a TFAP can enclose a single filter function, a part of a filter function, or a single resonator. The TFAP can be produced by applying and structuring a sacrificial material to preform the corresponding cavity. A thin film with mechanical stability is then deposited over the entire surface of the chip to cover the sacrificial structure. The cavity is then released by removing the sacrificial material.

[0023] Since the single-chip multiplexer eliminates the distance between the individual filter chips required for the multi-chip multiplexer, the surface area of ​​the board can be reduced if a packaging technology with a board (e.g., CSSP) is used. Since the size of the individual chips for the single-chip variant is significantly larger than that of the multi-chip variant, it is advantageous for the present invention to use a board material with a thermal expansion coefficient similar to that of the wafer material. This minimizes mechanical stress during temperature cycling.

[0024] Suitable board materials are for example laminates, HTCC or LTCC. The latter are particularly advantageous in connection with silicon-based TF-SAW wafer materials, allowing good adjustment of the thermal expansion coefficients of the stack / wafer and board. Overall, the competitive advantage stems from the lower cost and smaller size of the multiplexer.

[0025] The complete multiplexer interconnect can be measured at a very early stage in the manufacturing process and interactions between the individual filters can therefore be detected. Thus, production variations can be compensated at an early stage by, for example, trimming.

[0026] During the manufacturing of a monolithic multiplexer, fluctuations usually have a similar effect on all filters in the stack and can be corrected by the trimming process. This is in contrast to the situation with multi-chip components, where large statistical deviations in device characteristics and a wide distribution of filter functions may occur. If two of the filter functions are close to each other in frequency and therefore require a high degree of mutual selection of the corresponding counter bands, they can benefit from the monolithic setup of the new multiplexer, since both filter functions are affected by process variations running in parallel, i.e., the critical passband edges of different filter circuits on the same stack are shifted in frequency in the same direction.

[0027] Therefore, critical duplex spacing can be more easily guaranteed in process engineering. This is not the case with multi-chip modules.

[0028] Since all necessary bump connections for all filter circuits of a multiplexer can be processed in one step, other processing times and associated costs, for example during sawing or flip-chip bonding, can be reduced.

[0029] The application of the invention is particularly attractive for multiplexers where only a small number of filter circuits / filter functions are involved whose frequencies must be met very accurately due to the high proximity selection requirements, as well as for a large number of filters where the requirements are less stringent. The critical filters can then be trimmed in general and the filters can be designed so that there is sufficient margin to meet the less critical specifications.

[0030] According to one embodiment, the multiplexer includes four SAW filter circuits to form a quad multiplexer. The four filter functions form two duplexers configured to allow the quad multiplexer to operate at a band combination of bands B1 and B3 or a band combination of bands B25 and B66.

[0031] In this example, the filter functions for the B3 and B25 bands must be tailored very accurately, while the specifications for the B1 or B66 bands are less critical.

[0032] However, more complex selective multiple tailoring of the individual filter elements may also be used.

[0033] Initial trimming can be done during stack production. The thickness uniformity of deposited or otherwise produced layers is thus measured and controlled. If necessary, selective thinning can be performed by removing material by NF3 beam. The thicknesses of the dielectric and piezoelectric layers are most relevant to the filter specifications. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The invention is explained in more detail with reference to embodiments and to the accompanying drawings. The drawings are merely schematic and may not be drawn to scale.

[0035] Figure 1 shows a known multiplexer arrangement of four separate chips on a common multilayer board with the necessary chip-to-chip distance and edge margin;

[0036] Figure 2 A single chip multiplexer according to the present invention and the necessary margins are shown;

[0037] Figure 3 shows a schematic block diagram of four filter circuits arranged on a single chip and connected to a common antenna terminal;

[0038] Figure 4 A schematic filter circuit is shown in more detail;

[0039] Figure 5 shows a schematic block diagram of a DMS filter that can be used as a resonator in an Rx filter circuit;

[0040] Figure 6 shows a cross section through a single chip stack provided with a structured metallization including pads, electrode structures and terminals which can be used for a multiplexer;

[0041] Figure 7 A possible schematic packaging of a multiplexer is shown. DETAILED DESCRIPTION

[0042] Figure 1 The arrangement of four separate chips CH on a common multilayer board MLB with necessary chip-to-chip distances and edge margins is shown. Due to these necessary distances, the acoustically available area AA of the chip CH is smaller than the area of ​​the chip. Further, the chip must maintain a certain distance from the edge of the multilayer board and between adjacent chips.

[0043] Figure 2 The necessary area of ​​a multiplexer according to the invention implemented on a single chip is shown at the same scale. In this arrangement, no chip-to-chip distance is required and relative to Figure 1 The chip area required for the margin of a single chip is smaller. The same is true for the margin of a multilayer board MLB. Therefore, up to 50% and more of the chip area can be saved, and a multiplexer device whose size is correspondingly smaller than that of a multiplexer device according to the arrangement of the single chip and the margin of a multilayer board MLB can be realized. Figure 1 Dimensions of known multi-chip modules.

[0044] Figure 3An exemplary schematic block diagram of four filter circuits FC1 to FC4 arranged on a single chip CH and connected to a common antenna terminal AT is shown. Each of the filter circuits FC includes a series signal line SSL connecting each corresponding signal pad SP to the antenna terminal AT and a plurality of SAW resonators. The series resonators RS are connected in series, and the parallel resonators RP are connected in parallel to the series signal line SSL.

[0045] The filter circuit is a ladder arrangement and may include other elements that are not shown in the figure for clarity. The number of resonators may be greater to achieve better selectivity. Some of the resonators may be cascaded to increase their power resistance and to improve lifetime and reduce nonlinear behavior. The filter circuit may consist of only the series resonator RS. Passive elements may be connected to the resonator or to the series signal line. Capacitors may be connected to a single resonator in a parallel circuit to vary its bandwidth. The parallel resonator RP may be connected to ground via an inductor. Some of the ground connections may be combined on the chip. The antenna terminal is connected to ground via a coil for phase shifting and impedance matching. External matching elements may be connected to the signal pad or the series signal line.

[0046] Two filter circuits can be assigned to the same first cellular frequency band and form the Rx filter and the corresponding Tx filter of the frequency band. The other two filter circuits can be assigned to the second cellular frequency band to allow duplex operation in the second frequency band. Preferably, the filter circuits are assigned to a frequency band combination with a not too high frequency distance. Preferably, the two frequency bands are within the same frequency range selected from the high frequency band range and / or the medium frequency band range.

[0047] Figure 4 In more detail, the Figure 3 A schematic exemplary filter circuit FC similar to the filter circuit depicted in FIG. The filter circuit includes five series resonators RS arranged in a series signal line SSL. The corresponding node between each two adjacent series resonators is connected to ground via a parallel branch, and a parallel resonator RP is arranged in each parallel branch. An inductor (not shown) can be connected between the parallel resonator and ground.

[0048] Figure 5A schematic block diagram of an exemplary DMS filter that can be used as a series resonator in an Rx filter circuit of a multiplexer is shown. The DMS filter includes a first number of interdigital transducers / resonators IDT connected to an input terminal IN of the DMS filter. A second number of interdigital transducers IDTs are connected to an output terminal OUT of the DMS filter. All IDTs are arranged in an acoustic track extending between two reflectors REF and are therefore acoustically coupled. The first number and the second number can be set to be higher than the number depicted according to the desired selectivity specification. The bus bars of the IDTs that are not connected to the input or output can be grounded or floating. Two DMS filters can be connected in series within the filter circuit. Figure 3 and Figure 4 The other components of the filter circuit shown constitute the filter circuit.

[0049] Figure 6 A schematic cross section through a monolithic stack is shown, which has been provided with a structured metallization on top. Figure 3 According to the requirements of the multiplexer, pads, electrode structures ES such as interdigital transducers, reflectors, conductor lines, terminals AT and signal pads SP1, SP2 are formed from the metallization.

[0050] The carrier substrate SU is a crystalline silicon material having a thickness sufficient to provide the required mechanical stability. The stability must be high enough to allow handling of the entire wafer with the stack ST formed thereon. The crystalline silicon material of the carrier substrate SU may have a top surface that is a crystalline

[111] surface.

[0051] Optionally, a trap rich layer TRL is arranged on top of a carrier substrate SU, which includes, for example, a polysilicon layer with a thickness in the range of 100 nm to 2000 nm, to eliminate, for example, known free charges at a later Si / SiO2 junction. A dielectric layer DL of SiO2 is formed or deposited to act as a TCF compensation layer. The thickness of the dielectric layer is controlled and set to a value of about 300 nm to 2000 nm, for example, 500 nm. All layer junctions can have smooth top and bottom surfaces with little layer roughness.

[0052] After smoothing the surface of the dielectric layer DL, for example by a CMP method, the piezoelectric wafer is bonded to the dielectric layer DL. After atomic bonding, the thickness of the piezoelectric wafer is reduced to form a thin film piezoelectric layer PL with a thickness of about 400nm to 2000nm (e.g., 600nm). This is thin enough to allow rapid heat dissipation from the filter circuit to the substrate below and avoid exciting parasitic modes in the counter frequency band or other frequency bands that may be operated by the multiplexer. For a sufficiently thin piezoelectric layer, parasitic modes only appear at frequencies above the frequency band used by the multiplexer.

[0053] After the thickness has been reduced by an appropriate process, the thickness of the piezoelectric layer is measured and the entire layer is trimmed to achieve the desired thickness with only a small tolerance across the entire wafer. This is necessary because the frequency of the filter circuit formed on the piezoelectric layer may depend on its specific thickness and too high a tolerance results in frequency variations and frequency distribution across the wafer that depends on the remaining thickness variations.

[0054] Lithium tantalate LT and lithium niobate LN are preferred piezoelectric materials. However, other materials may also be used.

[0055] It is important that the thermal conductivity of the substrate SU is at least ten times higher than the corresponding thermal conductivity of the piezoelectric layer PL.The conductivities of the piezoelectric layers PL of the silicon substrates SU and LT proposed above differ by a factor of about 40.

[0056] The top surface of the stack ST is a main surface on which the electrode structure ES and the signal pad SP and the antenna terminal AT are formed. Figure 6 The metallization is shown in a very schematically depicted manner. Other pads are present on the main surface, such as a ground pad for connecting the shunt branch to ground, but are not shown in the schematic diagram.

[0057] Preferably, the electrode structure is formed by a metallization based on Al or an Al alloy. Further, Cu and / or Ti may be other components in the alloy or may be used as discrete sub-layers of a multilayer metallization. The surface of the metallization may be protected using a passivation layer. The pad is thickened and provided with a solderable surface layer, such as, for example, gold or nickel.

[0058] To complete the multiplexer, a package is formed on top of the stacked ST. For this reason, a multilayer board can be bonded to the main surface of the stack.

[0059] Figure 7 A cross section of such a multiplexer already provided with such a cover plate is shown.

[0060] The multilayer board MLB can be any material, such as an organic laminate (such as FR4) or formed of ceramic materials such as LTCC and HTCC. Ceramics are preferred because they have higher thermal conductivity and because the thermal expansion of ceramics matches the thermal expansion of the Si carrier. LTCC is preferred for multilayer boards MLB.

[0061] The wiring is integrated into the multilayer board, and the wiring includes through-contacts that pass through one or more of the ceramic or laminate layers and the wiring plane. The through-contacts connect different wiring planes arranged between two such ceramic or laminate layers, or connect the wiring plane with the contact pads CP on the bottom surface or the external contacts EC on the top surface. The wiring is used to interconnect and circuit-connect different signal pads and / or terminals, and provide connections between signal pads, antenna terminals, and external contacts EC arranged on the top of the multilayer board MLB.

[0062] Further, the multilayer board may include integrated passive components that may be formed by such integrated wiring. These passive components may support the filter function of the filter circuit. Such integrated passive components may be used to form a coil connected to the antenna terminals and an inductor in series with the parallel branch. Passive components that require a higher quality factor (such as passive components for matching the terminals of the filter circuit) must be implemented as external discrete components that can be connected to external contacts.

[0063] The mounting of the stacked ST to the multi-layer board MLB can be done at the wafer level. Then, in a final step, the individual devices can be separated by cutting the wafer level package (e.g., by sawing).

[0064] Alternatively, a large area multilayer board may be used on which to mount individual stacks that have been singulated previously.

[0065] The bumps BU are preferably used to connect the multilayer board to the respective pads SP and terminals AT on the main surface of the stack ST. To facilitate heat dissipation from the filter circuit and the respective active piezoelectric layers to the multilayer board, a maximum number of bumps is preferred.

[0066] exist Figure 3 In the example of FIG. 1 , at least 13 pads and terminals need to be contacted by separate protrusions, respectively. A greater number of parallel branches allows mounting to be performed by a greater number of protrusions. In addition, protrusions without any electrical function can be used to provide better heat dissipation.

[0067] In packaging, the areas of stacks and multilayer boards can be compatible. However, it may be advantageous if the margin of the stack or board extends beyond the edge of another packaging layer. The sealing layer can then be applied from the side of the layer or stack with the smaller area. The sealing layer can then more easily seal the protruding surfaces in the margin area.

[0068] Sealing can be done using resin, laminate or foil; and with a metal layer as the top sealing layer, a hermetic seal can be achieved. The sealing layer needs to be constructed to expose at least the external contacts EC of the package.

[0069] Since the invention has been described with reference to some embodiments, the invention should not be limited to any particular embodiment or figure. Features that are specified in more detail in writing or in the drawings with reference to the embodiments alone should not be limited to that detail, insofar as the corresponding features are disclosed in a more general form and covered by the claims.

[0070] List of terms and reference symbols used

[0071] Cavity

[0072] Metallization Department

[0073] Encapsulation

[0074] Rx Filter

[0075] Tx Filter

[0076] AA Acoustic Available Area

[0077] AT Antenna Terminal

[0078] BU bulge

[0079] CH Chip

[0080] CP Contact Pad

[0081] DL dielectric layer

[0082] EC external contacts

[0083] ES Electrode Structure

[0084] FC SAW filter circuit

[0085] IDT Interdigital Transducer

[0086] IN DMS filter input terminal

[0087] MLB Multilayer Board

[0088] OUT Output terminal of DMS filter

[0089] PL Piezoelectric Layer

[0090] REF Reflector

[0091] RS,RP Series and Parallel SAW Resonators

[0092] SP signal pad

[0093] SSL serial signal cable

[0094] ST Monolithic Stacking

[0095] SU Carrier Substrate

[0096] TRL Trap-rich layer

Claims

1. A multiplexer comprising: Monolithic stack, including: a carrier substrate; a piezoelectric layer disposed over the carrier substrate and having a major surface; and at least one dielectric layer disposed between the piezoelectric layer and the carrier substrate; A metallization, located on top of said major surface, comprising: Antenna terminal, used for connecting an antenna; Three signal pads; a trap rich layer (TRL), disposed between the carrier substrate and the piezoelectric layer, the trap rich layer comprising a polysilicon layer; three surface acoustic wave (SAW) filter circuits connected in parallel between the antenna terminal and corresponding signal pads, wherein each of the three SAW filter circuits includes a corresponding series signal line and a plurality of SAW resonators connected in series or in parallel with the corresponding series signal line; and A package is provided on top of the monolithic stack with a cavity being provided wherein the three SAW filter circuits are enclosed in the cavity, the cavity being formed between the major surface of the piezoelectric layer and a lid and / or cover.

2. The multiplexer according to claim 1, wherein the carrier substrate comprises Si, The piezoelectric layer is a single crystal thin film layer of lithium tantalate or lithium niobate, and the single crystal thin film layer has a thickness of 400nm to 2000nm.

3. The multiplexer according to claim 1, The at least one dielectric layer is a silicon oxide layer having a thickness of 300 nm to 2000 nm and a smooth top surface.

4. The multiplexer according to claim 1, The polysilicon layer has a thickness between 300 nm and 2000 nm.

5. The multiplexer according to claim 1, The thermal conductivity of the carrier substrate is at least ten times greater than the thermal conductivity of the piezoelectric layer.

6. The multiplexer according to claim 1, A multilayer board including contact pads on a bottom surface thereof, and integrated wiring connecting the contact pads to corresponding external contacts on a top surface opposite the bottom surface; wherein the multilayer board is mounted to the monolithic stack by a connection technique to electrically connect the contact pads with corresponding signal pads and the antenna terminals; wherein the connection comprises a protrusion, Sealing means are provided to seal the cavity formed between the multilayer board and the major surface.

7. The multiplexer according to claim 6, The multilayer board is selected from the group consisting of multilayer laminates, HTCC and LTCC.

8. The multiplexer according to claim 1, The three SAW filter circuits are enclosed in the cavity, and the cavity is integrally formed as a thin film acoustic package.

9. The multiplexer according to claim 1, In addition to the three SAW filter circuits, another SAW filter circuit (FC) is provided to form a quadplexer including two duplexers, wherein the two duplexers are configured to operate in frequency bands B1 and B3 or frequency bands B25 and B66.

10. The multiplexer according to claim 1, A trim layer is included, the trim layer being located on top of the monolithic stack, wherein one or more layers of the monolithic stack are trimmed to meet specifications of band B3 or B25.

11. The multiplexer according to claim 1, A filter circuit is included, the filter circuit being an Rx filter having a DMS filter in the corresponding series signal line.

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