An event tracking synchronization method based on TMS320C6678 distributed system

Abstract

The present application relates to the field of TMS320C6678 chips, and is an event tracking synchronization method based on a TMS320C6678 distributed system. The method starts the core 0 counter at the initial stage of power-on to complete the system time synchronization of core 0, so that the counting time of each DSP in the system is synchronized at this time, and then the synchronization of other cores is achieved by blocking other cores at the same position, and then the counting of other cores is started, so that the synchronization of all cores is achieved accurately and stably, and the method has strong adaptability, small system occupancy, and is easy to use.

Description

Technical Field

[0001] The present application belongs to the field of TMS320C6678 chips, and in particular to an event tracking synchronization method based on a TMS320C6678 distributed system. Background Art

[0002] C6678 is a high-performance multi-core DSP embedded chip, which is widely used in the field of signal and information processing with high computing requirements. TI provides a variety of C6678 loading methods, and can load software through interfaces such as JTAG (debugging test interface), Ethernet (ETH), PCIe (PCI Express bus), etc. The Bootloader of C6678 is divided into two levels. The first level is Rom Bootloader (RBL), which is the first code to run after the processor is powered on and reset. It is used to complete the system initialization configuration after the processor is powered on. Which way to run the secondary Bootloader. The code of RBL is fixed in the processor when the processor leaves the factory and cannot be changed by the user. The second level is Intermediate Bootloader (IBL). According to user needs, complete the system initialization configuration, such as initialization of working clock PLL, DDR memory, count timer, etc., as well as select the loading method of DSP and the transfer execution of application program.

[0003] Event tracking refers to recording the start and end time of an event in the system and the time it takes to process the event and other related information during the system operation. For example, for data transmission between processors, users want to know when the output processor starts outputting, when the receiving processor starts receiving, and how long the data transmission takes, which can all be recorded through event tracking. Event tracking is an extremely important debugging method in distributed systems.

[0004] In the distributed real-time system of C6678, each node processor has its own independent hardware clock. C6678 contains 8 cores, each of which has two counting registers TSCH and TSCL, which are in the same frequency as the CPU and represent a 64-bit number together. When the CPU runs a cycle, the register is incremented by 1 to record the time when the DSP runs or an event occurs. However, distributed systems that use ETH, PCIe, JTAG and other loading methods generally have inconsistent loading times for each DSP, which will cause the DSP time to be out of sync, and therefore the event tracking in the system cannot be synchronized. For example: when two DSPs communicate, due to inconsistent loading times, the system records inconsistent time, making it impossible to calculate the time required for this communication through event tracking.

[0005] Therefore, how to ensure the consistency of system recording time and accurately track and calculate event communication time is a problem that needs to be solved. Summary of the invention

[0006] The purpose of this application is to provide an event tracking synchronization method based on the TMS320C6678 distributed system to solve the problem that the system recording time in the C6678 chip in the prior art is inconsistent and the communication time cannot be calculated based on the event.

[0007] The technical solution of the present application is: an event tracking synchronization method based on a TMS320C6678 distributed system, comprising: system power-on initialization; starting the core 0 counter at the power-on initial node to complete the system time synchronization of core 0; starting all cores other than core 0, blocking the core that runs first at the same position, until it is determined that all cores that need to be synchronized have run to this position, and all cores continue to run backwards; starting other cores to count; and recording event information that needs to be tracked in the system.

[0008] Preferably, the specific method of multi-core synchronization is to define an array counter_instance in the chip external memory DDR, the values ​​in the array are randomly given by power-on initialization and can be accessed by all cores; each core copies the initial value in counter_instance to its own array on_entry, the on_entry array is stored in private memory, and only the core can access it; at the same time, an array element in counter_instance is allocated to each core; the program enters a loop processing, each loop adds 1 to the array element value allocated to the core, and compares whether the other element values ​​in the array are consistent with the corresponding array element values ​​of on_entry in the core, if they are consistent, then the next loop is performed, if not, the next step is executed; and the loop is exited.

[0009] Preferably, after multi-core synchronization, the values ​​of the counting timers TSCH and TSCL of core 0 are recorded and combined into a 64-bit time counter t0, the registers TSCH and TSCL of other cores except core 0 are cleared, and the counting timer is started; the system time difference between the cores inside the DSP is calibrated through t0.

[0010] Preferably, after event tracking, information of all tracking events in the system is obtained, and a fixed time difference t0 is added to the start and end times of the events respectively as calibrated event tracking events; all tracking events are displayed graphically on the same timeline.

[0011] Preferably, the system time synchronization method of core 0 is to electrically start BootLoader, initialize the second-level IBL after running the first-level program, clear the core count register in the IBL stage, and start the system timer of core 0.

[0012] Preferably, the event information to be tracked includes the start and end time of the event, the slice number and core number in the system, and the running position in the program.

[0013] The present application discloses an event tracking synchronization method based on a TMS320C6678 distributed system. The method starts the core 0 counter in the initial power-on stage to complete the system time synchronization of core 0, so that the counting time of each DSP in the system is synchronized at this time. The method then blocks other cores at the same position to achieve synchronization of other cores. The method then starts counting other cores, thereby accurately and stably achieving synchronization of all cores. The method has strong adaptability, small system occupancy, and is easy to use. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solution provided by the present application, the following is a brief introduction to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present application.

[0015] Figure 1 This is a schematic diagram of the overall process structure of this application;

[0016] Figure 2 This is a schematic diagram of the synchronization process of other cores other than core 0 in this application;

[0017] Figure 3 This is a synchronous display diagram for event tracking of this application. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the implementation of this application clearer, the technical solutions in the embodiments of this application will be described in more detail below in conjunction with the drawings in the embodiments of this application.

[0019] An event tracking synchronization method based on TMS320C6678 distributed system, such as Figure 1 As shown, the following steps are included:

[0020] Step S100, system power-on initialization;

[0021] When the C6678-based distributed system is powered on, the chip starts the RBL and completes the system initialization configuration. This stage is the factory-hardened program and cannot be modified; the DSP is guided into the secondary loading (IBL). Since the same power supply is used, the power-on initialization startup time of each C6678 is basically the same (after testing, the difference is at the microsecond level). At the same time, the RBL and IBL of the DSP are exactly the same, so the running time is also the same.

[0022] Step S200, start the core 0 counter at the power-on initial node to complete the system time synchronization of core 0; C56678 uses the BootLoader method of secondary booting when it is powered on. In the IBL initialization phase, the two system counters TSCH and TSCL of each C6678 core 0 are cleared, the counting timer of core 0 is started, and the core 0 system time starts counting. At this time, the counting time of core 0 of each DSP in the system is synchronized, so the core 0 time of all DSPs in the system can be synchronized.

[0023] Step S300, start all cores except core 0, block the core that runs first at the same position, and continue to run backwards until all cores that need to be synchronized have run to this position; cores 1-7 of C6678 cannot be started in the IBL stage, and can only be awakened by core 0 after the program is loaded. Figure 2 As shown, after the program is loaded, the program starts running. After all cores of C6678 are driven, multi-core synchronization processing is performed in the program. The specific method of multi-core synchronization processing is:

[0024] Step S310, define an array counter_instance in the chip external memory DDR, the values ​​in the array are randomly given by power-on initialization and can be accessed by all cores;

[0025] Step S320, each core copies the initial value in counter_instance to its own array on_entry. The on_entry array is stored in a private memory and can only be accessed by the core itself. At the same time, an array element in counter_instance is allocated to each core.

[0026] Step S330, the program enters a loop process, each loop adds 1 to the array element value assigned to the core, and compares whether the other element values ​​in the array are consistent with the corresponding array element value of on_entry in the core. If they are consistent, the next loop is performed, and if they are inconsistent, the next step is executed;

[0027] Step S340, exit the loop.

[0028] By newly defining an array and then comparing the values ​​of the array elements corresponding to the array to see if they are consistent, it is determined whether the cores are at the same time node and run at the same position. The determination is convenient and accurate.

[0029] Step S400, starting counting of other cores;

[0030] After the multi-core synchronization processing in step S300, the programs of all cores run to the same position at the same time node, record the values ​​of the counting timers TSCH and TSCL of core 0, combine them into a 64-bit time count t0, clear the registers TSCH and TSCL of other cores, start the counting timer, and at this time, the counts of other cores differ from those of core 0 by a fixed time difference t0. Through this fixed time difference, the position of core 0 and other cores at any fixed time node can be accurately determined.

[0031] Step S500: record event information that needs to be tracked in the system.

[0032] When you need to track an event on a core on the C6678, call the following two functions to record the relevant information of the event, including the start and end time of the event, the slice number and core number in the system, the running position in the program, etc.

[0033] INT32 lh_trace_func_entry(INT32 color,VOID*inter_func)

[0034] INT32 lh_trace_func_exit(INT32 color,VOID*inter_func)

[0035] Step S600, after event tracking, all tracking events are displayed graphically on the same time axis.

[0036] After obtaining the information of all tracking events in the system, the recorded events outside core 0 in each DSP are calibrated. The calibration method is to add the start and end events of the event to the time t0 recorded by this DSP in step S400 as the calibrated event tracking time; on the same timeline, the events that need to be tracked are displayed in a graphical manner, and finally the purpose of synchronizing the tracking of all events in the system is achieved.

[0037] Graphically display event tracking such as Figure 3 As shown in the figure, it can be seen that:

[0038] Inside DSP0, event 1 (Fun1) in core 1 to core 4 is aligned, and they are simultaneously controlled by event 1 in core 0. Event 1 is aligned in timing. Inside DSP1, event 1 (Fun1) in core 1 to core 4 is time-sharingly controlled by event 1 in core 0, and they are also time-sharingly synchronized.

[0039] Between DSP0 and DSP1, event 0 (Fun0) of DSP1 is controlled by event 0 of DSP0. There is an obvious timing alignment between these two events and they are synchronized on the system timeline.

[0040] In summary, all event tracking in the system can be synchronized and displayed graphically on the same timeline, whether within a DSP or between DSPs.

[0041] The advantages of the present invention are as follows:

[0042] 1. Small footprint. The present invention is a lightweight design with minimal system overhead and is easy to implement. It will not have any additional impact on the existing system software programs and timing.

[0043] 2. Wide applicability. The present invention is applicable to C6678 distributed systems with any number and any complex network architecture, and it does not need to consider what loading method C6678 adopts;

[0044] 3. Easy to use. The event tracking header synchronization implemented by the present invention is easy to use and does not require adding too much additional code to the program. It is convenient for software developers to perform system-level software program timing debugging and observation, which can save a lot of development time for R&D personnel.

[0045] 4. Widely applicable fields. Distributed systems based on C6678 are widely used in signal and information processing fields with high computing requirements, such as aviation, aerospace, shipping, communications, software radio, artificial intelligence and other fields. This application is also applicable.

[0046] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. An event tracking synchronization method based on TMS320C6678 distributed system, characterized in that: include, System power-on initialization; Start the core 0 count timer at the initial node of power-on to complete the system time synchronization of core 0; Start all cores except core 0, and block the core that runs first at the same position until all cores that need to be synchronized have run to this position, and then all cores continue to run backwards; Start other core counts; Record the event information that needs to be tracked in the system; The specific method to determine all cores that need to be synchronized is, Define an array counter_instance in the chip's external memory DDR. The values ​​in the array are randomly given by power-on initialization and can be accessed by all cores. Each core copies the initial value in counter_instance to its own array on_entry. The on_entry array is stored in private memory and can only be accessed by the core itself. At the same time, each core is allocated an array element in counter_instance. The program enters a loop process. Each time the loop increases the value of the array element assigned to the core by 1, and compares the values ​​of other elements in the array to see if they are consistent with the corresponding array element values ​​of on_entry in the core. If they are consistent, the next loop is performed. If not, the next step is executed. Exit the loop; After multi-core synchronization, the values ​​of the counting timers TSCH and TSCL of core 0 are recorded and combined into a 64-bit time counter t0. The counting timers TSCH and TSCL of other cores except core 0 are cleared and the counting timers are started. The system time difference between the cores inside the DSP is calibrated through t0.

2. The event tracking synchronization method based on the TMS320C6678 distributed system as claimed in claim 1, characterized in that: After event tracking, information of all tracking events in the system is obtained, and the start and end times of the events are added with a fixed time difference t0, which is used as the calibrated event tracking event; all tracking events are displayed graphically on the same timeline.

3. The event tracking synchronization method based on the TMS320C6678 distributed system as claimed in claim 1, characterized in that: The system time synchronization method of core 0 is to start BootLoader at power-on, initialize the second-level IBL after running the first-level program, clear the core count timer at the IBL stage, and start the system count timer of core 0.

4. The event tracking and synchronization method based on the TMS320C6678 distributed system as claimed in claim 1, characterized in that: The event information that needs to be tracked includes the start and end time of the event, the slice number and core number in the system, and the running position in the program.

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