Semiconductor device and method of manufacturing the same, memory, electronic device

Abstract

The present disclosure provides a semiconductor device and a manufacturing method thereof, a memory, and an electronic device. The device includes a stacked metal layer, an air gap, and a first spacer, etc. The air gap is arranged along the side surface of the stacked metal layer to surround the stacked metal layer. The first spacer is arranged along the side surface of the air gap to surround the air gap. A dynamic random access memory includes the semiconductor device of the present disclosure. The electronic device includes the dynamic random access memory of the present disclosure. The manufacturing method includes: forming a groove on the stacked metal layer by etching, sequentially forming a second spacer and a first spacer on the sidewall of the groove, the second spacer being between the stacked metal layer and the first spacer; and removing the second spacer to form an air gap between the stacked metal layer and the first spacer. The technical solution provided by the present disclosure can process an air gap beside the stacked metal layer, thereby effectively improving the problem of poor performance of a chip such as a memory caused by parasitic resistance and parasitic capacitance.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor device technology, and more specifically, to semiconductor devices and their manufacturing methods, memory, and electronic devices. Background Technology

[0002] To improve the characteristics of Dynamic Random Access Memory (DRAM), it is often necessary to reduce parasitic resistance and capacitance. Current techniques include using copper instead of aluminum as the constituent material of the conductive lines to reduce latency through copper interconnects, or using low-k oxide materials as insulating materials. However, these methods still result in limited reductions in parasitic resistance and capacitance, making it difficult to meet practical application requirements. Therefore, the use of air gaps as insulating films has been proposed. However, due to limitations in conventional techniques, fabricating air gaps and semiconductor device structures that meet design requirements is very difficult. For example, the dimensions of stacked metal layers at different locations are often different, making it difficult to create air gaps of the same shape at different locations using conventional techniques. Summary of the Invention

[0003] To address the challenges of using conventional technologies to fabricate air gaps and semiconductor device structures that meet design requirements and to achieve practical application needs, this disclosure innovatively provides a semiconductor device, its manufacturing method, a memory, and an electronic device.

[0004] To achieve the above-mentioned technical objectives, this disclosure provides a semiconductor device. The semiconductor device includes, but is not limited to, a semiconductor substrate, at least one stacked metal layer, an air gap, and a first spacer. The stacked metal layer is disposed above the semiconductor substrate. The air gap is disposed along the side of the stacked metal layer to surround the stacked metal layer. The first spacer is disposed along the side of the air gap to surround the air gap. The air gap is located between the stacked metal layer and the first spacer.

[0005] To achieve the above-mentioned technical objectives, this disclosure also provides a dynamic random access memory, which includes the semiconductor device in any embodiment of this disclosure.

[0006] To achieve the above-mentioned technical objectives, this disclosure also provides an electronic device that includes the dynamic random access memory in any embodiment of this disclosure.

[0007] To achieve the above-mentioned technical objectives, this disclosure provides a method for manufacturing a semiconductor device. The method includes, but is not limited to, the following steps: forming an intermetallic dielectric layer and a stacked metal layer sequentially on a semiconductor substrate; forming a groove on the stacked metal layer by etching to expose the intermetallic dielectric layer; sequentially forming a second spacer and a first spacer on the sidewall of the groove, the second spacer being located between the stacked metal layer and the first spacer; and removing the second spacer to form an air gap between the stacked metal layer and the first spacer.

[0008] The beneficial effects of this disclosure are as follows: Compared with the prior art, the technical solution provided by this disclosure can process an air gap with a certain shape and thickness next to the stacked metal layer, so as to effectively improve the problem of deterioration of chip performance such as dynamic random access memory caused by parasitic resistance and parasitic capacitance.

[0009] This disclosure enables the fabrication of the required air gap structure without the need for complex processes, meeting the practical application needs of various scenarios. It has outstanding advantages such as low semiconductor device processing cost, short process cycle, and suitability for large-scale promotion and application. Attached Figure Description

[0010] Figure 1 A schematic diagram of the longitudinal cross-sectional structure of a semiconductor device after grooves have been etched into the current stacked metal layers is shown.

[0011] Figure 2 A schematic diagram of the longitudinal cross-sectional structure of a semiconductor device after a second spacer is formed on the inner wall of the groove is shown.

[0012] Figure 3 A schematic diagram of the longitudinal cross-sectional structure of a semiconductor device after the first spacer is formed on the sidewall of the second spacer is shown.

[0013] Figure 4 A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device after the intermetallic dielectric layer has been re-deposited is shown.

[0014] Figure 5 A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device after etching the intermetallic dielectric layer and removing the second spacer is shown.

[0015] Figure 6 It shows in Figure 5 A schematic diagram of the longitudinal cross-sectional structure of a semiconductor device after a stop layer has been deposited over the entire device layer.

[0016] In the picture,

[0017] 100. Semiconductor substrate.

[0018] 200. Stacked metal layers.

[0019] 300, air gap; 301, second spacer.

[0020] 400. First spacer.

[0021] 500, intermetallic dielectric layer; 5000, groove.

[0022] 600, lower barrier layer; 601, upper barrier layer.

[0023] 700, Lower Stop Layer; 701, Upper Stop Layer.

[0024] 800, Electrode. Detailed Implementation

[0025] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0026] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0027] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0028] One or more embodiments of this disclosure provide a method for manufacturing a semiconductor device, which can create an air gap structure with a certain shape and thickness that meets design requirements next to a stacked metal layer, so as to utilize the air gap as an insulating film and improve chip performance. This method includes, but is not limited to, the following steps.

[0029] like Figure 1As shown, a semiconductor substrate 100 is provided. A lower stop layer 700, an inter-metal dielectric (IMD) layer 500, an electrode 800, a lower barrier layer 600, a stacked metal layer 200, and an upper barrier layer 601 can be sequentially formed on the semiconductor substrate 100, as detailed below. In some embodiments of this disclosure, a lower stop layer 700 is first deposited above the semiconductor substrate 100, and an inter-metal dielectric layer 500 is deposited on the lower stop layer 700. Then, an electrode 800 is formed on the inter-metal dielectric layer 500, and the electrode 800 can extend longitudinally through the inter-metal dielectric layer 500 and the lower stop layer 700. In some embodiments of this disclosure, the electrode 800 can be formed by photolithography, etching, metal plating, or sputtering, etc. These are mature processes and will not be described in detail here. A lower barrier layer 600, a stacked metal layer 200, and an upper barrier layer 601 are then formed sequentially. For example, the stacked metal layer 200 can be formed by sputtering. The stacked metal layer 200 is electrically connected to the electrode 800 and can serve as a conductive line for the semiconductor device. Both the lower barrier layer 600 and the upper barrier layer 601 are used to prevent metal from diffusing into other device layers (e.g., the intermetallic dielectric layer 500) and improve the reliability of the semiconductor device. The formation of the stacked metal layer 200 may include a chemical mechanical polishing (CMP) step, thereby making the upper surface of the stacked metal layer flush with the upper surfaces of other device layers in the same layer. After the above steps, this disclosure enables the sequential formation of the intermetallic dielectric layer 500 and the stacked metal layer 200 above the semiconductor substrate 100. Next, a groove 5000 is formed on the stacked metal layer 200 by etching, exposing the underlying intermetallic dielectric layer 500. In this embodiment, the groove 5000 may have a certain depth within the intermetallic dielectric layer 500.

[0030] like Figure 2 As shown, a second spacer 301 can be formed on the inner sidewall of the groove 5000. The thickness and shape of the second spacer 301 can be reasonably set according to the design requirements of the semiconductor device. The second spacer 301 occupies the space required by the subsequent air gap 300, so it plays a crucial role in determining the shape and thickness of the air gap 300. In some embodiments of this disclosure, the second spacer 301 can be formed along the sidewall of the groove 5000 through a sidewall fabrication process. Figure 2 The diagram shown is a longitudinal cross-sectional view of a semiconductor device. In fact, the second spacer 301 can be formed into a closed pattern on a plane, or it can be an open pattern. The specific process of the sidewall fabrication will not be described in detail in this embodiment. The second spacer 301 needs to be removed in subsequent processes; therefore, in some embodiments of this disclosure, the second spacer 301 can be, for example, an oxide, such as silicon oxide.

[0031] like Figure 3 As shown, the first spacer 400 can be formed after the second spacer 301 is formed. For example, the first spacer 400 with a certain thickness and shape can be formed along the inner sidewall of the second spacer 301 through a sidewall process. The specific shape and thickness of the first spacer 400 in some embodiments of this disclosure can be reasonably set according to the actual situation. Therefore, this disclosure can realize the sequential formation of the second spacer 301 and the first spacer 400 on the sidewall of the groove 5000 between metals, with the second spacer 301 located between the stacked metal layer 200 and the first spacer 400. The specific process of the sidewall process will not be described in detail in this embodiment.

[0032] like Figure 4 As shown, an intermetallic dielectric layer 500 is deposited again. In some embodiments of this disclosure, after the second spacer 301 and the first spacer 400 are formed sequentially, the following steps are further included: depositing one or more layers of intermetallic dielectric layer 500, and then performing chemical mechanical polishing on the deposited intermetallic dielectric layer 500 so that the polished intermetallic dielectric layer 500 is flush with the upper barrier layer 601.

[0033] like Figure 5 As shown, the re-deposited intermetallic dielectric layer 500 is etched to expose the second spacer 301 to be removed. The second spacer 301 can then be removed by dry etching or wet etching, thereby forming an air gap 300 with a predetermined shape and thickness between the stacked metal layer 200 and the first spacer 400, thus forming the semiconductor device structure in some embodiments of this disclosure. The semiconductor device provided by this disclosure includes an insulating film disposed beside the stacked metal layer 200 and composed of the air gap 300. Therefore, the technical solution provided by this disclosure can easily manufacture an air gap 300 with a certain thickness and shape by setting and removing the second spacer 301, thereby meeting the design requirements of semiconductor devices in different application scenarios. Therefore, this disclosure can utilize the fabricated air gap 300 as an insulating film to effectively improve problems such as degraded dynamic random access memory performance caused by parasitic capacitance and parasitic resistance. It should be understood that although only one stacked metal layer 200 is shown in the accompanying drawings, the technical solution of this disclosure can obviously be used in multi-layer stacked metal layer 200 structures with two or more layers.

[0034] like Figure 6 As shown, to facilitate subsequent semiconductor device fabrication processes (e.g., providing etching stop positions for the upper device layer), some embodiments of this disclosure further include the step of depositing one or more upper stop layers 701 above the intermetallic dielectric layer 500 after forming the air gap 300. Specifically, this includes... Figure 5A stop layer 701 is deposited over the entire device layer, thereby forming the semiconductor device in some other embodiments of this disclosure. Therefore, the manufacturing method provided in this disclosure can be used as a sub-process of the chip fabrication process. The material of the stop layer 701 may include, but is not limited to, silicon nitride.

[0035] like Figure 5 and 6 As shown, based on the same inventive concept as the semiconductor device manufacturing method, one or more embodiments of this disclosure can also provide a semiconductor device. A corresponding semiconductor device product can be fabricated through one or more embodiments of the manufacturing method. The semiconductor device includes, but is not limited to, a semiconductor substrate 100, a stacked metal layer 200, an air gap 300, a first spacer 400, an intermetallic dielectric layer 500, an upper barrier layer 601, a lower barrier layer 600, an upper stop layer 701, a lower stop layer 700, and electrodes 800, etc.

[0036] The semiconductor substrate 100 is, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate, on which multiple memory cells can be formed. A lower stop layer 700, an intermetallic dielectric layer 500, a lower barrier layer 600, a stacked metal layer 200, and an upper barrier layer 601 are disposed on the semiconductor substrate 100.

[0037] The stacked metal layer 200 is at least one layer and can be used to form part of the conductive lines of devices such as dynamic random access memory. In some embodiments of this disclosure, at least one stacked metal layer 200 may be disposed above the semiconductor substrate 100. The material of each stacked metal layer 200 may be aluminum and / or copper.

[0038] like Figure 5 and 6 As shown, the air gap 300 is disposed along the side of the stacked metal layer 200, thereby surrounding the stacked metal layer 200 circumferentially. In some embodiments of this disclosure, the air gap 300 can be understood as a cavity without solid material, the interior of which may be filled with a gaseous medium. The dielectric constant of this gaseous medium can be lower than that of silicon oxide. In some embodiments of this disclosure, the dielectric constant of the gaseous medium can be less than 2.8, for example, it can be close to 1. The gaseous medium can be, for example, air, which has good insulating properties. Of course, in some embodiments of this disclosure, the air gap 300 may also contain two or more gaseous media. The air gap 300 in the embodiments of this disclosure can be disposed on the side of one or more stacked metal layers 200, thereby achieving the purpose of providing an insulating film with a small dielectric constant next to the stacked metal layer 200, significantly improving the performance of semiconductor devices and solving the parasitic capacitance and parasitic resistance problems existing in conventional technologies.

[0039] like Figure 5 and 6As shown, the first spacer 400 is disposed along the side of the air gap 300, and the first spacer 400 surrounds the air gap 300 in the circumferential direction. The air gap 300 is located between the stacked metal layer 200 and the first spacer 400. The shape and thickness of the first spacer 400 are set according to the actual situation.

[0040] An upper barrier layer 601 is formed on the upper surface of the stacked metal layer 200. In the longitudinal section direction, the upper barrier layer 601, the lower barrier layer 600, and the surrounding air gap 300 completely surround each portion of the stacked metal layer 200. The upper barrier layer 601 can be made of at least one of titanium nitride (TiN), tungsten nitride (WN), and tantalum nitride (TaN). The lower barrier layer 600 is formed on the lower surface of the stacked metal layer 200, and the lower barrier layer 600 can be made of at least one of titanium nitride (TiN), tungsten nitride (WN), and tantalum nitride (TaN). Both the lower barrier layer 600 and the upper barrier layer 601 are used to prevent metal in the stacked metal layer 200 from diffusing to other layers, thereby improving the reliability of the semiconductor device operation.

[0041] An intermetallic dielectric layer 500 is disposed above the semiconductor substrate 100 and distributed below the lower barrier layer 600. In some embodiments of this disclosure, the intermetallic dielectric layer 500 further fills the groove 5000 formed by the first spacer 400, and can thus be distributed between the lower stop layer 700 and the upper stop layer 701. In some embodiments of this disclosure, both the first spacer 400 and the air gap 300 extend downward into the intermetallic dielectric layer 500.

[0042] A lower stop layer 700 is disposed above the semiconductor substrate 100, between the intermetallic dielectric layer 500 and the semiconductor substrate 100. The material of the lower stop layer 700 includes, but is not limited to, silicon nitride, silicon oxide nitride, and / or silicon carbon nitride (SiCN). An upper stop layer 701 is deposited on the upper surface of the upper barrier layer 601. The material of the upper stop layer 701 may also include, but is not limited to, silicon nitride, silicon oxide nitride, and / or silicon carbon nitride (SiCN).

[0043] Electrode 800 extends longitudinally through lower stop layer 700 and intermetallic dielectric layer 500, and is electrically connected to stacked metal layer 200 (not shown in the figure). Both electrode 800 and stacked metal layer 200 can be used to form conductive lines, wherein the material of electrode 800 includes, but is not limited to, tungsten.

[0044] Some embodiments of this disclosure may provide a dynamic random access memory, which may include the semiconductor device of any embodiment of this disclosure.

[0045] This disclosure also provides an electronic device that may include the dynamic random access memory (DRAM) in any embodiment of this disclosure. This electronic device includes, but is not limited to, smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, and power banks.

[0046] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0047] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor substrate; At least one stacked metal layer is disposed above the semiconductor substrate; An air gap is provided along the side of the stacked metal layer to surround the stacked metal layer; A first spacer is disposed along the side of the air gap to surround the air gap; The air gap is located between the stacked metal layers and the first spacer. Also includes: An intermetallic dielectric layer is disposed above the semiconductor substrate and fills the groove formed by the first spacer; Also includes: A lower barrier layer is formed on the lower surface of the stacked metal layers; An upper barrier layer is formed on the upper surface of the stacked metal layers; An upper stop layer is deposited on the upper surface of the upper barrier layer.

2. The semiconductor device according to claim 1, characterized in that, The intermetallic dielectric layer is also distributed below the lower barrier layer; the first spacer and the air gap both extend downward into the intermetallic dielectric layer.

3. The semiconductor device according to claim 2, characterized in that, Also includes: A lower stop layer is disposed above the semiconductor substrate and between the intermetallic dielectric layer and the semiconductor substrate; The electrode extends longitudinally through the lower stop layer and the intermetallic dielectric layer, and is electrically connected to the stacked metal layers.

4. A dynamic random access memory, characterized in that, Includes the semiconductor device as described in any one of claims 1 to 3.

5. An electronic device, characterized in that, Includes the dynamic random access memory as described in claim 4.

6. The electronic device according to claim 5, characterized in that, This includes smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, and power banks.

7. A method for manufacturing a semiconductor device, characterized in that, For fabricating the semiconductor device as described in any one of claims 1 to 3, comprising: An intermetallic dielectric layer and a stacked metal layer are formed sequentially on top of a semiconductor substrate; A groove is formed on the stacked metal layers by etching, exposing the intermetallic dielectric layer; A second spacer and a first spacer are sequentially formed on the sidewall of the groove, with the second spacer positioned between the stacked metal layer and the first spacer; After the second spacer and the first spacer are formed sequentially, the process further includes: Deposit another intermetallic dielectric layer; The deposited intermetallic dielectric layer was subjected to chemical mechanical polishing. The re-deposited intermetallic dielectric layer is etched to expose the second spacer to be removed; Remove the second spacer to form an air gap between the stacked metal layers and the first spacer; After the air gap is formed, it also includes: A stop layer is deposited on top of the intermetallic dielectric layer.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The steps of forming an intermetallic dielectric layer and a stacked metal layer sequentially on top of a semiconductor substrate include: A stop layer is deposited above the semiconductor substrate; Deposit the intermetallic dielectric layer on the lower stop layer; An electrode is formed on the intermetallic dielectric layer, the electrode extending longitudinally through the intermetallic dielectric layer and the lower stop layer; A lower barrier layer, a stacked metal layer, and an upper barrier layer are formed sequentially, and the stacked metal layer is electrically connected to the electrode.

9. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The steps of forming the second spacer and the first spacer include: The second spacer is formed along the sidewall of the groove through a sidewall process; The first spacer is formed along the inner sidewall of the second spacer through a sidewall process.

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