Methods of forming microelectronic devices and related microelectronic devices, memory devices, and electronic systems

Abstract

A method of forming a microelectronic device includes forming a sacrificial material over a base structure. Portions of the sacrificial material are replaced with an etch-resistant material. A stack structure is formed over the etch-resistant material and a remaining portion of the sacrificial material. The stack structure includes a vertically alternating sequence of insulative material and further sacrificial material arranged in layers and at least one stair structure horizontally overlapping the etch-resistant material and having a step including a horizontal end of the layers. A slot is formed vertically extending through the stack structure and the remaining portion of the sacrificial material. After forming the slot, the sacrificial material and the further sacrificial material are selectively replaced with a conductive material to form, respectively, a lateral contact structure and a conductive structure.

Description

[0001] Priority Statement

[0002] This application claims priority to U.S. Patent Application Serial No. 17 / 012,741, filed September 4, 2020, for “METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS”. Technical Field

[0003] In its various embodiments, this disclosure generally relates to the field of microelectronic device design and fabrication. More specifically, this disclosure relates to methods of forming microelectronic devices, and to related microelectronic devices, memory devices, and electronic systems. Background Technology

[0004] A continuous goal of the microelectronics industry is to increase the memory density (e.g., the number of memory cells per memory die) of memory devices such as non-volatile memory devices (e.g., compared to non-flash memory devices). One way to increase memory density in non-volatile memory devices is to utilize vertical memory array (also known as “three-dimensional (3D) memory array”) architectures. Conventional vertical memory arrays comprise memory strings extending through one or more stacked structures, each of which individually comprises layers of conductive and insulating structures. Each memory string may contain at least one selection device that is series-coupled to a series combination of vertically stacked memory cells. Compared to structures with a conventional planar (e.g., two-dimensional) transistor arrangement, such a configuration allows a greater number of switching devices (e.g., transistors) to be positioned in units of die area (e.g., the length and width of the active surface consumed) by building the array upwards (e.g., vertically) on the die.

[0005] Vertical memory array architectures typically include electrical connections between layered conductive structures and conductive routing structures within a stacked structure of memory devices, allowing memory cells in the vertical memory array to be uniquely selected for write, read, or erase operations. One method of forming such electrical connections involves forming so-called “steps” (or “staircases”) at the edges (e.g., horizontal ends) of the stacked structure of the memory devices. These step structures include individual “steps” defining contact areas of conductive structures, on which conductive contact structures can be positioned to provide electrical access to the conductive structures.

[0006] Unfortunately, as feature packing density increases and the margin for formation errors decreases, conventional methods for forming memory devices (e.g., 3D and non-flash memory devices) have led to undesirable damage that can degrade the desired performance, reliability, and durability of the memory devices. For example, conventional methods for forming stacked structures of memory devices (e.g., 3D and non-flash memory devices) using so-called “replacement gate” or “gate-last” processes, where a sacrificial structure of the initial stack is at least partially replaced by a conductive structure, can generate undesirable deformations (e.g., delamination bending, delamination warping, delamination flexing) and / or undesirable damages (e.g., delamination cracking, delamination collapse) near the step structures within the initial stack. Such deformations and / or damage can result in undesirable defects, undesirable reliability, and / or undesirable durability in memory devices comprising stacked structures formed by such conventional methods. Summary of the Invention

[0007] In some embodiments, a method of forming a microelectronic device includes forming a sacrificial material over a substrate structure. A portion of the sacrificial material is replaced with an etch-resistant material. A stacked structure is formed over the etch-resistant material and the remaining portion of the sacrificial material. The stacked structure includes a vertically alternating sequence of layered insulating material and additional sacrificial material, and at least one stepped structure that horizontally overlaps the etch-resistant material and has steps including horizontal ends of the layers. A groove is formed extending vertically through the stacked structure and the remaining portion of the sacrificial material. After forming the groove, the sacrificial material and the additional sacrificial material are selectively replaced with a conductive material to form a lateral contact structure and a conductive structure, respectively.

[0008] In another embodiment, a microelectronic device includes blocks, an etch-resistant material, lateral contact structures, and additional conductive structures. Each block has a vertically alternating sequence of layered conductive and insulating structures. Each block includes a stepped structure with steps including horizontal ends of the layers. The etch-resistant material is vertically located below each block and within the horizontal boundary of the stepped structure of each block. The lateral contact structures are vertically located below each block and outside the horizontal boundary of the stepped structure. The lateral contact structures are horizontally adjacent to the etch-resistant material and located at substantially the same vertical position as the etch-resistant material. The additional conductive structures are vertically located below the lateral contact structures and electrically connected to the lateral contact structures.

[0009] In another embodiment, a memory device includes a stacked structure, a stepped structure, an etch-resistant material, additional conductive structures, vertically extending strings of memory cells, and a substrate structure. The stacked structure includes blocks, each block having layers, each layer including conductive structures and insulating structures vertically adjacent to the conductive structures. The stepped structures are located within contact regions of each block of the stacked structure and have steps including the edges of the layers of the blocks. The etch-resistant material is vertically located below the stacked structure and within the horizontal boundaries of the contact regions of each block of the stacked structure. The additional conductive structures are vertically located below the stacked structure and within the horizontal boundaries of the memory array regions of each block of the stacked structure. The additional conductive structures are horizontally adjacent to the etch-resistant material and located at substantially the same vertical position as the etch-resistant material. The vertically extending strings of memory cells are located within the memory array regions of each block of the stacked structure and coupled to the additional conductive structures. The substrate structure is vertically located below the stacked structure and includes a control logic circuitry coupled to the vertically extending strings of memory cells.

[0010] In yet another embodiment, an electronic system includes an input device, an output device, a processor device operatively connected to the input device and the output device, and a memory device operatively connected to the processor device. The memory device includes blocks, memory cell strings, digital line structures, etch-resistant materials, lateral contact structures, at least one source structure, and a substrate structure. Each block has a vertically alternating sequence of layered conductive and insulating structures. Each block includes a stepped structure having steps at horizontal ends comprising the layers of the block. The memory cell strings extend vertically through the blocks. The digital line structures are vertically located above the blocks and coupled to the memory cell strings. The etch-resistant materials are vertically located below each block and within the horizontal boundaries of the stepped structures of each block. The lateral contact structures are vertically located below each block and outside the horizontal boundaries of the stepped structures of each block. Each lateral contact structure is coupled to some memory cells in the memory cell string and is directly and horizontally adjacent to some of the etch-resistant materials. The at least one source structure is vertically located below and coupled to the lateral contact structure. The substrate structure is vertically located below the at least one source structure and includes control logic devices coupled to the conductive structure, the digital line structure, and the at least one source structure of the block. Attached Figure Description

[0011] Figures 1A to 5B This is a simplified partial cross-sectional view illustrating a method of forming a microelectronic device according to embodiments of the present disclosure. Figure 1A , 2A 3A, 4A and 5A) and simplified partial top view ( Figure 1B , 2B (3B, 4B and 5B).

[0012] Figure 6 This is a simplified partial cross-sectional perspective view of a microelectronic device according to an embodiment of the present disclosure.

[0013] Figure 7 This is a schematic block diagram of an electronic system according to an embodiment of the present disclosure. Detailed Implementation

[0014] The following description provides specific details, such as material composition, shape, and size, to provide a comprehensive description of embodiments of this disclosure. However, those skilled in the art will understand that embodiments of this disclosure can be practiced without these specific details. In fact, embodiments of this disclosure can be practiced in conjunction with conventional microelectronic device manufacturing techniques used in the industry. Furthermore, the description provided below does not form a complete process flow for manufacturing microelectronic devices (e.g., memory devices, such as 3D NAND devices). The structures described below do not form a complete microelectronic device. Only those process actions and structures necessary for understanding embodiments of this disclosure are described in detail below. Additional actions to form a complete microelectronic device from the structures can be performed using conventional manufacturing techniques.

[0015] The accompanying drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device, or system. Variations in the shapes depicted in the drawings should be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas shown, but rather include shape deviations resulting from, for example, manufacturing processes. For example, areas shown or described as box-shaped may have coarse and / or non-linear characteristics, and areas shown or described as circular may contain some coarse and / or linear characteristics. Furthermore, acute angles shown may be rounded, and vice versa. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the precise shape of the areas and do not limit the scope of the claims of the invention. The drawings are not necessarily drawn to scale. Additionally, common elements between the drawings may retain the same numerical designations.

[0016] As used herein, “memory device” means and includes, but is not limited to, microelectronic devices that exhibit memory functionality but are not limited to it. In other words, and by way of non-limiting examples only, the term “memory device” includes not only conventional memory (e.g., conventional volatile memory, such as conventional DRAM; conventional non-volatile memory, such as conventional and non-volatile memory), but also application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), microelectronic devices combining logic and memory, and graphics processing units (GPUs) incorporating memory.

[0017] As used herein, the term “configured” refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device that facilitates the operation of one or more of said structures and devices in a predetermined manner.

[0018] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” are referenced to the principal plane of the structure and are not necessarily limited by the Earth’s gravitational field. A “horizontal” or “lateral” direction is a direction substantially parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is a direction substantially perpendicular to the principal plane of the structure. The principal plane of the structure is defined by structural surfaces having a relatively large area compared to the other surfaces of the structure. Referring to the accompanying drawings, a “horizontal” or “lateral” direction may be perpendicular to the indicated “Z” axis and may be parallel to the indicated “X” axis and / or parallel to the indicated “Y” axis; and a “vertical” or “longitudinal” direction may be parallel to the indicated “Z” axis, perpendicular to the indicated “X” axis, and perpendicular to the indicated “Y” axis.

[0019] As used herein, features described as “adjacent” to each other (e.g., regions, structures, devices) refer to and include features of one or more disclosed identities that are positioned closest to each other (e.g., closest). Additional features (e.g., additional regions, additional structures, additional devices) that do not match the disclosed identities of the “adjacent” features may be positioned between the “adjacent” features. In other words, “adjacent” features may be positioned directly adjacent to each other such that no other features intervene between the “adjacent” features; or “adjacent” features may be positioned indirectly adjacent to each other such that at least one feature having an identity other than the identity associated with at least one “adjacent” feature is positioned between the “adjacent” features. Therefore, features described as “vertically adjacent” to each other refer to and include features of one or more disclosed identities that are positioned closest to each other (e.g., most vertically adjacent). Furthermore, features described as “horizontally adjacent” to each other refer to and include features of one or more disclosed identities that are positioned closest to each other (e.g., most horizontally adjacent).

[0020] As used herein, for ease of description, spatially relative terms such as “below,” “under,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “back,” “left,” and “right” may be used to describe the relationship between one element or feature as shown in the accompanying drawings and one or more other elements or features. Unless otherwise specified, spatially relative terms are intended to encompass different orientations in addition to the material orientation depicted in the accompanying drawings. For example, if the material in the accompanying drawings is inverted, it is described as an element located “below,” “under,” “below,” or “bottom” of other elements or features, and then its orientation is described as located “above” or “top” of said other elements or features. Thus, depending on the context in which the term is used, the term “below” can encompass both upper and lower orientations, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped) and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0021] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” are intended to also include the plural forms.

[0022] As used in this article, "and / or" includes any and all combinations of one or more of the associated enumerated items.

[0023] As used herein, the phrase “coupled to” refers to structures that are operatively connected to each other, such as by direct ohmic connection or by indirect connection (e.g., by means of another structure) electrical connection.

[0024] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and is included in the extent to which a given parameter, property, or condition is satisfied given a degree of variation (such as variation within acceptable tolerances). For example, depending on whether a particular parameter, property, or condition is substantially satisfied, it may be satisfied at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0025] As used herein, “about” or “approximately” with respect to a particular parameter includes the value and will be understood by one of ordinary skill in the art as a degree of difference relative to the value within acceptable tolerances of the particular parameter. For example, “about” or “approximately” with respect to a value may include additional values ​​that are in the range of 90.0% to 110.0% of the value, such as 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0026] As used herein, “conductive material” means and includes one or more of the following conductive materials: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), alloys (e.g., Co-based alloys). This includes Fe-based alloys, Ni-based alloys, Fe-Ni-based alloys, Co-Ni-based alloys, Fe-Co-based alloys, Co-Ni-Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, low-carbon steel, stainless steel, materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), and conductive doped semiconductor materials (e.g., conductive doped polycrystalline silicon, conductive doped germanium (Ge), conductive doped silicon-germanium (SiGe)). Furthermore, "conductive structure" means and includes structures formed from and containing conductive materials.

[0027] As used herein, “insulating material” means and includes electrically insulating materials, such as one or more of the following: at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phosphorus silicate glass, borosilicate glass, borosilicate-phosphorus silicate glass, fluorosilicate glass, alumina (AlO) x ), Hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y()), at least one dielectric oxide nitride material (e.g., silicon oxynitride (SiO) x N y ()), at least one dielectric carbon oxide material (e.g., silicon oxycarbonate (SiO) x C y ()), and at least one hydrogenated dielectric carbon oxide material (e.g., hydrogenated silicon carbide (SiC) x O y H z and at least one dielectric carbon nitride material (e.g., silicon carbon nitride (SiO2)). x C z N y This text contains one or more of the formulas “x”, “y”, and “z” (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiO x N y SiO x C y SiC x O y H z SiO x C z N y The formula represents a material in which, for each atom of an element (e.g., Si, Al, Hf, Nb, Ti), the average ratio is as follows: "x" atoms of another element, "y" atoms of yet another element, and "z" atoms of yet another element (if any). Since the formula represents relative atomic ratios rather than strict chemical structures, insulating materials can include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if any) can be integers or non-integers. As used herein, the term "non-stoichiometric compound" means and includes compounds whose elemental composition cannot be expressed by a well-defined ratio of natural numbers and violates the law of definite proportions. Additionally, "insulating structure" means and includes structures formed of and containing insulating materials.

[0028] As used herein, the term "uniform" means that the relative amounts of elements contained in a feature (e.g., material, structure) do not change throughout different parts of the feature (e.g., different horizontal parts, different vertical parts). Conversely, as used herein, the term "non-uniform" means that the relative amounts of elements contained in a feature (e.g., material, structure) change throughout different parts of the feature. If a feature is non-uniform, the amounts of one or more elements contained in the feature may change gradually (e.g., abruptly) throughout different parts of the feature, or may change continuously (e.g., gradually, such as linearly, parabolically). The feature may, for example, be formed by and comprise a stack of at least two different materials.

[0029] Unless the context otherwise indicates, the materials described herein can be formed by any suitable technique, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, a person skilled in the art may choose the appropriate technique for depositing or growing the material. Furthermore, unless the context otherwise indicates, the materials described herein can be removed by any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor etching), ion milling, planarization (e.g., chemical mechanical planarization (CMP)), or other known methods.

[0030] Figures 1A to 5B This is a simplified partial cross-sectional view illustrating an embodiment of a method for forming a microelectronic device structure (e.g., a memory device, such as a 3D and non-flash memory device). Figure 1A , 2A 3A, 4A and 5A) and simplified partial top view ( Figure 1B , 2B (3B, 4B, and 5B). From the description provided below, it will be apparent to those skilled in the art that the methods described herein can be used to form a variety of devices. In other words, the methods of this disclosure can be used whenever it is desired to form a microelectronic device.

[0031] Collective Reference Figure 1A and Figure 1B ( Figure 1B Depicting in Figure 1AThe simplified partial top view of the microelectronic device structure 100 at the processing stage shown is illustrated. The microelectronic device structure 100 can be formed to include a substrate structure 108, a source layer 109 above the substrate structure 108, an isolation material 112 above the source layer 109, and a sacrificial material 114 above the isolation material 112. Further details are described below. Figure 1A and Figure 1B The aforementioned features and other features (e.g., other materials, other structures, other devices) of the microelectronic device structure 100 in the processing stage described herein. Figure 1A The view depicted is of the microelectronic device structure 100 surrounding... Figure 1B The simplified partial cross-sectional view of dashed line A1-A1 is shown in the image.

[0032] like Figure 1A and Figure 1B As shown, the microelectronic device structure 100 can be divided into multiple regions in a first horizontal direction (e.g., the X direction). For example, in Figure 1A and Figure 1B In the X direction depicted, the microelectronic device structure 100 may include at least one memory array region 102, at least one stepped region 104 (e.g., at least one access contact region), and at least one intermediate region 106 horizontally interposed (e.g., in the X direction) between the memory array region 102 and the stepped region 104. As described in further detail below, additional features (e.g., additional structures, additional materials, additional devices) that promote the desired functionality and characteristics of the microelectronic device structure may subsequently be formed in the different horizontal regions of the microelectronic device structure 100 (e.g., memory array region 102, stepped region 104, and intermediate region 106).

[0033] like Figure 1B As shown, the microelectronic device structure 100 can be further divided into additional regions in a second horizontal direction (e.g., the Y direction) orthogonal to the first horizontal direction (e.g., the X direction). For example, in Figure 1B In the Y direction depicted, the microelectronic device structure 100 may include a block region 116 and a slot region 118 horizontally surrounding (e.g., in the Y direction and in the X direction) the block region 116. The slot region 118 may be horizontally interposed between horizontally adjacent block regions 116. As described in further detail below, the block region 116 and the slot region 118 may define the area of ​​the block structure and the slot (e.g., slit, trench) formed during subsequent fabrication of the microelectronic device structure 100 to form the microelectronic device.

[0034] exist Figure 1A and Figure 1BIn the diagram, the interfaces between the horizontal boundaries of different horizontal regions of the microelectronic device structure 100 (e.g., memory array region 102, stepped region 104, intermediate region 106, block region 116) are depicted by dashed lines. For clarity and ease of understanding, the following is used: Figure 1A In the diagram, the dashed lines associated with the interfaces between the horizontal boundaries of memory array region 102, stepped region 104, and intermediate region 106 extend only into the sacrificial material 114. However, it should be understood that the different horizontal regions of the microelectronic device structure 100 are not limited to the sacrificial material 114. As described in further detail below, additional features (e.g., additional structures, additional materials, additional devices) may subsequently be formed within the different horizontal regions of the microelectronic device structure 100. Some of these additional features may be formed to be substantially confined by one or more horizontal regions within the different horizontal regions of the microelectronic device structure 100, such that these additional features are formed to be located in at least one but fewer than all of the different horizontal regions of the microelectronic device structure 100. Some other features may be formed to be located in each of the different horizontal regions of the microelectronic device structure 100, such that portions of these other additional features are located in all the different horizontal regions of the microelectronic device structure 100.

[0035] The substrate structure 108 includes the construction of additional features (e.g., materials, structures, devices) on which the microelectronic device structure 100 is formed. The substrate structure 108 may include a semiconductor structure (e.g., a semiconductor wafer) and / or a semiconductor material on or over another structure (e.g., a support structure). The semiconductor material of the substrate structure 108 may, for example, include one or more of silicon, such as monocrystalline silicon and / or polycrystalline silicon (also referred to herein as "polysilicon"); silicon germanium; germanium; gallium arsenide; gallium nitride; gallium phosphide; indium phosphide; indium gallium nitride; and aluminum gallium nitride. The substrate structure 108 may further include one or more additional materials (e.g., conductive materials, insulating materials), structures (e.g., conductive structures, insulating structures), devices (e.g., control logic devices), and / or regions therein. For example, the substrate structure 108 may include a control logic region therein, which contains various transistors and conductive routing structures (e.g., wire structures, conductive contact structures), which together form a control logic circuit system for various control logic devices of the microelectronic device structure 100. In some embodiments, the control logic devices within the substrate structure 108 include complementary metal-oxide-semiconductor (CMOS) circuit systems.

[0036] As described in further detail below, control logic devices within the control logic region of the substrate structure 108 can be configured to control various operations of additional features (e.g., an array of memory cells) subsequently formed within the memory array region 102 of the microelectronic device structure 100. As a non-limiting example, the control logic devices may include one or more (e.g., each) of the following: a charge pump (e.g., V... CCP Charge pump, V NEGWL Charge pumps, DVC2 charge pumps), delay-locked loop (DLL) circuit systems (e.g., ring oscillators), V dd Regulators, string drivers, page buffers, and various chip / stack control circuitry systems. As another non-limiting example, the control logic may include means configured to control column operations of an array (e.g., a memory cell array) formed within the memory array region 102 of the microelectronic device structure 100, such as decoders (e.g., local stack decoders, column decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSA), PMOS sense amplifiers (PSA)), repair circuitry systems (e.g., column repair circuitry systems), I / O devices (e.g., local I / O devices), memory test devices, array multiplexers (MUX), and error checking and correction (ECC) devices (e.g., each). As another non-limiting example, the control logic device may include means configured to control row operations of an array (e.g., a memory cell array) formed within the memory array region 102 of the microelectronic device structure 100, such as a decoder (e.g., a local stack decoder, a row decoder), a driver (e.g., an access line driver, a word line (WL) driver), a repair circuit system (e.g., a row repair circuit system), a memory test device, a MUX, an ECC device, and a self-refresh / wear leveling device (e.g., each of these).

[0037] Source layer 109 may be vertically inserted (e.g., in the Z direction) between substrate structure 108 and sacrificial material 114 located above substrate structure 108. Source layer 109 may include at least one source structure 110. Source layer 109 may also include one or more contact structures 111 (e.g., contact pads) that are horizontally adjacent to and electrically isolated from source structure 110. Figure 1A As shown, at least one dielectric material 107 can be inserted between the source structure 110 and the contact structure 111.

[0038] The source structure 110 and contact structure 111 of the source layer 109 can each be formed of and contain a conductive material. The material composition of the source structure 110 can be substantially the same as that of the contact structure 111. In some embodiments, the source structure 110 and contact structure 111 are formed of and contain a conductive doped semiconductor material, such as one or more conductive doped forms of silicon, such as single-crystal silicon or polycrystalline silicon; silicon-germanium; germanium; gallium arsenide; gallium nitride; and indium phosphide. As a non-limiting example, the source structure 110 and contact structure 111 can be formed of and contain silicon (e.g., polycrystalline silicon) doped with at least one dopant (e.g., at least one n-type dopant, at least one p-type dopant, and at least one or more other dopants). In another embodiment, the source structure 110 and the contact structure 111 may be formed and comprise one or more of metals, alloys, and materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides). As a non-limiting example, the source structure 110 and the contact structure 111 may be formed and comprise W.

[0039] The isolation material 112 located above the source layer 109 may be formed of and contain an insulating material. By way of non-limiting example, the isolation material 112 may be formed of and contain one or more of the following: at least one dielectric oxide material (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of the following), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y ), and at least one dielectric carbon oxide material (e.g., SiO2). x C y ), and at least one hydrogenated dielectric carbon oxide material (e.g., SiC) x O y H z ) and at least one dielectric carbonitride material (e.g., SiO2) x C z N yThe material composition of the insulating material 112 may be substantially the same as that of the dielectric material 107, or the material composition of the insulating material 112 may be different from that of the dielectric material 107. In some embodiments, the insulating material 112 is made of at least one dielectric oxide material (e.g., SiO2). x The insulating material 112 may be formed and comprise at least one dielectric oxide material, such as silicon dioxide (SiO2). The insulating material 112 may be substantially homogeneous or may be non-homogeneous.

[0040] refer to Figure 1A The vertical direct contact structure 113 can be formed to extend vertically through the insulating material 112. The vertical direct contact structure 113 can, for example, be formed to extend vertically (e.g., in the Z direction) from the sacrificial material 114 located above the insulating material 112, through the insulating material 112, and reach the source layer 109. At least some of the vertical direct contact structures 113 contact (e.g., physical contact, electrical contact) the source structure 110 of the source layer 109. As described in further detail below, the vertical direct contact structure 113 can couple the source structure 110 to another structure (e.g., a lateral contact structure) subsequently formed using the sacrificial material 114. The vertical direct contact structures 113 can each be formed of and contain a conductive material. By way of non-limiting example, the vertical direct contact structure 113 can be formed of and contain one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the vertical direct contact structure 113 is formed by W and includes W.

[0041] The sacrificial material 114 may be formed of and comprise at least one material (described in further detail below) that can be selectively removed relative to the insulating material 112 and the insulating structure of the stacked structure to be formed on or above the sacrificial material 114. The material composition of the sacrificial material 114 differs from that of the insulating material 112 and the insulating structure to be formed. The sacrificial material 114 may be selectively etched relative to the insulating material 112 and the insulating structure to be formed during co-exposure to a first etchant; and the insulating material 112 and the insulating structure may be selectively etched relative to the sacrificial material 114 during co-exposure to different second etchants. As used herein, a material is “selectively etchable” relative to another material if the etch rate of one material is at least about five times (5×), such as about ten times (10×), about twenty times (20×), or about forty times (40×) the etch rate of another material.

[0042] As a non-limiting example, the sacrificial material 114 may be formed of and comprise a semiconductor material, such as silicon (e.g., monocrystalline silicon and / or polycrystalline silicon), silicon germanium, germanium, gallium arsenide, gallium nitride, gallium phosphide, indium phosphide, indium gallium nitride, and aluminum gallium nitride, or one or more of these. In some embodiments, the sacrificial material 114 is formed of and comprises polycrystalline silicon.

[0043] As another non-limiting example, the sacrificial material 114 may be formed of and contain an insulating material different from the insulating material 112 and the subsequently formed insulating structure, such as at least one dielectric oxide material (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of the following), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y ), and at least one dielectric carbon oxide material (e.g., SiO2). x C y ), and at least one hydrogenated dielectric carbon oxide material (e.g., SiC) x O y H z ) and at least one dielectric carbonitride material (e.g., SiO2) x C z N y One or more of the following. In some embodiments, such as in the insulating material 112 and the subsequently formed insulating structure, dielectric oxide materials (e.g., SiO2) are included. x In embodiments such as SiO2, the sacrificial material 114 is made of at least one dielectric nitride material (e.g., SiN). y It forms and contains at least one dielectric nitride material, such as Si3N4.

[0044] Next, we will take a group reference. Figure 2A and Figure 2B ( Figure 2B Depicting in Figure 2A(Simplified partial top view of the microelectronic device structure 100 in the shown processing stage) An etch-resistant material 120 may be formed within the sacrificial material 114. During co-exposure to an etchant (e.g., collectively, jointly), the etch-resistant material 120 may be relatively more resistant to removal than the sacrificial material 114. During co-exposure to the etchant, the sacrificial material 114 may be selectively etched relative to the etch-resistant material 120. Figure 2A The view depicted is of the microelectronic device structure 100 surrounding... Figure 2B The simplified partial cross-sectional view of dashed line A1-A1 is shown in the image.

[0045] The etch-resistant material 120 may be formed at least within a horizontal area previously occupied by the sacrificial material 114, the horizontal area corresponding to the intersection (e.g., a horizontal overlap) of the stepped region 104 and the block region 116 of the microelectronic device structure 100. Optionally, the etch-resistant material 120 may also be formed within another horizontal area previously occupied by the sacrificial material 114, the other horizontal area corresponding to the intersection of the stepped region 104 and the trench region 118 of the microelectronic device structure 100. Additionally, optionally, the etch-resistant material 120 may also be formed within another horizontal area previously occupied by the sacrificial material 114, the other horizontal area corresponding to the intersection of the intermediate region 106 and at least the block region 116 (and optionally, the trench region 118) of the microelectronic device structure 100. The etch-resistant material 120 can be omitted from the horizontal area of ​​the sacrificial material 114 corresponding to the intersection of the memory area region 102 of the microelectronic device structure 100 and the block region 116 of the microelectronic device structure 100 (e.g., not formed within said horizontal area). In some embodiments, the etch-resistant material 120 is substantially confined within the horizontal area previously occupied by the intersection of the stepped region 104 and the block region 116 of the microelectronic device structure 100. In other embodiments, the etch-resistant material 120 is substantially confined within the horizontal area previously occupied by the intersection of the stepped region 104 and the block region 116 of the microelectronic device structure 100 and the intersection of the intermediate region 106 and the block region 116 of the microelectronic device structure 100.

[0046] Still for collective reference Figure 2A and Figure 2BIn some embodiments, the etch-resistant material 120 is formed by removing (e.g., etching) a portion of the sacrificial material 114 to form one or more openings (e.g., holes, trenches) within the sacrificial material 114 and then filling the openings with the etch-resistant material 120. The openings may be formed to extend substantially vertically through the sacrificial material 114. For example, the openings may extend vertically to a portion of the insulating material 112 located below the sacrificial material and expose (e.g., expose) that portion. The etch-resistant material 120 may be formed (e.g., deposited) to substantially fill the openings formed in the sacrificial material 114. The upper vertical boundary (e.g., upper surface) of the etch-resistant material 120 may be formed to be substantially coplanar with the upper vertical boundary (e.g., upper surface) of the remaining (e.g., unremoved) portion of the sacrificial material 114.

[0047] If a portion of the sacrificial material 114 is removed to form an opening that is then filled with the etch-resistant material 120, the etch-resistant material 120 may include one or more of the following: insulating materials, conductive materials, and semiconductor materials that have relatively greater etch resistance than the sacrificial material 114 during co-exposure (e.g., collective, joint) to at least one etchant (e.g., phosphoric acid (H3PO4), tetramethylammonium hydroxide (TMAH), or another etchant) employed in subsequent processing of the microelectronic device structure 100. As a non-limiting example, the etch-resistant material 120 may be formed of and contain at least one dielectric material, such as at least one dielectric oxide material, at least one dielectric nitride material, at least one dielectric oxynitride material, at least one dielectric carbon oxide material, at least one hydrogenated dielectric carbon oxide material, and at least one dielectric carbon nitride material. In some embodiments, the etch-resistant material 120 is composed of at least one dielectric oxide material, such as SiO2. x (e.g., SiO2) is formed and comprises the at least one dielectric oxide material. In another embodiment, the etch-resistant material 120 is formed of at least one dielectric nitride material (e.g., SiN) doped with one or more of carbon and oxygen. yThe etch-resistant material 120 may be formed from at least one conductive material and at least one conductive doped semiconductor material (e.g., conductive doped polysilicon, conductive doped Ge, conductive doped silicon SiGe) and may contain the at least one conductive material and the at least one conductive doped semiconductor material. The at least one conductive material may be one or more of at least one metal, at least one alloy, or at least one material containing a conductive metal (e.g., at least one conductive metal nitride, at least one conductive metal silicide, at least one conductive metal carbide, at least one conductive metal oxide). In some embodiments, the etch-resistant material 120 may be formed from one or more of the following and may contain one or more of the following: at least one metal (e.g., one or more of W, Co, and Mo), at least one conductive metal nitride (e.g., WN), and at least one conductive metal nitride (e.g., WN). x and TiN x One or more of the following), at least one conductive metal silicide (e.g., WSi) x and CoSi x One or more of the following) and at least one conductive metal oxide. In another embodiment, the etch-resistant material 120 is formed of polysilicon doped with one or more of the following and includes said polysilicon: at least one p-type dopant (e.g., one or more of boron (B), aluminum (Al), and gallium (Ga)), carbon, nitrogen, and oxygen. The sacrificial material 114 may be substantially homogeneous or may be non-homogeneous.

[0048] In another embodiment, the etch-resistant material 120 is formed by doping a portion of the sacrificial material 114 with at least one dopant (e.g., a chemical species) that alters the etch resistance of the doped portion of the sacrificial material 114 relative to other portions of the sacrificial material 114. The doped portion of the sacrificial material 114 can constitute the etch-resistant material 120. The dopant can be selected at least in part based on the material composition of the sacrificial material 114 to enhance the etch resistance of the doped portion of the sacrificial material 114 forming the etch-resistant material 120 relative to other portions of the sacrificial material 114 that remain undoped during exposure to at least one etchant. As a non-limiting example, if the sacrificial material 114 comprises polysilicon, a portion of the sacrificial material 114 can be doped with at least one p-type dopant (e.g., one or more of B, Al, and Ga), one or more of carbon, nitrogen, and oxygen to form the etch-resistant material 120. For example, the etch-resistant material 120 (e.g., doped polysilicon) may have greater etch resistance to TMAH compared to the remainder of the sacrificial material 114, which is undoped with one or more of the following: p-type dopant, carbon, nitrogen, and oxygen. As another non-limiting example, if the sacrificial material 114 comprises a dielectric nitride material (e.g., SiN...) y If the sacrificial material 114 is doped with one or more of carbon and oxygen to form an etch-resistant material 120, then a portion of the sacrificial material 114 may be doped with one or more of carbon and oxygen to form an etch-resistant material 120. For example, the etch-resistant material 120 (e.g., a doped dielectric nitride material) may have greater etch resistance to H3PO4 than the remaining portion of the sacrificial material 114 which is not doped with one or more of carbon and oxygen.

[0049] If the sacrificial material 114 is doped to form the etch-resistant material 120, the concentration range of the dopant within the etch-resistant material 120 can depend at least in part on the material composition of the sacrificial material 114 and the dopant. As a non-limiting example, if the sacrificial material 114 comprises polysilicon and the dopant comprises at least one p-type dopant, the concentration range of the p-type dopant within the etch-resistant material 120 (e.g., doped polysilicon) can be greater than or equal to per cubic centimeter (cm³). 3 Approximately 1E17 p-type dopant units (e.g., atoms, ions), such as greater than or equal to 1E17 p-type dopant units / cm². 3 Approximately 1E18 P-type dopant units / cm 3 Up to approximately 5E18 P-type dopant units / cm 3 As another non-limiting example, if the sacrificial material 114 comprises polycrystalline silicon or a dielectric nitride material (e.g., SiN...) yIf the dopant includes oxygen, then the etch-resistant material 120 (e.g., doped polysilicon or doped dielectric nitride material) may include more than or equal to 1 atomic percent oxygen, such as from about 1 atomic percent oxygen to about 66 atomic percent oxygen. As another non-limiting example, if the sacrificial material 114 comprises polysilicon or a dielectric nitride material (e.g., SiN4), then the etch-resistant material 120 may include more than 1 atomic percent oxygen, such as from about 1 atomic percent oxygen to about 66 atomic percent oxygen. y If the dopant includes carbon, then the etch-resistant material 120 (e.g., doped polysilicon or doped dielectric nitride material) may include more than or equal to 1 atomic percent of carbon, such as about 1 atomic percent to about 20 atomic percent of carbon.

[0050] Next, we will take a group reference. Figure 3A and Figure 3B ( Figure 3B Depicting in Figure 3A A simplified partial top view of the microelectronic device structure 100 at the processing stage shown indicates that an initial stacked structure 122, including at least one step structure 130, can be formed on or above the etch-resistant material 120 and the remainder of the sacrificial material 114. The initial stacked structure 122 can extend horizontally (e.g., in the X and Y directions) through the memory array region 102, the step region 104, and the intermediate region 106 of the microelectronic device structure 100. The step structure 130 can be formed within the step region 104 of the microelectronic device structure 100. Additionally, further features can be formed within portions of the memory array region 102 and the intermediate region 106 that horizontally overlap with the block region 116 of the microelectronic device structure 100. Non-limiting examples of such additional features include cell pillar structures 134, pseudo-pillar structures 136, and deep contact pillar structures 137. Further details are described below regarding... Figure 3A and Figure 3B The aforementioned features and other features of the microelectronic device structure 100 in the processing stage. Figure 3A The view depicted is of the microelectronic device structure 100 surrounding... Figure 3B The simplified partial cross-sectional view of dashed line A1-A1 is shown in the image.

[0051] The initial stack structure 122 may be formed as a vertically alternating sequence (e.g., in the Z direction) comprising insulating material 124 arranged as layers 128 and additional sacrificial material 126. Each layer of the initial stack structure 122 may contain additional sacrificial material 126 perpendicularly adjacent to the insulating material 124. The initial stack structure 122 may be formed to contain any desired number of layers 128, such as sixteen or more (16), thirty-two or more (32), sixty-four or more (64), one hundred and twenty-eight or more (128), or two hundred and fifty-six or more (256).

[0052] The insulating material 124 of the layer 128 of the initial stacked structure 122 may be formed of at least one dielectric material and may contain at least one dielectric material, such as at least one dielectric oxide material (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of the following), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y ) and at least one dielectric carbonitride material (e.g., SiO2) x C z N y One or more of the following. The material composition of insulating material 124 may differ from the material compositions of the other sacrificial materials 126 and 114. The material composition of insulating material 124 may be substantially the same as that of etch-resistant material 120, or the material composition of insulating material 124 may differ from that of etch-resistant material 120. In some embodiments, each of the insulating materials 124 is made of a dielectric oxide material, such as SiO2. x (e.g., SiO2) forms and contains the dielectric oxide material. The insulating material 124 of each layer in layer 128 may be substantially uniform, or one or more (e.g., each) layers of insulating material 124 in layer 128 may be non-uniform.

[0053] The additional sacrificial material 126 of the layers 128 of the initial stacked structure 122 may be formed of and comprise at least one material (e.g., at least one insulating material) that can be selectively removed relative to the insulating material 124, the etch-resistant material 120, and the insulating material 112. The material composition of the additional sacrificial material 126 differs from that of the insulating material 124, the etch-resistant material 120, and the insulating material 112. The material composition of the additional sacrificial material 126 may be substantially the same as that of the sacrificial material 114, or the material composition of the insulating material 124 may differ from that of the sacrificial material 114. During co-exposure (e.g., collectively, jointly) to the first etchant, the additional sacrificial material 126 may be selectively etched relative to the insulating material 124, the etch-resistant material 120, and the insulating material 112; and during co-exposure to different second etchants, the insulating material 124, the etch-resistant material 120, and the insulating material 112 may be selectively etched relative to the additional sacrificial material 126. In some embodiments, each of the additional sacrificial materials 126 is made of a dielectric nitride material, such as SiN. y (e.g., Si3N4) is formed and comprises the dielectric nitride material. In some embodiments of this type, the sacrificial material 114 is made of the same dielectric nitride material (e.g., SiN) as the additional sacrificial material 126. y The additional sacrificial materials 126 and 114 may be selectively etched relative to the insulating material 124, the etch-resistant material 120, and the isolating material 112 during co-exposure to a wet etchant comprising H3PO4. In another embodiment, each of the additional sacrificial materials 126 is formed of and comprises polysilicon. In some embodiments, the sacrificial material 114 is also formed of and comprises polysilicon. For example, during co-exposure to a wet etchant comprising TMAH, the additional sacrificial materials 126 and 114 may be selectively etched relative to the insulating material 124, the etch-resistant material 120, and the isolating material 112. The additional sacrificial material 126 may be substantially homogeneous or may be non-homogeneous.

[0054] The at least one stepped structure 130 may be formed and positioned within a portion of the initial stacked structure 122 located within the horizontal boundary (e.g., in the X direction) of the stepped region 104 of the microelectronic device structure 100. The stepped structure 130 may be formed to extend horizontally (e.g., in the Y direction) across the block region 116 and the slot region 118 of the microelectronic device structure 100. The stepped structure 130 includes a step 132 defined at least partially by the horizontal ends (e.g., in the X direction) of the layers 128 of the initial stacked structure 122. As described in further detail below, the step 132 of the stepped structure 130 may serve as a contact region to electrically connect conductive structures subsequently formed using additional sacrificial material 126 (e.g., by so-called “replacement gate” or “gate last” processing) to other features of the microelectronic device structure 100 (e.g., control logic devices located within the substrate structure 108). The number of steps 132 included in the stepped structure 130 may be substantially the same (e.g., equal to) or different (e.g., less than or greater than) the number of layers 128 in the initial stacked structure 122. Figure 3A As shown, in some embodiments, the steps 132 of the stepped structure 130 are arranged sequentially such that steps 132 that are directly horizontally adjacent to each other in the X direction correspond to layers 128 of the initial stacked structure 122 that are directly vertically adjacent to each other (e.g., in the Z direction). In other embodiments, the steps 132 of the stepped structure 130 are arranged out of order such that at least some steps 132 of the stepped structure 130 that are directly horizontally adjacent to each other in the X direction correspond to layers 128 of the initial stacked structure 122 that are not directly vertically adjacent to each other (e.g., in the Z direction). The stepped structure 130 may be vertically (e.g., in the Z direction) above the etch-resistant material 120 and horizontally overlap the etch-resistant material (e.g., in the X and Y directions).

[0055] Cellular pillar structure 134 can be formed and positioned within the horizontal area of ​​the initial stacked structure 122, the horizontal area corresponding to the intersection (e.g., horizontal overlap) of the memory array region 102 and block region 116 of the microelectronic device structure 100. Cellular pillar structure 134 can be at least partially vertical (e.g., in the Z direction) above and horizontally overlap (e.g., in the X and Y directions) the remaining portion of the sacrificial material 114. Figure 5AAs shown, in some embodiments, the cell pillar structure 134 extends vertically through the layers 128 of the initial stack structure 122 and reaches the remaining portion of the sacrificial material 114. The cell pillar structure 134 may terminate vertically at or within the remaining portion of the sacrificial material 114. In other embodiments, the cell pillar structure 134 extends vertically through the layers 128 of the initial stack structure 122 and also extends vertically through the remaining portion of the sacrificial material 114. The cell pillar structure 134 may terminate vertically below the remaining portion of the sacrificial material 114, such as terminating at or within the isolation material 112, terminating at or within the source layer 109, or terminating at or within the substrate structure 108.

[0056] Cell pillar structures 134 can each be individually formed from and comprise said material stacks. By way of non-limiting example, each cell pillar structure in cell pillar structure 134 can be formed to comprise a charge-blocking material, such as a first dielectric oxide material (e.g., SiO2). x Such as SiO2; AlO x Materials such as Al2O3; charge-trapping materials, such as dielectric nitride materials (e.g., SiN). y (e.g., Si3N4); tunneling dielectric materials, such as second oxide dielectric materials (e.g., SiO2). x The charge-blocking material may be formed on or above the insulating material 124 and additional sacrificial material 126 of the initial stacked structure 122, thereby at least partially defining the horizontal boundary of the cell pillar structure 134; the charge-trapping material may be horizontally surrounded by the charge-blocking material; the tunneling dielectric material may be horizontally surrounded by the charge-blocking material; the channel material may be horizontally surrounded by the tunneling dielectric material; and the dielectric filling material may be horizontally surrounded by the channel material.

[0057] The pseudo-pillar structure 136 (if present) may include pillar structures that are electrically disconnected from and / or will be electrically disconnected from other features of the microelectronic device structure 100 (e.g., conductive structures such as wires); and / or pillar structures that do not and / or will not facilitate electrical communication between other features of the microelectronic device structure 100. For example, the pseudo-pillar structure 136 may be employed to reduce damage and / or defects at the edges of the array of cell pillar structures 134 (e.g., commonly referred to as "array edge effect").

[0058] If formed, the pseudo-pillar structure 136 can be horizontally (e.g., in the X direction) adjacent to the outermost cell pillar structure 134, such as the cell pillar structure 134 positioned relative to the horizontal boundary (e.g., in the X direction) of the memory array region 102 closest to the microelectronic device structure 100. The pseudo-pillar structure 136 can be formed and positioned within the horizontal area of ​​the initial stack structure 122, which corresponds to the intersection (e.g., horizontal overlap) of the intermediate region 106 and block region 116 of the microelectronic device structure 100. The pseudo-pillar structure 136 can extend vertically through the layers 128 of the initial stack structure 122 to the remainder of the sacrificial material 114 and / or to the etch-resistant material 120. Figure 5A As shown, in some embodiments, the dummy pillar structure 136 extends vertically through the layers 128 of the initial stack structure 122 and reaches the remaining portion of the sacrificial material 114 and / or the etch-resistant material 120. The dummy pillar structure 136 may terminate vertically at or within the remaining portion of the sacrificial material 114 and / or at or within the etch-resistant material 120. In other embodiments, the dummy pillar structure 136 extends vertically through the layers 128 of the initial stack structure 122, and also extends vertically through the remaining portion of the sacrificial material 114 and / or the etch-resistant material 120. The dummy pillar structure 136 may terminate vertically below the remaining portion of the sacrificial material 114 and the etch-resistant material 120, such as terminating at or within the isolation material 112, terminating at or within the source layer 109, or terminating at or within the substrate structure 108.

[0059] The dummy pillar structure 136 (if present) may be formed of and comprise one or more materials (e.g., insulating, conductive, semiconductor materials) that can mitigate undesirable array edge effects in the array of cell pillar structures 134 subsequently formed within a block of the stacked structure formed by the initial stacked structure 122. In some embodiments, the dummy pillar structure 136 comprises a dielectric pillar structure. In another embodiment, the dummy pillar structure 136 comprises a semiconductor pillar structure. In yet another embodiment, the dummy pillar structure 136 comprises a conductive pillar structure. In yet another embodiment, the dummy pillar structure 136 comprises a pillar structure substantially similar to that of the cell pillar structure 134, but the pillar structure will not be electrically connected to one or more conductive structures (e.g., wires such as digital lines, lateral contact structures) to which the cell pillar structure 134 will be electrically connected. In such embodiments, the cell pillar structure 134 may be considered an “active” cell pillar structure, while the dummy pillar structure 136 may be considered a “passive” cell pillar structure.

[0060] Deep contact pillar structures 137 may be formed and positioned within a horizontal area of ​​the initial stacked structure 122, the horizontal area corresponding to the intersection (e.g., a horizontal overlap) of the intermediate region 106 and block region 116 of the microelectronic device structure 100. The deep contact pillar structures 137 may extend vertically through layers 128 of the initial stacked structure 122, through the remainder of the sacrificial material 114 and / or the etch-resistant material 120, through the insulating material 112, and to the source layer 109 of the microelectronic device structure 100. One or more of the deep contact pillar structures 137 may be configured and positioned to electrically connect one or more features of the source layer 109 (e.g., source structure 110, contact structure 111) to one or more conductive features (e.g., additional contact structures, wire structures) subsequently formed above the upper vertical boundary of the initial stacked structure 122. Optionally, one or more other deep contact pillar structures in the deep contact pillar structure 137 may be configured and positioned as support structures for subsequent processing of the initial stacked structure 122, such as subsequent replacement gate processing of the initial stacked structure 122. For example, the one or more other deep contact pillar structures in the deep contact pillar structure 137 may be configured and positioned to provide support for the initial stacked structure 122 at or near the stepped structure 130 to reduce collapse of the layer 128 at or near the stepped structure 130 during subsequent replacement gate processing. In some embodiments, the one or more other deep contact pillar structures in the deep contact pillar structure 137 are positioned to be electrically disconnected from conductive features (e.g., additional contact structures, wire structures) that will subsequently be formed above the upper vertical boundary of the initial stacked structure 122.

[0061] The deep contact pillar structure 137 may be formed and comprised solely of at least one conductive material and at least one insulating liner material that substantially horizontally surrounds and covers the conductive material (e.g., across the entire vertical height of the conductive material). In some embodiments, the conductive material of the deep contact pillar structure 137 comprises W. In another embodiment, the conductive material of the deep contact pillar structure 137 comprises conductive-doped polycrystalline silicon. The insulating liner material may be formed and comprised of at least one insulating material. In some embodiments, the insulating liner material of the deep contact pillar structure 137 comprises SiO₂. x (For example, SiO2).

[0062] In embodiments where the etch-resistant material 120 is formed to extend horizontally to the horizontal area corresponding to the intersection (e.g., horizontal overlap) of the initial stacked structure 122 with the intermediate region 106 and block region 116 of the microelectronic device structure 100, one or more (e.g., each) of the pseudo-pillar structures 136 and / or one or more (e.g., each) of the deep contact pillar structures 137 may be formed and provided within the horizontal boundary of the etch-resistant material 120. In further embodiments where the etch-resistant material 120 is not formed to extend horizontally to the horizontal area corresponding to the intersection (e.g., horizontal overlap) of the initial stacked structure 122 with the intermediate region 106 and block region 116 of the microelectronic device structure 100, the pseudo-pillar structures 136 and deep contact pillar structures 137 may be formed and provided outside the horizontal boundary of the etch-resistant material 120.

[0063] Next, we will take a group reference. Figure 4A and Figure 4B ( Figure 4B Depicting in Figure 4A A simplified partial top view of the microelectronic device structure 100 during the processing stage is shown, and the groove region 118 of the microelectronic device structure 100 is shown. Figure 3B At least a portion of the initial stacked structure 122 and the sacrificial material 114 within the horizontal boundary (e.g., in the Y and X directions) of the etch-resistant material 120 within the horizontal boundary of the trench region 118 (and a portion of the etch-resistant material 120 within the horizontal boundary of the trench region 118) can be removed to form a trench 140 (e.g., a slit, opening, or groove). The trench 140 can divide (e.g., partition) the initial stacked structure 122 into initial blocks 138 that are horizontally separated from each other by the trench 140. Additionally, the trench 140 can also divide the sacrificial material 114 into multiple segments individually confined within the horizontal boundary of individual initial blocks 138, which are vertically above the sacrificial material and horizontally separated from each other by the trench 140. Figure 4A The view depicted is of the microelectronic device structure 100 surrounding... Figure 4B The simplified partial cross-sectional view of dashed line A1-A1 is shown in the image.

[0064] like Figure 4BAs shown, the groove 140 can be formed as comprising a first groove 140A extending horizontally in a first horizontal direction (e.g., in the X direction) and a second groove 140B extending horizontally in a second horizontal direction orthogonal to the first horizontal direction (e.g., in the Y direction). The first groove 140A can be horizontally inserted between initial blocks 138 (and thus, segments of sacrificial material 114) that are horizontally adjacent to each other in the second horizontal direction; and the second groove 140B can be horizontally inserted between initial blocks 138 (and thus, segments of sacrificial material 114) that are horizontally adjacent to each other in the first horizontal direction. The first groove 140A can intersect the second groove 140B horizontally and can be integral and continuous with the second groove 140B. As described in further detail below, after the microelectronic device structure 100 undergoes so-called “replacement gate” or “gate final” processing, the groove 140 containing its first groove 140A and second groove 140B can then be filled with an insulating material.

[0065] Next, refer to Figure 5A and Figure 5B ( Figure 5B Depicting in Figure 5A The simplified partial top view of the microelectronic device structure 100 shown in the diagram illustrates a processing stage in which the microelectronic device structure 100 can undergo so-called "replacement gate" or "gate-final" processing. This replacement gate processing can at least partially replace the additional sacrificial material 126 with a conductive material. Figure 4A ) and sacrificial material 114 ( Figure 4A The remaining portion of the initial block 138 is used to form conductive structure 148 and lateral contact structure 152, respectively. The replacement gate processing can include the initial block 138 ( Figure 4A and Figure 4B The initial stacking structure 122 () Figure 4A and Figure 4B This is transformed into a stacked structure 142 containing block 150. The stacked structure 142 may contain a vertical (e.g., in the Z direction) alternating sequence of insulating structures 146 and conductive structures 148 arranged as layers 144. The insulating structure 146 may correspond to insulating material 124 (…). Figure 4A The remaining (e.g., unremoved) portion after the gate replacement process. The stacked structure 142 can be divided into blocks 150, and the shape and size of the blocks 150 can be similar to the initial stacked structure 122. Figure 4A and Figure 4B The initial block 138 () Figure 4A and Figure 4B The shapes and sizes of the slots are basically the same. The slot 140 can be inserted between horizontally adjacent blocks 150 of the stacked structure 142. Figure 5A The view depicted is of the microelectronic device structure 100 surrounding... Figure 5BThe simplified partial cross-sectional view of dashed line A1-A1 is shown in the image.

[0066] The conductive structure 148 of the stacked structure 142 can be used as an access line structure (e.g., a local access line structure, a local word line structure). In some embodiments, the conductive structure 148 is formed of and contains W. Optionally, at least one liner material (e.g., at least one insulating liner material, at least one conductive liner material) can be formed around the conductive structure 148. For example, the liner material can be formed of and contain one or more of the following: metals (e.g., titanium, tantalum), alloys, metal nitrides (e.g., tungsten nitride, titanium nitride, tantalum nitride), and metal oxides (e.g., aluminum oxide). In some embodiments, the liner material includes at least one conductive material used as a seed material for forming the conductive structure 148. In some embodiments, the liner material includes titanium nitride (TiN). x (e.g., TiN). In another embodiment, the lining material further comprises alumina (AlO2). x (e.g., Al2O3). As a non-limiting example, AlO x (For example, Al2O3) can be formed directly adjacent to the insulating structure 146, TiN x (For example, TiN) can be directly adjacent to AlO. x And thus formed, and W can be directly adjacent to TiN. x And thus formed. To make this description clear and easy to understand, Figure 5A and Figure 5B The lining material is not shown, but it should be understood that the lining material may be disposed around the conductive structure 148.

[0067] At least one lower conductive structure 148 of a single block 150 of the stacked structure 142 can be used as at least one lower select gate (e.g., at least one source-side select gate (SGS)) of a lower select transistor (e.g., a source-side select transistor) of block 150. In some embodiments, a single (e.g., only one) conductive structure 148 of the vertically bottommost layer 144 of block 150 of the stacked structure 142 is used as a lower select gate (e.g., SGS) of block 150. Additionally, an upper conductive structure 148 of a single block 150 of the stacked structure 142 can be used as an upper select gate (e.g., drain-side select gate (SGD)) of an upper select transistor (e.g., a drain-side select transistor) of block 150. In some embodiments, horizontally adjacent (e.g., in the Y direction) conductive structures 148 of the vertically topmost layer 144 of block 150 are used as upper select gates (e.g., SGDs) of block 150. The horizontally adjacent conductive structures of the vertical uppermost layer 144 of block 150 can be separated from each other by additional slots (e.g., SGD slots), which can then be filled with insulating material.

[0068] The intersection of the cell pillar structure 134 and the conductive structure 148 of the stacked structure 142 can define a vertically extending string of memory cells 154 coupled in series with each other within the stacked structure 142. In some embodiments, the memory cells 154 formed at the intersection of the conductive structure 148 and the cell pillar structure 134 within different layers 144 of the stacked structure 142 include so-called "MONOS" (metal-oxide-nitride-oxide-semiconductor) memory cells. In another embodiment, the memory cells 154 include so-called "TANOS" (tantalum nitride-aluminum oxide-nitride-oxide-semiconductor) memory cells or so-called "BETANOS" (bandgap / barrier engineered TANOS) memory cells, each of which is a subset of MONOS memory cells. In another embodiment, the memory cells 154 include so-called "floating gate" memory cells, comprising a floating gate (e.g., a metal floating gate) as a charge storage structure. The floating gate can be horizontally positioned between the cell pillar structure 134 of the different layers 144 of the stacked structure 142 and the central structure of the conductive structure 148.

[0069] Lateral contact structures 152 can be used to electrically connect cell pillar structures 134 (and thus strings of vertically extending memory cells 154) extending vertically through block 150 of stacked structure 142 to source structures 110 of source layer 109. Individual lateral contact structures 152 can extend and contact (e.g., physical contact, electrical contact) between channel materials (e.g., polysilicon) of multiple cell pillar structures 134 within individual block 150 of stacked structure 142, and can also contact (e.g., physical contact, electrical contact) at least some of the vertical direct contact structures 113 of source structures 110 coupled to source structures 110 within source layer 109 of microelectronic device structure 100. Within the horizontal boundary of individual block 150, individual lateral contact structures 152 can be positioned horizontally (e.g., in the X direction) adjacent to etch-resistant material 120 within the horizontal boundary of individual block 150.

[0070] Lateral contact structures 152 may be formed and positioned at least within the horizontal boundary (e.g., in the X direction) of the memory array region 102 of the microelectronic device structure 100. In some embodiments, the lateral contact structures 152 are substantially confined within the horizontal boundary of the memory array region 102 of the microelectronic device structure 100. In another embodiment, based on the remaining portion of the sacrificial material 114 ( Figure 4A With the horizontal geometric configuration of the etch-resistant material 120, the lateral contact structure 152 is formed to extend beyond the horizontal boundary of the memory array region 102 of the microelectronic device structure 100. For example, if the remaining portion of the sacrificial material 114 ( Figure 4A If the lateral contact structure 152 extends horizontally into the middle region 106 of the microelectronic device structure 100, then the lateral contact structure 152 can also extend horizontally into the middle region 106 of the microelectronic device structure 100. The lateral contact structure 152 may not extend substantially horizontally into the stepped region 104 of the microelectronic device structure 100. The stepped region 104 of the microelectronic device structure 100 may substantially lack the lateral contact structure 152. Figure 5A As shown, after the replacement gate processing of the microelectronic device structure 100, the etch-resistant material 120 can be retained in the stepped region 104 of the microelectronic device structure 100.

[0071] The material composition of the lateral contact structure 152 may be substantially the same as that of the conductive structure 148 of the stacked structure 142, or the material composition of the lateral contact structure 152 may be different from that of the conductive structure 148 of the stacked structure 142. In some embodiments, the lateral contact structure 152 is formed of and includes W. The lateral contact structure 152 may be substantially uniform on its own, or the lateral contact structure 152 may be non-uniform on its own.

[0072] The replacement gate processing for forming the stacked structure 142 and the lateral contact structure 152 may include treating the microelectronic device structure 100 with at least one wet etchant, said wet etchant being formulated to selectively remove portions of the sacrificial material 114 exposed by the trench 140. Figure 4A ) and other sacrificial materials 126 ( Figure 4A ), without substantially removing portions of the insulating material 112, anti-etching material 120, and insulating material 124 exposed by the trench 140. Figure 4A ), to form a groove. By way of non-limiting example, according to sacrificial material 114 ( Figure 4A ), and another 126 sacrificial materials Figure 4A ), isolation material 112, anti-etching material 120 and insulating material 124 ( Figure 4A The material composition, the wet etchant can be one or more of TMAH, H3PO4, sulfuric acid (H2SO4), hydrochloric acid (HCl), nitric acid (HNO3) and another material. In sacrificial material 114 ( Figure 4A ) and other sacrificial materials 126 ( Figure 4A In some embodiments, including polycrystalline silicon, a wet etchant including TMAH is used to at least partially remove the sacrificial material 114. Figure 4A ) and other sacrificial materials 126 ( Figure 4A ), without substantially removing the insulating material 112, the anti-etching material 120, and the insulating material 124. Figure 4A ). In sacrificial material 114 ( Figure 4A) and other sacrificial materials 126 ( Figure 4A This includes dielectric nitride materials (such as SiN). y In another embodiment, such as Si3N4, a wet etchant including H3PO4 is used to at least partially remove the sacrificial material 114. Figure 4A ) and other sacrificial materials 126 ( Figure 4A ), without substantially removing the insulating material 112, the anti-etching material 120, and the insulating material 124. Figure 4A In the section where sacrificial material 114 is selectively removed ( Figure 4A ) and other sacrificial materials 126 ( Figure 4A Afterwards, the resulting grooves can be filled with conductive material to form lateral contact structure 152 and conductive structure 148, respectively.

[0073] During gate replacement processing, the anti-etching material 120 within at least the stepped region 104 of the microelectronic device structure 100 can prevent or inhibit etching of the initial stacked structure 122 within the stepped region 104 of the microelectronic device structure 100. Figure 4A Undesired damage (e.g., delamination collapse, delamination cracking, delamination lift) and / or undesired deformation (e.g., delamination bending, delamination warping, delamination flexing) to the material 114 if a portion of the material is sacrificed. Figure 4A (In previous reference) Figure 2A and Figure 2B If the etch-resistant material 120 is not replaced during the described processing stages, the undesirable damage and / or undesirable deformation may occur in other ways. For example, forming the etch-resistant material 120 within the stepped region 104 of the microelectronic device structure 100 avoids the removal of the sacrificial material 114 within the stepped region 104. Figure 4A The removal may otherwise occur during the replacement gate processing and may be applied to the initial stacked structure 122 within the stepped region 104 prior to the formation of the conductive structure 148. Figure 4A ) layer 122 ( Figure 4A The stress that causes undesirable damage and / or undesirable deformation in certain parts.

[0074] Therefore, according to embodiments of this disclosure, a method of forming a microelectronic device includes forming a sacrificial material over a substrate structure. A portion of the sacrificial material is replaced with an etch-resistant material. A stacked structure is formed over the etch-resistant material and the remaining portion of the sacrificial material. The stacked structure includes a vertically alternating sequence of layered insulating material and additional sacrificial material, and at least one stepped structure that horizontally overlaps the etch-resistant material and has steps including horizontal ends of the layers. A groove is formed extending vertically through the stacked structure and the remaining portion of the sacrificial material. After forming the groove, the sacrificial material and the additional sacrificial material are selectively replaced with a conductive material to form a lateral contact structure and a conductive structure, respectively.

[0075] Figure 6 A partial cross-sectional perspective view of a portion of a microelectronic device 201 (e.g., a memory device, such as a 3D and non-flash memory device) including a microelectronic device structure 200 is shown. (See previous references.) Figure 5A and Figure 5B After the described processing stages, the microelectronic device structure 200 can be substantially similar to the microelectronic device structure 100. In some embodiments, the microelectronic device structure 200 is based on previously referenced... Figures 1A to 5B It is formed by the described process. To avoid repetition, this article does not describe it in detail. Figure 6 All features shown (e.g., structure, materials, areas, devices). Conversely, unless otherwise described below, in Figure 6 In, by comparing with previous references Figures 1A to 5B The reference numerals for one or more described features are incremented by 100. Features designated by reference numerals should be understood as substantially similar to the previously described features. Furthermore, for clarity and ease of understanding of the figures and associated descriptions, Figure 6 Previous references are not shown in the text. Figure 5A and Figure 5B The description describes some features of the microelectronic device structure 100 after the fabrication stages. However, it should be understood that the previous references Figure 5A and Figure 5B Any features of the microelectronic device structure 100 after the described fabrication stages may be included in the references herein. Figure 6 The microelectronic device 201 described is in the microelectronic device structure 200.

[0076] like Figure 6As shown, in addition to the features of the microelectronic device structure 200 previously described with respect to the microelectronic device structure 100, the microelectronic device 201 may further include digital lines 256 (e.g., data lines, bit lines), access line router structure 258, access line contact structure 260, select line router structure 262, and select line contact structure 264. The access line contact structure 260 and select line contact structure 264 may contact (e.g., physical contact, electrical contact) the steps 232 of the step structure 230 within the step region 204 of the microelectronic device 201, and may couple the components to each other as shown (e.g., coupling the select line router structure 262 to the conductive structure 248 of the stacked structure 242 serving as the upper select gate (e.g., SGD); coupling the access line router structure 258 to the conductive structure 248 of the stacked structure 242 serving as the local access line). Additionally, as... Figure 6 As shown, at least a portion of the substrate structure 208 is located within the horizontal boundary of the memory array region 202 of the microelectronic device 201. The substrate structure 208 may include a control logic region comprising a control logic circuitry (e.g., a CMOS circuitry) that can be coupled to the digital line 256, the source structure 210 within the source layer 209, the access line router structure 258, and the select line router structure 262. In such embodiments, the control logic region of the substrate structure 208 may be characterized as having a “CMOS under Array” (“CuA”) configuration.

[0077] Therefore, according to embodiments of this disclosure, a microelectronic device includes blocks, an etch-resistant material, lateral contact structures, and additional conductive structures. Each block has a vertically alternating sequence of layered conductive and insulating structures. Each block includes a stepped structure with steps including horizontal ends of the layers. The etch-resistant material is vertically located below each block and within the horizontal boundary of the stepped structure of each block. The lateral contact structures are vertically located below each block and outside the horizontal boundary of the stepped structure. The lateral contact structures are horizontally adjacent to the etch-resistant material and located at substantially the same vertical position as the etch-resistant material. The additional conductive structures are vertically located below the lateral contact structures and electrically connected to the lateral contact structures.

[0078] Furthermore, according to embodiments of this disclosure, a memory device includes a stacked structure, a stepped structure, an etch-resistant material, additional conductive structures, vertically extending memory cell strings, and a substrate structure. The stacked structure includes blocks, each block having a layer, the layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure. The stepped structure is located within a contact region of each block of the stacked structure and has steps including the edges of the layers of the block. The etch-resistant material is vertically located below the stacked structure and within the horizontal boundary of the contact region of each block of the stacked structure. The additional conductive structure is vertically located below the stacked structure and within the horizontal boundary of the memory array region of each block of the stacked structure. The additional conductive structure is horizontally adjacent to the etch-resistant material and located at substantially the same vertical position as the etch-resistant material. The vertically extending memory cell strings are located within the memory array region of each block of the stacked structure and coupled to the additional conductive structures. The substrate structure is vertically located below the stacked structure and includes a control logic circuitry coupled to the vertically extending memory cell strings.

[0079] Microelectronic device structures according to embodiments of the present disclosure (e.g., microelectronic device structure 100) Figure 5A and 5B )) and microelectronic devices (e.g., microelectronic device 201 ( Figure 6 This can be used in embodiments of the electronic systems disclosed herein. For example, Figure 7 This is a block diagram of an illustrative electronic system 300 according to embodiments of the present disclosure. The electronic system 300 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer (e.g.,...). or Tablet computers, e-books, navigation devices, etc. Electronic system 300 includes at least one memory device 302. Memory device 302 may include, for example, the microelectronic device architecture previously described herein (e.g., microelectronic device architecture 100). Figure 5A and 5B )) and microelectronic devices (e.g., microelectronic device 201 ( Figure 6 One or more of the following. Electronic system 300 may further include at least one electronic signal processor device 304 (generally referred to as a “microprocessor”). Optionally, electronic signal processor device 304 may include the microelectronic device architecture previously described herein (e.g., microelectronic device architecture 100). Figure 5A and 5B)) and microelectronic devices (e.g., microelectronic device 201 ( Figure 6 One or more of the following. Although in Figure 7 The memory device 302 and the electronic signal processor device 304 are depicted as two (2) separate devices, but in another embodiment, the electronic system 300 includes a single (e.g., only one) memory / processor device having the functions of both the memory device 302 and the electronic signal processor device 304. In such embodiments, the memory / processor device may comprise the microelectronic device architecture previously described herein (e.g., microelectronic device architecture 100). Figure 5A and 5B )) and microelectronic devices (e.g., microelectronic device 201 ( Figure 6 The electronic system 300 may further include one or more input devices 306 for users to input information into the electronic system 300, such as a mouse or other pointing device, keyboard, touchpad, button, or control panel. The electronic system 300 may further include one or more output devices 308 for outputting information to the user (e.g., visual or audio output), such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, the input device 306 and output device 308 may include a single touchscreen device that can be used both to input information into the electronic system 300 and to output visual information to the user. The input device 306 and output device 308 may be in electrical communication with one or more of the memory device 302 and the electronic signal processor device 304.

[0080] Therefore, according to embodiments of this disclosure, an electronic system includes: an input device; an output device; a processor device operatively connected to the input device and the output device; and a memory device operatively connected to the processor device. The memory device includes blocks, memory cell strings, digital line structures, etch-resistant materials, lateral contact structures, at least one source structure, and a substrate structure. Each block has a vertically alternating sequence of layered conductive and insulating structures. Each block includes a stepped structure having steps at horizontal ends comprising the layers of the block. The memory cell strings extend vertically through the blocks. The digital line structures are vertically located above the blocks and coupled to the memory cell strings. The etch-resistant materials are vertically located below each block and within the horizontal boundaries of the stepped structures of each block. The lateral contact structures are vertically located below each block and outside the horizontal boundaries of the stepped structures of each block. Each of the lateral contact structures is coupled to some memory cells in the memory cell string and is directly and horizontally adjacent to some of the etch-resistant materials. The at least one source structure is vertically located below and coupled to the lateral contact structure. The substrate structure is vertically located below the at least one source structure and includes control logic devices coupled to the conductive structure, the digital line structure, and the at least one source structure of the block.

[0081] Compared to conventional structures, conventional devices, and conventional systems, the methods and structures disclosed herein (e.g., microelectronic device structure 100) offer advantages over conventional structures, conventional devices, and conventional systems. Figure 5A and 5B )), devices (e.g., microelectronic devices 201) Figure 6 )) and systems (e.g., electronic system 300) Figure 7 This advantageously promotes one or more of the following: improved performance, reliability and durability, lower cost, increased component miniaturization, improved pattern quality, and greater package density. By way of non-limiting examples, compared with conventional methods, conventional structures, and conventional devices, the methods and structures of this disclosure can reduce the risk of undesirable deformation (e.g., delamination bending, delamination warping, delamination bending) and damage (e.g., delamination collapse) during the formation of the device of this disclosure (e.g., microelectronic device 201), and can increase yield and reduce leakage current (e.g., leakage current may otherwise be caused by said undesirable deformation and / or damage).

[0082] Further non-limiting example embodiments of this disclosure are described below.

[0083] Example 1: A method for forming a microelectronic device, the method comprising: forming a sacrificial material over a substrate structure; replacing a portion of the sacrificial material with an etch-resistant material; forming a stacked structure over the etch-resistant material and the remaining portion of the sacrificial material, the stacked structure comprising: a vertically alternating sequence of layered insulating material and additional sacrificial material; and at least one stepped structure, the at least one stepped structure horizontally overlapping the etch-resistant material and having a step including the horizontal ends of the layers; forming a groove extending vertically through the stacked structure and the remaining portion of the sacrificial material; and after forming the groove, selectively replacing the sacrificial material and the additional sacrificial material with a conductive material to form a lateral contact structure and a conductive structure, respectively.

[0084] Example 2: According to the method of Example 1, replacing a portion of the sacrificial material with an etch-resistant material includes: removing the portion of the sacrificial material to form an opening extending vertically through the remaining portion of the sacrificial material; and filling the opening with the etch-resistant material.

[0085] Example 3: The method according to Example 2 further includes selecting the etch-resistant material to include at least one material that has relatively greater etch resistance compared to the sacrificial material during co-exposure to at least one etchant.

[0086] Example 4: The method according to one of Examples 2 and 3 further includes: selecting the sacrificial material to include one of polysilicon and dielectric nitride materials; and selecting the etch-resistant material to include dielectric oxide materials.

[0087] Example 5: The method according to any one of Examples 1 to 4, wherein replacing the sacrificial material with an etch-resistant material comprises doping the sacrificial material with at least one chemical species to form the etch-resistant material, which has relatively greater etch resistance than the sacrificial material during co-exposure to at least one etchant.

[0088] Example 6: The method according to Example 5 further includes: selecting the sacrificial material to include polycrystalline silicon; and selecting the at least one chemical species to include one or more of boron, aluminum, gallium, carbon, nitrogen and oxygen.

[0089] Example 7: The method according to Example 5 further includes: selecting the sacrificial material to include a dielectric nitride material; and selecting the at least one chemical species to include one or more of carbon and oxygen.

[0090] Example 8: The method according to any one of Examples 1 to 7, wherein replacing a portion of the sacrificial material with an etch-resistant material includes replacing a first portion of the sacrificial material to be positioned within the horizontal boundary of the at least one stepped structure with the etch-resistant material, while maintaining a second portion of the sacrificial material to be positioned within the horizontal boundary of the array of vertically extending memory cell strings to be formed within the stacked structure.

[0091] Example 9: The method according to any one of Examples 1 to 8, wherein forming a sacrificial material over a substrate structure comprises: forming a source layer including at least one conductive electrode structure over the substrate structure; forming an isolation material over the source layer; forming a conductive contact structure extending vertically through the isolation material and reaching the at least one conductive electrode structure within the source layer; and forming the sacrificial material over the isolation material and the conductive contact structure.

[0092] Example 10: The method according to any one of Examples 1 to 9 further includes forming a cell pillar structure extending vertically through the stacked structure, the cell pillar structure being positioned outside the horizontal boundary of the etch-resistant material.

[0093] Example 11: The method according to Example 10 further includes forming additional pillar structures horizontally inserted between the cell pillar structure and the at least one step structure, at least some of the additional pillar structures being positioned within the horizontal boundary of the etch-resistant material.

[0094] Example 12: According to the method of Example 11, forming the additional column structure includes forming a pseudo-column structure that extends vertically into or beyond the etch-resistant material.

[0095] Example 13: According to the method of Example 11, forming the additional column structure includes forming a conductive contact structure that extends vertically to one or more additional conductive structures, the conductive contact structure being vertically inserted between the sacrificial material and the substrate structure.

[0096] Example 14: The method according to any of Examples 1 to 13, wherein selectively replacing the sacrificial material and the additional sacrificial material with a conductive material includes at least partially replacing the sacrificial material and the additional sacrificial material with the conductive material, without substantially replacing the etch-resistant material and the insulating material with the conductive material.

[0097] Example 15: A microelectronic device comprising: blocks, each block having a vertically alternating sequence of layered conductive and insulating structures arranged in layers, each block including a stepped structure having steps including horizontal ends of the layers; an etch-resistant material vertically located below each block and within the horizontal boundary of the stepped structure of each block; a lateral contact structure vertically located below each block and outside the horizontal boundary of the stepped structure, the lateral contact structure being horizontally adjacent to the etch-resistant material and located at substantially the same vertical position as the etch-resistant material; and a further conductive structure vertically located below the lateral contact structure and electrically connected to the lateral contact structure.

[0098] Example 16: The microelectronic device according to Example 15 further includes a substrate structure, the substrate structure being vertically located below the additional conductive structure and including a control logic circuit system electrically connected to at least some of the conductive structures in the additional conductive structure and at least some of the conductive structures in the block.

[0099] Example 17: The microelectronic device according to Example 16 further includes a string of memory cells extending vertically through each of the blocks, the string of memory cells being located within the horizontal boundary of the lateral contact structure.

[0100] Example 18: The microelectronic device according to Example 17 further includes an additional conductive structure, which is vertically located above the block and electrically connected to the memory cell string and the control logic circuit system.

[0101] Example 19: A microelectronic device according to one of Examples 17 and 18, further comprising a column structure extending vertically through each of the blocks, the column structure being horizontally interposed between the memory cell string and the ladder structure within each of the blocks.

[0102] Example 20: The microelectronic device according to Example 19, wherein at least some of the pillar structures are located within the horizontal boundary of the etch-resistant material.

[0103] Example 21: A memory device comprising: a stacked structure including blocks, each block having a layer, the layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure; a stepped structure located in a contact region of each block of the stacked structure, the stepped structure having steps including the edges of the layers of the blocks; an etch-resistant material vertically located below the stacked structure and within a horizontal boundary of the contact region of each block of the stacked structure; a further conductive structure vertically located below the stacked structure and within a horizontal boundary of a memory array region of each block of the stacked structure, the further conductive structure being horizontally adjacent to the etch-resistant material and located at substantially the same vertical position as the etch-resistant material; a vertically extending string of memory cells located in the memory array region of each block of the stacked structure and coupled to the further conductive structure; and a substrate structure vertically located below the stacked structure and including a control logic circuitry system coupled to the vertically extending string of memory cells.

[0104] Example 22: The memory device according to Example 21 further includes: at least one source structure, the at least one source structure being vertically located below and coupled to the other conductive structure; and a digital line structure, the digital line structure being vertically located above the stacked structure and coupled to the vertically extending memory cell string.

[0105] Example 23: A memory device according to one of Examples 21 and 22, wherein the additional conductive structure is confined outside the horizontal boundary of the contact region of each block of the stacked structure.

[0106] Example 24: The memory device according to Example 23, wherein the etch-resistant material is confined outside the horizontal boundary of the memory array region of each block of the stacked structure.

[0107] Example 25: An electronic system comprising: an input device; an output device; a processor device operatively connected to the input device and the output device; and a memory device operatively connected to the processor device and comprising: blocks, each block having a vertically alternating sequence of layered conductive and insulating structures arranged in layers, each block including a stepped structure having steps including horizontal ends of the layers of the block; a string of memory cells extending vertically through the blocks; a digital line structure vertically located above the blocks and coupled to the string of memory cells; and an etch-resistant material vertically located below each block and located within the blocks. Within the horizontal boundary of the stepped structure of each block in the block; lateral contact structures, which are vertically located below each block in the block and outside the horizontal boundary of the stepped structure of each block in the block, each lateral contact structure being coupled to some memory cell strings in the memory cell strings and each being directly and horizontally adjacent to some etch-resistant materials in the etch-resistant materials; at least one source structure, which is vertically located below the lateral contact structure and coupled to the lateral contact structure; and a substrate structure, which is vertically located below the at least one source structure and includes control logic devices coupled to the conductive structure, the digital line structure, and the at least one source structure of the block.

[0108] While this disclosure may take various modifications and alternatives, specific embodiments have been illustrated by way of example in the accompanying drawings and described in detail herein. However, this disclosure is not limited to the specific forms disclosed. Rather, this disclosure is intended to cover all modifications, equivalents, and alternatives falling within the scope of the appended claims and their legal equivalents. For example, elements and features disclosed with respect to one embodiment of this disclosure may be combined with elements and features disclosed with respect to other embodiments of this disclosure.

Claims

1. A method for forming a microelectronic device, the method comprising: Sacrificial material is formed above the substrate structure; Replace a portion of the sacrificial material with an etch-resistant material; A stacked structure is formed over the etch-resistant material and the remaining portion of the sacrificial material, the stacked structure comprising: Arranged in a vertical alternating sequence of layered insulating material and additional sacrificial material; and At least one stepped structure, the at least one stepped structure horizontally overlapping the etch-resistant material and having a step including the horizontal end of the layer, the remaining portion of the sacrificial material being positioned outside the horizontal boundary of the at least one stepped structure; Forming a vertically extending groove through the stacked structure and the remaining portion of the sacrificial material; and After the groove is formed, the sacrificial material and the other sacrificial material are selectively replaced with conductive material to form a lateral contact structure and a conductive structure, respectively.

2. The method of claim 1, wherein replacing a portion of the sacrificial material with an etch-resistant material comprises: The portion of the sacrificial material is removed to form an opening that extends vertically through the remaining portion of the sacrificial material; as well as The opening is filled with the etch-resistant material.

3. The method of claim 2, further comprising selecting the etch-resistant material to include at least one material that, during co-exposure to at least one etchant, has relatively greater etch resistance compared to the sacrificial material.

4. The method of claim 2, further comprising: The sacrificial material may be selected to include one of polycrystalline silicon and dielectric nitride materials; as well as The etch-resistant material is selected to include dielectric oxide materials.

5. The method of claim 1, wherein replacing a portion of the sacrificial material with an etch-resistant material comprises doping the sacrificial material with at least one chemical species to form the etch-resistant material, which has relatively greater etch resistance compared to the sacrificial material during co-exposure to at least one etchant.

6. The method of claim 5, further comprising: The sacrificial material is selected to include polycrystalline silicon; and The at least one chemical species is selected to include one or more of boron, aluminum, gallium, carbon, nitrogen, and oxygen.

7. The method of claim 5, further comprising: The sacrificial material is selected to include dielectric nitride materials; as well as Choose at least one chemical species to include one or more of carbon and oxygen.

8. The method according to any one of claims 1 to 7, wherein replacing a portion of the sacrificial material with an etch-resistant material comprises replacing a first portion of the sacrificial material to be positioned within the horizontal boundary of the at least one stepped structure with the etch-resistant material, while maintaining a second portion of the sacrificial material to be positioned within the horizontal boundary of the array of vertically extending memory cell strings to be formed within the stacked structure.

9. The method according to any one of claims 1 to 7, wherein forming the sacrificial material over the substrate structure comprises: A source layer comprising at least one conductive electrode structure is formed above the substrate structure; An isolation material is formed above the source electrode layer; A conductive contact structure is formed that extends vertically through the insulating material and reaches at least one conductive electrode structure within the source layer; as well as The sacrificial material is formed over the insulating material and the conductive contact structure.

10. The method according to any one of claims 1 to 7, further comprising forming a cell pillar structure extending vertically through the stacked structure, the cell pillar structure being positioned outside the horizontal boundary of the etch-resistant material.

11. The method of claim 10, further comprising forming additional pillar structures horizontally inserted between the cell pillar structure and the at least one stepped structure, at least some of the additional pillar structures being positioned within the horizontal boundary of the etch-resistant material.

12. The method of claim 11, wherein forming the additional pillar structure comprises forming a pseudo-pillar structure that extends vertically into, into, or beyond the etch-resistant material.

13. The method of claim 11, wherein forming the additional column structure comprises forming a conductive contact structure extending vertically to one or more additional conductive structures, the conductive contact structure being vertically inserted between the sacrificial material and the substrate structure.

14. The method according to any one of claims 1 to 7, wherein selectively replacing the sacrificial material and the additional sacrificial material with a conductive material comprises at least partially replacing the sacrificial material and the additional sacrificial material with the conductive material, without substantially replacing the etch-resistant material and the insulating material with the conductive material.

15. A microelectronic device comprising: The blocks, each having a vertically alternating sequence of layered conductive and insulating structures, each block including a stepped structure having steps at the horizontal ends of the layers; An etch-resistant material is located vertically below each of the blocks and within the horizontal boundaries of the stepped structure of each of the blocks; A lateral contact structure, wherein the lateral contact structure is vertically located below each of the blocks and outside the horizontal boundary of the stepped structure, the lateral contact structure being horizontally adjacent to the etch-resistant material and located at substantially the same vertical position as the etch-resistant material; and An additional conductive structure is located vertically below the lateral contact structure and is electrically connected to the lateral contact structure.

16. The microelectronic device of claim 15, further comprising a substrate structure vertically positioned below the additional conductive structure and including a control logic circuitry system electrically connected to at least some of the conductive structures in the additional conductive structure and at least some of the conductive structures in the block.

17. The microelectronic device of claim 16, further comprising a string of memory cells extending vertically through each of the blocks, the string of memory cells being located within the horizontal boundary of the lateral contact structure.

18. The microelectronic device of claim 17, further comprising an additional conductive structure, the additional conductive structure being vertically positioned above the block and electrically connected to the memory cell string and the control logic circuitry system.

19. The microelectronic device according to any one of claims 17 and 18, further comprising a pillar structure extending vertically through each of the blocks, the pillar structure being horizontally interposed between the memory cell string and the ladder structure within each of the blocks.

20. The microelectronic device of claim 19, wherein at least some of the pillar structures are located within the horizontal boundary of the etch-resistant material.

21. A memory device comprising: A stacked structure comprising blocks, each block having a layer, the layer comprising a conductive structure and an insulating structure vertically adjacent to the conductive structure; A stepped structure, located within the contact area of ​​each block of the stacked structure, the stepped structure having steps comprising the edges of the layers of the blocks; An etch-resistant material is located vertically below the stacked structure and within the horizontal boundary of the contact area of ​​each block of the stacked structure; An additional conductive structure is located vertically below the stacked structure and within the horizontal boundary of the memory array region of each block of the stacked structure. The additional conductive structure is horizontally adjacent to the etch-resistant material and located at substantially the same vertical position as the etch-resistant material. Vertically extending strings of memory cells are located within the memory array region of each block of the stacked structure and coupled to the additional conductive structure. as well as A substrate structure, which is vertically located below the stacked structure and includes a control logic circuitry system coupled to the vertically extending memory cell string.

22. The memory device of claim 21, further comprising: At least one source structure, the at least one source structure being vertically located below the other conductive structure and coupled to the other conductive structure; as well as A digital line structure, which is vertically positioned above the stacked structure and coupled to the vertically extending memory cell string.

23. The memory device according to any one of claims 21 and 22, wherein the additional conductive structure is confined outside the horizontal boundary of the contact region of each block of the stacked structure.

24. The memory device of claim 23, wherein the etch-resistant material is confined outside the horizontal boundary of the memory array region of each block of the stacked structure.

25. An electronic system comprising: Input device; Output device; A processor device operatively connected to the input device and the output device; as well as A memory device operatively connected to the processor device and comprising: The blocks, each having a vertically alternating sequence of layered conductive and insulating structures, each block including a stepped structure having steps at the horizontal ends of the layers of the block; A memory cell string that extends vertically through the block; A digital line structure, wherein the digital line structure is vertically positioned above the block and coupled to the memory cell string; An etch-resistant material is located vertically below each of the blocks and within the horizontal boundaries of the stepped structure of each of the blocks; Lateral contact structures, which are vertically located below each of the blocks and outside the horizontal boundary of the stepped structure of each of the blocks, are each coupled to some of the memory cell strings and are each directly and horizontally adjacent to some of the etch-resistant materials. At least one source structure, the at least one source structure being vertically located below the lateral contact structure and coupled to the lateral contact structure; and A substrate structure, the substrate structure being vertically located below the at least one source structure and including control logic devices coupled to the conductive structure, the digital line structure and the at least one source structure of the block.

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