A leakage protection circuit with automatic tripping on power failure and delayed manual reset

Abstract

The invention discloses a leakage protection circuit with automatic tripping upon power failure and delayed manual reset, comprising a power input end and a load end, wherein a controlled switch and a residual current transformer for detecting leakage signals are arranged in sequence between the power input end and the load end, a signal output end of the residual current transformer is connected to a leakage protection control chip U1, an output end of the leakage protection chip U1 is connected to a solenoid drive circuit and a delayed reset circuit, an output end of the solenoid drive circuit is connected to a solenoid L1 for controlling the on and off of the controlled switch, a power input end is connected to a power supply circuit and supplies power to the leakage protection control chip U1, the solenoid drive circuit, the delayed reset circuit and the solenoid L1 respectively, so that the solenoid is powered off when the leakage protection control chip latches and keeps outputting a power-off signal, and cannot be manually reset to connect the controlled switch to power on the load end, and the leakage protection control chip outputs a power-on signal after the delayed protection ends, so that the load end can be powered on only when the power-on signal is manually reset.

Description

[Technical field]

[0001] The invention relates to a leakage protection circuit which can automatically trip when power is off and can be manually reset after a delay. [Background Technology]

[0002] The power supply circuit in the existing leakage protection circuit generally draws power from the load end. Therefore, when leakage occurs, after the switch in the leakage protection circuit is disconnected, the power supply circuit cannot draw power, that is, the control circuit and the drive circuit are in a power-off state, and need to be reconnected to work, which poses a safety hazard; the existing leakage protection circuit does not have the function of latching the output signal of the control chip. When leakage occurs and the switch is disconnected, the switch can be immediately re-locked and connected by pressing the reset button, which poses a safety hazard in use; the existing leakage protection circuit uses a coil with a large suction force. Therefore, by slightly pressing the reset button on the leakage protector to reduce the gap between the armature and the yoke, the armature and the yoke can be attracted by the coil, and the connection switch can be easily locked and closed. [Summary of the invention]

[0003] The present invention overcomes the shortcomings of the above-mentioned technology and provides a leakage protection circuit which can automatically trip when power is off and can be manually reset with a time delay.

[0004] To achieve the above object, the present invention adopts the following technical solutions:

[0005] A leakage protection circuit with automatic tripping upon power failure and delayed manual reset comprises a power input terminal and a load terminal, wherein a controlled switch for controlling the on and off of a live wire L and a neutral wire N and a residual current transformer for detecting leakage signals are arranged in sequence between the power input terminal and the load terminal, the signal output terminal of the residual current transformer is connected to a leakage protection control chip U1 for latching and outputting a power-off signal when leakage is detected, the output terminal of the leakage protection chip U1 is connected to a solenoid drive circuit and a delayed reset circuit for delaying unlocking the power-off signal output by the leakage protection control chip U1, the output terminal of the solenoid drive circuit is connected to a solenoid L1 for controlling the on and off of the controlled switch, the power input terminal is connected to a power supply circuit for converting alternating current into direct current, and the power supply circuit supplies power to the leakage protection control chip U1, the solenoid drive circuit, the delayed reset circuit and the solenoid L1 respectively.

[0006] As described above, a leakage protection circuit with automatic tripping upon power failure and delayed manual reset is characterized in that one end of the test line passing through the residual current transformer is connected to the live wire L at the load end, and the other end of the test line passing through the residual current transformer is connected to the neutral wire N at the power input end via a resistor R1 and a test button SW1.

[0007] As described above, a leakage protection circuit with automatic tripping when power is cut off and manual reset with delay is characterized in that: the solenoid drive circuit includes a transistor Q1, the base of the transistor Q1 is connected to one end of a resistor R7 and one end of a resistor R8 respectively, the other end of the resistor R7 is connected to the output end of the leakage protection control chip U1, the emitter of the transistor Q1 and the other end of the resistor R8 are connected to the negative output end of the power supply circuit respectively, the collector of the transistor Q1 is connected to one end of the solenoid L1 as the output end of the solenoid drive circuit, and the other end of the solenoid L1 is connected to the positive output end of the power supply circuit.

[0008] The leakage protection circuit with automatic tripping upon power failure and delayed manual reset as described above is characterized in that the delayed reset circuit is a delayed reset circuit composed of a pair of MOS tubes with opposite polarities or a delayed reset circuit composed of a pair of transistors with opposite polarities.

[0009] As described above, a leakage protection circuit with automatic tripping upon power failure and delayed manual reset is characterized in that: the delayed reset circuit includes a MOS tube Q2 and a MOS tube Q3 with opposite polarities, the gate end of the MOS tube Q2 is respectively connected to one end of a resistor R11 and the output end of a leakage protection control chip U1, the other end of the resistor R11 is respectively connected to the drain end of the MOS tube Q2 and one end of a resistor R3, the other end of the resistor R3 is connected to the positive output end of a power supply circuit, the source end of the MOS tube Q2 is respectively connected to the gate end of the MOS tube Q3, one end of a resistor R10, and one end of a capacitor C2 through a resistor R9, the source end of the MOS tube Q3, the other end of the resistor R10, and the other end of the capacitor C2 are respectively connected to the negative output end of the power supply circuit, and the drain end of the MOS tube Q3 is connected to the positive output end of the power supply circuit through a resistor R4.

[0010] As described above, a leakage protection circuit with automatic tripping when power is cut off and manual reset after delay is characterized in that: the leakage protection chip U1 includes a power module and an amplification module, a comparison and judgment module, a latch and drive module connected in sequence, the input end of the power module serves as the pin 1 of the leakage protection chip U1, the pin 1 of the leakage protection chip U1 is connected to the positive output end of the power supply circuit through a resistor R4, the output end of the power module serves as the pin 2 of the leakage protection chip U1, the pin 2 of the leakage protection chip U1 is connected to the negative output end of the power supply circuit, the in-phase input end of the amplification module serves as the pin 1 of the leakage protection chip U1 6. Pin 6 of the leakage protection chip U1 is connected to a signal output end of the residual current transformer. The inverting input end of the amplifying module serves as pin 5 of the leakage protection chip U1. Pin 5 of the leakage protection chip U1 is respectively connected to another signal output end of the residual current transformer and one end of the resistor R6. The output end of the amplifying module serves as pin 4 of the leakage protection chip U1. Pin 4 of the leakage protection chip U1 is connected to the other end of the resistor R6. The output end of the latch and driving module serves as pin 3 of the leakage protection chip U1. Pin 3 of the leakage protection chip U1 is also used as the output end to be connected to the solenoid driving circuit and the delay reset circuit respectively.

[0011] A leakage protection circuit with automatic tripping upon power failure and delayed manual reset as described above is characterized in that: the power supply circuit includes a rectifier bridge DB1, pin 1 of the rectifier bridge DB1 is connected to the neutral line N of the power input terminal, pin 3 of the rectifier bridge DB1 is connected to the live line L of the power input terminal through a resistor R2, pin 3 of the rectifier bridge DB1 is connected to the positive terminal of the electrolytic capacitor C1, pin 4 of the rectifier bridge DB1 is connected to the negative terminal of the electrolytic capacitor C1, and the positive terminal and negative terminal of the electrolytic capacitor C1 serve as the positive output terminal and negative output terminal of the power supply circuit respectively.

[0012] The beneficial effects of the present invention are:

[0013] 1. The power supply circuit in the present invention draws power from the power input terminal. Therefore, when the controlled switch is disconnected and the load terminal is powered off when leakage is detected, the power supply circuit can still draw power from the power input terminal, so that the leakage protection control chip U1 and the solenoid drive circuit remain in the powered working state, realizing continuous leakage detection and leakage protection function, thereby improving safety of use.

[0014] 2. The leakage protection control chip in the present invention is provided with a function of latching the output signal. When leakage is detected, the leakage protection control chip outputs a power-off signal and latches and maintains the output power-off signal, so that the solenoid is powered off and cannot be manually reset to connect the controlled switch, thereby putting the load end in a power-off state.

[0015] 3. The present invention is provided with a delayed reset circuit. When leakage occurs and the leakage protection control core latches and keeps outputting a power-off signal, the capacitor C2 in the delayed reset circuit discharges through the resistor R10. After the discharge, the leakage protection control chip is powered off and unlocked. At this time, the leakage protection control core does not output a signal after power is turned on again. After power is turned on again, the leakage protection control core outputs a power-on signal and waits for the next manual pressing of the reset button to cause the solenoid to attract the armature and the yoke and connect the controlled switch. The resistor R10 and the capacitor C2 determine the delay duration.

[0016] 4. The time-delay reset circuit in the present invention is a time-delay reset circuit composed of a pair of MOS tubes with opposite polarities or a time-delay reset circuit composed of a pair of transistors with opposite polarities, and has a simple structure.

[0017] 5. In the present invention, the disengagement coil is replaced by a solenoid. Since the gap between the armature and the yoke is large and the suction force of the solenoid is weak, when the solenoid is energized, there is not enough suction force to make the armature and the yoke fit together. A large manual reset external thrust is required to reduce the gap between the armature and the yoke until the armature and the yoke fit together. Thereafter, the external thrust is canceled and the suction force of the solenoid is relied on to keep the armature and the yoke fit together, so that the controlled switch can be closed and connected, thereby improving the safety of use. [Drawings]

[0018] Figure 1 It is a schematic diagram of the circuit structure of the present invention. [Specific implementation method]

[0019] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. In addition, the descriptions of "preferred", "sub-preferred", etc. in the present invention are only used for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "preferred" or "sub-preferred" may explicitly or implicitly include at least one such feature.

[0021] like Figure 1 As shown, a leakage protection circuit with automatic tripping when power is cut off and delayed manual reset includes a power input terminal 1 and a load terminal 2, wherein a controlled switch 3 for controlling the on and off of a live wire L and a neutral wire N, and a residual current transformer 4 for detecting a leakage signal are arranged in sequence between the power input terminal 1 and the load terminal 2, wherein the signal output terminal of the residual current transformer 4 is connected to a leakage protection control chip U1 for latching and outputting a power-off signal when leakage is detected, the output terminal of the leakage protection chip U1 is connected to a solenoid drive circuit 5, and a delayed reset circuit 6 for delaying unlocking the output power-off signal of the leakage protection control chip U1, the output terminal of the solenoid drive circuit 5 is connected to a solenoid L1 for controlling the on and off of the controlled switch 3, the power input terminal 1 is connected to a power supply circuit 7 for converting AC power into DC power, and the power supply circuit 7 supplies power to the leakage protection control chip U1, the solenoid drive circuit 5, the delayed reset circuit 6, and the solenoid L1 respectively.

[0022] In the initial state, the power supply circuit 7 draws power from the power input terminal 1, and supplies power to the leakage protection control chip U1 and the solenoid drive circuit 5 respectively. After power-on, the leakage protection control chip U1 outputs a power-on signal to control the solenoid drive circuit 5 to energize the solenoid L1. When the manual reset pushes the armature and the yoke to close and connect the controlled switch 3, the solenoid L1 attracts the fitted armature and the yoke to keep the controlled switch 3 closed and connected. At the same time, the power supply circuit 7 charges the delay reset circuit 6; when the residual current transformer 4 detects leakage, the leakage protection control chip U1 outputs a power-off signal and latches and maintains the output power-off signal, so that the solenoid drive circuit 5 is powered off, thereby powering off the solenoid L1. At this time, the solenoid L1 loses its suction force, and the armature and the yoke are separated under the action of the reverse spring, so that the controlled switch 3 is disconnected; at the same time, the delayed reset circuit 6 realizes the delayed reset protection function by discharging. During the delayed protection process, the leakage protection control chip U1 continuously outputs a power-off signal, and the solenoid L1 is in a power-off state and cannot attract the armature and the yoke. Therefore, the controlled switch 3 cannot be closed and energized by manual reset. After the delay protection ends, the leakage protection control chip U1 is powered off and does not output a control signal until the leakage protection control chip U1 is powered on again and outputs a power-on signal, waiting for the next manual pressing of the reset button to make the solenoid L1 attract the armature and the yoke and connect the controlled switch 3.

[0023] like Figure 1 As shown, one end of the test line passing through the residual current transformer 4 is connected to the live wire L of the load terminal 2, and the other end of the test line passing through the residual current transformer 4 is connected to the neutral wire N of the power input terminal 1 through the resistor R1 and the test button SW1. The leakage condition is simulated for testing by pressing the test button SW1.

[0024] like Figure 1 As shown, the circuit structure of the solenoid driving circuit 5 includes a transistor Q1, the base of the transistor Q1 is connected to one end of a resistor R7 and one end of a resistor R8 respectively, the other end of the resistor R7 is connected to the output end of the leakage protection control chip U1, the emitter of the transistor Q1 and the other end of the resistor R8 are connected to the negative output end of the power supply circuit 7 respectively, the collector of the transistor Q1 is connected to one end of the solenoid L1 as the output end of the solenoid driving circuit 5, and the other end of the solenoid L1 is connected to the positive output end of the power supply circuit 7.

[0025] like Figure 1As shown, the circuit structure of the delay reset circuit 6 includes a MOS transistor Q2 and a MOS transistor Q3 with opposite polarities, the gate end of the MOS transistor Q2 is respectively connected to one end of the resistor R11 and the output end of the leakage protection control chip U1, the other end of the resistor R11 is respectively connected to the drain end of the MOS transistor Q2 and one end of the resistor R3, the other end of the resistor R3 is connected to the positive output end of the power supply circuit 7, the source end of the MOS transistor Q2 is respectively connected to the gate end of the MOS transistor Q3, one end of the resistor R10, and one end of the capacitor C2 through the resistor R9, the source end of the MOS transistor Q3, the other end of the resistor R10, and the other end of the capacitor C2 are respectively connected to the negative output end of the power supply circuit 7, and the drain end of the MOS transistor Q3 is connected to the positive output end of the power supply circuit 7 through the resistor R4.

[0026] like Figure 1 As shown, the leakage protection chip U1 includes a power module and an amplification module, a comparison and determination module, a latch and drive module connected in sequence. The input end of the power module serves as the pin 1 of the leakage protection chip U1. The pin 1 of the leakage protection chip U1 is connected to the positive output end of the power supply circuit 7 through a resistor R4. The output end of the power module serves as the pin 2 of the leakage protection chip U1. The pin 2 of the leakage protection chip U1 is connected to the negative output end of the power supply circuit 7. The in-phase input end of the amplification module serves as the pin 6 of the leakage protection chip U1. The pin 6 of the leakage protection chip U1 is connected to the remaining A signal output end of the current transformer 4 is connected, the inverting input end of the amplifier module serves as the pin 5 of the leakage protection chip U1, and the pin 5 of the leakage protection chip U1 is respectively connected to the other signal output end of the residual current transformer 4 and one end of the resistor R6. The output end of the amplifier module serves as the pin 4 of the leakage protection chip U1, and the pin 4 of the leakage protection chip U1 is connected to the other end of the resistor R6. The output end of the latch and drive module serves as the pin 3 of the leakage protection chip U1, and the pin 3 of the leakage protection chip U1 is also used as the output end to be connected to the solenoid drive circuit 5 and the delay reset circuit 6 respectively.

[0027] like Figure 1 As shown, the circuit structure of the power supply circuit 7 includes a rectifier bridge DB1, pin 1 of the rectifier bridge DB1 is connected to the neutral line N of the power input terminal 1, pin 3 of the rectifier bridge DB1 is connected to the live line L of the power input terminal 1 through a resistor R2, pin 3 of the rectifier bridge DB1 is connected to the positive terminal of the electrolytic capacitor C1, pin 4 of the rectifier bridge DB1 is connected to the negative terminal of the electrolytic capacitor C1, and the positive terminal and negative terminal of the electrolytic capacitor C1 serve as the positive output terminal and negative output terminal of the power supply circuit 7 respectively.

[0028] like Figure 1As shown, after the power input terminal 1 is connected to the mains, the AC power supply is limited by the resistor R2 in the power supply circuit 7 and rectified by the rectifier bridge DB1, and a DC voltage V is output at both ends of the electrolytic capacitor C1; the DC voltage V supplies power to the power module of the leakage protection chip U1 through the resistor R4. After the leakage protection chip U1 is powered on, the latch and drive module outputs a high level. At this time, the high level output by the latch and drive module passes through the resistor R7 in the solenoid drive circuit 5 to turn on the triode Q1, and the solenoid L1 is energized and generates suction. At this time, the manual reset When the armature and the yoke are pushed and closed to connect the controlled switch 3, the solenoid L1 attracts the fitted armature and the yoke to keep the controlled switch 3 connected and energize the load end 2; at the same time, the high level output by the latch and drive module turns on the MOS tube Q2 in the delay reset circuit 6, and the DC voltage V charges the capacitor C2 through the resistor R3, the MOS tube Q2, and the resistor R9. On the other hand, the MOS tube Q3 is in the cut-off state, so that the power supply voltage of the power supply module in the leakage protection chip U1 remains unchanged, and the latch and drive module keeps outputting a high level.

[0029] When the residual current transformer 4 detects a leakage signal, it is sent to the amplification module in the leakage protection chip U1, and after being processed by the comparison and judgment module, it outputs a low level through the latch and drive module and latches to maintain the output low level. At this time, the transistor Q1 in the solenoid drive circuit 5 is cut off, the solenoid L1 is powered off and loses its suction force, and the armature and the yoke are separated under the action of the reverse spring, so that the controlled switch 3 is disconnected. When the latch and drive module latches and maintains the output low level, the solenoid L1 is always in a power-off state and cannot attract the armature and the yoke. Therefore, the controlled switch 3 cannot be closed and energized by manual reset.

[0030] When the latch and drive module outputs a low level and latches to maintain the output of the low level, the MOS tube Q2 in the delay reset circuit 6 is turned off, and the capacitor C2 discharges through the resistor R10. During the discharge process, the latch and drive module is in a state of latching and maintaining the output of the low level; after the discharge is completed, the transistor Q3 is turned on, and the power module in the leakage protection chip U1 is powered off. At this time, the latch and drive module does not output a level signal, so that the MOS tube Q2 is turned on, and the MOS tube Q3 is turned off. The DC voltage V re-powers the power module of the leakage protection chip U1 through the resistor R4. At this time, the latch and drive module outputs a high level, so that the triode Q1 in the solenoid drive circuit 5 is turned on, and the solenoid L1 is energized and generates suction, waiting for the next manual pressing of the reset button to make the solenoid L1 attract the armature and the yoke and connect the controlled switch 3. At the same time, the MOS tube Q2 in the delay reset circuit 6 is turned on, so that the capacitor C2 is charged, and prepares for the delayed reset protection when the leakage power is off next time.

[0031] In this case, the delay reset circuit 6 is a delay reset circuit composed of a pair of MOS tubes with opposite polarities or a delay reset circuit composed of a pair of transistors with opposite polarities; the resistor R10 and the capacitor C2 in the delay reset circuit 6 determine the delay time.

[0032] Figure 1 After the leakage protection chip U1 is powered on, the output end of the leakage protection chip U1 outputs a high level. After detecting a leakage fault, the output is a low level. The control chip whose output logic is opposite to that of the leakage protection chip U1 in this case is also applicable to the principle of this circuit. It only requires changing the polarity of the transistor Q1, the MOS tube Q2 and the MOS tube Q3.

[0033] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. All equivalent structural changes made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or directly or indirectly applied in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A leakage protection circuit with automatic tripping upon power failure and delayed manual reset, characterized in that: The invention comprises a power input terminal (1) and a load terminal (2), wherein a controlled switch (3) for controlling the on and off of a live wire L and a neutral wire N and a residual current transformer (4) for detecting a leakage signal are arranged in sequence between the power input terminal (1) and the load terminal (2), wherein the signal output terminal of the residual current transformer (4) is connected to a leakage protection control chip U1 for latching and outputting a power-off signal when leakage is detected, the output terminal of the leakage protection chip U1 is connected to a solenoid drive circuit (5), and a time-delay reset circuit (6) for delaying unlocking the power-off signal output by the leakage protection control chip U1, and the output terminal of the solenoid drive circuit (5) is connected to a solenoid L for controlling the on and off of the controlled switch (3). 1, a power supply input end (1) is connected to a power supply circuit (7) for converting alternating current into direct current, the power supply circuit (7) supplies power to a leakage protection control chip U1, a solenoid drive circuit (5), a delay reset circuit (6), and a solenoid L1 respectively, the delay reset circuit (6) comprises a MOS tube Q2 and a MOS tube Q3 with opposite polarities, the gate end of the MOS tube Q2 is respectively connected to one end of a resistor R11 and the output end of the leakage protection control chip U1, the other end of the resistor R11 is respectively connected to the drain end of the MOS tube Q2 and one end of the resistor R3, the other end of the resistor R3 is respectively connected to the positive output end of the power supply circuit (7), the source end of the MOS tube Q2 is respectively connected to the gate end of the MOS tube Q3 and the resistor R9. The source end of the MOS tube Q3, the other end of the resistor R10, and the other end of the capacitor C2 are respectively connected to the negative output end of the power supply circuit (7), and the drain end of the MOS tube Q3 is connected to the positive output end of the power supply circuit (7) through the resistor R4; the leakage protection chip U1 includes a power module and an amplification module, a comparison and determination module, and a latch and drive module connected in sequence; the input end of the power module serves as the pin 1 of the leakage protection chip U1, the pin 1 of the leakage protection chip U1 is connected to the positive output end of the power supply circuit (7) through the resistor R4, the output end of the power module serves as the pin 2 of the leakage protection chip U1, and the pin 2 of the leakage protection chip U1 is connected to the negative output end of the power supply circuit (7). The same-phase input end of the amplifying module is used as the pin 6 of the leakage protection chip U1, and the pin 6 of the leakage protection chip U1 is connected to a signal output end of the residual current transformer (4). The inverting input end of the amplifying module is used as the pin 5 of the leakage protection chip U1, and the pin 5 of the leakage protection chip U1 is respectively connected to the other signal output end of the residual current transformer (4) and one end of the resistor R6. The output end of the amplifying module is used as the pin 4 of the leakage protection chip U1, and the pin 4 of the leakage protection chip U1 is connected to the other end of the resistor R6. The output end of the latch and driving module is used as the pin 3 of the leakage protection chip U1, and the pin 3 of the leakage protection chip U1 is also used as the output end to be respectively connected to the solenoid driving circuit (5) and the delay reset circuit (6).

2. A leakage protection circuit with automatic tripping upon power failure and delayed manual reset according to claim 1, characterized in that: One end of the test line passing through the residual current transformer (4) is connected to the live wire L of the load end (2), and the other end of the test line passing through the residual current transformer (4) is connected to the neutral wire N of the power input end (1) through the resistor R1 and the test button SW1.

3. A leakage protection circuit with automatic tripping upon power failure and delayed manual reset according to claim 1, characterized in that: The solenoid drive circuit (5) comprises a transistor Q1, the base of the transistor Q1 is respectively connected to one end of a resistor R7 and one end of a resistor R8, the other end of the resistor R7 is connected to the output end of a leakage protection control chip U1, the emitter of the transistor Q1 and the other end of the resistor R8 are respectively connected to the negative output end of a power supply circuit (7), the collector of the transistor Q1 is connected to one end of a solenoid L1 as the output end of the solenoid drive circuit (5), and the other end of the solenoid L1 is connected to the positive output end of the power supply circuit (7).

4. A leakage protection circuit with automatic tripping upon power failure and delayed manual reset according to claim 1, characterized in that: The time-delay reset circuit (6) is a time-delay reset circuit composed of a pair of MOS tubes with opposite polarities or a time-delay reset circuit composed of a pair of triodes with opposite polarities.

5. The leakage protection circuit with automatic tripping upon power failure and delayed manual reset according to claim 1, characterized in that: The power supply circuit (7) includes a rectifier bridge DB1, wherein pin 1 of the rectifier bridge DB1 is connected to a neutral line N of a power input terminal (1), pin 3 of the rectifier bridge DB1 is connected to a live line L of a power input terminal (1) via a resistor R2, pin 3 of the rectifier bridge DB1 is connected to a positive terminal of an electrolytic capacitor C1, pin 4 of the rectifier bridge DB1 is connected to a negative terminal of the electrolytic capacitor C1, and the positive terminal and negative terminal of the electrolytic capacitor C1 serve as a positive output terminal and a negative output terminal of the power supply circuit (7), respectively.

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