Fixed frequency DC-DC converters

Abstract

The present application relates to a fixed frequency DC-DC converter. In a power converter system (200), a circuit system (240) generates a first PWM signal and a second PWM signal during a PWM period for controlling the application of power to an inductor. The circuit system (210) generates an error signal having an AC component and a DC component. The error signal is generated in response to an indication of power applied to or generated by the inductor. The circuit system (230) generates a feedback control signal in response to the error signal. The first PWM signal and the second PWM signal are controlled in response to the feedback control signal.

Description

[0001] This application is a divisional application of Chinese patent application No. 201880013387.0, entitled “Fixed Frequency DC-DC Converter”, filed on February 26, 2018. Background Art

[0002] Electronic devices are increasingly used in a wider variety of applications, requiring switching power supplies to operate more efficiently and effectively over an increasingly wide range of conditions. The control circuitry of some power supplies is optimized to have a wide stability range. However, control circuitry optimized for maintaining stability over a wide range of conditions may have a slower ability to respond to fast transients in DC (direct current) loads. Conversely, control circuitry optimized for responding to fast transients may have lower stability and often emit relatively high amounts of EMI when responding to fast transients. Summary of the Invention

[0003] In a power converter system, circuitry generates first and second PWM signals during a PWM period for controlling the application of power to an inductor. The circuitry generates an error signal having an AC component and a DC component, the error signal being generated in response to an indication of power applied to or generated by the inductor. The circuitry generates a feedback control signal in response to the error signal. The first and second PWM signals are controlled in response to the feedback control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a schematic diagram of a buck converter system with direct amplified ramp tracking control according to the present disclosure.

[0005] Figure 2 is a schematic diagram of a direct-amplification ramp-tracking converter according to the present disclosure.

[0006] Figure 3 is a schematic diagram of an integrator for directly amplified ramp tracking according to the present disclosure.

[0007] Figure 4 is a spectrum diagram of the frequency response of an integrator for direct amplified ramp tracking according to the present disclosure.

[0008] Figure 5A is a functional diagram of a gain and level shifter for direct amplified ramp tracking according to the present disclosure.

[0009] Figure 5B is a schematic diagram of a differential difference amplifier based gain and level shifter for direct amplified ramp tracking according to the present disclosure.

[0010] Figure 5Cis a schematic diagram of a transconductance-based gain and level shifter for direct amplified ramp tracking according to the present disclosure.

[0011] Figure 6A is a functional diagram of a transient feed-forward circuit for directly amplified ramp tracking according to the present disclosure.

[0012] Figure 6B is a schematic diagram of a transient feed-forward circuit based on a differential difference amplifier for directly amplifying ramp tracking according to the present disclosure.

[0013] Figure 6C is a schematic diagram of a transconductance-based transient feed-forward circuit for directly amplified ramp tracking according to the present disclosure.

[0014] Figure 7 is a functional diagram of a ramp loop circuit for direct amplified ramp tracking according to the present disclosure.

[0015] Figure 8 is a schematic diagram of a switching circuit sample-and-hold current information generator for direct amplified ramp tracking according to the present disclosure.

[0016] Figure 9 is a schematic diagram of a loop comparator for directly amplified slope tracking according to the present disclosure.

[0017] Figure 10 is a schematic diagram of a pulse width modulation logic circuit for direct amplified ramp tracking according to the present disclosure.

[0018] Figure 11 is a waveform diagram of selected waveforms in steady-state operation of a direct amplified ramp tracking converter according to the present disclosure.

[0019] Figure 12 is a waveform diagram of a combined waveform of a direct amplified ramp tracking converter according to the present disclosure.

[0020] Figure 13 is a waveform diagram of a combined waveform in response to a load increase of a directly amplified ramp tracking converter according to the present disclosure.

[0021] Figure 14 is a waveform diagram of a combined waveform in response to a load reduction of a directly amplified ramp tracking converter according to the present disclosure.

[0022] Figure 15 is a waveform diagram of waveforms in response to a load increase followed by a load decrease of a direct amplified ramp tracking converter according to the present disclosure. DETAILED DESCRIPTION

[0023] Example embodiments respond quickly to transients while providing relatively stable operation and minimizing EMI emissions.

[0024] A DC-DC power converter controls (e.g., switches on and off) the application of input power to an inductive component so that a current greater than the input power can be output. The application of input power to the inductive component is switched on and off according to a switching frequency, which can be fixed or variable. Fixed-frequency converters include true fixed-frequency converters (in which the switching frequency remains fixed) and pseudo fixed-frequency converters (in which the switching frequency can be changed to respond to transient load conditions).

[0025] A DC-DC power converter may include compensation circuitry for responding to transient load conditions (e.g., for maintaining a constant output voltage as the applied load changes). Internal compensation circuitry may be implemented entirely within the package of the DC-DC power converter, while external compensation circuitry requires external components.

[0026] Fixed-frequency power converters with internal compensation can operate according to peak current mode control techniques. However, fixed-frequency power converters with internal compensation can be relatively slow in responding to fast transient load conditions. The lack of external compensation components (often omitted due to size, cost, and power considerations) can limit the stability range of the compensation circuit and the speed at which the internal loop compensation and slope compensation circuits can respond to fast transient (e.g., rapidly changing) load conditions. In addition, due to the difficulties associated with measuring large load currents, internally compensated fixed-frequency power converters are generally limited to small load current applications.

[0027] Pseudo-fixed frequency converters can operate according to constant on-time (or hysteresis) control of a feedback-based phase-locked loop (PLL) circuit. Pseudo-fixed frequency converters can also operate according to internal compensation and / or external compensation. Internally compensated pseudo-fixed frequency converters can respond to fast transient load conditions by changing the switching frequency. However, changing the switching frequency typically results in additional electromagnetic interference (EMI) radiation, which increases electrical noise and reduces the signal-to-noise ratio. In compensation circuits designed for wide loop bandwidth operation, changing the switching frequency typically causes jitter in the switching frequency, which contributes to EMI emission.

[0028] In portable applications (such as handheld applications or automotive applications), relatively high switching frequencies are used to reduce the size and weight of fixed frequency power converters. However, the switching speed of fixed frequency converters can be limited by switching noise and architectural limitations. For example, the high current / low R dsonLatency is caused by the noise blanking time of the (drain-source on-resistance) sensing, loop comparator response time, and driver (e.g., for switching input power) propagation delay. This latency often limits the overall frequency at which the converter can operate. For example, the overall frequency limit can limit the switching frequency of a fixed-frequency converter to less than about 3 MHz.

[0029] In contrast, direct amplified ramp tracking (DART) control for fixed-frequency operation of the power converter described herein allows true fixed-frequency power converter operation to respond to fast transient load conditions while relying on internal compensation control even at relatively high load currents. For example, a fixed-frequency power converter operating according to the described DART control method can operate at high switching frequencies greater than approximately 3 MHz or 4 MHz.

[0030] Figure 1 is a schematic diagram of a buck converter system (generally referred to as 100) with direct amplified ramp tracking control according to an example of the present disclosure. Figure 1 In FIG. 1 , the DART converter 110 is an internally compensated controller that is used to control the operation of the buck converter system 100 .

[0031] In operation, the DART converter 110 receives an input signal V IN The DART converter 110 responds to the input signal V IN And in response to the feedback voltage signal V FB Generates the switching output power signal V SW . Switch output power signal V SW is arranged to regulate the generated output voltage V out . Switch output power signal V SW is coupled to the coil L O The first terminal of the coil L O For example, it is used to switch the output power signal V SW The voltage of the coil L is converted into O a second voltage at the second terminal of the inductor.

[0032] Coil L O The second voltage output at the second terminal of the capacitor C out Low-pass filtering to generate the output voltage V out Load R load receives the regulated output voltage V out The current I O However, the load R loaddynamic changes (such as when generating fast transient load conditions), which changes the voltage V out . It consists of a series of R s1 and R s2 The voltage divider formed generates the signal V FB (at the center node) to provide a voltage V out The optional feed-forward capacitor C FF Can be used with R s1 Parallel coupling to increase the voltage V out The change in the indication of the control circuit system within the DART converter 110 (e.g., reference below) Figure 2 discussion) conversion rate.

[0033] Thus, the DART converter 110 can operate with or without external compensation components and can use (e.g., only) one voltage regulation control loop input pin (e.g., for coupling an externally generated feedback voltage V FB , which can reduce packaging costs) to adjust the voltage V out Reducing the number of required external components can reduce system cost and overall size. Reducing the number of required external components can also simplify the end-use design of the packaged DART converter 110.

[0034] Figure 2 is a schematic diagram of an example direct-amplification ramp tracking converter (generally referred to as 200) according to the present disclosure. Figure 2 , an example DART converter 200 (which is similar to DART converter 110) is generally described as including a voltage loop 210 circuit, a loop comparator 220, a ramp loop 230 circuit, a PWM logic 240 circuit, a fixed frequency oscillator 250, a driver 260, a switching circuit 270, a sample / hold 280 circuit, and a DC current feedback indicator generator 290. The components of DART converter 200 can be formed on a single substrate (e.g., coextensive with 200). Alternatively, converter 200 can be implemented with a DART controller integrated circuit (IC) and external switching circuit 270 (i.e., an external switching transistor), wherein the DART controller IC includes a driver output terminal for driving the switching circuit.

[0035] The voltage loop 210 circuit and the ramp loop 230 circuit are each arranged to optimize the AC (alternating current) component and the DC (direct current) component of the control signal used to internally generate the feedback control signal (e.g., presented at the output of the loop comparator 220). The control signal is coupled for controlling the switching of the external inductor (e.g., via the output signal V SW ).

[0036] The example voltage loop 210 circuit responds to an externally generated VFB The voltage loop 210 circuit includes a DC portion that is optimized for generating a higher gain and very slow slew rate control signal (e.g., V as discussed below). REF-INT signal and V ctrl signal, as described below.) The voltage loop 210 circuit also includes an AC portion for generating a high slew rate and relatively limited gain control signal (eg, a voltage feed-forward VTFF signal, also discussed below).

[0037] The voltage loop 210 circuit includes a transient feed-forward 212 circuit, a gain and level shifter 214, and an integrator 216. Typically, the voltage loop 210 circuit feeds back a voltage signal V FB With the voltage reference signal V REF The comparison is performed to generate a control signal (eg, V TFF 、V COM and V crtl ).

[0038] The transient feed forward 212 circuit responds to the signal V FB and signal V REF Generate signal V TFF and signal V COM The transient feedforward 212 circuit compares V FB and V REF To generate the V FB signal and V REF The first error signal is amplified with a fixed gain between about 500% and about 1000%. The first amplified error signal is high-pass filtered to generate V TFF The transient feed forward block improves the response of the DART converter 200 to fast transient load conditions by quickly providing high frequency information to the loop comparator 220 for immediate processing. Figure 6A 、 Figure 6B and Figure 6C The transient feed forward 212 circuit is further described.

[0039] Signal V COM is a DC voltage reference signal that can be generated by a voltage divider to generate a voltage between the upper and lower analog power rails. When the generated voltage is exactly halfway between the upper and lower analog power rails (e.g., their average), it is equal to the signal V COM Compared to this the dynamic range of the generated signal is optimized.

[0040] Integrator 216 integrates V FBand V REF The difference between the two and generates the signal V REF-INT Integrator 216 operates according to a long time constant to reduce, if not actually eliminate, DC output voltage errors in a system such as system 100. For example, V FB The decrease of the signal causes the signal V REF-INT It rises according to a time constant determined in response to an input resistor (eg, 5 MΩ) and a feedback capacitor (eg, 20 pF).

[0041] The gain and level shifter 214 responds to V FB signal and V REF-INT Signal Generation V crtl signal. The gain and level shifter 214 senses V FB signal and V REF-INT The difference between the signals is used to generate a second error signal (eg, which is responsive to V FB The second error signal is amplified with a fixed gain of about 500% to about 1000%. The second amplified error signal is normalized (eg, level shifted) based on a fixed common voltage to generate V for output. crtl Signal.

[0042] Refer to the following Figure 5A 、 Figure 5B and Figure 5C The gain and level shifter 214 is further described.

[0043] The ramp loop 230 circuit responds to the input voltage V IN The ramp loop 230 circuit includes an AC component portion for generating a first error signal (of the ramp loop 230 circuit), which is used to increase the stability of the loop feedback and minimize switching jitter. The ramp loop 230 circuit also includes a DC component portion optimized for generating a second error signal, which is used for slope compensation. The second error signal includes a low DC offset, which reduces the speed requirement for integrating the second error signal.

[0044] The ramp loop 230 circuit includes a ramp generator 232 and a slope compensation 234 circuit. The ramp loop 230 circuit responds to V IN and PWM INT Generates a ramp voltage signal V RAMP (For example, refer to Figure 11-Figure 15 Signal V for discussion RAMP Sum signal PWM INT ). When PWM INT When the duty cycle is greater than 50%, slope compensation function can also be provided.

[0045] The ramp generator 232 is based on the voltage V IN Change V SLOPE (For example, refer to Figure 11 Signal V for discussion SLOPE ) of the ramp. The voltage VIN is an indication of the power applied to the switching inductor. When the signal PWM INT When high, the signal V RAMP rises to its peak amplitude (during the rising edge). INT When it is low, the signal V RAMP Falling (during the falling edge).

[0046] The slope compensation 234 circuit generates V SLOPE signal and V S / H Signal. V SLOPE The signal is a sawtooth waveform with a rising slope of about 80 mV / μs and a nearly vertical falling slope. S / H The signal is generated in response to the DISCHARGE signal and the S / H signal generated by the PWM logic 240 circuit. Figure 7 As described, RAMP Low-pass filtering is performed to generate V SLOPE , and in response to the S / H signal, each PWM cycle is applied to V SLOPE Sampling is performed to generate V S / H Signal.

[0047] Refer to the following Figure 7 The ramp loop 230 circuit (as well as the ramp generator 232 and slope compensation 234 circuits) is further described.

[0048] The loop comparator 220 combines each input signal (e.g., each error signal) and generates a feedback control signal that indicates when to terminate the PWM cycle. When the sum of the positive inputs to the loop comparator 220 is higher than the sum of the negative inputs to the loop comparator 220, the indication to terminate the PWM cycle becomes valid. Figure 9 The operation of loop comparator 220 is discussed.

[0049] The PWM logic 240 circuit is responsive to a feedback control signal that indicates when to terminate the PWM cycle. The PWM logic 240 circuit generates the PWM INT signal (the “internal” PWM signal used to control the ramp generator 232) and generate the PWM EXT The PWM is generated in response to the system clock (generated by the fixed frequency oscillator 250) and the indication output by the loop comparator 220 (e.g., the feedback control signal) for terminating the PWM cycle.INT Signal and PWM EXT Signal. Refer to the following Figure 10 The PWM logic 240 circuit is further described.

[0050] The (e.g., fixed frequency) oscillator 250 is arranged to generate a (e.g., fixed frequency) clock signal. The control signal generated by the PWM logic 240 circuit is synchronized with respect to the clock signal. Although electrical noise (e.g., EMI) is generated by varying the frequency of the oscillator 250, embodiments are contemplated in which the operating frequency of the oscillator can be varied (e.g., so that the frequency of the clock signal can be varied). In various examples, the DART converter can be used to respond to an external oscillator and / or a pseudo fixed frequency oscillator, although higher EMI levels may ensue.

[0051] The switch circuit 270 responds to the PWM EXT signal to provide (eg, apply) current through the high-side transistor to energize the external coil (eg, Figure 1 Coil L O , which is coupled to node V SW ) and provides current through the low-side transistor to energize the external coil. In continuous operation mode, the current in the coil will not reach zero level at any point in the PWM switching cycle. Refer to the following Figure 8 The switching circuit 270 is further described.

[0052] The current provided by the low-side transistor of the switching circuit 270 can be measured to provide a current load (e.g., Figure 1 The current I O The sample / hold circuit 280 is arranged to sample the voltage generated across the lower transistor during the noise blanking time. The sampled voltage is based on the R dson (Drain-source on-resistance) The voltage developed across the drain-source terminals of the lower transistor. The sample / hold circuit is arranged to hold the sampled voltage constant during each PWM switching cycle. The DC current feedback indicator generator 290 is arranged to generate a signal DCI (direct current indication). The loop comparator 220 can use the signal DCI to generate an indication for terminating the PWM cycle (as described below with reference to Figure 9 discussed).

[0053] Figure 3 is a schematic diagram of an example integrator (generally referred to as 300) for direct amplified ramp tracking according to the present disclosure. Figure 3 , an example integrator 300 (which is similar to integrator 216) is generally described as including a differential amplifier 310 (AMP ERROR ). The differential amplifier 310 includes a first gm (Transconductance) amplifier 312 and the second g m Amplifier 314. First g m Amplifier 312 and second g m The outputs of amplifiers 314 are added together and buffered by unity gain buffer 316 (X1). The output of buffer 316 is the output signal V of differential amplifier 312. REF-INT .

[0054] The differential difference amplifier 310 is arranged as a four-input error amplifier, which is arranged as an integrator. m The amplifier 312 includes a non-inverting input V1 and an inverting input V2. m Amplifier 312 responds to resistor R int (integrator resistor) and capacitor C int (integrator capacitor) and the output of the differential amplifier 310, the feedback voltage V FB and reference voltage V REF Integrate the difference.

[0055] Second g m Amplifier 314 includes a non-inverting input V3 and an inverting input V4. m The amplifier 314 responds to the reference voltage V REF (coupled to node V3 via buffer 320) and in response to the resistor R K1 , resistor R K2 and resistor R DCM The feedback resistor network controls the integrator gain. Buffer 320 converts V REF Signal and R K1 and R k2 The resistor R DCM In response to the selection signal DCM, the resistor R K2 During discontinuous mode operation, the selection signal DCM is activated to reduce the feedback resistor R K2 To reduce the integral result V REF-INT Reducing the gain of integrator 300 helps, for example, prevent integrator 300 from saturating during long periods of time that occur when the power stage is in tri-state.

[0056] In various examples where the DCM function is not required, the DCM selection signal terminal can be eliminated so that the resistor R k2 is constant and the integrator 300 has a fixed gain.

[0057] The differential difference amplifier 310 includes a V1 input, a V2 input, a V3 input, and a V4 input, such that:

[0058] V1-V2=V4-V3 (1)

[0059] And, solve V4:

[0060] V4=2V REF -V2 (2)

[0061] For V2 and V4, respectively:

[0062]

[0063]

[0064] Therefore, the AC response (eg, transfer function) of integrator 300 is:

[0065]

[0066] in,

[0067]

[0068] And s is the Laplace operator.

[0069] Figure 4 is an example spectrum plot of the frequency response of an integrator for direct amplified ramp tracking according to the present disclosure. Figure 4 A frequency spectrum graph (generally referred to as 400) is shown. Curve 402 shows the gain (e.g., in dB) over frequency (e.g., DC to 1 GHz). At lower frequencies (e.g., approximately 10 Hz), the gain varies from approximately 23 dB for a value of k of 15 to approximately 34 dB for a value of k of 50, where k is the output resistor R of the integrator 300. k2 With the input resistor R K1 ratio.

[0070] The DC gain of the integrator 300 is a function of k, which is a function of the resistor R k1 The value of the resistor R k2 The value of k is selected to provide sufficient (but not excessive) gain to offset system losses without requiring excessive gain (which might increase disturbances in the main fast control loop). The "zero" of the integrator transfer function helps enhance the stability of the DART controller's feedback loop.

[0071] In the hysteretic control example (e.g., in a PLL pseudo-fixed frequency converter), the location of the "pole" of the integrator 300 is chosen to be low enough so as not to interfere with the fast loop of the feedback controller. intThe Miller effect (e.g., parasitic capacitance input to output) is incorporated to minimize the pole location of the integrator 300. The pole location can be expressed as:

[0072]

[0073] Figure 5A is a functional diagram of an example gain and level shifter for direct amplified ramp tracking according to the present disclosure. Figure 5A Shows V ctrl Signal generator (collectively referred to as 500). V ctrl Signal generator 500 is similar to gain and level shifter 214. V ctrl The signal generator 500 includes a circuit for determining the signal V REF-INT and signal V FB The difference between the two (eg, error signal) is subtracted from the subtractor (SUB) 502. The gain buffer 504 is arranged to normalize the output of the subtractor 502 for comparison with the signal V COM Add. Signal V COM is a constant signal that is the average (eg, “common”) of the analog high power rail (eg, AVDD) and the analog low power rail (eg, analog ground). The adder 506 is arranged to be responsive to the signal V COM The normalized output of the gain buffer 504 is added to generate V ctrl Signal.

[0074] In various examples, V ctrl The signal generator 500 may be a differential amplifier (see, for example, Figure 5B DDA510) or g m Amplifiers (e.g., transconductance, e.g. Figure 5C g m Amplifier 510). Typically, DDA includes low output impedance and precise gain control, but requires higher cost and consumes higher bias current. In contrast, g m The amplifier needs to have a low implementation cost and include a higher bandwidth, but also a higher output impedance.

[0075] V ctrl The signal generator 500 generates V for controlling the DART converter 110. ctrl signal, the DART converter 110 in turn controls the buck converter system 100. When the buck converter system 100 does not include additional (eg, internal) control circuitry (eg, which further loads V ctrl signal output), V ctrl The signal generator does not necessarily need a low output impedance. In this case, g can be selected for reasons of lower cost and lower power consumption.m Amplifier Example. When the buck converter system 100 does include additional control circuitry, the DDA example may be chosen for reasons of lower cost and lower power consumption.

[0076] Figure 5B is a schematic diagram of an example differential difference amplifier-based gain and level shifter for direct amplified ramp tracking according to the present disclosure. Figure 5B A differential amplifier circuit (generally referred to as 510) is shown. The differential amplifier circuit 510 is a V ctrl An example of a DDA implementation of the signal generator 500. The differential difference amplifier circuit 510 includes a DDA 512, which includes a g m Amplifier 514 and g m Amplifier 516, capacitor C T , resistor R T and buffer 518 .

[0077] Buffer 518 is a low impedance output buffer for fully driving the signal V ctrl To overcome the injection of EMI-based noise. Signal V ctrl coupled to a first resistor R N1 and the second resistor R N2 The gain control resistor network. Resistor-based feedback helps ensure accurate gain control. Capacitor C T and resistor R T Provides compensation to help ensure the stability of the feedback loop architecture.

[0078] g m Amplifier 514 and g m Amplifier 516 can draw a large quiescent current and is relatively expensive. m Amplifier 514 includes a REF-INT The non-inverting input and coupled to V FB The inverting input of g m Amplifier 516 includes a COM The non-inverting input and coupled to V Fbfn The inverting input of

[0079] In response to the resistor network, the signal V COM and signal V ctrl , in the first resistor R N1 and the second resistor R N2 The signal V is generated at the common node of fbn (Resistor network "n" feedback voltage). g m Amplifier 514 and g m The outputs of amplifier 516 are coupled together so that the N1 and RN2 The feedback loops formed for both outputs are equal to each other. Therefore:

[0080] Vfbn-V COM =V REF-INT -V FB (8)

[0081] In addition, V ctrl It can be expressed as:

[0082]

[0083] Figure 5C is a schematic diagram of an example transconductance-based gain and level shifter for direct amplified ramp tracking according to the present disclosure. Figure 5C Shown g m amplifier circuit (collectively referred to as 520), the g m The amplifier circuit includes g m Amplifier 520 and resistor R gain . g m Amplifier 520 is V ctrl Signal generator 500g m Example of amplifier implementation.

[0084] Compared with the differential difference amplifier circuit 510, g m Amplifier 520 can be implemented at a lower cost and have lower quiescent power consumption. m The gain of the amplifier circuit 520 is given by g m Amplifier 522 and resistor R gain The transconductance output is determined by the (e.g. fixed) resistor R gain The voltage generated across the two ends of the transconductance output is 1 / R gain Therefore, the output signal V ctrl The overall gain is determined by resistor R gain is well controlled and can be expressed as:

[0085] Vctrl=Gm·Rgain·(V REF-INT -V FB )+V COM (10)

[0086] g m The output impedance of the amplifier circuit 520 is related to the resistor R gain Parallel g m The output impedance of amplifier 522. Therefore, additional output buffers can be used to support the signal V when the input is heavily loaded (loaded down) by the additional circuit. ctrl Additional lines loaded.

[0087] Figure 6A is a functional diagram of an example transient feed-forward circuit for direct amplified ramp tracking according to the present disclosure. Figure 6A Shows V TFF (Transient feedforward voltage) signal generator (collectively referred to as 600). V TFF Signal generator 600 is similar to transient feed forward 212 circuit. TFF The signal generator 600 includes a circuit for determining the signal V FB and signal V REF A subtractor (SUB) 602 is used to calculate the difference between α and β (eg, which is a).

[0088] The gain buffer 604 is arranged to buffer the output of the subtractor 602 for addition by the capacitor C HPF and resistor R HPF Perform high pass filtering. The output of gain buffer 604 is coupled to capacitor C HPF The first terminal of the capacitor C HPF The second terminal is coupled to the resistor R HPF The first terminal of the resistor R HPF The second terminal is coupled to the signal V COM Signal V TFF The signal on capacitor C HPF and resistor R HPF The common nodes between them are generated.

[0089] Signal V TFF The signal can be represented as:

[0090]

[0091] Figure 6B is a schematic diagram of an example differential difference amplifier-based transient feed-forward circuit for directly amplified ramp tracking according to the present disclosure. Figure 6B A differential amplifier circuit (generally referred to as 610) is shown. The differential amplifier circuit 610 is a V TFF An example of a DDA implementation of the signal generator 600. The differential difference amplifier circuit 610 includes a DDA 612, which includes a g m Amplifier 614 and g m Amplifier 616, capacitor C T , resistor R T and buffer 618 .

[0092] Buffer 618 is a low impedance output buffer for sufficiently driving the signal V TFF To overcome the injection of EMI-based noise. Buffer 618 is arranged to buffer g m Amplifier 614 and gm Amplifier 616 (and compensation network capacitor C T and resistor R T ) output for the capacitor C HPF and resistor R HPF The output of buffer 618 is coupled to capacitor C HPF The first terminal of the capacitor C HPF Including coupling to resistor R HPF The first terminal of the resistor R HPF The second terminal is coupled to the signal V COM Signal V TFF The signal on capacitor C HPF and resistor R HPF The common nodes between them are generated.

[0093] g m Amplifier 614 and g m Amplifier 616 can draw a large quiescent current and is relatively expensive. m Amplifier 614 includes a FB The non-inverting input and coupled to V REF The inverting input of g m Amplifier 616 includes a COM The non-inverting input is coupled to the resistor R n2 and R n1 Common nodes between fbn )’s inverting input.

[0094] In response to the resistor network, the signal V COM and signal V fbn , in the first resistor R n1 and the second resistor R n2 The signal V is generated at the common node of fbn (Feedback voltage "n"). g m Amplifier 614 and g m The outputs of amplifier 616 are coupled together so that the n1 and R n2 The feedback loop formed for both outputs is driven from the same node. Therefore, the gain of the differential difference amplifier circuit 610 can be expressed as:

[0095] R n1 =(GAIN-1)×R n2 (12)

[0096] Figure 6C is a schematic diagram of an example transconductance-based transient feed-forward circuit for direct amplified ramp tracking according to the present disclosure. Figure 6C Shown g mamplifier circuit (collectively referred to as 620), the g m The amplifier circuit includes g m Amplifier 622, resistor R gain , capacitor C HPF and resistor R HPF . g m Amplifier 620 is V TFF Signal generator 600g m Example of amplifier implementation.

[0097] Compared with the differential difference amplifier circuit 610, g m Amplifier 620 can be implemented at a lower cost and with lower quiescent power consumption. m The transfer function of amplifier circuit 620 is given by g m The gain of amplifier 622 and resistor R gain and a high-pass filter (comprising capacitor C HPF and resistor R HPF Therefore, g m The output of the amplifier circuit 620 can be expressed according to Equation 11.

[0098] Differential amplifier circuit 610 and / or g m Amplifier circuit 620 transient feed-forward transient block is used to amplify (eg, isolate and enhance) V FB and V REF The amplified transient signal is high-pass filtered (e.g., by C HPF and R HPF ) to generate the signal V TFF The signal V TFF With signal V COM A comparison is performed to generate a loop comparator output signal (which forms part of a feedback control loop including the PWM logic 240 circuit, the ramp loop 230 circuit, and the loop comparator 220 itself).

[0099] In the same gain stage DDA example, the output of the gain buffer 504 can also be used to drive the capacitor C of the differential difference amplifier circuit 610. HPF and resistor R HPF However, the loading effect of the high-pass filter can affect the signal V ctrl .

[0100] At the same gain level g m In the amplifier example, an additional branch (e.g., a current mirror) can provide output current to couple to the current sourced by g m Capacitor C of amplifier example 620 HPF and resistor RHPF The high-pass filter formed by the extra branch is relatively low cost.

[0101] Figure 7 is a functional diagram of an example ramp loop circuit for direct amplified ramp tracking according to the present disclosure. Figure 7 A ramp loop circuit, generally referred to as 700, is shown. The ramp loop circuit 700 (similar to the ramp loop 230 circuit) includes a ramp generator 710 and a slope compensator 720 circuit.

[0102] The ramp generator 710 includes a level shifter 712 and a level shifter 714 and an RC network including a resistor R RAMP and resistor R BIAS and the programmable capacitor C RAMP The ramp generator 710 is arranged to receive a timing signal PWM INT . Timing signal PWM INT Is the internal PWM signal, characterized by the external PWM signal PWM EXT The rising edge occurs approximately 80 ns before the rising edge of the switching circuit 270 (which is used to control the driver 260 to selectively toggle the switching circuit 270). EXT ) and a second PWM signal (eg, PWM INT ) can overlap (eg, such that at least a portion of the first PWM signal and a portion of the second PWM signal are simultaneously active).

[0103] PWM INT The high portion of the signal is level shifted up to VDD by level shifter 712 and up to VIN by level shifter 714. Level shifted PWM INT The signal is coupled to drive the RC network. V RAMP Signal in C RAMP V RAMP The slew rate (and V SLOPE The conversion rate of the signal can be changed by changing the value of the RAMP-ADJ (ramp adjustment) signal. RAMP The RAMP-ADJ signal value can be adjusted (e.g., fine-tuned) by adjusting the capacitor. The RAMP-ADJ signal value can be adjusted via pin-strapping or PMBus (Power Management Bus) commands to optimize transient response performance.

[0104] The slope compensator 720 circuit includes an averaging low-pass filter (LPF) 722, a buffer 724, and a resistor R SLOPE and the programmable capacitor C SLOPEThe RC network is used to make the slope capacitor C SLOPE The discharge switch 726 and the average LPF 728. The slope compensator 720 circuit generates a sawtooth waveform V SLOPE (For example, refer to Figure 11 Signal V for discussion SLOPE ). V RAMP The falling edge of the signal has the same SLOPE The slope of the rising edge of is similar and / or equal (but of opposite polarity) to the slope of .

[0105] Average LPF 722 and buffer 724 respond to V RAMP signal generates an average DC voltage (e.g., with the actual V out The average DC voltage is used to drive the RC network of the slope compensator 720 (including R SLOPE and C SLOPE ), where the slope compensation voltage V SLOPE In R SLOPE and C SLOPE The slope compensation voltage V SLOPE The slope of V is determined by the RC (resistance-capacitance) time constant of the RC network. SLOPE is coupled to an input of the loop comparator 220 to generate a loop comparator output signal.

[0106] The DISCHARGE signal is a short pulse generated by the PWM logic circuit 240 in response to the clock signal changing from zero to one (logic state). The DISCHARGE signal closes the switch 726 to cause the slope capacitor C SLOPE discharge (which terminates V SLOP The rising signal makes V SLOPE After the DISCHARGE signal pulse ends (transitions to an inactive state), switch 726 is opened, causing the slope capacitor C SLOPE Based on the average DC voltage recharge (which makes V SLOPE The signal rises again, creating a sawtooth waveform).

[0107] The S / H signal is the PWM logic circuit 240 responding to the PWM INT A short pulse is generated when the signal changes from zero to one. INT When the S / H signal transitions to the inactive state, the average LPF 728 is triggered to respond to the slope compensation signal V SLOPE The (eg, instantaneous) value of the DC voltage is used to generate a holding DC voltage. SLOPE coupled to the input of the loop comparator 220 to reduce V SLOPE The influence of DC offset of the signal.

[0108] To help ensure that when PWM INT When the duty cycle of the converter 200 is higher than 50% (eg, feedback driven), the slope compensation is input to the loop comparator 220 to generate the loop comparator output signal. RAMP The average value can be expressed as:

[0109]

[0110] where R BIAS and R RAMP is the resistor of the RC network of the ramp generator 710 .

[0111] By R RAMP and R BIAS The discharge current can be expressed as:

[0112]

[0113] The descending slope m2 can be expressed as:

[0114]

[0115] To help ensure that when PWM INT When the duty cycle is higher than 50%, the loop stability and rising slope m can be expressed as:

[0116]

[0117] V OUT 、R RAMP and C RAMP The value may be predetermined so that slope compensation can be inherently optimized (eg, before deploying the system 100). The inherently optimized slope compensation of the DART converter may be more efficient than certain peak current mode control methods.

[0118] For peak current mode control, the slope compensation can be fixed relative to the worst-case conditions that may occur due to the selection of a specific inductor after deployment. As a result, relatively large slope compensation margins are provided, allowing the system response to load transients to be reduced from the optimal response time.

[0119] Instead, V RAMP Therefore, the slope compensation design of the converter that directly amplifies the ramp tracking control can be optimized without providing a relatively wide design margin that would otherwise affect the system transient response.

[0120] Figure 8is a schematic diagram of an example switching circuit sample and hold signal generator for direct amplified ramp tracking according to the present disclosure. Figure 8 , an example switching circuit sample and hold signal generator 800 is generally described as including a switching circuit 810 (which is similar to the switching circuit 270), a sample / hold 812 circuit (which is similar to the sample / hold 280 circuit), and a DC current feedback indicator generator 814 (which is similar to the DC current feedback indicator generator 290 circuit).

[0121] To reduce the Q value (e.g., quality factor) at bipolar frequencies (where a Q value of 1 or less increases loop stability), a small DC current feedback is added to the feedback loop driven by loop comparator 220. Current information is sensed from the power stage of the buck converter (e.g., from the voltage developed across the low-side FET of switching circuit 810). The voltage developed across the low-side FET is proportional to the current (e.g., the current flowing through the external inductor when the low-side FET is on).

[0122] After the noise blanking time, the sample / hold circuit 812 samples and holds the voltage generated across the low-side FET. The DC current feedback indicator generator 814 is a transimpedance amplifier that converts the current information from the sampled and held (S / H) voltage into a current proportional to the current flowing through the lower FET of the switching circuit 810. The output of the DC current (DCI) feedback indicator generator 814 (e.g., signal DCI) is coupled to the loop comparator 220 as the feedback current.

[0123] Since V RAMP The AC portion of the inductor current change is simulated, so there is a complex impedance. For example, according to the Bode diagram analysis of DART, there is a bipolar peak based on the LC-based transfer function. The complex impedance causes the feedback signal to have a frequency dependence in amplitude and phase. Therefore, the phase angle decreases near the bipolar point. When the transimpedance bandwidth is near the bipolar point frequency, the phase margin is generally reduced. In order to maintain sufficient phase margin, a relatively small amount of DC current information is added as an input to the loop comparator 220 via the signal DCI. The signal DCI is processed by the loop comparator 220 to adjust V ctrl Thus, adding DCI signal feedback improves phase margin at bipolar frequencies and may enable a wider stability range with the DART (e.g., when the DART circuitry is coupled to an inductor having an inductance selected by a user of the deployed DART circuit).

[0124] Figure 9 is a schematic diagram of an example loop comparator (generally referred to as 900) for direct amplified ramp tracking according to the present disclosure. Figure 9, an example loop comparator 900 (which may be similar to loop comparator 220 ) is generally described as including a DCI feedback 910 circuit, subtractors (SUB) 920 , 922 , and 924 , an adder 930 , and an output buffer 940 .

[0125] The loop comparator 900 is arranged to compare the input signal V TFF (transient feedforward voltage), input signal V COM (common reference voltage), input signal V RAMP 、Input signal V ctrl , input signal DCI (load current feedback information), input signal V SLOPE and the input signal V S / H (In response to PWM INT The slope compensation signal V is sampled at the falling edge of the signal SLOPE In response to the feedback control signal output by the loop comparator 220, the PWM INT Signal and PWM EXT Thus, the loop comparator 220 terminates a PWM pulse (eg, for driving an external coil) based on a comparison of the input signals in a feedback loop based configuration.

[0126] For example, the subtractor 920 is arranged to subtract COM Subtract V from TFF signal and provides the compared (eg analog) result to a first input of adder 930. DCI feedback circuit 910 is arranged to receive the signal from V ctrl The DCI signal is subtracted from the signal to generate V CVI (control voltage-current) signal. Subtractor 922 is arranged to subtract the voltage from V RAMP Subtract V from CVI signal and provides the compared (eg analog) result to a second input of adder 930. Subtractor 924 is arranged to receive the signal from V SLOPE Subtract V from S / H signals and provides a (e.g., analog) result of the comparison to a third input of adder 930. Adder 930 is arranged to add the first, second, and third inputs to generate a combined output signal, which is buffered by buffer 940 to generate a loop comparator output.

[0127] Therefore, the sum of the positive inputs: Vpos = V TFF +V RAMP +V SL0PE The sum of the negative input: Vneg = V CVI +V COM +V S / H When Vpos becomes greater than V neg When the output of the loop comparator turns high, the PWM INT and PWM EXT Valid (for example, forcing the PWM INT and PWM EXT signal goes low).

[0128] The load current feedback information DCI can also be combined with any of the six other inputs to the loop comparator. For example, because V COM signal and V ctrl The signal change rate is relatively slow and the source impedance is low, so the signal DCI can be COM signal and V ctrl signal combination. Therefore, V CVI and V ctrl The voltage difference between the two voltages changes in proportion to the load current in response to the load current feedback information DCI.

[0129] Figure 10 is a schematic diagram of an example pulse width modulation logic circuit (generally referred to as 1000) for direct amplified ramp tracking according to the present disclosure. Figure 10 In FIG. 1 , the example PWM logic 1000 circuit (which may be similar to the PWM logic 240 circuit) includes a latch 1002, an AND gate 1004, a rising edge delay buffer 1006, an inverter 1008, an S / H pulse generator 1010, and a discharge pulse generator 1012. In general, the PWM logic 1000 circuit is arranged to receive the loop comparator output and the system clock signal for generating a PWM INT signal (for driving the ramp generator 232), PWM EXT signal (for driving the driver 260), and the S / H signal and the discharge signal (for driving the slope compensation circuit 234).

[0130] Clock signal 1022 (as shown in waveform 1020) synchronizes the circuitry of DART converter 200 for controlling the DART in each PWM cycle. For example, in response to the rising edge of clock signal 1022, discharge pulse generator 1012 is triggered to generate a discharge signal 1030 pulse in each clock cycle.

[0131] The latch 1002 responds to the rising edge of the clock signal 1022 to enable the PWM INT Signal 1026 becomes active. Latch 1002 responds to the rising edge of loop comparator signal 1024 to enable PWM INT Signal 1026 becomes invalid. PWM INT Signal 1026 controls V RAMP For example, when PWMINT When signal 1026 is high, V RAMP signal rises, and when the PWM INT When signal 1026 is low, V RAMP Signal degradation (see, for example, Figure 11 waveform 1114 and waveform 1108).

[0132] PWM EXT Signal 1028 is in response to PWM INT Signal 1026 is generated by delay. For example, PWM INT Signal 1026 is coupled to rising edge delay buffer 1006. Rising edge delay buffer 1006 is arranged to delay the rising edge of the input signal by, for example, 80ns. The output of rising edge delay buffer 1006 is connected to PWM INT Signal 1026 is logically ANDed to generate PWM EXT signal 1028. Therefore, PWM EXT Signal 1028 in PWM INT The PWM signal is driven high after a fixed rising edge delay time 1034 (eg, approximately 80 ns) following the rising edge of the signal 1028. EXT Signal 1028 and PWM INT The falling edge of signal 1026 is simultaneously driven low. EXT Signal 1028 is coupled to driver 260 for driving the switch node voltage of switch circuit 270. When the switch node voltage of switch circuit 270 is driven high, signal V SW The node of the node is driven high.

[0133] Response to PWM INT The S / H signal 1032 is generated by the signal 1026. For example, the S / H signal 1032 is coupled to the inverter 1008, which is coupled to the S / H pulse generator 1010. The generated S / H signal 1032 includes narrow pulses (approximately 10 ns wide) generated by the PWM INT The falling edge of signal 1026 triggers the S / H signal 1032 in response to PWM INT The falling edge of signal 1026 initiates sampling of the slope compensation sawtooth voltage (eg, by closing switch 726). The sampled and held voltage is coupled to the loop comparator 220 input for use in reducing V SLOP The DC offset of the signal.

[0134] Figure 11 is an example waveform diagram of selected waveforms (generally 1100) in steady-state operation of a direct-amplified ramp tracking converter according to the present disclosure. Figure 11 , waveform 1100 includes waveform VCOM 1102, Waveform V TFF 1104, Waveform V CVI 1106, Waveform V RAMP 1108, Waveform V S / H 1110, Waveform V SLOPE 1112, Waveform PWM INT 1114 and waveform PWM EXT 1116. Waveform 1100 shows DART converter 200 operating, for example, in steady state.

[0135] Combine the first pair of signals V COM 1102 and V TFF 1104 (eg, by switching from V TFF Subtract V from 1104 COM 1102) to remove V TFF 1104, thereby enhancing the response to load transients of the loop comparator 220. Signal V COM 1102 is a constant signal generated (e.g., by a voltage divider) as the average of the analog high power rail and the analog low power rail, and is proportional to V COM 1102, which maximizes the dynamic range of the signal. TFF 1104 is signal V FB (For example, in response to Figure 1 The generated output voltage V out By a series of R s1 and R s2 The amplified AC component is generated by the voltage divider formed).

[0136] During steady-state operation of a DART converter (e.g., DART converter 110 and / or DART converter 200), the transient change is zero, and signal V TFF The value of 1104 is approximately equal to V COM 1102 signal value. As shown in the waveform, V TFF 1104 includes a relatively small amount of V out Ripple. V TFF The average voltage level of 1104 is equal to V COM 1102 value, which minimizes the COM Normalized offset of other system signals.

[0137] Combine the second pair of signals V CVI 1106 and V RAMP 1108 (e.g., from V RAMP Subtract V from 1108 CVI1106) to enhance the stability of the feedback loop. During steady-state operation, V RAMP The average voltage of 1108 is V COM The voltage of 1102 is roughly the same. When PWM INT When 1114 is high, V RAMP The waveform of 1108 ramps up. In response to VIN and the resistor R of the ramp generator 710 RAMP and capacitor C RAMP Determine V RAMP The slope of 1108. When V RAMP 1108 amplitude reaches V CVI When the level of signal 1106 is INT 1114 transitions low in response (e.g., after a propagation delay of loop comparator 220). INT After the 1114 signal turns low, V RAMP Signal 1108 ramps down until the PWM INT The 1114 signal becomes valid again.

[0138] In response to the DC current feedback signal DCI (eg, generated by the DC current feedback indicator generator 290) and in response to V ctrl The signal (eg, generated by gain and level shifter 214) generates V CVI Signal 1106. When the load current increases, the increase in signal DCI causes signal V CVI 1106 is lowered (e.g., from V ctrl The signal level shifts downward). In response to V CVI 1106 is reduced, the DART feedback loop forces V ctrl signal is higher (for example, making V ctrl signal is forced higher in response to an increase in load current). Therefore, the signal V CVI 1106 and V RAMP 1108 intersects the peak, and V ctrl The level of the signal changes in response to changes in the load current. When there is no load current, the signal V CVI The voltage of 1106 and V ctrl The voltage of the signals is roughly the same.

[0139] Combine the third pair of signals V S / H 1110 and V SLOPE 1112 (e.g., from V via loop comparator 220) SLOPE Subtract V from 1112 S / H 1110) to provide slope compensation. Slope compensation sawtooth waveform VSLOPE 1112 adds slope compensation to the feedback control loop. By responding to each PWM INT Falling edge sampling and holding V SLOPE The value of 1112 generates V S / H 1110 signal. From V SLOPE 1112 (eg, instantaneous) value minus the sampled voltage V S / H 1110 reduces the DC offset of the feedback control loop before integration (this increases the dynamic range of the feedback control loop).

[0140] As discussed above, PWM EXT The 1116 signal controls the switching circuit (eg, 270) to switch the external inductor. PWM INT 1114 signal (used to control the internal feedback control loop) than PWM EXT 1116 signal width is about 80ns (and in PWM EXT The 80 ns delay time provides time for the loop comparator 220 circuit to respond to the feedback control loop (eg, before the external inductor is switched).

[0141] Figure 12 is an example waveform diagram of the combined waveforms (generally referred to as 1200) of a direct amplified ramp tracking converter according to the present disclosure. Figure 12 , waveform 1200 includes a combined positive input waveform (V pos ) 1204 and the combined negative input waveform (Vneg) 1202. For example, the positive input waveform 1204 can be represented as the positive sum:

[0142] V pos =V TFF +V RAMP +V SLOPE (17)

[0143] And the negative input waveform 1202 can be represented as a negative sum:

[0144] V neg =V CVI +V COM +V S / H (18)

[0145] When the signal V pos 1204 is higher than V neg At 1202, the loop comparator 220 transitions to high (eg, after a wait time of the loop comparator 220). The signal PWM INT 1206 and signal PWM EXT1208 are both forced low (eg, in response to the output of loop comparator 220 transitioning to a high state), which terminates the “on-time” portion of the PWM cycle during which the external inductor is being energized.

[0146] In the signal PWM INT 1206 starts with the discharge pulse being enabled (eg, see 1012) to force V pos 1204 signal drops below the minimum V neg Voltage 1210. After the discharge pulse ends, the VRAMP signal and VSLOPE signal increase, which causes V pos 1204 signal rises above the minimum voltage 1210. When V pos 1204 signal arrives at V neg 1202 signal, trigger the loop comparator 220 to end PWM INT Signal 1206 and PWM EXT Signal 1208 is valid.

[0147] V pos 1204 signal rises from the minimum voltage 1210 to reach V neg The rise time of the 1202 signal determines the PWM EXT The minimum on-time of signal 1208. By examining the voltage and time scaling, it is clear that even when PWM EXT When the width of signal 1208 is relatively close to zero (e.g., 10 nanoseconds), there is also sufficient PWM INT Signal 1206 width and V RAMP The DART technique is therefore well suited for very high switching frequency operation (e.g., compared to the lower frequency limits of some peak current mode controls).

[0148] Figure 13 is an example waveform diagram of combined waveforms (generally 1300) in response to a load increase of a direct amplified ramp tracking converter according to the present disclosure. Figure 13 , waveform 1300 includes V neg 1302 signal, V pos 1304 signal, PWM INT Signal 1310, PWM EXT signal 1312 and SW 1314 signal. Figure 13 An example system response to a load increase is generally shown.

[0149] During a load step-up transient, the output voltage V outIn response to the reduced output voltage V out , V neg 1302 signal (the sum of the negative inputs of loop comparator 220) increases, and V pos The slope of the 1304 signal (the sum of the positive inputs of the loop comparator 220) decreases. The on percentage of the duty cycle increases to increase the output voltage V toward the target voltage. out .

[0150] In the example scenario, the load step transient occurs around the 1ms mark. Without the delay introduced by the delay buffer (and / or clock synchronization gating), the DART control loop quickly initiates the response to the load step transient. For example, V neg 1302 signal rises and exceeds the nearest voltage, while V pos 1304 signal V TFF The voltage component decreases the valley point 1306 and changes V pos The slope of the signal 1304. Thus, in response to a load step-up transient, the on percentage of the duty cycle increases.

[0151] Since V neg The 1302 signal continues to increase in the next PWM cycle, V pos 1304 signal V TFF The voltage component will cause V pos 1304 signal reaches another valley point, and the duty cycle is subsequently extended to increase the output voltage V out Therefore, in response to the load step-up transient, the on-percentage of the duty cycle increases. The switching signal SW 1314 is similar to a PWM EXT 1312 (eg, propagation latency modification by the switch circuit driver) timing (and on percentage).

[0152] Figure 14 is an example waveform diagram of combined waveforms (generally 1400) in response to a load reduction of a direct amplified ramp tracking converter according to the present disclosure. Figure 14 , waveform 1400 includes V neg 1402 signal, V pos 1404 signal, PWM INT Signal 1406, PWM EXT signal 1408 and SW 1410 signal. Figure 14 An example system response to load reduction is generally shown.

[0153] During a load step-down transient, the output voltage V outIn response to the increased output voltage V out , V neg 1402 signal (the sum of the negative inputs of loop comparator 220) decreases, and V pos The slope of the 1404 signal (the sum of the positive inputs of the loop comparator 220) initially increases. The on percentage of the duty cycle decreases (even to zero percent) to help the output voltage V out Decrease towards the target voltage.

[0154] In the example scenario, the load step-down transient occurs around the 1.5ms mark and the output voltage V out Without the delay introduced by the delay buffer (and / or clock synchronization gating), the DART control loop has no effect on the output voltage V out For example, V neg 1402 signal drops, while V pos 1404 signal V TFF The voltage component is based on V pos 1404 signal slope changes and rises upward. Because the amplitude of the load step-down transient is relatively large, V pos 1404 signal V TFF The weight is relatively large, and V pos A portion of the 1404 signal (eg, generally trending downward) becomes positively sloped. Thus, the on-percentage of the duty cycle is reduced in response to the load step-down transient, and the output voltage V out Towards target voltage decrease.

[0155] When the load transient relief is large enough, PWM can be omitted EXT signal 1408 and SW signal 1410 to provide the best response to load step-down transients. EXT 1408 signal does not become valid (for example, because the PWM becomes valid EXT 1408 signal otherwise will not meet the minimum PWM EXT width requirement), internal PWM INT 1406 signal still becomes valid periodically, so that the output voltage V out The DART control loop is maintained during continuous periods of decrease towards the target voltage.

[0156] Figure 15 is an example waveform diagram of waveforms (generally 1500) of a load increase followed by a load decrease in response to a direct amplified ramp tracking converter according to the present disclosure. Figure 15 , waveform 1500 includes V out 1502 signal, inductor current 1504, Vctrl Signal 1508 and V CVI Signal 1510. Figure 15 Example system responses to load increases and load decreases are generally shown.

[0157] For example, when the load current increases, V out 1502 signal decreases until the inductor current 1504 rises enough to pull V out 1502 signal returns to the target (eg, regulated) voltage level. out 1502 signal drops, V ctrl Signal 1508 and V CVI Signal 1510 rises, causing the PWM on-percentage to increase (which increases inductor current 1504). When the load current changes from 0A to 20A, the inductor current 1504 changes by the same amount. For a 20A load current increase, the DC current feedback (DCI) increases V CVI The level of signal 1508 is raised to V CVI The signal 1510 is about 60mV above.

[0158] For example, when the load current decreases, V out 1502 signal rises until the PWM conduction percentage reduces the inductor current 1504 enough to make V out 1502 signal drops to the target (eg, regulated) voltage level. out When the 1502 signal rises above the target voltage, V ctrl Signal 1508 and V CVI Signal 1510 falls, causing the PWM on-percentage to decrease (which reduces the inductor current 1504). out When the 1502 signal drops below the target voltage, V ctrl Signal 1508 and V CVI Signal 1510 rises, causing the PWM on-percentage to increase (which increases the inductor current 1504) and V out 1502 signal rises so that V out 1502 The signal is regulated around the target voltage.

[0159] When the load current changes, the DCI signal (eg, which is used to form a DC current feedback loop) changes V ctrl The voltage level of signal 1508. The DCI signal reduces the Q of the power stage bipolar and increases the capacitance to the relatively large output capacitor (eg, capacitor C of the buck converter system 100). out ) associated with the phase margin.

[0160] At the 1ms mark, the control voltage V ctrl 1508 and control voltage V CVI 1510 rises quickly to quickly respond to load step-up transients. After a load step-up transient event, the control voltage V CVI returns to the same level as the low load current condition, while V ctrl Signal 1508 returns above V ctrl The low load current condition level of signal 1508 is approximately 60 mV. Integrator 216 is arranged to effectively accommodate voltage swings of at least 60 mV system offset. Thus, a converter arranged according to the DART description is suitable for high frequency operation at high load currents (e.g., operation above approximately 4 MHz at currents greater than approximately 40 amperes).

[0161] In contrast, the control voltage for peak current mode control can change by approximately 400 mV in response to a similar load current. The relatively large voltage swing of the control voltage presents a greater challenge for optimizing the internal compensation during peak current mode.

[0162] Modifications may be made in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. A control circuit comprising: A first loop circuit system adapted to receive a feedback signal, the first loop circuit system comprising: a transient feedforward circuit configurable to generate a first error signal by high-pass filtering a difference between the feedback signal and a reference signal; an integrator circuit configurable to generate an integrated signal by integrating the difference between the feedback signal and the reference signal; and a gain and level shifter circuit coupled to the integrator circuit and configurable to generate a second error signal based on a difference between the integrated signal and the feedback signal; a comparator configurable to generate a feedback control signal based on the first error signal and the second error signal; and The pulse width modulation logic circuit, ie, the PWM logic circuit, can be configured to generate a first PWM signal based on the feedback control signal during a PWM period.

2. The control circuit of claim 1 , wherein the transient feed-forward circuit is further configurable to generate a common voltage signal based on a high power rail and a low power rail, wherein the comparator is configured to generate the feedback control signal based on a combination of the first error signal, the second error signal, and the common voltage signal. 3 . The control circuit of claim 2 , wherein the first error signal is generated based on the common voltage signal and the difference between the feedback signal and the reference signal.

4. The control circuit according to claim 3, wherein the transient feedforward circuit comprises: a subtractor configurable to determine the difference between the feedback signal and the reference signal; as well as A high pass filter is coupled to the subtractor and can be configured to generate the first error signal by high pass filtering the difference between the feedback signal and the reference signal based on the common voltage.

5. The control circuit of claim 3 , wherein the transient feedforward circuit comprises: a first amplifier configurable to amplify the difference between the feedback signal and the reference signal; a second amplifier configurable to amplify a difference between the common voltage and a feedback voltage of the transient feed-forward circuit, the feedback voltage being generated at a common node of outputs of the first and second amplifiers; a compensation resistor and a compensation capacitor coupled in parallel between the common node and a voltage potential; as well as A high pass filter is coupled to the common node and can be configured to generate the first error signal based on the common voltage by high pass filtering the amplified difference between the feedback signal and the reference signal.

6. The control circuit of claim 3 , wherein the transient feedforward circuit comprises: an amplifier configurable to amplify the difference between the feedback signal and the reference signal; as well as A high pass filter is coupled to the amplifier and can be configured to generate the first error signal by high pass filtering the amplified difference between the feedback signal and the reference signal based on the common voltage.

7. The control circuit of claim 2 , wherein the gain and level shifter comprises: a subtractor configurable to determine the difference between the feedback signal and the integrated signal; as well as An adder coupled to the subtractor and configurable to generate the second error signal by adding the common voltage to the difference between the feedback signal and the integrated signal.

8. The control circuit of claim 2 , wherein the gain and level shifter comprises: a first amplifier configurable to amplify the difference between the feedback signal and the integrated signal; a second amplifier configurable to amplify a difference between the common voltage and a feedback voltage of the gain and level shifter, the feedback voltage being generated at a common node of outputs of the first and second amplifiers; as well as A compensation resistor and a compensation capacitor are coupled in parallel between the common node and a voltage potential, wherein the second error signal is generated based on the voltage at the common node.

9. The control circuit of claim 1 , wherein the gain and level shifter comprises: An amplifier can be configured to generate the second error signal by amplifying the difference between the feedback signal and the integrated signal.

10. The control circuit according to claim 2, further comprising: a second loop circuit system that can be configured to generate a ramp signal and a slope compensation signal based on an input voltage and the first PWM signal, wherein the comparator can be configured to generate the feedback control signal based on a combination of the first error signal, the second error signal, the common voltage signal, the ramp signal, and the slope compensation signal.

11. The control circuit of claim 10 , wherein the slope compensation signal is generated in response to an average voltage of a sawtooth waveform for emulating a voltage response of an inductor, wherein the slope compensation signal includes a slope determined in response to a resistor-capacitor time constant (RC time constant), and wherein the slope compensation signal is reset in response to the first PWM signal.

12. The control circuit of claim 10, wherein the ramp signal is generated by charging and discharging an emulation capacitor in response to the first PWM signal, and wherein the emulation capacitor is arranged to emulate a ramp response of an inductor to the input voltage provided to the inductor. 13 . The control circuit of claim 10 , wherein the slope compensation signal is generated by low-pass filtering the ramp signal.

14. The control circuit of claim 13 , wherein the second loop circuit system is configurable to generate a holding voltage by low-pass filtering the slope compensation signal, wherein the comparator is configurable to generate the feedback control signal based on a combination of: the first error signal, the second error signal, the common voltage signal, the ramp signal, the slope compensation signal, and the holding voltage to reduce an effect of a DC offset of the slope compensation signal.

15. The control circuit of claim 1 , wherein the PWM logic circuit is configurable to further generate a second PWM signal during the PWM period for controlling application of power to the inductor, the second PWM signal overlapping the first PWM signal and becoming active after the first PWM signal, wherein the feedback signal represents an output voltage generated by the inductor.

16. A converter system comprising: Switching circuit; as well as A control circuit system comprising: A first loop circuit system adapted to receive a feedback signal, the first loop circuit system comprising: a transient feedforward circuit configurable to generate a first error signal by high-pass filtering a difference between the feedback signal and a reference signal; an integrator circuit configurable to generate an integrated signal by integrating the difference between the feedback signal and the reference signal; and a gain and level shifter circuit coupled to the integrator circuit and configurable to generate a second error signal based on a difference between the integrated signal and the feedback signal; a comparator configurable to generate a feedback control signal based on the first error signal and the second error signal; and A pulse width modulation logic circuit (PWM logic circuit) can be configured to generate a first PWM signal based on the feedback control signal during a PWM period, wherein the switching circuit can be configured to couple power to the inductor based on the first PWM signal.

17. The converter system of claim 16, wherein the PWM logic circuit is configurable to further generate a second PWM signal during the PWM period, such that the second PWM signal overlaps with the first PWM signal and becomes active before the first PWM signal, wherein the feedback signal represents an output voltage generated by the inductor.

18. The converter system of claim 17, further comprising: a second loop circuit system that can be configured to generate a ramp signal and a slope compensation signal based on an input voltage and the second PWM signal, wherein the comparator can be configured to generate the feedback control signal based on a combination of the first error signal, the second error signal, a common voltage signal, the ramp signal, and the slope compensation signal.

19. The converter system of claim 18, wherein the switching circuit comprises a first transistor adapted to be coupled between an input terminal of the inductor and the input voltage, and a second transistor adapted to be coupled between the input terminal of the inductor and ground.

20. A method for power conversion, comprising: determining a difference between the feedback signal and the reference signal; generating a first error signal by high-pass filtering the difference between the feedback signal and a reference signal; generating an integrated signal by integrating the difference between the feedback signal and the reference signal; as well as generating a second error signal based on a difference between the integrated signal and the feedback signal; generating a feedback control signal based on the first error signal and the second error signal; as well as A first PWM signal is generated based on the feedback control signal during a PWM period.

21. The method according to claim 20, further comprising: A second PWM signal is generated during the PWM period for controlling application of power to the inductor, the second PWM signal overlapping the first PWM signal and becoming active after the first PWM signal, wherein the feedback signal represents an output voltage produced by the inductor.

22. The method according to claim 21, further comprising: A ramp signal and a slope compensation signal are generated based on an input voltage and the first PWM signal, wherein the feedback control signal is generated based on a combination of the first error signal, the second error signal, a common voltage signal, the ramp signal, and the slope compensation signal.

23. The method according to claim 22, comprising: An input terminal of an inductor is coupled to the input voltage when the second PWM signal is active, and the input terminal of the inductor is coupled to ground when the second PWM signal is inactive.

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