Integrated Circuit and Its Power-On Reset Circuit

Abstract

The present disclosure provides an integrated circuit having a power-on reset circuit, including an inverter circuit, a stacked circuit, an impedance element, and an internal circuit. The inverter circuit is electrically connected between a first power supply node and a second power supply node. The stacked circuit includes n transistors, where n is a positive integer from 1 to N, and is electrically connected between the first power supply node and the input node of the inverter circuit. The impedance element is electrically connected between the input node of the inverter circuit and the second power supply node. When the voltage across between the input node and the first power supply node is greater than the threshold voltage of the stacked circuit, the stacked transistors in the stacked circuit pull up the voltage of the input node to be higher than the trigger point voltage. The internal circuit is electrically connected between the first power supply node and the second power supply node to respond to the power-on reset signal output by the inverter circuit.

Description

Technical Field

[0001] The present disclosure relates to a low-voltage integrated circuit and to a power-on reset circuit suitable for use in such a circuit. Background Art

[0002] Integrated circuits are fabricated to operate with a low supply voltage. The supply voltage is typically applied to pins on the power rails of the integrated circuit chip that carry the supply power (i.e., VDD on the circuit). The supply power is typically a positive voltage, and the ground voltage is typically denoted as VSS. The pins connected to the power rails are also referred to as supply pins.

[0003] Many integrated circuits utilize a power-on-reset (POR) circuit connected to a supply pin (such as a supply pin or a power rail) to detect the restoration of the supply power across the pin or power rail after a power down event and to generate a control signal (commonly referred to as a power-on reset signal). The internal circuitry responds to the pulse of the power-on reset signal to establish a known state (such as reset or initial) for the internal circuitry when the power is restored.

[0004] The supply voltage may be interrupted for various reasons and may rise or fall over time or with a voltage slope. The slope of time or voltage can be measured in microseconds per volt (µsec / V) and peaks and valleys can occur as the power fluctuates during reset.

[0005] As the specification value of the supply power for integrated circuits drops below 3.3 volts, it becomes increasingly complex to implement a stable power-on reset circuit.

[0006] Therefore, a stable power-on reset circuit for use in an integrated circuit is desired that can cover any supply power slope, operate at low voltage, and remain consistent over process / voltage / temperature (PVT) variations. Summary of the Invention

[0007] The following describes a circuit that can generate a control signal (such as a power-on reset signal) that responds to a change in the voltage across a first supply node and a second supply node, operates at a low supply voltage, and remains stable over process / voltage / temperature (PVT) variations.

[0008] The present disclosure relates to a circuit for generating a control signal based on a voltage across a first power supply node (e.g., a first power rail) and a second power supply node (e.g., a second power rail). The circuit includes a P-channel transistor, an N-channel transistor, and an impedance element. The P-channel transistor has a gate, a source, and a drain. The source of the P-channel transistor is electrically connected to the first power supply node. The drain of the P-channel transistor is electrically connected to the output node. The N-channel transistor has a gate, a source, and a drain. The gate of the N-channel transistor is electrically connected to the gate of the P-channel transistor. The drain of the N-channel transistor is electrically connected to the output node. The source of the N-channel transistor is electrically connected to the second power supply node. The impedance element is electrically connected between the gate of the P-channel transistor and the second power supply node. The stacked circuit includes N stacked P-channel transistors, where n is a positive integer between 1 and N and is greater than or equal to 2. These stacked P-channel transistors are electrically connected between the first power supply node and the gate of the P-channel transistor.

[0009] The present disclosure also relates to an integrated circuit applied to power-on reset, having a first power supply node and a second power supply node, and including an inverter circuit, a P-channel transistor, an impedance element, a stacked circuit, and an internal circuit. The inverter circuit is electrically connected between the first power supply node and the second power supply node and has an input node and an output node. The P-channel transistor is electrically connected between the first power supply node and the input node of the inverter circuit. The impedance element is electrically connected between the input node of the inverter circuit and the second power supply node. The stacked circuit is used to generate a source-to-base voltage across the P-channel transistor to reduce the pull-up driving ability of the P-channel transistor relative to the inverter circuit. The internal circuit is electrically connected between the first power supply node and the second power supply node and is used to establish a known state based on a pulse at the output node of the inverter circuit.

[0010] The present disclosure also relates to a circuit for generating a control signal based on a change in the voltage across a first power supply node and a second power supply node. The circuit includes a first P-channel transistor, a first N-channel transistor, an impedance element, and a stacked circuit. The first P-channel transistor has a gate, a source, and a drain. The source of the first P-channel transistor is electrically connected to the first power supply node. The drain of the first P-channel transistor is electrically connected to the output node. The first N-channel transistor has a gate, a source, and a drain. The gate of the first N-channel transistor is directly connected to the gate of the first P-channel transistor. The drain of the first N-channel transistor is electrically connected to the output node. The source of the first N-channel transistor is electrically connected to the second power supply node. The impedance element is electrically connected between the gate of the first P-channel transistor and the second power supply node. The stacked circuit includes a second P-channel transistor. The second P-channel transistor is located between the gate of the first P-channel transistor and the first power supply node. The stacked circuit is used to make the source-to-base voltage of the second P-channel transistor lower than the source-to-base voltage of the first P-channel transistor.

[0011] The present disclosure describes an integrated circuit having a first power supply node and a second supply node. The integrated circuit includes an inverter circuit connected between the first power supply node and the second power supply node. The inverter circuit has an input node and an output node. As the voltage (e.g., VDD) on the first power supply node increases, when the first voltage across between the input node and the first power supply node is greater than the first trigger point voltage, the inverter circuit switches the output node to the first power supply node (e.g., VDD). When the second voltage across between the input node and the second supply node is greater than the second trigger point voltage, the inverter circuit switches the output node to the second supply node (e.g., VSS), thereby generating a pulse for a power-on reset signal (POR). A stacking circuit is connected between the first power supply node of the inverter circuit and the input node. A resistive element is connected between the input node of the inverter circuit and the second power supply node to control the voltage on the input node of the inverter circuit so as to safely generate the pulse of the power-on reset signal. The stacking circuit includes a p-channel transistor and is used to generate a source-to-substrate voltage on the p-channel transistor to reduce the pull-up driving ability of the p-channel transistor relative to the inverter circuit. In some embodiments, the stacking circuit includes N stacked p-channel transistors, where n is a positive integer from 1 to N, and is connected between the first power supply node (e.g., VDD) and the input node of the inverter circuit. The stacked p-channel transistors are configured such that there is an increasing voltage difference or an increasingly negative voltage difference between the source and the substrate of the transistors in the stack. In the embodiments described in the present disclosure, the gates of the stacked p-channel transistors are electrically connected to the second power supply node (e.g., VSS). The substrates of the stacked p-channel transistors are electrically connected to the first power supply node (e.g., VDD). BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 Schematic diagram of a circuit for generating a power-on reset signal.

[0013] Figure 2 Similar to Figure 1 Timing diagram of a circuit where the threshold voltage of transistor Mb is less than the threshold voltage of transistor Ma.

[0014] Figure 3 Similar to Figure 1 Timing diagram of a circuit where the threshold voltage of transistor Mb is greater than the threshold voltage of transistor Ma.

[0015] Figure 4 Schematic diagram of a circuit using low-voltage transistors.

[0016] Figure 5 Graph showing the relationship between the threshold voltages and channel lengths of "high-voltage" and "low-voltage" transistors.

[0017] Figure 6 It is a formula for determining the threshold voltage of a PMOS transistor.

[0018] Figure 7A It is a schematic diagram of a P-channel transistor of an overlapping circuit, where there is a source-to-body bias.

[0019] Figure 7B It is a schematic diagram of a P-channel transistor that does not have a source-to-body bias.

[0020] Figure 8 It is a graph showing the relationship between the channel lengths and threshold voltages of a single transistor and an overlapping transistor.

[0021] Figure 9 It is an optimized circuit for generating a power-on reset signal.

[0022] Figure 10 The figure shows a simplified schematic diagram of an integrated circuit including a power-on reset circuit.

[0023] Figure 11 It is similar to Figure 9 the process corner chart of the circuit

[0024] Description of reference numerals

[0025] VDD: Voltage

[0026] VSS: Voltage

[0027] Ma - Mf: Transistors

[0028] M1: Transistor

[0029] M2 - M3: Overlapping transistors

[0030] MN: Overlapping transistor

[0031] POR: Power-on reset signal

[0032] R1: Impedance element

[0033] R2: Impedance element

[0034] N1: Node

[0035] MC1: Overlapping P-channel transistor

[0036] MC2: Overlapping P-channel transistor

[0037] MCN: Overlapping P-channel transistor

[0038] X1: Overlapping circuit

[0039] MP1: P-channel transistor

[0040] MN1: N-channel transistor

[0041] 500: Power supply rail

[0042] 501: Power supply rail

[0043] 510: Overlap circuit

[0044] 511: Impedance element

[0045] 520: Inverting circuit

[0046] 530: Internal circuit Detailed implementation manners

[0047] The following provides multiple implementation manners of the present disclosure with reference to the accompanying drawings. For the sake of clear illustration, many practical details will be described together in the following description. However, it should be understood that these practical details are not used to limit the present invention. That is to say, in some implementation manners of the present disclosure, these practical details are not necessary. In addition, for the sake of simplifying the accompanying drawings, some structures and elements commonly used in the prior art will be shown in a simple schematic manner in the accompanying drawings.

[0048] In this article, when an element is referred to as "connected" or "coupled", it may mean "electrically connected" or "electrically coupled". "Connected" or "coupled" can also be used to indicate the mutual cooperation or interaction between two or more elements. In addition, although terms such as "first", "second",... are used in this article to describe different elements, these terms are only used to distinguish elements or operations described with the same technical terms. Unless clearly specified in the context, these terms do not particularly refer to or imply an order or sequence, nor are they used to limit the present disclosure.

[0049] The following is based on Figures 1 to 11 Describe the implementation details of the present disclosure.

[0050] Figure 1A circuit schematic diagram of a circuit for generating a power-on reset (POR) pulse signal, including a P-channel transistor Ma and an impedance element R1. The P-channel transistor Ma is electrically connected between a power supply node and a node N1, where the power supply node is used to receive a voltage VDD. The impedance element R1 is electrically connected between the node N1 and a reference voltage node, where the reference voltage node is used to receive a voltage VSS (such as ground). In addition, the circuit further includes a P-channel transistor Mb and an N-channel transistor Mc. The P-channel transistor Mb is electrically connected between a power supply node receiving a voltage VDD (such as 3.3 volts) and an output node, where the output node is used to generate a power-on reset signal POR. The N-channel transistor Mc is electrically connected between the node POR and the reference voltage node. The gates of the transistor Mb and the transistor Mc are electrically connected to the node N1 and are used as an inverter. In implementation, the channel length of the transistor Ma can be greater than the channel length of the transistor Mb, so that the transistor Mb has a stronger driving ability and a lower threshold voltage compared to the transistor Ma.

[0051] Herein, Figure 2 and 3 illustrate the operation mode of the circuit. Figure 2 In the embodiment of, the P-channel transistor Mb at the output end has a stronger driving ability and a lower threshold voltage compared to the P-channel transistor Ma at the input end. In the attached figure, it is represented by V th indicates.

[0052] During the power-up sequence, the voltage of the power supply rail in the integrated circuit will ramp up, such as the trend trajectory of the voltage VDD in the attached figure. The rising trend slope will vary with the recovery state of the power supply.

[0053] When the voltage VDD is extremely low, the node N1 will be held at the reference voltage through the grounded impedance element R1. At time point 200, both the transistor Mb and the transistor Mc are maintained in the off state until the power supply voltage VDD exceeds the voltage of the node N1 by the threshold voltage of the transistor Mb. Then, the transistor Mb is turned on. After the output node POR is pulled up to the voltage VDD. Since the threshold voltage of the transistor Ma is greater than the threshold voltage of the transistor Mb, the node N1 will remain at a low potential. When the voltage VDD continues to rise and is greater than the threshold voltage of the transistor Ma, the voltage of the node N1 will be pulled up as the transistor Ma starts to conduct current. At time point 201, the voltage of the node N1 reaches the threshold voltage of the transistor Mc to turn on and pull down the voltage of the output node POR. As the transistor Ma is fully turned on, the voltage of the node N1 will rise to the maximum value.

[0054] The power-on reset signal POR of the reset has a peak value of 202. The peak value 202 is greater than the threshold voltage of the transistor Mc. In the logic circuit, the threshold voltage of the transistor designed to switch in response to the power-on reset signal POR of the reset is sufficient to achieve reliable operation.

[0055] However, as Figure 3 shown, if the threshold voltage of the transistor Ma is lower than the threshold voltage of the transistor Mb (denoted as V in the attached drawing th ), no pulse signal will be generated. Figure 3 An embodiment is illustrated in which the threshold voltage of the P-channel transistor Mb at the output terminal is greater than the threshold voltage of the P-channel transistor Ma at the input terminal. As shown, if the threshold voltage of the transistor Ma is lower than the threshold voltage of the transistor Mb, the transistor Ma will start to conduct current and the voltage of the node N1 will rise before the transistor Mb conducts and pulls up the output node POR. As the voltage VDD rises, the voltage of the node N1 will rise to be greater than the threshold voltage of the transistor Mc. The threshold voltage of the transistor Mc is used to maintain the voltage of the output node POR at a low level, so that the voltage of the output node POR can be maintained at a low potential. In this case, no power-on reset pulse signal will be generated.

[0056] In order to ensure that the transistor Ma has a larger threshold voltage and weaker driving ability compared to the transistor Mb, one way is to configure the channel length of the transistor Ma to be greater than the channel length of the transistor Mb.

[0057] In addition, as the specification of the voltage VDD decreases, the threshold voltage of the high-voltage transistor in the power-on reset circuit may be too high, so that the power-on reset circuit cannot operate within the specification range. Therefore, a circuit for generating a power-on reset pulse signal is needed, which is applied to a lower power supply voltage, such as 1.2 volts. Figure 4 The circuit of can be implemented using low-voltage transistors, which have a lower threshold voltage and are suitable for circuits with a low power supply voltage. The circuit includes a P-channel transistor Md and an impedance element R2. The P-channel transistor Md is electrically connected between the power supply node (receiving the voltage VDD) and the node N1. The impedance element R2 is electrically connected between the node N1 and the reference voltage node (receiving the reference voltage VSS or grounded). In addition, the circuit also includes a P-channel transistor Me and an N-channel transistor Mf. The P-channel transistor Me is electrically connected between the power supply node (receiving the voltage VDD) and the output node POR. The output node is used to generate the pulse of the power-on reset signal POR. The N-channel transistor Mf is electrically connected between the output node POR and the reference voltage node. The gates of the transistors Me and Mf are both connected to the node N1 to serve as an inverter.

[0058] However, low-voltage transistors may suffer from the reverse short channel effect, causing the threshold voltage to decrease as the channel length increases.

[0059] Figure 5 It is a graph showing the relationship between the threshold voltage and the channel length of "high-voltage" transistors and "low-voltage" transistors. High-voltage transistors (HV MOS) have the short channel effect, that is, the smaller the channel length, the lower the threshold voltage will be. Therefore, as Figure 1 shown, if transistor Mb has a length of approximately 0.8 micrometers near position 100 and transistor Ma has a length of approximately 5 micrometers near position 101, then transistor Mb will have a lower threshold voltage and higher driving ability than transistor Ma. Therefore, the circuit can operate normally as Figure 2 shown.

[0060] As Figure 5 shown, low-voltage transistors (LV MOS) have a lower threshold voltage and can operate safely at a reduced supply voltage. However, the threshold voltage will vary with the reverse short channel effect, that is, it increases with a short channel or decreases with a long channel. This reverse short channel effect causes the channel length of transistor Md to increase, resulting in a decrease in the threshold voltage. Therefore, the aforementioned Figure 3 effect is more likely to occur, leading to the circuit being unable to generate a power-on reset pulse signal.

[0061] Therefore, as Figure 4 shown, if transistor Me has a length of approximately 0.8 micrometers near position 110 and transistor Md has a length of approximately 5 micrometers near position 111, then transistor Md will have a lower threshold voltage and higher driving ability than transistor Me. Therefore, the circuit will exhibit a fault as Figure 3 shown. Figure 6 It is a formula for determining the threshold voltage of a PMOS transistor, where the parameter VSB is the source-to-base voltage. The formula includes a factor added to the constant VT0, which increases when the parameter VSB is negative and becomes lower, and causes the number VT to increase. The relationship between the parameter VSB and the number VT is due to the body effect.

[0062] Figure 7A and 7BShown is a stacked circuit including a plurality of stacked transistors (M2, M3... MN), and a single transistor (M1) configured to be connected to a voltage VDD. The single transistor M1 will have VSB = 0V. In the stacked transistors (M2, M3... MN) of the stacked circuit, the source voltage drops along the stack, so VSB becomes more negative in series.

[0063] Figure 8 For Figure 7B the transistor M1 shown and Figure 7A a graph showing the relationship between the channel length and the threshold voltage of the stacked transistor M3 of the stacked circuit shown. The transistor M3 has a lower source voltage relative to the transistor M1, so its VSB will be negative. Due to the substrate effect, in Figure 8 the channel length range shown, the threshold voltage of the transistor M3 is higher than the threshold voltage of the transistor M1.

[0064] In one embodiment, Figure 7A the threshold voltages of the stacked transistors M2, MN of the stacked circuit shown are respectively simulated to be approximately 0.5722 and 0.6506. Figure 7B The threshold voltage of the transistor M1 shown is then simulated to be 0.5617. Therefore, compared with the transistor M1, Figure 7A the stacked transistors of the stacked circuit shown will have a lower driving ability and a higher threshold voltage.

[0065] In Figure 8 it, the upper trace line represents the threshold voltage of the transistor M3. The threshold voltage of the circuit will fall above this trace line because the transistor MN will have a larger negative VSB. Therefore, assuming the effective length of the stacked circuit is 50 microns, the threshold voltage will be close to or higher than point 121. Assuming the length of the transistor M1 is about 0.8 microns, the threshold voltage will be close to point 120. Therefore, the threshold voltage of the transistor M1 will be lower than the threshold voltage (121) of the stacked circuit, and the driving ability of the stacked circuit will be less than the driving ability of the transistor M1.

[0066] Figure 9Shown is an optimized circuit for generating a power-on reset signal, which circuit includes a stacked circuit X1 and an impedance element R1. In some embodiments, the first end of the stacked circuit X1 is electrically connected or directly connected to a first power supply node. In this embodiment, the first power supply node is a power supply node to receive a voltage VDD. The second end of the stacked circuit X1 is electrically connected or directly connected to node N1 at node N1. The impedance element R1 is electrically connected or directly connected to node N1. The impedance element R1 is electrically connected or directly connected to a second power supply node. In some embodiments, the second power supply node is a reference voltage node to receive a voltage VSS (e.g., ground). The stacked circuit X1 may include a stack of stacked P-channel transistors, wherein the gates of the transistors are electrically connected or directly connected to the reference voltage node to receive a voltage VSS.

[0067] In addition, the circuit includes a P-channel transistor MP1. The source of the P-channel transistor MP1 is electrically connected or directly connected to the power supply node to receive a voltage VDD. The drain of the P-channel transistor MP1 is electrically connected or directly connected to an output node POR for generating a power-on reset signal. The circuit further includes an N-channel transistor MN1. The drain of the N-channel transistor MN1 is electrically connected or directly connected to the output node POR. The source of the N-channel transistor MN1 is electrically connected or directly connected to the reference voltage node to receive a voltage VSS. The gates of the P-channel transistor MP1 and the N-channel transistor MN1 are electrically connected or directly connected to node N1 to serve as an inverter.

[0068] The impedance element R1 can be implemented by any type of resistor, including passive impedance elements such as diffusion resistors or polysilicon resistors (polysilicon strips).

[0069] In one embodiment, the stacked circuit X1 includes n stacked P-channel transistors MCN, where n is a value from 1 to N (a positive integer). The stacked P-channel transistors MCN are electrically connected between the power supply node VDD and node N1 (i.e., the gate of the P-channel transistor MP1). These transistors are a plurality of stacked P-channel transistors. The number of transistors "N" in the stacked circuit depends on a specific manufacturing process and is at least 2. In some embodiments, N can be a value equal to or greater than 4. In some embodiments, N is at least 5.

[0070] The gates of the stacked P-channel transistors MC1 to MCN in the stacked P-channel transistor are electrically connected to the reference voltage node VSS. The bodies of the stacked P-channel transistors MC1 to MCN in the stacked P-channel transistor are electrically connected to the power supply node VDD. The stacked P-channel transistors MC1 to MCN in the stacked P-channel transistor can be formed in independent n-wells, connected to the voltage VDD respectively, connected to the voltage VDD through a shared n-well, or can be formed in n-wells with other configurations.

[0071] As a result of the stacked configuration, the source-to-body voltage (VSB) of the transistors in the stacked circuit becomes more negative (i.e., n increases), making the source-to-body voltage VSB of the stacked P-channel transistor MCN lower (more negative) than the source-to-body voltage VSB of the transistor MC1, which will cause a change in the threshold voltage of the transistor due to the substrate effect. For example, the threshold voltage of the transistor increases with the substrate effect. Using the technology of the present disclosure, even when using very small transistors, the threshold voltage of the stacked circuit X1 can be reliably achieved to be greater than the threshold voltage of the P-channel transistor MP1.

[0072] In one embodiment, the stacked circuit generates a source-to-body voltage VSB on at least one stacked P-channel transistor (such as MCN) in the stack. This will reduce the pull-up driving ability of the stacked circuit X1 relative to the inverter circuit.

[0073] Figure 9 The shown circuit can operate with a supply power less than 2 volts, and in other embodiments, the circuit is operable when the maximum value of the voltage across the first power supply node and the second power supply node is less than 1.6 volts. In some embodiments, the circuit can be applied to integrated circuits rated for operation with a 1.2-volt power supply voltage, and its operating range is between the specified values of 1.05 volts and 1.3 volts.

[0074] In one embodiment, the stacked circuit X1 is a metal oxide semiconductor (MOS) circuit, and its driving ability is less than that of the inverter circuit.

[0075] The inverter circuit includes a first P-channel transistor and a first N-channel transistor. The stacked circuit X1 includes one or more second P-channel transistors (such as the stacked P-channel transistors MC1 to MCN). The equivalent threshold voltage of the stacked circuit X1 (or the second P-channel transistor) is greater than the threshold voltage of the first P-channel transistor. The equivalent channel length of the stacked circuit X1 (or the second P-channel transistor) is greater than the channel length of the first P-channel transistor.

[0076] Figure 10 Shown is a simplified schematic diagram of an integrated circuit including a power-on reset circuit. The integrated circuit includes power rails 500 and 501 for carrying supply voltage VDD and reference voltage VSS respectively. The stacked circuit X1 (510) is electrically connected between the power rail 500 and the node N1. The impedance element 511 is electrically connected between the node N1 (the gate of the P-channel transistor MP1) and the power rail 501. The inverter circuit 520 is electrically connected between the power rails 500 and 501, and the node N1 is its input point. The output of the inverter circuit 520 is the power-on reset signal POR. The power-on reset signal POR is provided to the internal circuit 530. The internal circuit 530 is electrically connected between the first power rail 500 and the second power rail 501. The power-on reset signal POR can be a pulse signal for resetting, or a signal set to a known safe state, and this signal is provided to other circuits outside the integrated circuit, such as a status device.

[0077] In Figure 10 the circuit shown, the inverter circuit 520 is electrically connected between the first power rail 500 and the second power rail 501, has an input terminal at the node N1, and has an output node. When the voltage between the input node N1 and the first power rail 500 is greater than the first trip point (for example Figure 9 the threshold voltage of the P-channel transistor MP1 in Figure 9 ), the inverter circuit 520 switches the output node to the first power rail 500 (i.e., VDD). When the voltage between the node N1 and the second power rail 501 is greater than the second trip point (such as:

[0078] the threshold voltage of the N-channel transistor MN1 in ), the inverter circuit 520 switches the output node to the second power rail 501 (i.e., VSS). When the voltage between the first power rail 500 and the second power rail 501 is greater than the threshold voltage of the stacked circuit X1, the stacked circuit X1 pulls up the voltage of the input node N1 above the second trip point. The stacked circuit X1 can include a circuit that generates a source-to-base voltage on at least one P-channel transistor in the circuit, and this circuit is used to establish "a driving ability less than that of the inverter circuit" and "a threshold voltage higher than the first trip point of the inverter circuit". Accordingly, the threshold voltage of the stacked circuit X1 is greater than the first trip point, and the pull-up driving ability of the stacked circuit X1 is less than the pull-up driving ability of the inverter circuit. Therefore, as the voltage VDD increases after recovering from a power-down event. After the inverter circuit pulls up the output node to the first power rail 500, the stacked circuit X1 should conduct. When the stacked circuit X1 conducts, the voltage of the node N1 rises, and the inverter circuit will pull down the output node of the inverter circuit after the output node reaches a sufficient amplitude, thereby forming the power-on reset pulse signal POR.The magnitude and duration of the pulse are functions of the effective threshold voltage and the difference in pull-up driving capabilities of the overlapping circuit X1 and the inverter circuit. The magnitude and duration of the power-on reset signal POR must be sufficient to ensure the operation of the internal circuit 530. Therefore, the magnitude must be greater than the operating voltage of the internal circuit 530. This operating voltage must be greater than the threshold voltage of the transistor. Typically, MOS transistors used in the circuit are required to drive the initialization function of the integrated circuit in response to the power-on reset signal POR.

[0079] Figure 11 A process corner chart of a circuit, used to present Figure 9 The circuit has excellent operating characteristics with respect to process, voltage, and temperature (PVT) variations. As shown in the figure, the magnitude (or potential) of the output power-on reset signal POR is sufficient to meet the following requirements: within the temperature range of "-50°C, +25°C, +95°C, and +135°C" and within the supply voltage range of "1.05 V, 1.2 V, 1.4 V, and 1.6 V", it can exceed the threshold voltage of small MOS transistors produced by processes such as TT, SS, FF, SF, and FS.

[0080] In the present disclosure, if two nodes have current transmission during the operation of the circuit, they are "electrically connected". If two nodes have physical ohmic contact, they are "directly connected", for example, through resistive elements such as polysilicon bars or plugs, resistive diffusion regions, wires, or metal connectors.

[0081] Although the present disclosure has been disclosed as above in embodiments, it is not intended to limit the present disclosure, but is merely exemplary. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, and these modifications and combinations will fall within the spirit of the present disclosure and the scope of the appended claims.

Claims

1. A power-on reset circuit, connected to generate a control signal in response to a voltage across a first power supply node and a second power supply node, comprising: a P-channel transistor having a gate, a source and a drain, wherein the source of the P-channel transistor is electrically connected to the first power supply node, and the drain of the P-channel transistor is electrically connected to an output node; an N-channel transistor having a gate, a source and a drain, wherein the gate of the N-channel transistor is electrically connected to the gate of the P-channel transistor, the drain of the N-channel transistor is electrically connected to the output node, and the source of the N-channel transistor is electrically connected to the second power supply node; an impedance element electrically connected between the gate of the P-channel transistor and the second power supply node; and A stacked circuit includes n stacked P-channel transistors, the n stacked P-channel transistors include multiple gates and multiple bases, the gates of the n stacked P-channel transistors are electrically connected to the second power supply node, the bases of the n stacked P-channel transistors are electrically connected to the first power supply node, wherein n is a positive integer between 1 and N, and is greater than or equal to 2, the n stacked P-channel transistors are electrically connected between the first power supply node and the gate of the P-channel transistor, wherein when a voltage at the first power supply node rises ramp from a power-off state, the P-channel transistor and the N-channel transistor are used to generate a power-on reset signal, the power-on reset signal is a voltage pulse on the output node, and includes a ramp portion that rises with the voltage of the first power supply node, so that the voltage pulse drops to a voltage on the second power supply node during a period in which the voltage at the first power supply node continues to increase to an operating voltage.

2. The power-on reset circuit according to claim 1, wherein N is greater than 4. 3 . The power-on reset circuit as claimed in claim 1 , wherein the impedance element comprises a diffusion resistor. 4 . The power-on reset circuit as claimed in claim 1 , wherein the impedance element comprises a polysilicon resistor. 5 . The power-on reset circuit as claimed in claim 1 , wherein a maximum value of the voltage across the first power node and the second power node is less than 1.6 volts.

6. The power-on reset circuit according to claim 1, wherein the n cascaded P-channel transistors include a plurality of gates and a plurality of bases, the gates of the n cascaded P-channel transistors are directly connected to the second power supply node, and the bases of the n cascaded P-channel transistors are directly connected to the first power supply node.

7. An integrated circuit for power-on reset, having a first power supply node and a second power supply node, comprising: an inverter circuit electrically connected between the first power supply node and the second power supply node and having an input node and an output node; a P-channel transistor electrically connected between the first power supply node and the input node of the inverter circuit; an impedance element electrically connected between the input node of the inverter circuit and the second power supply node; A stacking circuit is used to generate a source-to-base voltage on the P-channel transistor to reduce the pull-up driving ability of the P-channel transistor relative to an inverter circuit; and an internal circuit, electrically connected between the first power supply node and the second power supply node, and configured to establish a known state according to a pulse on the output node of the inverter circuit, wherein when a voltage at the first power supply node ramps up from a power-off state, the inverter circuit is configured to generate a power-on reset signal, the power-on reset signal being a voltage pulse on the output node and including a ramp portion as the voltage at the first power supply node rises, such that subsequently during a period when the voltage at the first power supply node continues to increase to an operating voltage, the voltage pulse drops to a voltage at the second power supply node.

8. The integrated circuit for power-on reset according to claim 7, wherein the stacking circuit includes a plurality of stacked P-channel transistors, and the stacked P-channel transistors include the aforementioned P-channel transistor.

9. The integrated circuit for power-on reset according to claim 8, wherein the stacked P-channel transistors include a plurality of gates and a plurality of bases, the gates of the stacked P-channel transistors are electrically connected to the second power supply node, and the bases of the stacked P-channel transistors are electrically connected to the first power supply node.

10. The integrated circuit for power-on reset according to claim 9, wherein the number of the stacked P-channel transistors is N, and N is an integer greater than or equal to 4.

11. The integrated circuit for power-on reset according to claim 7, wherein the impedance element includes a diffused resistor.

12. The integrated circuit for power-on reset according to claim 7, wherein the impedance element includes a polysilicon resistor.

13. The integrated circuit having a power-on reset circuit according to claim 7, wherein a maximum value of a voltage across between the first power supply node and the second power supply node is less than 1.6 volts.

14. The integrated circuit for power-on reset according to claim 7, wherein when a first voltage across between the input node and the first power supply node is greater than a first trigger point voltage, the inverter circuit switches the output node to the first power supply node; when a second voltage across between the input node and the second power supply node is greater than a second trigger point voltage, the inverter circuit switches the output node to the second power supply node.

15. A power-on reset circuit for generating a control signal according to a change in a voltage across between a first power supply node and a second power supply node, comprising: a first P-channel transistor having a gate, a source, and a drain, wherein the source of the first P-channel transistor is electrically connected to the first power supply node, and the drain of the first P-channel transistor is electrically connected to an output node; A first N-channel transistor having a gate, a source, and a drain, wherein the gate of the first N-channel transistor is directly connected to the gate of the first P-channel transistor, the drain of the first N-channel transistor is electrically connected to the output node, and the source of the first N-channel transistor is electrically connected to the second power supply node; An impedance element electrically connected between the gate of the first P-channel transistor and the second power supply node; and A stacked circuit including a second P-channel transistor, wherein the second P-channel transistor is located between the gate of the first P-channel transistor and the first power supply node; the stacked circuit is configured to make the source-to-base voltage of the second P-channel transistor lower than the source-to-base voltage of the first P-channel transistor, wherein when a voltage at the first power supply node ramps up from a power-off state, the first P-channel transistor and the first N-channel transistor are used to generate a power-on reset signal, the power-on reset signal is a voltage pulse on the output node, and includes a ramp portion as the voltage at the first power supply node rises, such that subsequently during a period when the voltage at the first power supply node continues to increase to an operating voltage, the voltage pulse drops to a voltage on the second power supply node.

16. The power-on reset circuit according to claim 15, wherein an equivalent threshold voltage of the second P-channel transistor is greater than a threshold voltage of the first P-channel transistor.

17. The power-on reset circuit according to claim 16, wherein an equivalent channel length of the second P-channel transistor is greater than a channel length of the first P-channel transistor.

18. The power-on reset circuit according to claim 16, wherein the stacked circuit includes a plurality of stacked P-channel transistors, and the stacked P-channel transistors include the second P-channel transistor.

19. The power-on reset circuit according to claim 18, wherein the stacked P-channel transistors include a plurality of gates and a plurality of bases, the gates of the stacked P-channel transistors are electrically connected to the second power supply node, and the bases of the stacked P-channel transistors are electrically connected to the first power supply node.

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