Analog calculation device, array and method, chip, electronic device

Abstract

The present application provides an analog computing device, an array and method, a chip, and an electronic device. The analog computing device includes: a programmable charge storage unit, the programmable charge storage unit including a control gate, a source end, and a drain end, the control gate including a first end and a second end, the first end and the second end being oppositely arranged; a first word line (WL) connected to the first end; a second word line (WL') connected to the second end; a bit line (BL) connected to the drain end; and a source line (SL) connected to the source end. During the process of analog computing, after the programmable charge storage unit is programmed based on a target parameter, equal read voltages are input to the first word line (WL) and the second word line (WL'), a target voltage is input to the bit line (BL), the programmable charge storage unit operates in the linear region, the target parameter has a mapping relationship with a first analog quantity, the target voltage has a mapping relationship with a second analog quantity, and the product of the first analog quantity and the second analog quantity has a mapping relationship with the current output by the source line (SL). By adopting the above solution, the multiplication calculation of two analog quantities is realized.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to an analog quantity calculation device, an array and a method, a chip, and an electronic device. Background Art

[0002] Flash Memory is a form of electronically erasable programmable read-only memory that allows the memory to be erased or written multiple times during operation. According to the different array structures, flash memory can be divided into NOR flash memory and NAND flash memory. In an AI chip, for NOR flash memory, by applying different programming voltages and / or programming times to the control gates of transistors in the NOR flash memory, electrons will be written into the floating gates of the transistors, changing the amount of charge stored in the floating gate (Floating Gate) or charge trap (Charge Trap) of the transistor, thereby changing the threshold voltage of the transistor. Summary of the Invention

[0003] The purpose of the embodiments of this application is to provide an analog quantity calculation device, an array and a method, a chip, and an electronic device, in which the product of the first analog quantity and the second analog quantity has a proportional mapping relationship with the current output from the source line, so that the product of the first analog quantity and the second analog quantity can be obtained based on the current output from the source line, realizing the multiplication calculation of two analog quantities.

[0004] The embodiments of this application provide an analog quantity calculation device, including: a programmable charge storage unit, the programmable charge storage unit includes a control gate, a source end, and a drain end, the control gate includes a first end and a second end, and the first end and the second end are oppositely arranged; a first word line is connected to the first end; a second word line is connected to the second end; a bit line is connected to the drain end; and a source line is connected to the source end; during the process of analog quantity calculation, after the programmable charge storage unit is programmed based on a target parameter, equal read voltages are input to the first word line and the second word line, a target voltage is input to the bit line, the programmable charge storage unit operates in the linear region, the target parameter has a mapping relationship with the first analog quantity, the target voltage has a mapping relationship with the second analog quantity, and the product of the first analog quantity and the second analog quantity has a mapping relationship with the current output from the source line.

[0005] An embodiment of the present application provides an analog quantity calculation method, which is applied to the above-mentioned analog quantity calculation device. The method includes: mapping a first analog quantity to a target parameter, and programming the analog quantity calculation device based on the target parameter; inputting equal read voltages on a first word line and a second word line connected to the analog quantity calculation device respectively; inputting a target voltage obtained by mapping a second analog quantity on a bit line connected to the analog quantity calculation device, and reading the current at the source end of the analog quantity calculation device; the programmable charge storage unit operates in the linear region, and there is a mapping relationship between the product of the first analog quantity and the second analog quantity and the current on the source line.

[0006] An embodiment of the present application provides an analog quantity calculation array, including a plurality of the above-mentioned analog quantity calculation devices; the analog quantity calculation devices in the same row share a first word line and a second word line, the analog quantity calculation devices in the same row share a source line, and the analog quantity calculation devices in the same column share a bit line; during the analog quantity calculation process, after each analog quantity calculation device is programmed based on the target parameter, equal read voltages are input on the first word line and the second word line connected to each analog quantity calculation device, corresponding target voltages are input on the bit lines of each column connected to each analog quantity calculation device, and the programmable charge storage unit in the analog quantity calculation device operates in the linear region; there is a mapping relationship between the target parameter and the analog quantity corresponding to the analog quantity calculation device in the target matrix, there is a mapping relationship between the target voltage and the analog quantity corresponding to the column number of the analog quantity calculation device in the target vector in the array, and there is a mapping relationship between the product of the target matrix and the target vector and the vector composed of the currents on the source lines of each row in the array.

[0007] An embodiment of the present application provides an analog quantity calculation method, which is applied to the above-mentioned analog quantity calculation array. The method includes: for each analog quantity calculation device in the analog quantity calculation array, mapping the analog quantity corresponding to the analog quantity calculation device in the target matrix to a target parameter, and programming the analog quantity calculation device based on the target parameter; inputting equal read voltages on the first word line and the second word line connected to each analog quantity calculation device respectively; mapping the analog quantity corresponding to the column number of the analog quantity calculation device in the target vector to a target voltage, inputting the corresponding target voltage on the bit lines of each column in the analog quantity calculation array, and sequentially reading the currents on the source lines of each row in the array; the programmable charge storage unit in the analog quantity calculation device operates in the linear region, and there is a mapping relationship between the product of the target matrix and the target vector and the vector composed of the currents on the source lines of each row in the array.

[0008] An embodiment of the present application further provides a chip, including at least one of the above-mentioned analog quantity calculation arrays.

[0009] An embodiment of the present application further provides an electronic device, including the above-mentioned chip.

[0010] In the embodiments of the present application, for the prior art, the first end of the control gate of the programmable charge storage unit of the analog quantity calculation device is connected to the first word line, the second end is connected to the second word line, the drain end is connected to the bit line, and the source end is connected to the source line; during the analog quantity calculation process, the first analog quantity is mapped to a target parameter, the programmable charge storage unit is programmed based on the target parameter, equal read voltages are input to the first word line and the second word line, and a target voltage obtained by mapping the second analog quantity is input to the bit line. At this time, the programmable charge storage unit operates in the linear region, and the product of the target parameter and the target voltage is in a proportional mapping relationship with the current output from the source line of the programmable charge storage unit, that is, the product of the first analog quantity and the second analog quantity is in a proportional mapping relationship with the current output from the source line. Therefore, the product of the first analog quantity and the second analog quantity can be obtained based on the current output from the source line, realizing the multiplication calculation of two analog quantities. Description of the Drawings

[0011] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the drawings in the figures do not constitute a proportional limitation.

[0012] Figure 1 is a schematic circuit diagram of a transistor of a NOR-type flash memory used for analog quantity calculation;

[0013] Figure 2 is a schematic circuit diagram of a programmable charge storage transistor in an analog quantity calculation device according to the first embodiment of the present application;

[0014] Figure 3 is a schematic circuit diagram of a 2flash transistor according to the first embodiment of the present application;

[0015] Figure 4 is a schematic diagram of the programming area of a programmable charge storage transistor according to the first embodiment of the present application;

[0016] Figure 5 is a schematic circuit diagram of a programmable charge storage unit including multiple programmable charge storage transistors in an analog quantity calculation device according to the second embodiment of the present application;

[0017] Figure 6 is a schematic circuit diagram of an analog quantity calculation array according to the third embodiment of the present application;

[0018] Figure 7 is Figure 6 a schematic diagram of the structure of a column of analog quantity calculation devices in the analog quantity calculation array in

[0019] Figure 8 is Figure 6 The schematic cross-sectional structure diagram obtained by cutting the analog quantity calculation array in

[0020] Figure 9 is Figure 6 The schematic cross-sectional structure diagram obtained by cutting the analog quantity calculation array in along the dashed line L0;

[0021] Figure 10 The schematic diagram of the analog quantity calculation array according to the fourth embodiment of the present application;

[0022] Figure 11 is Figure 9 The schematic structure diagram of a column of analog quantity calculation devices in the analog quantity calculation array in

[0023] Figure 12 The specific flowchart of the analog quantity calculation method according to the fifth embodiment of the present application, and this analog quantity calculation method is applied to the analog quantity calculation device in the first embodiment;

[0024] Figure 13 The specific flowchart of the analog quantity calculation method according to the sixth embodiment of the present application, and this analog quantity calculation method is applied to the analog quantity calculation device in the second embodiment;

[0025] Figure 14 The specific flowchart of the analog quantity calculation method according to the seventh embodiment of the present application, and this analog quantity calculation method is applied to the analog quantity calculation array in the third embodiment;

[0026] Figure 15 The specific flowchart of the analog quantity calculation method according to the eighth embodiment of the present application, and this analog quantity calculation method is applied to the analog quantity calculation array in the fourth embodiment. Detailed implementation manners

[0027] In order to make the purpose, technical solutions and advantages of the present application clearer, the following further elaborates on the embodiments of the present application in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0028] Such as Figure 1As shown, it is the structure of a transistor of an existing NOR flash memory for analog quantity calculation. The gate of the transistor is connected to the word line (abbreviated as WL), the drain of the transistor is connected to the bit line (abbreviated as BL), and the source of the transistor is connected to the source line (abbreviated as SL). When performing analog quantity calculation, an analog quantity is pre-programmed and mapped to a voltage value, which is the difference (VGS - VTH) obtained by subtracting the threshold voltage VTH of the transistor from the gate voltage VGS of the transistor; when reading, another analog quantity is mapped to the input voltage VDS of the bit line BL. Therefore, when the transistor operates in the linear region, the channel current ID read by the source line SL = K(VGS - VTH) * VDS * W / L, where one analog quantity has a mapping relationship with (VGS - VTH), and another analog quantity has a mapping relationship with VDS. It can be seen that ID has a mapping relationship with the product of the two analog quantities, so that the product of the two analog quantities can be mapped from ID, realizing the multiplication operation of analog quantities; where K is a coefficient, W is the channel width of the transistor, and L is the channel length of the transistor.

[0029] However, when the analog quantity is mapped to the difference (VGS - VTH), the mapping relationship is not linear, and there is also a non-linear relationship between VTH and K; therefore, a large number of peripheral circuits and operation time are required to complete the mapping relationship. Based on this, the inventor proposed the technical solution of this application.

[0030] The first embodiment of this application relates to an analog quantity calculation device, which is applied to a processing chip in an electronic device, and the electronic device is, for example, a mobile phone, a computer, etc. The analog quantity calculation device is used to realize the multiplication calculation of two analog quantities, and the analog quantity calculation device is composed of an electrically erasable programmable read-only memory (abbreviated as EEPROM) that can perform independent read and write operations.

[0031] In this embodiment, the analog quantity calculation device includes: a programmable charge storage unit, the programmable charge storage unit includes a control gate, a source end and a drain end, the control gate includes a first end and a second end, and the first end and the second end are oppositely arranged; a first word line is connected to the first end; a second word line is connected to the second end; a bit line is connected to the drain end; and a source line is connected to the source end.

[0032] During the process of analog quantity calculation, after the programmable charge storage unit is programmed based on the target parameter, equal read voltages are input to the first word line and the second word line, a target voltage is input to the bit line, the programmable charge storage unit operates in the linear region, there is a mapping relationship between the target parameter and the first analog quantity, there is a mapping relationship between the target voltage and the second analog quantity, and there is a mapping relationship between the product of the first analog quantity and the second analog quantity and the current output from the source line.

[0033] Compared with the prior art, for the programmable charge storage unit of the analog quantity calculation device, the first end of the control gate is connected to the first word line, the second end is connected to the second word line, the drain end is connected to the bit line, and the source end is connected to the source line; during the analog quantity calculation process, the first analog quantity is mapped to the target parameter, the programmable charge storage unit is programmed based on the target parameter, equal read voltages are input to the first word line and the second word line, and the target voltage mapped from the second analog quantity is input to the bit line. At this time, the programmable charge storage unit operates in the linear region, and the product of the target parameter and the target voltage is in a proportional mapping relationship with the current output from the source line of the programmable charge storage unit, that is, the product of the first analog quantity and the second analog quantity is in a proportional mapping relationship with the current output from the source line. Therefore, the product of the first analog quantity and the second analog quantity can be obtained based on the current output from the source line, realizing the multiplication calculation of two analog quantities.

[0034] Taking the programmable charge storage unit including a programmable charge storage transistor as an example, the implementation details of the analog quantity calculation device in this embodiment are specifically described below. The following content is only the implementation details provided for convenient understanding and is not necessary for implementing this solution.

[0035] Please refer to Figure 2 , the analog quantity calculation device includes a programmable charge storage transistor. The programmable charge storage transistor is a non-volatile transistor with a charge storage function, and the charge is locally stored in the transistor, that is, the charge is localized in the charge storage layer of the transistor.

[0036] The gate of the programmable charge storage transistor forms the control gate of the programmable charge storage unit. The two ends of the gate of the programmable charge storage transistor respectively form the first end and the second end. The source of the programmable charge storage transistor forms the source end of the programmable charge storage unit, and the drain of the programmable charge storage transistor forms the drain end of the programmable charge storage unit.

[0037] In this embodiment, the two ends of the gate of the programmable charge storage transistor are respectively connected to the first word line WL and the second word line WL', the source of the programmable charge storage transistor is connected to the source line SL, and the drain of the programmable charge storage transistor is connected to the bit line BL.

[0038] In this embodiment, the transistor is a charge trap transistor, such as a SONOS transistor or a nanocrystalline floating gate transistor. The transistor can be a single transistor or a split gate structure transistor. In one example, the transistor may further include a select transistor, please refer to Figure 3 , which is a 2-transistor flash cell. The transistor connected to the first word line WL and the second word line WL' is used to implement two analog multiplication operations. The select transistor SG connected to the CG line controls the flash cell.

[0039] Please refer to Figure 4 . For a SONOS transistor, when the voltages of the source, drain, and gate of the transistor are configured to certain voltage values such that the programming voltage input to the gate of the transistor is greater than the programming threshold voltage of the transistor, a large number of electrons will enter the charge storage layer of the transistor, causing the transistor to be programmed. The width of the programmed area changes, and the electrons are localized in the programmed area of the charge storage layer and do not move extensively. That is, the width of the programmed area of the programmed transistor does not change; when the programming voltage input to the gate of the transistor is less than or equal to the programming threshold voltage of the transistor, the width of the programmed area of the transistor basically does not change; based on this, by adjusting the voltages of the two word lines of the control gate of the transistor, the width of the programmed area of the transistor can be controlled. In other words, the width of the unprogrammed area of the transistor can be controlled. In the programmed area of the transistor, a large number of electrons are trapped in the charge storage layer, and its read threshold voltage increases; in the unprogrammed area, the probability of electron trapping is very low, and its read threshold voltage remains basically unchanged. Since the voltage change of the control gate of the transistor is continuous, the width of the unprogrammed area can be continuously mapped to an analog quantity.

[0040] In this embodiment, the programming method of the programmable charge storage transistor is any one of the following: hot electron injection, FN tunneling, band-to-band tunneling, direct tunneling, defect-assisted tunneling.

[0041] In this embodiment, using Figure 2 's analog calculation device to implement the multiplication operation of two analog quantities (the first analog quantity and the second analog quantity), the specific process is as follows. The target parameter that has a mapping relationship with the first analog quantity is the target width, that is, the first analog quantity has a mapping relationship with the target width.

[0042] The first step is to map the first analog quantity to the target width W, and program the analog calculation device based on the target width W so that the width of the unprogrammed area of the transistor in the programmable charge storage unit matches the target width.

[0043] Taking FN tunneling as an example programmatically, the voltages and voltage differences input to the first word line WL and the second word line WL' connected to the transistor are adjusted. The voltage input on one word line is greater than the programming threshold voltage of the transistor, and the voltage input on the other word line is less than the programming threshold voltage of the transistor. A 0 voltage is applied to the bit line BL and the source line SL of the transistor. Due to FN tunneling, a large number of electrons are injected into a part of the charge storage layer of the transistor for programming, and the width of the programmed area of the transistor changes. Correspondingly, the width of the unprogrammed area of the transistor also changes accordingly. Based on this, the width of the unprogrammed area of the transistor can be made to match the target width W, that is, the first analog quantity is mapped to the width of the unprogrammed area of the transistor.

[0044] In the first step, after the transistor is programmed based on the target width W, both the width of its programmed area and the width of its unprogrammed area change. Correspondingly, the threshold voltage V1 of the programmed area and the threshold voltage V2 of the unprogrammed area also change. When the read voltage is greater than the threshold voltage V1, the entire transistor can be turned on; when the read voltage is between the threshold voltage V1 and the threshold voltage V2, only the unprogrammed area of the transistor can be turned on; when the read voltage is less than the threshold voltage V2, the entire transistor cannot be turned on.

[0045] In the second step, the same read voltage is input on the two word lines (the first word line WL and the second word line WL') connected to the transistor. The read voltage is greater than the threshold voltage (turn-on voltage) of the unprogrammed area of the transistor in the programmable charge storage unit and less than the threshold voltage (turn-on voltage) of the programmed area of the transistor. At this time, the unprogrammed area of the transistor can be turned on, and the programmed area of the transistor cannot be turned on.

[0046] In the third step, the second analog quantity is mapped to a target voltage, and this target voltage is input on the bit line BL of the transistor, so that the unprogrammed area of the transistor operates in the linear region; at this time, the current I of the source line SL of the transistor is read D , I D = K(V GS - V TH ) * V DS * W / L. It can be seen that the current ID is directly proportional to the product of W and V DS . And W and V DS are respectively mapped to the first analog quantity and the second analog quantity. Therefore, the current I D is directly proportional to the product of the first analog quantity and the second analog quantity. Thus, the product of the first analog quantity and the second analog quantity can be obtained according to this current I D , realizing the multiplication operation of analog quantities; where K represents a coefficient, V GS represents the gate voltage of the transistor, V THrepresents the threshold voltage of the unprogrammed region of the transistor, W is the width of the unprogrammed region of the transistor channel, and L is the channel length of the transistor.

[0047] In this embodiment, both ends of the gate of the programmable charge storage transistor in the programmable charge storage unit of the analog quantity calculation device are respectively connected to the first word line and the second word line, so that the width of the unprogrammed region of the transistor can be controlled by programming the transistor, making the width of the unprogrammed region of the programmed transistor equal to the target width mapped from the first analog quantity, that is, the first analog quantity is mapped to the width of the unprogrammed region of the transistor; then the same read voltage is input on the first word line and the second word line, and this read voltage is greater than the threshold voltage of the unprogrammed region of the transistor in the analog quantity calculation device and less than the threshold voltage of the programmed region of the transistor, so that the unprogrammed region of the transistor can be turned on; at this time, the target voltage mapped from the second analog quantity is input on the bit line connected to the drain of the transistor, making the unprogrammed region of the transistor operate in the linear region, and then the current of the source line connected to the source of the transistor is read. The current of the source line is in direct proportion to the product of the width of the unprogrammed region and the target voltage, that is, in direct proportion to the product of the first analog quantity and the second analog quantity. Thus, the product of the first analog quantity and the second analog quantity can be obtained according to the current of the source line, realizing the multiplication calculation of two analog quantities; the mapping relationship between the first analog quantity and the width of the unprogrammed region tends to be linear, which can save the peripheral circuit and operation time and improve the operation speed. At the same time, a large range of analog quantity calculations can be realized by increasing the width of the transistor, which is easier to implement; and because the mapping relationship between the first analog quantity and the width of the unprogrammed region tends to be linear, even if the width of the transistor is increased, the calculation accuracy will not be affected. In addition, since the multiplication calculation of two analog quantities can be realized by only one programmable charge storage transistor, the area of the chip is saved.

[0048] The second embodiment of the present application relates to an analog quantity calculation device. The main difference between this embodiment and the first embodiment is that: in the first embodiment, the programmable charge storage unit includes one programmable charge storage transistor as an example for description, and in this embodiment, the programmable charge storage unit includes multiple programmable charge storage transistors as an example for description.

[0049] Please refer to Figure 5 , the programmable charge storage unit in the analog quantity calculation device includes multiple programmable charge storage transistors, and the threshold voltages of the multiple transistors are matched, that is, the threshold voltages of the multiple transistors are approximately equal; the transistor can be a charge trapping transistor or a floating gate transistor.

[0050] The gates of multiple programmable charge storage transistors are sequentially connected to form the control gate of the programmable charge storage cell. The target ends of the gates of the two programmable charge storage transistors located at both ends of the control gate respectively form a first end and a second end, and the target end is the end of the gate of the programmable charge storage transistor that is not connected to the adjacent programmable charge storage transistor.

[0051] In this embodiment, the gates of multiple programmable charge storage transistors are sequentially connected to form the control gate of the programmable charge storage cell. The target ends of the gates of the two programmable charge storage transistors located at both ends of the control gate form the first end and the second end of the programmable charge storage cell, that is, the target ends of the gates of the two programmable charge storage transistors located at both ends of the control gate are respectively connected to the first word line WL and the second word line WL'; the sources of multiple transistors are connected to each other to form the source end of the programmable charge storage cell, and this source end is connected to the source line SL; the drains of multiple programmable charge storage transistors are connected to each other to form the drain end of the programmable charge storage cell, and this drain end is connected to the bit line BL; among them, the gates of multiple transistors can be connected through any conductor. In one example, the gates of multiple programmable charge storage transistors are sequentially connected to form a shared gate for multiple programmable charge storage transistors, and the two ends of the shared gate respectively form a first end and a second end.

[0052] In this embodiment, the programming method of the analog computing device is any one of the following: hot electron injection, FN tunneling, band-to-band tunneling, direct tunneling, defect-assisted tunneling.

[0053] In this embodiment, using Figure 5 the specific process of realizing the multiplication operation of two analog quantities (the first analog quantity and the second analog quantity) by the analog computing device therein is as follows, where the target parameter having a mapping relationship with the first analog quantity is the target quantity, that is, the first analog quantity has a mapping relationship with the target quantity.

[0054] In the first step, map the first analog quantity to the target quantity m, and program the programmable charge storage cell of the analog computing device based on the target quantity m, so that the number of unprogrammed transistors in the programmable charge storage cell is equal to the target quantity.

[0055] Taking the programming method of hot electron injection as an example, the voltage and voltage difference input to the first word line WL and the second word line WL' connected to the programmable charge storage unit are adjusted, and a positive voltage is applied to the bit line BL connected to the programmable charge storage unit and a voltage of 0 is applied to the source line SL. Due to the channel hot electron injection effect, electrons will enter the floating gate layer of each transistor. At this time, by adjusting the change of the voltage and voltage difference on the first word line WL and the second word line WL', the number of transistors that are programmed can be controlled, that is, the number of unprogrammed transistors can be controlled, so that the number of unprogrammed transistors in the analog quantity calculation device is equal to the target number m, that is, the number of unprogrammed transistors m is mapped to the first analog quantity. Among them, if the analog quantity calculation device includes n transistors, the analog quantity calculation device can realize the mapping of n+1 analog quantities.

[0056] In the second step, the same read voltage is input to the two word lines (the first word line WL and the second word line WL') connected to the programmable charge storage unit. The read voltage is greater than the threshold voltage (turn-on voltage) of the unprogrammed transistor in the programmable charge storage unit and less than the threshold voltage (turn-on voltage) of the programmed transistor. At this time, only the unprogrammed transistor in the programmable charge storage unit can be turned on.

[0057] The third step is to map the second analog quantity to the target voltage V DS , and input the target voltage V on the bit line BL connected to the programmable charge storage unit DS , so that the unprogrammed transistor in the programmable charge storage unit operates in the linear region; read the current I of the source line SL connected to the programmable charge storage unit D , I D =K(V GS -V TH )*V DS *m, we can know the current I D With m and V DS The product of is directly proportional to m and V DS are mapped to the first analog quantity and the second analog quantity respectively, so the current I D It is directly proportional to the product of the first analog quantity and the second analog quantity, so that the current I D The product of the first analog quantity and the second analog quantity is obtained, and the multiplication operation of the analog quantity is realized; wherein K represents the coefficient, V GS Represents the gate voltage of the transistor, V TH Represents the threshold voltage of an unprogrammed transistor.

[0058] In an embodiment of the present application, the gates of multiple programmable charge storage transistors are sequentially connected to form the control gate of the programmable charge storage unit. The two ends of the control gate of the programmable charge storage unit are respectively connected to the first word line and the second word line. Thus, by programming the programmable charge storage unit, the number of unprogrammed transistors in the programmable charge storage unit can be controlled, so that the number of unprogrammed transistors is the target number mapped from the first analog quantity, that is, the first analog quantity is mapped to the number of unprogrammed transistors. Then, the same read voltage is input on the first word line and the second word line connected to the programmable charge storage unit. The read voltage is greater than the threshold voltage of the unprogrammed transistors in the analog quantity calculation device and less than the threshold voltage of the programmed transistors, so that only the unprogrammed transistors in the programmable charge storage unit can be turned on. At this time, the target voltage mapped from the second analog quantity is input on the bit line connected to the programmable charge storage unit, so that the unprogrammed transistors operate in the linear region, and the current of the source line connected to the programmable charge storage unit is read. The current of the source line is in direct proportion to the product of the number of unprogrammed transistors and the target voltage, that is, in direct proportion to the product of the first analog quantity and the second analog quantity. Thus, the product of the first analog quantity and the second analog quantity can be obtained according to the current of the source line, realizing the multiplication calculation of two analog quantities. The mapping relationship between the first analog quantity and the number of unprogrammed transistors tends to be linear, which can save the peripheral circuit and operation time and improve the operation speed. At the same time, by increasing the number of transistors, a large range of analog quantity calculations can be realized. And because the mapping relationship between the first analog quantity and the number of unprogrammed regions tends to be linear, even if the number of transistors is increased, the calculation accuracy will not be affected.

[0059] The programmable charge storage unit in this embodiment includes multiple programmable charge storage transistors. When programming the programmable charge storage unit, since the voltage differences of the gates of different programmable charge storage transistors are relatively large, the tolerance for the performance differences between multiple programmable charge storage transistors is relatively high, reducing the influence of the performance differences between programmable charge storage transistors on analog quantity calculation and improving the accuracy of analog quantity calculation.

[0060] The third embodiment of the present application relates to an analog quantity calculation array, which can realize the multiplication operation of a matrix and a vector. The analog quantity calculation array includes multiple analog quantity calculation devices in the first embodiment.

[0061] In the analog quantity calculation array, the analog quantity calculation devices in the same row share the first word line and the second word line, the analog quantity calculation devices in the same row share one source line, and the analog quantity calculation devices in the same column share one bit line.

[0062] During the analog quantity calculation process, after each analog quantity calculation device is programmed based on the target parameters, equal read voltages are input to the first word line and the second word line connected to each analog quantity calculation device, and corresponding target voltages are input to the bit lines of each column connected to each analog quantity calculation device. The programmable charge storage unit in the analog quantity calculation device operates in the linear region; there is a mapping relationship between the target parameters and the analog quantity corresponding to the analog quantity calculation device in the target matrix, a mapping relationship between the target voltage and the analog quantity corresponding to the column number of the analog quantity calculation device in the target vector in the array, and a mapping relationship between the product of the target matrix and the target vector and the vector composed of the currents of the source lines of each row in the array.

[0063] Taking the example that the programmable charge storage unit in the analog quantity calculation device includes a programmable charge storage transistor, the implementation details of the analog quantity calculation array in this embodiment will be specifically described below. The following content is only the implementation details provided for convenient understanding and is not necessary for implementing this solution.

[0064] Please refer to Figure 6 , taking the analog quantity calculation array including 15 analog quantity calculation devices, divided into 3 rows and 5 columns as an example, the programmable charge storage unit in each analog quantity calculation device includes a programmable charge storage transistor.

[0065] In the analog quantity calculation array, the analog quantity calculation devices in the same row share the first word line and the second word line. Taking the first row of the array as an example, the first end and the second end of the control gate of the programmable charge storage unit of each analog quantity calculation device in this row are respectively connected to the first word line WL0 and the second word line WL0'; in the analog quantity calculation array, the analog quantity calculation devices in the same row share one source line. Taking the first column as an example, the drain end of the programmable charge storage unit of each analog quantity calculation device in this column is connected to the bit line BL0; in the analog quantity calculation array, the analog quantity calculation devices in the same column share one bit line. Taking the first column as an example, the source end of the programmable charge storage unit of each analog quantity calculation device in this column is connected to the source line SL0. In an example, the first word line or the second word line can be shared between the analog quantity calculation devices in adjacent rows. For example Figure 6 the first word line WL0' and the second word line WL1 in

[0066] Please refer to Figure 7 for Figure 6Schematic diagram of the structure of a column of analog quantity calculation devices in the analog quantity calculation array. Each analog quantity calculation device in the analog quantity calculation array includes only one programmable charge storage transistor. In the figure, 100 is the substrate, such as a silicon substrate, 300 is the control gate of the transistor, 101 is the isolation shallow trench between adjacent transistors, 200 is the charge storage layer, such as silicon nitride, 400 is the contact hole on the non-conductive medium 600. Both ends of the gate 300 of each transistor are connected to the first word line 500 and the second word line 501 through two contact holes 400. The non-conductive medium 600 is, for example, silicon dioxide.

[0067] Please refer to Figure 8 , for Figure 6 Schematic cross-sectional structure diagram obtained by cutting the analog quantity calculation array in along any bit line. 102 represents the drain of the transistor, and 103 represents the source of the transistor. Please refer to Figure 9 , for Figure 6 Schematic cross-sectional structure diagram obtained by cutting the analog quantity calculation array in along the dashed line L0. The drain 102 of the transistor is connected to the bit line 502 through the contact hole 400, and the source 103 of the transistor is connected to the source line 503 through the contact hole 400.

[0068] In this embodiment, Figure 6 The analog quantity calculation array in can be used to implement the multiplication operation between a 3×5 matrix and a 5-element vector. Taking the target matrix and the target vector as the two quantities to be multiplied, the target parameter that has a mapping relationship with the analog quantity in the target matrix is the target width, that is, there is a mapping relationship between the analog quantity in the target matrix and the target width. The specific operation process is as follows:

[0069] In the first step, for each analog quantity calculation device in the analog quantity calculation array, map the analog quantity corresponding to the analog quantity calculation device in the target matrix to the target width, and program the analog quantity calculation device based on the target width, so that the width of the unprogrammed area of the transistor in the programmable charge storage unit in the analog quantity calculation device matches the target width.

[0070] Taking the transistor (analog computing device) in the first row and first column as an example, this transistor corresponds to the analog quantity a11. The analog quantity a11 is mapped to obtain the target width W. The voltages and voltage differences input to the first word line WL and the second word line WL' connected to the transistor are adjusted. The voltage input on one word line is greater than the programming threshold voltage of the transistor, and the voltage input on the other word line is less than the programming threshold voltage of the transistor. A 0 voltage is applied to the bit line and the source line connected to the transistor. Due to FN tunneling, a large number of electrons are injected into a part of the charge storage layer of the transistor for programming, and the width of the programmed area of the transistor changes. Correspondingly, the width of the unprogrammed area of the transistor also changes accordingly. Based on this, the width of the unprogrammed area of the transistor can be made to match the target width W, that is, the analog quantity a11 corresponding to the transistor is mapped to the width of the unprogrammed area of the transistor.

[0071] In the first step, after each transistor is programmed based on the target width, both the width of its programmed area and the width of its unprogrammed area change. Correspondingly, the threshold voltage V1 of the programmed area and the threshold voltage V2 of the unprogrammed area also change. When the read voltage is greater than the threshold voltage V1, the entire transistor can be turned on; when the read voltage is between the threshold voltage V1 and the threshold voltage V2, only the unprogrammed area of the transistor can be turned on; when the read voltage is less than the threshold voltage V2, the entire transistor cannot be turned on.

[0072] In the second step, equal read voltages are input to the first word line and the second word line connected to each analog computing device in the analog computing array, that is, equal read voltages are input to the two word lines (the first word line and the second word line) connected to each row of analog computing devices in the analog computing array; the read voltage is greater than the threshold voltage (turn-on voltage) of the unprogrammed area of the transistor in the analog computing device and less than the threshold voltage (turn-on voltage) of the programmed area of the transistor. At this time, the unprogrammed area of the transistor can be turned on, and the programmed area of the transistor cannot be turned on.

[0073] In the third step, the analog quantity corresponding to the column number of the analog computing device in the target vector is mapped to the target voltage, and the corresponding target voltage is input to the bit lines of each column in the analog computing array, so that the unprogrammed areas of the transistors of the programmable charge storage units of the analog computing devices in each column operate in the linear region, and the currents on the source lines of each row of the array are read in sequence. There is a mapping relationship between the product of the target matrix and the target vector and the vector composed of the currents on the source lines of each row in the array.

[0074] Specifically, each analog quantity in the target vector corresponds to each column in the analog quantity calculation array according to its position. The analog quantities in each row of the target vector correspond to the bit lines of each column of the array. That is, the analog quantity b1 corresponds to the first column, the analog quantity b2 corresponds to the second column, ……, the analog quantity b5 corresponds to the fifth column. Map each analog quantity to a target voltage, and input the target voltage obtained by mapping each analog quantity into the bit line of the corresponding column, so that each transistor operates in the linear region. At this time, sequentially read the current of the source line of each row of the analog quantity calculation array, and the combination of the currents read on the three source lines forms a three-element vector. Taking the current c1 output from the source line SL0 of the first row as an example, c1 = a11*b1 + a12*b2 + a13*b3 + a14*b4 + a15*b5. There is a mapping relationship between the product of the target matrix and the target vector and this three-element vector.

[0075] It should be noted that the above takes the calculation of the product of a matrix and a vector using an analog quantity calculation array as an example for illustration, but it is not limited to this. This analog quantity calculation array can also be used to implement the product operation between matrices, specifically including the following two implementation methods:

[0076] First, when implementing the product operation between the first matrix and the second matrix, divide each column in the second matrix into a column vector, so that multiple column vectors can be obtained. Then perform the above first to third steps to calculate the product of the first matrix and each column vector respectively, and obtain multiple column vectors. Then form a matrix with these multiple column vectors, and this matrix is the product of the first matrix and the second matrix.

[0077] Second, expand the analog quantity device array to the right, that is, combine multiple analog quantity calculation devices to calculate the product between matrices. Taking the analog quantity calculation array above Figure 6 as an example, if you want to implement the multiplication operation between a 3×5 first matrix and a 5×3 second matrix, then 3 Figure 6 of the above analog quantity calculation arrays need to be combined. The rows of the 3 analog quantity calculation arrays can share two word lines. When calculating, perform the above first and second steps to program the first matrix into each analog quantity calculation array respectively, divide the 3 columns of the second matrix into 3 column vectors, and then perform the third step to input these three column vectors into each analog quantity calculation array respectively, and collect the current output from the source line of each analog quantity calculation array. The current output from the source line of each analog quantity calculation array can form a column vector. Form a matrix with the three column vectors obtained from the three analog quantity calculation arrays. There is a mapping relationship between the product of the first matrix and the second matrix and the matrix formed by the three column vectors.

[0078] In the embodiments of the present application, an analog quantity calculation array including multiple analog quantity calculation devices in the first embodiment is provided to implement the product operation between a vector and a matrix.

[0079] The fourth embodiment of the present application relates to an analog computing array. The main difference between this embodiment and the third embodiment is that in the third embodiment, it is described by taking the programmable charge storage unit of the analog computing device in the analog computing array including a programmable charge storage transistor as an example, while in this embodiment, it is described by taking the programmable charge storage unit of the analog computing device in the analog computing array including multiple programmable charge storage transistors as an example.

[0080] In this embodiment, the analog computing array includes multiple analog computing devices in the second embodiment. Please refer to Figure 10 , taking the analog computing array including 10 analog computing devices in the second embodiment, divided into 2 rows and 5 columns, and the programmable charge storage unit in each analog computing device including 7 programmable charge storage transistors as an example.

[0081] The analog computing devices in the same row in the analog computing array share the first word line and the second word line. Taking the first row of the array as an example, the first end and the second end of the control gate of the programmable charge storage unit of each analog computing device in this row are respectively connected to the first word line WL0 and the second word line WL0'; the analog computing devices in the same row in the analog computing array share one source line. Taking the first column as an example, the drain end of the programmable charge storage unit of each analog computing device in this column is connected to the bit line BL0; the analog computing devices in the same column in the analog computing array share one bit line. Taking the first column as an example, the source end of the programmable charge storage unit of each analog computing device in this column is connected to the source line SL0. In one example, the analog computing devices in adjacent two rows can share one first word line or one second word line. For example Figure 10 the first word line WL0' and the second word line WL1 in

[0082] Please refer to Figure 11 , which is a longitudinal cross-sectional schematic diagram of the analog computing array. The programmable charge storage unit of each analog computing device in the analog computing array includes multiple programmable charge storage transistors. In the figure, 100 is a substrate, such as a silicon substrate, 300 is the control gate of the programmable charge storage unit, 101 is the isolation shallow trench between two adjacent transistors in the programmable charge storage unit, 200 is the floating gate layer, such as a polysilicon floating gate, 400 is the contact hole on the non-conductive medium 600. The control gate 300 of the programmable charge storage unit of each analog computing device is connected to the first word line 500 and the second word line 501 through two contact holes 400. The non-conductive medium 600 is, for example, silicon dioxide.

[0083] In this embodiment, Figure 10The analog computing array therein can be used to implement the multiplication operation between a 2×5 matrix and a 5-element vector, with the target matrix and the target vector representing the two quantities to be multiplied. The target parameter that has a mapping relationship with the analog quantity in the target matrix is the target quantity, that is, there is a mapping relationship between the analog quantity in the target matrix and the target quantity. The specific operation process is as follows:

[0084] First step, for each analog computing device in the analog computing array, map the analog quantity corresponding to the analog computing device in the target matrix to the target quantity, and program the analog computing device based on the target quantity, so that the number of unprogrammed transistors in the programmable charge storage unit in the analog computing device is equal to the target quantity.

[0085] Taking the analog computing device in the first row and the second column as an example, this analog computing device corresponds to the analog quantity a21. Map the analog quantity a21 to the target quantity K. Adjust the voltages and voltage differences input to the two word lines (the first word line WL0 and the second word line WL0’) connected to the analog computing device. Apply a voltage greater than the programming threshold voltage of the transistors in the programmable charge storage unit on one word line, and apply a voltage less than the programming threshold voltage of the transistors in the programmable charge storage unit on the other word line. Apply a positive voltage on the bit line BL1 of the analog computing device and a voltage of 0 on the source line SL0. Due to the channel hot electron injection effect, electrons will enter the floating gate layer of the transistor. At this time, by adjusting the changes in the voltages and voltage differences of the two word lines (the first word line WL0 and the second word line WL0’), the number of programmed transistors in the programmable charge storage unit can be controlled, that is, the number of unprogrammed transistors in the programmable charge storage unit can be controlled to be equal to the target quantity K, so that the number of unprogrammed transistors in the programmable charge storage unit is mapped to the corresponding analog quantity a21.

[0086] Second step, input equal reading voltages on the first word line and the second word line connected to each analog computing device in the analog computing array, that is, input reading voltages on the two word lines (the first word line and the second word line) connected to each row of analog computing devices in the analog computing array; the reading voltage is greater than the threshold voltage (turn-on voltage) of the unprogrammed transistors in the programmable charge storage unit and less than the threshold voltage (turn-on voltage) of the programmed transistors in the programmable charge storage unit. At this time, only the unprogrammed transistors in the programmable charge storage unit of each analog device can be turned on.

[0087] In the third step, map the analog quantities corresponding to the number of columns of the analog quantity calculation devices in the array in the target vector to target voltages, and input the corresponding target voltages to the bit lines of each column in the analog quantity calculation array, so that the unprogrammed transistors in the programmable charge storage units of each analog quantity calculation device operate in the linear region, and then sequentially read the currents on the source lines of each row in the array. There is a mapping relationship between the product of the target matrix and the target vector and the vector composed of the currents on the source lines of each row in the array.

[0088] Specifically, each analog quantity in the target vector corresponds to each column in the analog quantity calculation array according to its position, and the analog quantity in each row of the target vector corresponds to the bit line of each column in the array. That is, the analog quantity b1 corresponds to the first column, the analog quantity b2 corresponds to the second column,..., and the analog quantity b5 corresponds to the fifth column. Map each analog quantity to a target voltage, and input the target voltage obtained by mapping each analog quantity into the corresponding column bit line, so that the unprogrammed transistors in the programmable charge storage units of each analog quantity calculation device operate in the linear region. At this time, sequentially read the currents on the source lines of each row in the analog quantity calculation array, and the currents read on the two source lines are combined to obtain a two-element vector. Taking the current c1 output from the source line SL0 of the first row as an example, c1 = a11*b1 + a12*b2 + a13*b3 + a14*b4 + a15*b5. There is a mapping relationship between the product of the target matrix and the target vector and this two-element vector.

[0089] It should be noted that the above takes the calculation of the product of a matrix and a vector using an analog quantity calculation array as an example for illustration, but it is not limited to this. This analog quantity calculation array can also be used to implement the product operation between matrices, specifically including the following two implementation methods:

[0090] The first one, when implementing the product operation between the first matrix and the second matrix, divide each column in the second matrix into a column vector, so that multiple column vectors can be obtained. Then perform the above first step to the third step to calculate the product of the first matrix and each column vector respectively, and obtain multiple column vectors. Then combine these multiple column vectors into a matrix, and this matrix is the product of the first matrix and the second matrix.

[0091] The second one, expand the analog quantity device array to the right, that is, combine multiple analog quantity calculation devices to calculate the product between matrices. Taking the above Figure 10 analog quantity calculation array as an example, if you want to implement the multiplication operation between a 2×5 first matrix and a 5×2 second matrix, then 2 Figure 10Combine with the analog quantity calculation arrays. Each row of the two analog quantity calculation arrays can share two word lines. When performing calculations, execute the above first step and second step to program the first matrix into each analog quantity calculation array respectively. Divide the two columns of the second matrix into two column vectors, and then execute the third step to input these two column vectors into each analog quantity calculation array respectively. Collect the currents output from the source lines of each analog quantity calculation array. The currents output from the source lines of each analog quantity calculation array can form a column vector. Combine the two column vectors obtained from the two analog quantity calculation arrays into a matrix. There is a mapping relationship between the product of the first matrix and the second matrix and the matrix composed of three column vectors.

[0092] In the embodiments of the present application, an analog quantity calculation array including a plurality of analog quantity calculation devices in the second embodiment is provided to implement the product operation of two matrices.

[0093] The fifth embodiment of the present application relates to an analog quantity calculation method applied to the analog quantity calculation device in the first embodiment. This embodiment takes Figure 2 the analog quantity calculation device therein as an example for description. The programmable charge storage unit of the analog quantity calculation device includes a programmable charge storage transistor. Among them, the analog quantity calculation device is applied to a processing chip in an electronic device, and the processing chip can be used to execute the analog quantity calculation method in this embodiment.

[0094] Please refer to Figure 12 , which is the specific flowchart of the analog quantity calculation method in this embodiment.

[0095] Step 101, map the first analog quantity to a target parameter, and program the analog quantity calculation device based on the target parameter.

[0096] Specifically, the target parameter with a mapping relationship to the first analog quantity is the target width, that is, there is a mapping relationship between the first analog quantity and the target width. Map the first analog quantity to the target width W, and program the analog quantity calculation device based on the target width W so that the width of the unprogrammed area of the transistor in the programmable charge storage unit matches the target width.

[0097] Step 102, input equal read voltages on the first word line and the second word line connected to the analog quantity calculation device respectively.

[0098] Specifically, input the same read voltage on the two word lines (the first word line WL and the second word line WL') connected to the transistor. The read voltage is greater than the threshold voltage (turn-on voltage) of the unprogrammed area of the transistor in the programmable charge storage unit and less than the threshold voltage (turn-on voltage) of the programmed area of the transistor. At this time, the unprogrammed area of the transistor can be turned on, and the programmed area of the transistor cannot be turned on.

[0099] Step 103: Input the target voltage obtained by mapping the second analog quantity to the bit line connected to the analog quantity calculation device, and read the current at the source terminal of the analog quantity calculation device; the programmable charge storage unit operates in the linear region, and there is a mapping relationship between the product of the first analog quantity and the second analog quantity and the current in the source line.

[0100] Specifically, map the second analog quantity to the target voltage, and input the target voltage to the bit line BL of the transistor, so that the unprogrammed region of the transistor operates in the linear region; at this time, read the current ID of the source line SL of the transistor, ID = K(VGS - VTH)*VDS*W / L. It can be seen that the current ID is directly proportional to the product of W and VDS, and W and VDS are mapped to the first analog quantity and the second analog quantity respectively. Therefore, the current ID is directly proportional to the product of the first analog quantity and the second analog quantity, so that the product of the first analog quantity and the second analog quantity can be obtained according to the current ID, realizing the multiplication operation of analog quantities; where K represents a coefficient, VGS represents the gate voltage of the transistor, VTH represents the threshold voltage of the unprogrammed region of the transistor, W is the width of the unprogrammed region of the transistor channel, and L is the length of the transistor channel.

[0101] It is not difficult to find that this embodiment is a method embodiment corresponding to the first embodiment, and this embodiment can be implemented in cooperation with the first embodiment. The relevant technical details mentioned in the first embodiment are still valid in this embodiment. To avoid repetition, they will not be elaborated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied in the first embodiment.

[0102] The sixth embodiment of the present application relates to an analog quantity calculation method. The main difference between this embodiment and the fifth embodiment is that: the analog quantity calculation method in this embodiment is applied to the analog quantity calculation device in the second embodiment, and this embodiment takes Figure 5 the analog quantity calculation device in as an example for illustration. The programmable charge storage unit of the analog quantity calculation device includes a plurality of programmable charge storage transistors.

[0103] Please refer to Figure 13 for the specific flowchart of the analog quantity calculation method in this embodiment.

[0104] Step 201: Map the first analog quantity to the target quantity, and program the analog quantity calculation device based on the target quantity, so that the number of unprogrammed programmable charge storage transistors in the programmable charge storage unit is equal to the target quantity.

[0105] Specifically, map the first analog quantity to the target quantity m, and program the programmable charge storage unit of the analog quantity calculation device based on the target quantity m, so that the number of unprogrammed transistors in the programmable charge storage unit is equal to the target quantity.

[0106] Step 202: Apply equal read voltages to the first word line and the second word line connected to the analog computing device. The read voltage is greater than the threshold voltage of the unprogrammed region of the programmable charge storage transistor and less than the threshold voltage of the programmed region of the programmable charge storage transistor.

[0107] Specifically, apply the same read voltage to two word lines (the first word line WL and the second word line WL') connected to the programmable charge storage unit. The read voltage is greater than the threshold voltage (turn-on voltage) of the unprogrammed transistor in the programmable charge storage unit and less than the threshold voltage (turn-on voltage) of the programmed transistor. At this time, only the unprogrammed transistor in the programmable charge storage unit can be turned on.

[0108] Step 203: Apply the target voltage obtained by mapping the second analog quantity to the bit line connected to the analog computing device, and read the current at the source terminal of the analog computing device; wherein, the unprogrammed region of the programmable charge storage transistor in the programmable charge storage unit operates in the linear region.

[0109] Specifically, map the second analog quantity to the target voltage V DS , and apply this target voltage V DS to the bit line BL connected to the programmable charge storage unit, so that the unprogrammed transistor in the programmable charge storage unit operates in the linear region; read the current I D at the source line SL connected to the programmable charge storage unit.

[0110] I D = K(V GS - V TH ) * V DS * m. It can be seen that the current I D is directly proportional to the product of m and V DS . And m and V DS are respectively mapped to the first analog quantity and the second analog quantity. Therefore, the current I D is directly proportional to the product of the first analog quantity and the second analog quantity. Thus, the product of the first analog quantity and the second analog quantity can be obtained according to this current I D , realizing the multiplication operation of analog quantities; wherein, K represents a coefficient, V GS represents the gate voltage of the transistor, and V TH represents the threshold voltage of the unprogrammed transistor.

[0111] Since the second embodiment corresponds to this embodiment, this embodiment can be implemented in cooperation with the second embodiment. The relevant technical details mentioned in the second embodiment are still valid in this embodiment, and the technical effects achievable in the second embodiment can also be achieved in this embodiment. To avoid repetition, they will not be elaborated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the second embodiment.

[0112] The seventh embodiment of this application relates to an analog quantity calculation method, which is applied to the analog quantity calculation array in the third embodiment. The analog quantity calculation array includes a plurality of analog quantity calculation devices, and each programmable charge storage unit in each analog quantity calculation device includes a programmable charge storage transistor. In this embodiment, the analog quantity calculation array in Figure 6 is taken as an example for illustration.

[0113] Please refer to Figure 14 , which is the specific flowchart of the analog quantity calculation method of this embodiment.

[0114] Step 301, for each analog quantity calculation device in the analog quantity calculation array, map the analog quantity corresponding to the analog quantity calculation device in the target matrix to a target parameter, and program the analog quantity calculation device based on the target parameter.

[0115] Specifically, the target parameter having a mapping relationship with the analog quantity in the target matrix is the target width, that is, there is a mapping relationship between the analog quantity in the target matrix and the target width. For each analog quantity calculation device in the analog quantity calculation array, map the analog quantity corresponding to the analog quantity calculation device in the target matrix to the target width, and program the analog quantity calculation device based on the target width, so that the width of the unprogrammed area of the transistor in the programmable charge storage unit of the analog quantity calculation device matches the target width.

[0116] Step 302, input equal read voltages on the first word line and the second word line connected to each analog quantity calculation device.

[0117] Specifically, input equal read voltages on the first word line and the second word line connected to each analog quantity calculation device in the analog quantity calculation array, that is, input equal read voltages on the two word lines (the first word line and the second word line) connected to each row of analog quantity calculation devices in the analog quantity calculation array; the read voltage is greater than the threshold voltage (turn-on voltage) of the unprogrammed area of the transistor in the analog quantity calculation device and less than the threshold voltage (turn-on voltage) of the programmed area of the transistor. At this time, the unprogrammed area of the transistor can be turned on, and the programmed area of the transistor cannot be turned on.

[0118] Step 303: Map the analog quantity corresponding to the number of columns of the analog quantity calculation device in the array in the target vector to a target voltage, input the corresponding target voltage on the bit lines of each column of the analog quantity calculation array, and sequentially read the currents of the source lines of each row of the array; the programmable charge storage units in the analog quantity calculation device operate in the linear region.

[0119] Specifically, map the analog quantity corresponding to the number of columns of the analog quantity calculation device in the array in the target vector to a target voltage, input the corresponding target voltage on the bit lines of each column of the analog quantity calculation array, so that the unprogrammed regions of the transistors of the programmable charge storage units in the analog quantity calculation device in each column operate in the linear region, and sequentially read the currents of the source lines of each row of the array. There is a mapping relationship between the product of the target matrix and the target vector and the vector composed of the currents of the source lines of each row in the array.

[0120] Since the third embodiment corresponds to this embodiment, this embodiment can be implemented in cooperation with the third embodiment. The relevant technical details mentioned in the third embodiment are still valid in this embodiment, and the technical effects achievable in the third embodiment can also be achieved in this embodiment. To avoid repetition, they will not be elaborated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the third embodiment.

[0121] The eighth embodiment of the present application relates to an analog quantity calculation method. The main difference between this embodiment and the seventh embodiment is that: the analog quantity calculation method in this embodiment is applied to the analog quantity calculation array in the fourth embodiment. The analog quantity calculation array includes a plurality of analog quantity calculation devices, and each programmable charge storage unit in each analog quantity calculation device includes a plurality of programmable charge storage transistors. In this embodiment, Figure 10 the analog quantity calculation array is taken as an example for illustration.

[0122] Please refer to Figure 15 , which is the specific flowchart of the analog quantity calculation method of this embodiment.

[0123] Step 401: For each analog quantity calculation device in the analog quantity calculation array, map the analog quantity corresponding to the analog quantity calculation device in the target matrix to a target quantity, and program the analog quantity calculation device based on the target quantity, so that the number of unprogrammed programmable charge storage transistors in the programmable charge storage unit is equal to the target quantity.

[0124] Specifically, the target parameter that has a mapping relationship with the analog quantity in the target matrix is the target quantity, that is, there is a mapping relationship between the analog quantity in the target matrix and the target quantity. For each analog quantity calculation device in the analog quantity calculation array, map the analog quantity corresponding to the analog quantity calculation device in the target matrix to the target quantity, and program the analog quantity calculation device based on the target quantity, so that the number of unprogrammed transistors of the programmable charge storage unit in the analog quantity calculation device is equal to the target quantity.

[0125] Step 402: Input equal read voltages on the first word line and the second word line connected to each analog quantity calculation device. The read voltage is greater than the threshold voltage of the unprogrammed programmable charge storage transistor in the analog quantity calculation device and less than the threshold voltage of the programmed programmable charge storage transistor.

[0126] Specifically, input equal read voltages on the first word line and the second word line connected to each analog quantity calculation device in the analog quantity calculation array, that is, input read voltages on the two word lines (the first word line and the second word line) connected to each row of analog quantity calculation devices in the analog quantity calculation array; the read voltage is greater than the threshold voltage (turn-on voltage) of the unprogrammed transistor in the programmable charge storage unit and less than the threshold voltage (turn-on voltage) of the programmed transistor in the programmable charge storage unit. At this time, only the unprogrammed transistors in the programmable charge storage unit of each analog device can be turned on.

[0127] Step 403: Map the analog quantity corresponding to the column number of the analog quantity calculation device in the array in the target vector to the target voltage, input the corresponding target voltage on the bit lines of each column in the analog quantity calculation array, and sequentially read the currents of the source lines of each row in the array; the unprogrammed programmable charge storage transistors in the analog quantity calculation device operate in the linear region.

[0128] Specifically, map the analog quantity corresponding to the column number of the analog quantity calculation device in the array in the target vector to the target voltage, and input the corresponding target voltage on the bit lines of each column in the analog quantity calculation array, so that the unprogrammed transistors in the programmable charge storage unit of each analog quantity calculation device operate in the linear region, and sequentially read the currents of the source lines of each row in the array. There is a mapping relationship between the product of the target matrix and the target vector and the vector composed of the currents of the source lines of each row in the array.

[0129] Since the fourth embodiment corresponds to this embodiment, this embodiment can be implemented in cooperation with the fourth embodiment. The relevant technical details mentioned in the fourth embodiment are still valid in this embodiment, and the technical effects achievable in the fourth embodiment can also be achieved in this embodiment. To avoid repetition, they are not elaborated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the fourth embodiment.

[0130] The ninth embodiment of the present application relates to a chip, which can be a voice recognition chip, an image processing chip, etc. The chip includes at least the analog computing array in the third or fourth embodiment. The analog computing array in the chip can be used to construct a convolutional neural network to implement functions such as voice recognition and image processing, and can execute the analog computing method in the seventh embodiment.

[0131] The tenth embodiment of the present application relates to an electronic device, including the processing chip of the ninth embodiment.

[0132] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made to them in form and details without departing from the spirit and scope of the present application.

Claims

1. An analog computing device, characterized in that, it includes: A programmable charge storage unit, the programmable charge storage unit includes a control gate, a source terminal and a drain terminal, the control gate includes a first end and a second end, and the first end and the second end are oppositely arranged; A first word line is connected to the first end; a second word line is connected to the second end; a bit line is connected to the drain terminal; And a source line is connected to the source terminal; During the process of analog computing, after the programmable charge storage unit is programmed based on a target parameter, equal read voltages are input to the first word line and the second word line, a target voltage is input to the bit line, the programmable charge storage unit operates in the linear region, the target parameter has a mapping relationship with a first analog quantity, the target voltage has a mapping relationship with a second analog quantity, and the product of the first analog quantity and the second analog quantity has a mapping relationship with the current output by the source line.

2. The analog computing device according to claim 1, characterized in that, The programmable charge storage unit includes a programmable charge storage transistor, the gate of the programmable charge storage transistor forms the control gate of the programmable charge storage unit, and the two ends of the gate of the programmable charge storage transistor respectively form the first end and the second end; The source of the programmable charge storage transistor forms the source terminal of the programmable charge storage unit, and the drain of the programmable charge storage transistor forms the drain terminal of the programmable charge storage unit; The target parameter is a target width; After the programmable charge storage unit is programmed based on the target width, the width of the unprogrammed area of the programmable charge storage transistor matches the target width, the read voltage is greater than the threshold voltage of the unprogrammed area of the programmable charge storage transistor and less than the threshold voltage of the programmed area of the programmable charge storage transistor; when the target voltage is input to the bit line of the programmable charge storage unit, the unprogrammed area of the programmable charge storage transistor operates in the linear region.

3. The analog computing device according to claim 2, characterized in that, The transistor is a charge trapping transistor.

4. The analog computing device according to claim 1, characterized in that, The programmable charge storage unit includes a plurality of programmable charge storage transistors; the gates of the plurality of programmable charge storage transistors are sequentially connected to form the control gate of the programmable charge storage unit, and the target ends of the gates of the two programmable charge storage transistors located at both ends of the control gate respectively form the first end and the second end, and the target end is the end of the gate of the programmable charge storage transistor that is not connected to the adjacent programmable charge storage transistor; The sources of the plurality of programmable charge storage transistors are connected to each other to form the source terminal of the programmable charge storage unit, and the drains of the plurality of programmable charge storage transistors are connected to each other to form the drain terminal of the programmable charge storage unit; The target parameter is a target quantity; After the programmable charge storage unit is programmed based on the target quantity, the number of unprogrammed programmable charge storage transistors in the programmable charge storage unit is equal to the target quantity; the read voltage is greater than the threshold voltage of the unprogrammed programmable charge storage transistors in the programmable charge storage unit and less than the threshold voltage of the programmed programmable charge storage transistors; when the target voltage is input on the bit line of the programmable charge storage unit, the unprogrammed programmable charge storage transistors operate in the linear region.

5. The analog quantity calculation device according to claim 4, wherein, the gates of the plurality of programmable charge storage transistors are sequentially connected to form a common gate for the plurality of programmable charge storage transistors, and the first end and the second end are respectively formed at both ends of the common gate.

6. The analog quantity calculation device according to claim 4, wherein, the transistor is a floating gate transistor.

7. An analog quantity calculation array, wherein, comprising a plurality of analog quantity calculation devices according to any one of claims 1 to 6; the analog quantity calculation devices in the same row share the first word line and the second word line, the analog quantity calculation devices in the same row share a source line, and the analog quantity calculation devices in the same column share a bit line; During the analog quantity calculation process, after each analog quantity calculation device is programmed based on the target parameter, an equal read voltage is input to the first word line and the second word line connected to each analog quantity calculation device, a corresponding target voltage is input to the bit lines of each column connected to each analog quantity calculation device, and the programmable charge storage unit in the analog quantity calculation device operates in the linear region; there is a mapping relationship between the target parameter and the analog quantity corresponding to the analog quantity calculation device in the target matrix, there is a mapping relationship between the target voltage and the analog quantity corresponding to the column number of the analog quantity calculation device in the target vector in the array, and there is a mapping relationship between the product of the target matrix and the target vector and the vector composed of the currents of the source lines of each row in the array.

8. The analog quantity calculation array according to claim 7, wherein, the analog quantity calculation devices in two adjacent rows share one of the first word line or the second word line.

9. The analog quantity calculation array according to claim 7, wherein, the analog quantity calculation device is the analog quantity calculation device according to claim 2 or 3; the target parameter is the target width, after each analog quantity calculation device is programmed based on the target width, the width of the unprogrammed region of the programmable charge storage transistors in the analog quantity calculation device matches the target width, the read voltage is greater than the threshold voltage of the unprogrammed region of the programmable charge storage transistors and less than the threshold voltage of the programmed region of the programmable charge storage transistors; when the target voltage is input on the bit line of the analog quantity calculation device, the unprogrammed region of the programmable charge storage transistors in the analog quantity calculation device operates in the linear region.

10. The analog quantity calculation array according to claim 7, wherein, the analog quantity calculation device is the analog quantity calculation device described in any one of claims 4 to 6; the target parameter is the target quantity; after each analog quantity calculation device is programmed based on the target quantity, the number of unprogrammed transistors in the analog quantity calculation device is equal to the target quantity, the read voltage is greater than the threshold voltage of the unprogrammed programmable charge storage transistor in the analog quantity calculation device and less than the threshold voltage of the programmed programmable charge storage transistor; when the target voltage is input on the bit line of the analog quantity calculation device, the unprogrammed programmable charge storage transistor operates in the linear region.

11. An analog quantity calculation method, wherein, it is applied to the analog quantity calculation device described in any one of claims 1 to 6; the method includes: mapping a first analog quantity to a target parameter and programming the analog quantity calculation device based on the target parameter; inputting equal read voltages on a first word line and a second word line connected to the analog quantity calculation device respectively; inputting a target voltage obtained by mapping a second analog quantity on the bit line connected to the analog quantity calculation device and reading the current at the source end of the analog quantity calculation device; the programmable charge storage unit operates in the linear region, and there is a mapping relationship between the product of the first analog quantity and the second analog quantity and the current of the source line.

12. The analog quantity calculation method according to claim 11, wherein, the analog quantity calculation device is the analog quantity calculation device described in claim 2 or 3; the target parameter is the target width; after the programmable charge storage unit is programmed based on the target width, the width of the unprogrammed region of the programmable charge storage transistor in the programmable charge storage unit matches the target width; the read voltage is greater than the threshold voltage of the unprogrammed region of the programmable charge storage transistor and less than the threshold voltage of the programmed region of the programmable charge storage transistor; when the target voltage is input on the bit line of the programmable charge storage unit, the unprogrammed region of the programmable charge storage transistor in the programmable charge storage unit operates in the linear region.

13. The analog quantity calculation method according to claim 11, wherein, the analog quantity calculation device is the analog quantity calculation device described in any one of claims 4 to 6; the target parameter is the target quantity; after the programmable charge storage unit is programmed based on the target quantity, the number of unprogrammed programmable charge storage transistors in the programmable charge storage unit is equal to the target quantity; the read voltage is greater than the threshold voltage of the unprogrammed programmable charge storage transistor in the programmable charge storage unit and less than the threshold voltage of the programmed programmable charge storage transistor; when the target voltage is input on the bit line of the programmable charge storage unit, the unprogrammed programmable charge storage transistor operates in the linear region.

14. An analog quantity calculation method, wherein, Applied to the analog quantity calculation array according to any one of claims 7 to 10; the method includes: For each of the analog quantity calculation devices in the analog quantity calculation array, map the analog quantity corresponding to the analog quantity calculation device in the target matrix to a target parameter, and program the analog quantity calculation device based on the target parameter; Input equal read voltages on the first word line and the second word line connected to each of the analog quantity calculation devices respectively; Map the analog quantity corresponding to the column number of the analog quantity calculation device in the target vector to a target voltage, input the corresponding target voltage on the bit lines of each column of the analog quantity calculation array, and sequentially read the currents of the source lines of each row of the array; the programmable charge storage unit in the analog quantity calculation device operates in the linear region, and there is a mapping relationship between the product of the target matrix and the target vector and the vector composed of the currents of the source lines of each row in the array.

15. The analog quantity calculation method according to claim 14, characterized in that the analog quantity calculation devices in the analog quantity calculation array are the analog quantity calculation devices according to claim 2 or 3; after each analog quantity calculation device is programmed based on the target width, the width of the unprogrammed area of the programmable charge storage transistor in the analog quantity calculation device matches the target width; the read voltage is greater than the threshold voltage of the unprogrammed area of the programmable charge storage transistor and less than the threshold voltage of the programmed area of the programmable charge storage transistor; when the target voltage is input on the bit line of the analog quantity calculation device, the unprogrammed area of the programmable charge storage transistor in the analog quantity calculation device operates in the linear region.

16. The analog quantity calculation method according to claim 14, characterized in that the analog quantity calculation devices in the analog quantity calculation array are the analog quantity calculation devices according to any one of claims 4 to 6; the target parameter is a target quantity; after each analog quantity calculation device is programmed based on the target quantity, the number of unprogrammed transistors in the analog quantity calculation device is equal to the target quantity; the read voltage is greater than the threshold voltage of the unprogrammed programmable charge storage transistor in the analog quantity calculation device and less than the threshold voltage of the programmed programmable charge storage transistor; when the target voltage is input on the bit line of the analog quantity calculation device, the unprogrammed programmable charge storage transistor operates in the linear region.

17. A chip, characterized in that it includes: the analog quantity calculation array according to any one of claims 7 to 10.

18. An electronic device, characterized in that it includes the chip according to claim 17.

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