Cache control method and control system for a memory

Abstract

This invention proposes a cache control method and control system for memory, comprising: acquiring user operation information and determining a cache space allocation mode based on the operation information; generating control instructions based on the cache space allocation mode and transmitting the control instructions to a receiving end, wherein the control instructions include multiple instruction sets; determining the instruction sets based on the control instructions and marking the setting status of the cache space; invoking the instruction sets based on the setting status of the cache space; and configuring the space management form of the cache space according to the instruction sets so that the space management form matches the space allocation mode. The cache control method and control system for memory proposed in this invention can improve the adaptability of memory operation in various scenarios.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a cache control method and control system for a memory. Background Technology

[0002] Non-volatile memory (NVMemory) is widely used in personal computers and other electronic devices due to its advantages of allowing data to be written, read, and erased multiple times, and the data stored therein not being lost after power failure. However, existing cache space control systems based on NVMemory control the cache space through firmware, making it difficult to adapt to diverse customer usage scenarios. Therefore, improving the adaptability of memory in various scenarios has become an urgent problem to be solved. Summary of the Invention

[0003] In view of the above-mentioned shortcomings, this application proposes a cache control method and control system for memory, which can realize the user's control over the cache space of non-volatile memory through software, thereby improving the adaptability of memory in various scenarios.

[0004] To achieve the above and other objectives, this application proposes a memory control method, including:

[0005] Obtain user operation information and determine the cache space allocation mode based on the operation information;

[0006] Control instructions are generated according to the cache space allocation mode, and the control instructions are transmitted to the receiving end, wherein the control instructions include multiple instruction sets;

[0007] The instruction set is determined according to the control instructions, and the setting status of the cache space is marked;

[0008] Based on the cache space's configuration state, invoke the instruction set; and

[0009] Configure the space management method of the cache space according to the instruction set so that the space management method matches the space allocation mode.

[0010] In one embodiment of this application, the cache space includes multiple allocation modes, wherein when the cache space is in selection mode, the instruction set is invoked.

[0011] In one embodiment of this application, the instruction set includes commands, parameters, and data, wherein the commands are used to modify the cache space of the memory, the parameters are used to indicate the form of the cache space, and the data is used to indicate the current setting state of the cache space.

[0012] In one embodiment of this application, generating control instructions according to the cache space allocation mode and transmitting the control instructions to the receiving end includes:

[0013] The mode unit state is determined based on the cache space allocation pattern.

[0014] The control command is generated by calling the list unit according to the state of the mode unit; and

[0015] The control command is transmitted to the receiving end via the selection unit.

[0016] In one embodiment of this application, configuring the space management method of the cache space according to the instruction set so that the space management method matches the space allocation mode includes:

[0017] Receive instruction packets;

[0018] Parse the instruction packet to obtain commands, parameters, and data; and

[0019] Configure the cache space according to the command, the parameters, and the data.

[0020] In one embodiment of this application, the allocation mode of the cache space further includes an automatic mode.

[0021] In one embodiment of this application, the automatic mode sets the cache space of the memory to a read-write mixed mode.

[0022] Based on the same concept, this application also proposes a control system for the memory, including:

[0023] The control module is used to acquire user operation information and determine the cache space allocation mode based on the operation information.

[0024] The control module generates control instructions based on the cache space allocation mode and transmits the control instructions to the receiving end, wherein the control instructions include multiple instruction sets; and

[0025] A response module is used to determine the instruction set according to the control instructions and mark the setting status of the cache space;

[0026] The response module invokes the instruction set according to the setting status of the cache space;

[0027] The response module configures the space management method of the cache space according to the instruction set so that the space management method matches the space allocation mode.

[0028] In one embodiment of this application, the control module includes:

[0029] The mode unit determines its state based on the cache space allocation mode.

[0030] The list unit, based on the state of the mode unit, calls the list unit to generate the control command; and

[0031] The selection unit transmits the control commands to the receiving end.

[0032] In one embodiment of this application, the response module includes:

[0033] A receiving unit to receive the instruction packet;

[0034] The parsing unit parses the instruction packet to obtain commands, parameters, and corresponding data; and

[0035] The configuration unit configures the cache space based on the acquired command, parameters, and data.

[0036] In summary, this application proposes a cache control method and control system for memory, which can improve the adaptability of memory in various scenarios by enabling users to control the cache space of non-volatile memory. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the cache control method in one embodiment of the present application;

[0039] Figure 2 This is a flowchart illustrating step S2 in one embodiment of the present application;

[0040] Figure 3 This is a flowchart illustrating step S5 in one embodiment of the present application;

[0041] Figure 4 This is a schematic diagram of the cache control system structure in one embodiment of the present application;

[0042] Figure 5 This is a schematic diagram of the control module composition in one embodiment of the present application. Figure 1 ;

[0043] Figure 6 This is a schematic diagram of the control module composition in one embodiment of the present application. Figure 2;

[0044] Figure 7 This is a schematic diagram of the response module composition in one embodiment of the present application;

[0045] Figure 8 This is a schematic diagram of the internal structure of the cache control system in one embodiment of this application;

[0046] Figure 9 This is a schematic diagram of cache space management in one embodiment of the present application. Figure 1 ;

[0047] Figure 10 This is a schematic diagram of cache space management in one embodiment of the present application. Figure 2 ;

[0048] Figure 11 This is a schematic diagram of cache space management in one embodiment of the present application. Figure 3 .

[0049] Label Explanation:

[0050] 100 Cache Control System;

[0051] 10. Control module;

[0052] 101 Mode Unit;

[0053] 102 list cells;

[0054] 103 Select Unit;

[0055] 20. Response module;

[0056] 201 Receiving Unit;

[0057] 202. Analysis Unit;

[0058] 203 Configuration Unit. Detailed Implementation

[0059] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0060] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0061] Non-volatile memory (NVMemory) can include various types of chips as storage media, such as flash chips, which may also include physical flash memory blocks. Each physical flash memory block consists of numerous pages, which are the smallest addressable unit for read and write operations. Read and write operations require a certain amount of cache space. Existing cache space control systems based on NVMemory control cache space through firmware, which is difficult to adapt to increasingly diverse customer usage scenarios.

[0062] Please see Figure 1 This embodiment proposes a memory cache control method, which can improve the memory's adaptability in various scenarios by enabling users to control the cache space of non-volatile memory. In one embodiment of this application, the memory cache control method may include, for example, the following steps:

[0063] S1. Obtain user operation information and determine the cache space allocation mode based on the operation information;

[0064] S2. Generate control instructions according to the cache space allocation mode, and transmit the control instructions to the receiving end, wherein the control instructions include multiple instruction sets;

[0065] S3. Determine the instruction set according to the control instructions, and mark the setting status of the cache space;

[0066] S4. Invoke the instruction set according to the setting status of the cache space;

[0067] S5. Configure the space management method of the cache space according to the instruction set, so that the space management method matches the space allocation mode.

[0068] Please see Figure 1 and Figure 4 , Figure 1This is a schematic flowchart of a cache control method in one embodiment of this application. This application proposes a cache control method for a memory. In one embodiment, step S1 acquires user operation information and determines a cache space allocation mode based on the operation information. In one embodiment, the memory cache control system may include a control module 10 and a response module 20, with the control module 10 connected to the response module 20. In this embodiment, the control module 10 can be located on the host side of the memory to receive user operation information. The control module 10 can generate control instructions according to the cache space allocation mode and transmit the control instructions to the receiving end.

[0069] Please see Figure 1 and Figure 2 , Figure 2 This is a flowchart illustrating step S3 in one embodiment of the present application. In one embodiment of the present application, through step S2, control instructions can be generated according to the cache space allocation mode, and the control instructions can be transmitted to the receiving end, wherein the control instructions include multiple instruction sets.

[0070] In this embodiment, step S2 may include the following steps:

[0071] S21. Determine the mode unit state according to the allocation mode of the cache space;

[0072] S22. Based on the state of the mode unit, call the list unit to generate the control command; and

[0073] S23. The control command is transmitted to the receiving end through the selection unit.

[0074] Please see Figure 1 , Figure 2 as well as Figure 5 , Figure 6 In step S21, the mode unit state can be determined according to the cache space allocation mode. In some embodiments of this application, the memory cache space allocation mode may include, for example, a default mode, a selection mode, and an automatic mode. In step S22, the list unit can be invoked according to the mode unit state to generate the control instructions. In this embodiment, when the memory is in selection mode, different working options in the list unit can be invoked to determine and generate control instructions for cache space memory control. In step S23, the control instructions can be transmitted to the receiving end through the selection unit. The selected control instructions can be sent to the receiving end through the selection unit.

[0075] Please see Figure 1In one embodiment of this application, step S3 can determine the instruction set according to the control instruction and mark the setting status of the cache space. In another embodiment of this application, the cache control system of the memory may include a control module 10 and a response module 20, with the control module 10 connected to the response module 20. In this embodiment, the response module 20 can be located at the receiving end of the memory to receive user operation information. After the control module 10 transmits the control instruction, the setting status of the cache space is marked according to the control instruction.

[0076] Please see Figure 1 In one embodiment of this application, step S4 can be used to invoke the instruction set according to the setting state of the cache space. In some embodiments of this application, the instruction set may include commands, parameters, and data, wherein the commands are used to modify the cache space of the memory, the parameters are used to indicate the form of the cache space, and the data is used to indicate the current setting state of the cache space.

[0077] Please see Figure 1 and Figure 3 In one embodiment of this application, step S5 can be used to configure the space management form of the cache space according to the instruction set, so that the space management form matches the space allocation mode.

[0078] Please see Figure 3 , Figure 3 This is a flowchart illustrating step S5 in one embodiment of the present application. In this embodiment, step S5 may further include step S51 receiving an instruction packet. Step S52 parsing the instruction packet to obtain commands, parameters, and data. Step S53 configuring the cache space based on the commands, parameters, and data. In some embodiments of the present application, the instruction packet may be transmitted via bus protocols such as NVMe, EMMC, or SATA.

[0079] Please see Figure 5 , Figure 6 as well as Figure 8 , Figure 8This is a schematic diagram of the internal structure of the cache control system in one embodiment of this application. The response module 20 can be used to determine the instruction set according to control instructions and mark the setting state of the cache space. The response module 20 can invoke the instruction set according to the setting state of the cache space. The response module 20 configures the space management form of the cache space according to the invoked instruction set, so that the configured space management form matches the space allocation mode in the control module 10. In one embodiment of this application, the control module 10 may include a mode unit 101, a list unit 102, and a selection unit 103. In some embodiments of this application, the mode unit 101 may include multiple memory allocation modes. In some embodiments of this application, the mode unit 101 may include, for example, a default mode and a selection mode. When the mode unit 101 is in the default mode, its configuration can adopt the initial mode and can be adjusted according to different situations. When the mode unit 101 is in the default mode, the cache space of the non-volatile memory can be set to a fixed allocation method, at which time the proportion of read and write operations in the cache space remains unchanged. In one embodiment of this application, the read space range of the default mode can be, for example, 64-128K. In this embodiment, the read space of the default mode can be, for example, 64K. In one embodiment of this application, the write space range of the default mode can be, for example, 160K-224K. In this embodiment, the write space of the default mode can be, for example, 192K.

[0080] Please see Figure 8 In one embodiment of this application, when the mode unit 101 is in selection mode, the user is allowed to selectively configure according to their needs. When the mode unit 101 is in selection mode, the size of the space occupied by read and write operations in the cache space can be set according to the user's needs. When the mode unit 101 is in selection mode, the optional instructions in the selection list 102 corresponding to the selection mode can be a preset set of configurable schemes based on the memory model, or they can be adjusted and modified independently according to the user's needs. In some embodiments of this application, the optional list includes multiple instruction modes, for example:

[0081] mode0: R(32K)W(224K), (Read 32K, Write 224K);

[0082] mode1: R(64K)W(192K), (Read 64K, Write 192K);

[0083] mode2: R(96K)W(160K), (Read 96K, Write 160K);

[0084] mode3: R(128K)W(128K), (Read 128K, Write 128K);

[0085] mode4: R(160K)W(96K), (Read 160K, Write 96K);

[0086] mode5: R(192K)W(64K), (Read 192K, Write 64K);

[0087] mode6: R(224K)W(32K), (Read 224K, Write 32K).

[0088] As mode 0 progresses to mode 6, the read cache space gradually increases, while the write cache space gradually decreases. Users can configure corresponding options based on the subsequent read / write ratio. In one embodiment of this application, for example, mode 2: R(96K)W(160K) instructions can be selected. In another embodiment of this application, mode unit 101 can also be in automatic mode. In automatic mode, the cache space of the non-volatile memory can be set to a mixed read / write configuration, automatically adjusting the size of the space occupied by read and write operations according to actual conditions.

[0089] Please see Figure 9 , Figure 9 This is a schematic diagram of cache space management in one embodiment of the present application. Figure 1 During the configuration of the memory cache space, a Bitmap can be used to manage whether the corresponding space is occupied. In this embodiment, each bit indicates the status of 4K space. A 1 indicates that the space is occupied, and a 0 indicates that the space is not occupied. The cut_off_rule can also be used to record the split point between read and write spaces. When configuring the cache space, the write space and read space are separated by the cut_off_rule. When the requested space is insufficient, the requested space is at the split line, and the space to be expanded is idle, the storage space is expanded.

[0090] Please see Figure 10 and Figure 11 , Figure 10 This is a schematic diagram of cache space management in one embodiment of the present application. Figure 2 , Figure 11 This is a schematic diagram of cache space management in one embodiment of the present application. Figure 3In this embodiment, the write buffer space can be expanded. When a command sends 16K of data, four buffer segments need to be requested (starting from idx 15), but there is only 4K of free space in the write buffer (i.e., bit

[15] is 0). If the requested space is exactly at the boundary of the dividing line, the write buffer space can be expanded to the right. If bit[16~17] = 0 is found, that is, it is in a free state, the read buffer space size can meet the minimum requirement, and the write buffer space size can be expanded smoothly.

[0091] Please see Figure 4 , Figure 4 This is a schematic diagram of the cache control system structure in one embodiment of this application. This application also proposes a cache control system for a memory. In one embodiment, the cache control system may include a control module 10 and a response module 20, with the control module 10 connected to the response module 20. The control module 10 can acquire user operation information and determine the cache space allocation mode based on the user operation information. The control module 10 can generate control instructions according to the cache space allocation mode and transmit the control instructions to the receiving end. The control instructions may include multiple instruction sets. The response module 20 can determine the instruction sets according to the control instructions and mark the cache space setting status. The response module 20 can invoke the instruction sets according to the cache space setting status. The response module 20 configures the cache space management form according to the invoked instruction sets so that the configured space management form matches the space allocation mode in the control module 10.

[0092] Please see Figure 5 and Figure 6 , Figure 5 This is a schematic diagram of the control module composition in one embodiment of the present application. Figure 1 , Figure 6 This is a schematic diagram of the control module composition in one embodiment of the present application. Figure 2In one embodiment of this application, the control module 10 may include a mode unit 101, a list unit 102, and a selection unit 103. In some embodiments of this application, the mode unit 101 may include multiple memory allocation modes. In some embodiments of this application, the mode unit 101 may include, for example, a default mode and a selection mode. In this embodiment, the selection of the default mode and the selection mode in the mode unit 101 can be achieved, for example, by virtual buttons. In this embodiment, the selection unit 103 may be, for example, a virtual button. In this embodiment, the list unit 102 may include multiple instructions, and the user can select from multiple instructions. The optional instructions in the list unit 102 may be a set of preset configurable schemes based on the memory model, or they may be adjusted and modified according to the user's needs.

[0093] Please see Figure 5 and Figure 6 In one embodiment of this application, when the mode unit 101 is in default mode, the cache space of the non-volatile memory can be set to a fixed allocation method, and the proportion of read and write operations in the cache space remains unchanged. When the mode unit 101 is in selection mode, the size of the space occupied by read and write operations in the cache space can be set according to the user's needs. When the mode unit 101 is in selection mode, the optional instructions in the selection list 102 corresponding to the selection mode can be a set of preset configurable schemes based on the memory model, or they can be adjusted and modified according to the user's needs. To avoid the user's configuration of the cache space not conforming to the current usage mode, which would not only fail to accelerate performance but may also seriously affect it, the mode unit 101 may also include, for example, an automatic mode. When the mode unit 101 is in automatic mode, the cache space of the non-volatile memory can be set to a mixed read and write configuration, and the size of the space occupied by read and write operations can be automatically adjusted according to the actual situation.

[0094] Please see Figure 7 , Figure 7 This is a schematic diagram illustrating the composition of a response module in one embodiment of the present application. In one embodiment of the present application, the response module 20 may include a receiving unit 201, a parsing unit 202, and a configuration unit 203. In this embodiment, the receiving unit 201 can be used to receive instruction packets generated by the control module 10. The parsing unit 202 can be used to parse the instruction packets to obtain commands, parameters, and corresponding data. The configuration unit 203 can configure a cache space according to the obtained commands, parameters, and data.

[0095] In summary, this application proposes a cache control method and control system for memory, which can improve the adaptability of memory in various scenarios by enabling users to control the cache space of non-volatile memory.

[0096] Throughout this specification, the terms "one embodiment," "an embodiment," or "a specific embodiment" refer to a particular feature, structure, or characteristic described in connection with an embodiment that is included in at least one embodiment of the invention, but not necessarily in all embodiments. Therefore, the various representations of the phrases "in one embodiment," "in an embodiment," or "in a specific embodiment" in different places throughout the specification do not necessarily refer to the same embodiment. Furthermore, a particular feature, structure, or characteristic of any specific embodiment of the invention may be combined with one or more other embodiments in any suitable manner. It should be understood that other variations and modifications of the embodiments of the invention described and illustrated herein may be based on the teachings herein and will be considered part of the spirit and scope of the invention.

[0097] It should also be understood that one or more of the elements shown in the figures may be implemented in a more separate or more integrated manner, or may even be removed because they are inoperable in certain circumstances or provided because they may be useful for a particular application.

[0098] Furthermore, unless otherwise expressly stated, any arrows in the accompanying drawings should be considered illustrative only and not limiting. Additionally, unless otherwise stated, the term "or" as used herein is generally intended to mean "and / or". Where a term is anticipated to provide a separation or combination capability that is unclear, a combination of components or steps will also be considered as indicated.

[0099] As used herein and throughout the claims below, unless otherwise specified, “a”, “an” and “the” include the plural references. Similarly, as used herein and throughout the claims below, unless otherwise specified, “in” means both “in” and “on”.

[0100] The above description of the embodiments shown in this invention (including the content set forth in the abstract of the specification) is not intended to be an exhaustive enumeration or to limit the invention to the precise forms disclosed herein. Although specific embodiments and examples of the invention have been described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the invention, as will be recognized and understood by those skilled in the art. As indicated, these modifications can be made to the invention in accordance with the above description of the embodiments described herein, and such modifications will be within the spirit and scope of the invention.

[0101] This document has generally described the systems and methods in detail to aid in understanding the invention. Furthermore, various specific details have been set forth to provide a general understanding of embodiments of the invention. However, those skilled in the art will recognize that embodiments of the invention can be practiced without one or more specific details, or using other means, systems, accessories, methods, components, materials, parts, etc. In other instances, well-known structures, materials, and / or operations have not been specifically shown or described in detail to avoid obscuring aspects of embodiments of the invention.

[0102] Therefore, although the invention has been described herein with reference to specific embodiments thereof, freedom of modification, various changes and substitutions are intended within the scope of the foregoing disclosure, and it should be understood that in some cases, certain features of the invention may be adopted without departing from the scope and spirit of the invention and without corresponding use of other features. Thus, many modifications can be made to adapt a particular environment or material to the essential scope and spirit of the invention. The invention is not intended to be limited to the specific terminology used in the following claims and / or the specific embodiments disclosed as the best mode contemplated for carrying out the invention, but the invention will include any and all embodiments and equivalents falling within the scope of the appended claims. Therefore, the scope of the invention will be defined only by the appended claims.

Claims

1. A method for controlling a memory, characterized in that, include: The system obtains user operation information and determines the cache space allocation mode based on the operation information. The cache space includes multiple allocation modes. When the cache space is in selection mode, the system sets the size of the space occupied by read and write operations in the cache space according to the user's needs and calls the instruction set. The allocation mode of the cache space also includes an automatic mode. The automatic mode sets the cache space of the memory to a read-write mixed form and automatically adjusts the size of the space occupied by read and write operations according to the actual situation. Control instructions are generated according to the cache space allocation mode, and the control instructions are transmitted to the receiving end, wherein the control instructions include multiple instruction sets; The instruction set is determined according to the control instructions, and the setting status of the cache space is marked; Invoke the instruction set according to the setting status of the cache space; as well as Configure the space management method of the cache space according to the instruction set, so that the space management method matches the space allocation mode; The instruction set includes commands, parameters, and data, wherein the commands are used to modify the cache space of the memory, the parameters are used to indicate the form of the cache space, and the data are used to indicate the current setting state of the cache space. Specifically, when the requested space is insufficient, the requested space is at the dividing line, and the space to be expanded is in an idle state, the cache space is expanded.

2. The memory control method according to claim 1, characterized in that: The step of generating control instructions according to the cache space allocation mode and transmitting the control instructions to the receiving end includes: The mode unit state is determined based on the cache space allocation pattern. The control command is generated by calling the list unit according to the state of the mode unit; and The control command is transmitted to the receiving end via the selection unit.

3. The memory control method according to claim 1, characterized in that: The step of configuring the space management method of the cache space according to the instruction set, so that the space management method matches the space allocation mode, includes: Receive instruction packets; Parse the instruction packet to obtain commands, parameters, and data; and Configure the cache space according to the command, the parameters, and the data.

4. A control system for a memory, characterized in that, include: The control module is used to acquire user operation information and determine the cache space allocation mode based on the operation information. The cache space includes multiple allocation modes. When the cache space is in selection mode, the size of the space occupied by read and write operations in the cache space is set according to the user's needs, and the instruction set is called. The allocation mode of the cache space also includes an automatic mode. The automatic mode sets the cache space of the memory to a read-write mixed form and automatically adjusts the size of the space occupied by read and write operations according to the actual situation. The control module generates control instructions based on the cache space allocation mode and transmits the control instructions to the receiving end, wherein the control instructions include multiple instruction sets; and A response module is used to determine the instruction set according to the control instructions and mark the setting status of the cache space; The response module invokes the instruction set according to the setting status of the cache space; The response module configures the space management method of the cache space according to the instruction set, so that the space management method matches the space allocation mode; The instruction set includes commands, parameters, and data, wherein the commands are used to modify the cache space of the memory, the parameters are used to indicate the form of the cache space, and the data are used to indicate the current setting state of the cache space. Specifically, when the requested space is insufficient, the requested space is at the dividing line, and the space to be expanded is in an idle state, the cache space is expanded.

5. The control system for the memory according to claim 4, characterized in that: The control module includes: The mode unit determines its state based on the cache space allocation mode. The list unit, based on the state of the mode unit, calls the list unit to generate the control command; and The selection unit transmits the control commands to the receiving end.

6. The control system for the memory according to claim 4, characterized in that: The response module includes: A receiving unit to receive the instruction packet; The parsing unit parses the instruction packet to obtain commands, parameters, and corresponding data; and The configuration unit configures the cache space based on the acquired command, parameters, and data.

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