New memory architecture for serial EEPROM

Abstract

Embodiments of this disclosure relate to novel memory architectures for serial EEPROMs. In one embodiment, an electrically erasable programmable readable memory includes: a plurality of memory cells organized in a memory plane arranged in rows and columns in a matrix manner, wherein each memory cell includes a state transistor having a source region, a drain region, an injection window located on the drain side, a control gate and a floating gate, and an isolation transistor having a source region, a drain region and a gate; and an isolation barrier including a buried layer and at least one wall extending from the buried layer to a surface of a substrate, wherein the at least one wall is perpendicular to the buried layer, and wherein the isolation barrier forms an inner substrate surrounding at least one of the memory cells and isolating it from the remainder of the substrate.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of French patent application No. 2009060, filed on 7 September 2020, which is incorporated herein by reference. Technical Field

[0003] This invention relates to non-volatile memory of the electrically erasable programmable read-only memory (EEPROM) type. Background Technology

[0004] EEPROM (also known as E2PROM or E) 2 EEPROM (EEPROM) is a read-only memory that can be erased and reprogrammed multiple times (from 100,000 to 1,000,000 times) and has an unlimited number of reads. EEPROM typically consists of multiple memory cells.

[0005] Figure 1 A memory cell, such as those described in the prior art, is illustrated schematically.

[0006] More specifically, cell CELL represents an example of the structure of such a memory cell derived from French Patent No. FR3071355 of an EEPROM. This memory cell includes a state transistor TE, an isolation transistor TI, and connections to the source line SL and the bit line BL (also referred to by the terms "binary line" or "bit line").

[0007] A state transistor TE includes a source TEs, a drain TEd, a control gate CG, and a floating gate FG. The state transistor TE enables the storage of charge representing logic data in its floating gate FG in a non-volatile manner. Charge injection and extraction occur via an injection window INJT located on the source TEs side of the state transistor TE, thereby realizing the Fowler-Nordheim effect.

[0008] An isolation transistor TI consists of a source TIs, a drain TId, and a control gate CGI. The isolation transistor TI enables the state transistor TE to be coupled to the source line SL via a conduction terminal, thus allowing the state transistor TE to be isolated or not isolated.

[0009] Typically, in a known manner, EEPROM-type memories are capable of storing memory words belonging to a memory plane comprising rows and columns. A memory word typically comprises eight memory cells (CELL') located in the same row. A row (also called a "page") then comprises a series of memory words organized in a first direction X, and a column (COL) comprises a series of memory words organized in a second direction Y, perpendicular to the first direction X. The intersection of rows and columns forms a memory word (also called a "byte").

[0010] Within the scope of this type of memory cell application, writing typically involves an erase step followed by a programming step. The voltage (+ / -15V) applied to the state transistor TE during writing is high. This results in high power consumption and size on the chip substrate, especially considering the need to house the charge pump to make such a voltage possible. Summary of the Invention

[0011] The embodiment overcomes the above-mentioned disadvantages by providing an EEPROM and a method for writing to the memory, making it possible to limit the voltage required for writing.

[0012] The embodiment proposes an electrically erasable programmable read-only memory (EEPROM) type memory formed in and on a semiconductor substrate, and comprising a plurality of memory cells organized in a memory plane arranged in rows and columns in a matrix manner. Each memory cell includes a state transistor and an isolation transistor. The state transistor includes a source region, a drain region, an injection window (INJT) on the drain (Ted) side, a control gate, and a floating gate. The isolation transistor has a source region, a drain region, and a gate (CGI), and the drain region of the isolation transistor and the source region of the state transistor are common. The memory is characterized in that it further includes an isolation barrier comprising a buried layer and at least one wall extending from the buried layer to the surface of the substrate and perpendicular to the buried layer. The isolation barrier forms an inner substrate that surrounds at least one of the memory cells and isolates it from the rest of the substrate.

[0013] The memory can be implemented in the following ways.

[0014] In one embodiment, the control gate of the state transistor is connected to the control gate line of the memory. The source region of the isolation transistor is connected to the source line of the memory. The gate of the isolation transistor is connected to the word line of the memory. The drain region of the state transistor is connected to the bit line.

[0015] In one embodiment, the isolation barrier is configured to isolate all memory cells of the memory plane together.

[0016] In one embodiment, the memory includes a means for erasing a memory word, the means being configured to float bit lines, apply a first positive voltage to a control gate line associated with a memory cell of the memory word to be erased, ground a control gate line of a memory cell not associated with the memory word to be erased, ground a word line, ground a source line, and ground an internal substrate.

[0017] In one embodiment, the difference between the first voltage and ground enables the Fowler-Nordheim effect by injecting electronic charge into the floating gate of the state transistor.

[0018] In one embodiment, the isolation barrier is configured to isolate all memory cells belonging to a column of the memory plane together.

[0019] In one embodiment, the memory includes means for erasing memory words, the means being configured to float bit lines, apply a second positive voltage to a control gate line associated with a memory cell of the memory word to be erased, ground a control gate line of a memory cell not associated with the memory word to be erased, ground a word line, apply a first negative voltage to a source line, and apply a first negative voltage to an internal substrate.

[0020] In one embodiment, the voltage difference between the second positive voltage and the first negative voltage achieves the Fowler-Nordheim effect by injecting electron charge into the floating gate of the state transistor.

[0021] In one embodiment, the memory includes a programming device configured to apply a positive voltage to the bit lines of the memory cells to be programmed in a memory word to be programmed, apply a positive voltage to the bit lines of memory cells not to be programmed, wherein the positive voltage applied to the bit lines of the memory cells not to be programmed is less than the positive voltage applied to the bit lines of the memory cells to be programmed, apply a negative voltage to the control gate lines of the memory cells associated with the memory word to be programmed, apply a positive voltage to the control gate lines of memory cells located in the same column as the memory word to be programmed, ground the control gate lines of memory cells not associated with the memory word to be programmed, ground the word lines, apply a positive voltage to the source lines, and ground the internal substrate.

[0022] In one embodiment, a positive voltage of approximately 9.5V is applied to the bit lines of the memory cells to be programmed in the memory word to be programmed, a positive voltage of approximately 3.3V is applied to the bit lines of the memory cells not to be programmed, a negative voltage of approximately -3.3V is applied to the control gate lines of the memory cells associated with the memory word to be programmed, a positive voltage of approximately 6V is applied to the control gate lines of the memory cells located in the same column as the memory word to be programmed, and a positive voltage of approximately 3.3V is applied to the source lines.

[0023] In one embodiment, the memory includes a read device configured to apply a positive voltage to the bit lines of the memory cells of the memory word to be read, apply a positive voltage to the control gate lines of the memory cells of the memory word to be read, ground the control gate lines of memory cells not associated with the memory word to be read, apply a positive voltage to the word lines of the memory cells of the row associated with the memory word to be read, ground the word lines of memory cells not located in the row associated with the memory word to be read, ground the source lines, and ground the internal substrate.

[0024] In one embodiment, the positive voltage applied to the bit line of the memory cell of the memory word to be read is 1V, the positive voltage applied to the control gate line of the memory cell of the memory word to be read is 0.5V, and the positive voltage applied to the word line of the memory cell of the row associated with the memory word to be read is VDD.

[0025] Another aspect of the present invention provides a method for writing at least one memory cell of a memory word into a memory. The method includes a step of erasing the memory word by applying a positive voltage to a control gate line associated with the memory cell of the memory word to be written, connecting the control gate line of a memory cell not associated with the memory word to ground, connecting a word line to ground, applying a negative voltage to a source line, and applying a second negative voltage to an internal substrate. The method also includes a step of programming the memory word by applying a positive voltage to the bit line of the memory cell to be written, applying a positive voltage to the bit line of a memory cell not to be written, applying a negative voltage to the control gate line of the memory cell associated with the memory word to be written, applying a positive voltage to the control gate line of a memory cell located in the same column as the memory word to be written, connecting the control gate line of a memory cell not associated with the memory word to ground, connecting a word line to ground, applying a positive voltage to a source line, and connecting an internal substrate to ground.

[0026] This method can be implemented in the following way.

[0027] In one embodiment, a positive voltage of 11V is applied to the control gate line associated with the memory cell of the memory word to be written, a negative voltage of -3.3V is applied to the source line, a negative voltage of -3.3V is applied to the internal substrate, a positive voltage of 9.5V is applied to the bit line of the memory cell to be written, a positive voltage of 3.3V is applied to the bit line of the memory cell not to be written, a negative voltage of -3.3V is applied to the control gate line of the memory cell associated with the memory word to be written, a positive voltage of 6V is applied to the control gate line of the memory cell located in the same column as the memory word to be written, and a positive voltage of 3.3V is applied to the source line. Attached Figure Description

[0028] Other features, objects, and advantages of the invention will become clear from the following description, which is purely illustrative and non-limiting, and should be read in conjunction with the accompanying drawings, wherein:

[0029] Figure 1 A prior art memory cell is schematically illustrated;

[0030] Figure 2 A memory cell according to an embodiment is schematically shown;

[0031] Figure 3 It shows according to Figure 2 A cross-sectional view of the memory cell;

[0032] Figure 4 A memory according to another embodiment is schematically shown;

[0033] Figure 5 This is a block diagram of a process for writing a memory word according to an embodiment;

[0034] Figure 6 A memory according to another embodiment is illustrated schematically; and

[0035] Figure 7 A memory according to yet another embodiment is illustrated schematically. Detailed Implementation

[0036] Unless otherwise stated, when referring to two elements connected together, it means that there is no intermediate element other than a conductor directly connecting them, and when referring to two elements connected or coupled together, it means that the two elements can be connected, linked or coupled through one or more other elements.

[0037] Figure 2 A memory cell according to an embodiment is illustrated schematically.

[0038] The memory cell (CELL) includes a status transistor (TE), an isolation transistor (TI), and connections to the source line (SL) and the bit line (BL).

[0039] A state transistor TE includes a source TEs, a drain TEd, a control gate CG, and a floating gate FG. This state transistor TE enables the storage of charge representing logic data in its floating gate in a non-volatile manner. An isolation transistor TI includes a source TIs, a drain TId, and a control gate CGI. The isolation transistor TI enables coupling of the state transistor TE to the source line SL via a conduction terminal.

[0040] and Figure 1 Unlike the cell CELL' shown, charge injection and extraction occur through the injection window (INJT) located on the drain TEd side of the state transistor TE.

[0041] Figure 3 It shows according to Figure 2 A cross-sectional view of a memory cell.

[0042] The memory cell (CELL) includes an isolation transistor (TI) and a state transistor (TE) connected in series, formed in and on a semiconductor substrate (SUB) having a first conductivity type (e.g., P-type).

[0043] The state transistor TE includes source regions TEs and drain regions Ted implanted on the surface of the substrate SUB. The source regions TEs and drain regions Ted are semiconductorized with a second conductivity type opposite to a first conductivity type. If the first conductivity type is P-type, the second conductivity type will be N-type, and vice versa. The state transistor TE includes a control gate CG that extends beyond the floating gate FG.

[0044] An isolation transistor TI comprises source regions TIs, drain regions TId, and a control gate CGI. These source regions TIs and drain regions TId are also implanted onto the surface of the substrate SUB, semiconductorized, and have the same type of conductivity as the source regions TEs and drain regions TEd of a state transistor TE. The control gate CGI may be located on a dielectric layer OXHV (200 Å) that separates it from the substrate.

[0045] The isolation transistor TI is coupled to the source line SL on its source region TIs, and the state transistor TE is coupled to the bit line BL (not shown) on its drain region TEd. The source TEs of the state transistor and the drain TId of the isolation transistor are formed by the injection region shared by the two transistors TI and TE.

[0046] In the state transistor TE, the control gate CG and the floating gate FG are electrically isolated from each other by the control gate dielectric layer ONO. The ONO layer (140 Å) comprises alternating layers of, for example, silicon nitride and silicon oxide. The floating gate FG may be located on a dielectric layer OXTN (76 Å) that separates it from the substrate.

[0047] A memory cell (CELL) is formed in a substrate region completely isolated from the rest of the substrate by a combination of the following elements forming a semiconductor isolation barrier (BI), which includes:

[0048] Burial layer CEnt, and

[0049] The wall Par extends from the buried layer to the surface of the substrate, perpendicular to the buried layer and following the perimeter of the buried layer CEnt.

[0050] The dimensions (thickness, width, etc.) of these components depend on the technology used.

[0051] These elements can be generated in N-doped substrates and can be isolated (often referred to as "NISO regions").

[0052] The combination of the buried layer CEnt and the wall Par makes it possible to completely isolate the substrate surrounding the cell (referred to as the inner substrate SUBint) from the rest of the substrate SUB. This allows the potential of the inner substrate SUBint to be placed at a voltage different from that of the substrate SUB.

[0053] This isolation can be achieved in several different ways:

[0054] - By using all memory cells of the memory (such as Figure 4 As shown, WD1 to WD8 are isolated together;

[0055] - By using the cells of several columns (such as Figure 6 As shown, WD1 to WD4 and W5 to W8 are isolated together; or

[0056] - By isolating and separating the cells of each column (e.g.) Figure 7 As shown, WD1 and WD2, WD3 and WD4, WD5 and WD6, WD7 and WD8 are isolated together.

[0057] These solutions each have their own advantages and disadvantages.

[0058] The isolation of columns makes it possible to reduce EEPROM consumption during writing (by applying voltage uniquely to the memory word to be written), thereby compromising the surface area of ​​the memory plane PM.

[0059] Figure 4 The memory MEM1 according to the first embodiment is schematically shown.

[0060] For simplicity, memory MEM1 comprises memory cells distributed only in two rows RWi (i being indices from 0 to 1, here RW0, RW1) and four columns COLj (j being indices from 0 to 1, here COL0, COL1, COL2, COL3), totaling 64 memory cells, forming eight words WD1 to WD8. Each row RWi then comprises 32 memory cells distributed across four memory words, thus each memory word comprises eight memory cells. Therefore, Figure 4 The memory represented in the figure consists of eight memory words (WD1 to WD8).

[0061] exist Figure 4 In the embodiments, the memory plane PM has:

[0062] -32 bit lines BLk (k is an index from 0 to K, here BL0~BL31) are connected to the drain region TEd of all state transistors TE, respectively.

[0063] - Eight control gate lines CGLij (CGL00, CGL01, CGL02, CGL03, CGL10, CGL11, CGL12, CGL13) are connected to the control gate CG of the state transistor TE of one of the eight memory words via control gate switches dedicated to each memory word WD1 to WD8. Figure 4 Not shown in the image.

[0064] - Two word lines WLi (WL0 and WL1), each connected to the gate CGI of the isolation transistor TI for each row RWi (RW0, RW1), and

[0065] - The source line SL is connected to the source regions TIs of all isolated transistors TI.

[0066] Figure 4 The memory shown further includes a control device DCOM, which includes a memory erase device DEFF, a programming device DPROG, and a read device DLEC.

[0067] The eraser device DEFF is designed to implement a method for erasing memory cells (CELL) by applying voltages to the control gate line CGLij, bit line BLk, word line WLi, and source line SL.

[0068] refer to Figure 4 The memory words WD1 to WD8 are represented in the diagram. If memory word WD1 is to be erased while memory words WD2 to WD8 are to be retained (i.e., not erased), the erase device DEFF is configured as follows:

[0069] - Make all bit lines BLk (BL0 to BL31) float.

[0070] - Apply a high positive voltage, such as 10.5V, to the control gate line CGLij associated with the memory word to erase (CGL00 in this case).

[0071] - Ground (GND) the control gate lines CGLij (CGL01, CGL02, CGL03, CGL10, CGL11, CGL12, CGL13) associated with the memory word to reserve (WD2 to WD8).

[0072] - Ground all word lines WLi (WL0, WL1) to GND.

[0073] - Apply a negative voltage, for example -3.3V, to the source line SL, and

[0074] - Place the internal substrate SUBint at a negative voltage, such as -3.3V.

[0075] The difference between the high positive and negative voltages allows electrons to be injected into the floating gate via the Fowler-Nordheim effect. These voltages can then be varied depending on the memory's architecture and the manufacturing techniques used.

[0076] Table 1 below summarizes the voltages applied for erasing memory word WD1 and retaining memory words WD2 through WD8.

[0077] [Table 1]

[0078] Row selection Column selection Mot BL CGL WL SL SUBint yes yes WD1 floating 10.5V GND -3.3V -3.3V yes no WD3, WD5, WD7 floating GND GND -3.3V -3.3V no yes WD2 floating GND GND -3.3V -3.3V no no WD4, WD6, WD8 floating GND GND -3.3V -3.3V

[0079] Table 1: Erasure voltage of memory plane ( Figure 4 )

[0080] refer to Figure 4 The memory words WD1 to WD8 are represented in the diagram. If it is desired to program at least some memory cells of at least one memory word WD1, the programming device DPROG is configured to, during programming:

[0081] - Apply a high positive voltage, such as 9.5V, to the bit line BLk (e.g., BL1, BL3, BL5, BL7) coupled to the cell to be programmed.

[0082] - Apply a low positive voltage, such as 3.3V, to the other bit lines BLk (e.g., BL0, BL2, BL4, BL6, and BL8 to BL31) coupled to the unprogrammed cells.

[0083] - Apply a negative voltage, such as -3.3V, to the control gate line (CGL00) associated with the memory word (WD1) to be programmed.

[0084] - Apply a positive voltage, such as 6V, to the control gate line (CGL10) associated with the memory word (WD2) located in the same column (COL0) as the memory word (WD1) to be programmed.

[0085] - Ground (GND) the control gate lines (CGL01, CGL02, CGL03, CGL11, CGL12, CGL13) associated with other memory words (WD3 to WD8).

[0086] - Ground all word lines (WL0, WL1) to GND.

[0087] - Apply a positive voltage (e.g., 3.3V) to the source line (SL), and

[0088] - Ground the internal substrate SUBint (GND).

[0089] Table 2 below summarizes the voltage applied to program memory word WD1 without affecting memory words WD2 to WD8.

[0090] [Table 2]

[0091] Row selection Column selection Mot BL CGL WL SL SUBint yes yes WD1 9.5V / 3.3V -3.3V GND 3.3V GND yes no WD3, WD5, WD7 3.3V GND GND 3.3V GND no yes WD2 9.5V / 3.3V 6V GND 3.3V GND no no WD4, WD6, WD8 3.3V GND GND 3.3V GND

[0092] Table 2: Programming voltage of memory plane ( Figure 4 )

[0093] As a reminder, for a memory word to be programmed (WD1), the bit line BLk of the memory cell to be programmed is set to 9.5V, while the bit line BL of the memory cell not to be programmed is set to 3.3V. The bit line BLk of a given column is common to all words in that column, and these voltages are also applied to the unprogrammed memory cells of a word (WD2) in the same column (COL0). However, the voltage applied to the control gate line (CGL10) of the unprogrammed word prevents any rewriting of these memory cells.

[0094] refer to Figure 4 For memory words WD1 to WD8, as represented in the table, in order to read at least some memory cells (e.g., a single cell, multiple cells, or all cells of the word), the read device DLEC is configured to:

[0095] - Apply a weak positive voltage, such as 1V, to the bit line BLk belonging to column COLj containing the memory cell to be read.

[0096] - Float the bit line BLk that belongs to the column containing the memory cell that does not need to be read.

[0097] - Apply, for example, a positive voltage of 0.5V to the control gate line CGLij associated with the memory word to be read. Alternatively, the control gate line CGLij associated with the memory word to be read can be grounded. Applying a positive voltage (0.5V) can speed up the read, while connecting the control gate line CGLij to ground can limit power consumption.

[0098] - Ground the control gate lines (CGL01, CGL02, CGL03, CGL10, CGL11, CGL12, CGL13) associated with the memory words that do not need to be read.

[0099] - Apply a positive voltage, such as VDD (the value of which depends on the technology), to the word line WLi (WL0) of the row of the memory word to be read.

[0100] - Ground the word line WLi (WL1) of the row that does not contain the memory word to be read.

[0101] - Ground the source line SL, and

[0102] - Ground the internal substrate SUBint.

[0103] Table 3 below shows the voltage applied to read memory word WD1 without affecting memory words WD2 to WD8.

[0104] [Table 3]

[0105] Row selection Column selection Mot BL CGL WL SL SUBint yes yes WD1 Precharge voltage 0.5 volts VDD GND GND yes no WD3, WD5, WD7 floating GND VDD GND GND no yes WD2 Precharge voltage GND GND GND GND no no WD4, WD6, WD8 floating GND GND GND GND

[0106] Table 3: Read voltage of memory plane ( Figure 4 )

[0107] The precharge voltage PRE (1V) enables the bit line BLk of the memory word to be read to be polarized to 0.5V before reading. During the read phase, approximately 100nA of current is injected into each bit line BLk.

[0108] Figure 5 A block diagram showing the steps involved in writing a memory word.

[0109] More specifically, the word WD1 is first erased in the first stage (as described with respect to Table 1), and then programmed (as described with respect to Table 2). This memory word is stored in a memory, such as Figure 4 As shown.

[0110] The method 500, including steps 501 to 513, is implemented by a data processing unit capable of controlling the erasing device DEFF and the programming device DPRO.

[0111] Method 500 includes:

[0112] Phase P1, which erases memory words, is performed by the erase device DEFF through the following steps:

[0113] - Step 501: Apply a positive voltage, for example, 10.5V, to the control gate line CGL00 associated with the memory word to be erased and float the bit line BLk.

[0114] - Step 502: Ground the control gate lines CGL01, CGL02, CGL03, CGL10, CGL11, CGL12, and CGL13 associated with the memory word not to be erased.

[0115] - Step 503: Ground word lines WL0 and WL1.

[0116] - Step 504, apply a negative voltage, for example -3.3V, to the source line SL, and

[0117] - Step 505: Connect the inner substrate to a negative voltage, such as -3.3V.

[0118] Phase P2, performed by the programming device DPROG, involves programming the memory word through the following steps:

[0119] - Step 506: Apply a positive voltage, such as 3.3V, to the bit line BL of the cell not to be programmed.

[0120] - Step 507: Apply a positive voltage, such as 9.5V, to the bit line BLk of the cell to be programmed.

[0121] - Step 508: Apply a negative voltage, such as -3.3V, to the control gate line CGL00 associated with the memory word to be programmed.

[0122] - Step 509: Apply a positive voltage, such as 6V, to the control gate line CGL10 associated with the memory word located in the same column as the memory word to be programmed.

[0123] - Step 510: Ground the control gate lines CGL01, CGL02, CGL03, CGL11, CGL12, and CGL13 associated with other memory words.

[0124] - Step 511: Ground the word lines WL0 and WL1 associated with the memory word.

[0125] - Step 512, apply a positive voltage, for example, 3.3V, to the source line SL, and

[0126] - Step 513, ground the internal substrate SUBint.

[0127] Figure 6 The memory MEM2 according to the second embodiment is schematically shown.

[0128] The organization of memory MEM2 is basically the same as Figure 4 The same as described above, except that the isolation barriers do not surround all cells, but rather surround several columns of memory words. Here, barrier BI01 surrounds columns COL0 and COL1, and barrier BI23 surrounds columns COL2 and COL3. In addition, source lines SL01 and SL23 specific to each group of columns (COL0 and COL1, and COL2 and COL3) are implemented.

[0129] The steps of the erasure process performed by the DEFF erasure device are basically the same as those of... Figure 4 The steps described are the same, but the applied voltage is different.

[0130] about Figure 6 The memory words WD1 to WD8 are represented in the table below. Table 4 below indicates the voltage applied to erase memory word WD1 and retain memory words WD2 to WD8.

[0131] [Table 4]

[0132] Row selection Column selection memory word BL CGL WL SL SUBint yes yes WD1 floating 10.5V GND -3.3V -3.3V yes no WD3 floating GND GND -3.3V -3.3V yes no WD5, WD7 floating GND GND GND GND no yes WD2 floating GND GND -3.3V -3.3V no no WD4 floating GND GND -3.3V -3.3V no no WD6, WD8 floating GND GND GND GND

[0133] Table 4: Erasure voltage of memory plane ( Figure 6 )

[0134] Similarly, the programming process implemented by the programming device DPROG involves the same steps as... Figure 4 The steps described are basically the same, but the applied voltage is different.

[0135] Compared with Table 1, it can be observed that the voltage applied to the words (WD3, WD5, WD7 and WD4, WD6, WD8) is different depending on whether the word is located in the same isolation barrier as the word to be programmed (WD1).

[0136] In other words, the voltages for words WD3 and WD4 in barrier BI01 and for words WD5, WD6, WD7, and WD8 in barrier BI23 are different here, but there is no difference for the embodiment described in conjunction with Table 1.

[0137] about Figure 6 The memory words WD1 to WD8 are shown below. Table 5 below indicates the voltage applied to program memory word WD1 without affecting memory words WD2 to WD8.

[0138] [Table 5]

[0139]

[0140]

[0141] Table 5: Programming voltage of memory plane ( Figure 6 )

[0142] Compared with Table 2, it can be observed that the voltage applied to words (WD4, WD6, WD8) differs depending on whether the word is located in the same isolation barrier as the word to be programmed (WD1). That is, here, the voltage of word WD4 in barrier BI01 is different from the voltages of words WD6 and WD8 in barrier BI23, while for the embodiment described in conjunction with Table 2, there is no difference.

[0143] Finally, the steps of the reading process implemented by the reading device DLEC are basically the same as... Figure 4 The steps are the same as those implemented in [the previous section].

[0144] Figure 7 A memory according to a third embodiment is schematically shown.

[0145] The organization of memory MEM2 is basically the same as Figure 4 The same as described above, except that the isolation barriers do not surround all cells, but rather surround each column of memory words. Here, barriers BI0, BI1, BI2, and BI3 surround columns COL0, COL1, COL2, and COL3, respectively. Furthermore, source lines SL0, SL1, SL2, and SL3 are implemented for each column (COL0, COL1, COL2, and COL3).

[0146] The steps of the erasure process performed by the DEFF erasure device are basically the same as those of... Figure 4 The steps described are the same, but the applied voltage is different.

[0147] about Figure 7 The memory words WD1 to WD8 are represented in the table below. Table 6 below indicates the voltage applied to erase memory word WD1 and retain memory words WD2 to WD8.

[0148] [Table 6]

[0149] Row selection Column selection Mot BL CGL WL SL SUBint yes yes WD1 floating 10.5V GND -3.3V -3.3V yes no WD3, WD5, WD7 floating GND GND GND GND no yes WD2 floating GND GND -3.3V -3.3V no no WD4, WD6, WD8 floating GND GND GND GND

[0150] Table 6: Erasure voltage of memory plane ( Figure 6 )

[0151] Compared to Table 1, it can be observed that the voltages applied to the words (WD3, WD5, WD7 and WD4, WD6, WD8) are different. In particular, the source line SL and the internal substrate SUBint are grounded (GND) instead of -3.3V. Since each column is isolated, it is no longer necessary to apply them to the same voltage.

[0152] Similarly, the programming process implemented by the programming device DPROG involves the same steps as... Figure 4 The steps described are basically the same, but the applied voltage is different.

[0153] about Figure 7 The memory words WD1 to WD8 are shown below. Table 7 indicates the voltage applied to program memory word WD1 without affecting memory words WD2 to WD8.

[0154] [Table 7]

[0155]

[0156] Table 7: Programming voltage of memory plane ( Figure 6 )

[0157] Compared to Table 2, it can be observed that the voltages applied to the words (WD3, WD5, WD7 and WD4, WD6, WD8) are different. In particular, the bit line BLk and the source line SL are grounded (GND) instead of at 3.3V. Since each column is isolated, it is no longer necessary to apply them to the same voltage.

[0158] The reading process implemented by the reading device DLEC and Figure 4 The reading process implemented in the two languages ​​is basically the same.

[0159] Column isolation makes it possible to reduce EEPROM consumption during writing (by applying voltage only to the memory word to be written), thereby compromising the surface area of ​​the memory plane PM.

[0160] In summary, the embodiments of the memory have the following advantages:

[0161] - Lower positive voltages (absolute values) are allowed, namely 10.5V during the erase step and 9.5V during the programming step.

[0162] This makes it possible to reduce EEPROM consumption during writing.

[0163] This makes it possible to reduce the voltage that the charge pump must generate by 30%.

[0164] - It can reduce the requirements for high-voltage equipment in the peripheral circuit.

[0165] Description of the writing voltage of the present invention

[0166] The two charge pumps providing -3.3V+ / -5% and +3.3V+ / -5% were developed using so-called GO2 (65 angstroms "gate oxide 2") transistors.

[0167] In the eraser DEFF, the analog circuitry can adjust the positive voltage applied to the control gate line CGLij associated with the memory word to be erased from 10.5V to 11.5V.

[0168] During the erase step, the potential difference between the control gate CG and the source TEs of the state transistor TE (also known as "VPP erase") makes it possible to inject electronic charge into the floating gate via the Fowler-Nordheim effect.

[0169] VPP erasure = V CG(Byte Sel.) –V TEs

[0170] [Table 8]

[0171] Adjustment code 000 001 010 011 100 VCG (Byte Sel.) 10.50V 10.75V 11.00V 11.25V 11.50V VPP erasure 13.80V 14.05V 14.30V 14.55V 14.80V

[0172] Table 8: Erasure Values

[0173] In the programming device DPROG, analog circuitry can adjust the positive voltage applied to the bit line BLk associated with the memory word to be programmed from 9.5V to 10.5V.

[0174] During the programming process, the potential difference between the drain Ted and the control gate CG of the state transistor TE (also known as "VPP Prog") allows the extraction of potential electronic charge stored in the floating gate via the Fowler-Nordheim effect.

[0175] VPP Prog = V BL(Sel.) –V CG(Byte Sel.)

[0176] [Table 9]

[0177]

[0178]

[0179] Table 9: Programming Values

[0180] In order not to interfere with other memory words located in the same column as the memory word to be programmed, it is necessary to meet the following conditions:

[0181] VCG(Byte Unsel. in the same column) = VBL(Sel.) – 3.5V.

Claims

1. A memory of the electrically erasable programmable read-only memory type, arranged in and on a semiconductor substrate, the memory comprising: a plurality of memory cells organized in a memory plane arranged in rows and columns in a matrix, each memory cell comprising: a state transistor comprising a source region, a drain region, an implant window, a control gate and a floating gate, the implant window being located on one side of the drain; and an isolation transistor having a source region, a drain region and a gate; and an isolation barrier comprising: a buried layer; and at least one wall extending from the buried layer to a surface of the substrate, wherein the at least one wall is perpendicular to the buried layer, and wherein the isolation barrier forms an inner substrate, the inner substrate surrounding at least one of the memory cells and isolating the at least one memory cell from a remainder of the substrate; wherein the control gate of the state transistor is connected to a control gate line of the memory, wherein the source region of the isolation transistor is connected to a source line of the memory, wherein the gate of the isolation transistor is connected to a word line of the memory, and wherein the drain region of the state transistor is connected to a bit line; wherein the isolation barrier is configured to isolate all memory cells of the memory plane together; further comprising circuitry for erasing a memory word, the circuitry being configured to: float the bit line, apply a first positive voltage to the control gate line associated with the memory cell of the memory word to be erased, ground the control gate lines of the memory cells not associated with the memory word to be erased, ground the word line, ground the source line, and ground the inner substrate.

2. The memory of claim 1, wherein a difference between the first positive voltage and ground effects a Fowler-Nordheim effect by injecting a charge of electrons into the floating gate of the state transistor.

3. The memory of claim 1, further comprising: circuitry for programming a memory word, the circuitry being configured to: apply a positive voltage to the bit line of the memory cell of the memory word to be programmed, apply a positive voltage to the bit line of the memory cell not to be programmed, the positive voltage applied to the bit line of the memory cell not to be programmed being less than the positive voltage applied to the bit line of the memory cell to be programmed, apply a negative voltage to the control gate line of the memory cell associated with the memory word to be programmed, apply a positive voltage to the control gate line of the memory cell on the same column as the memory word to be programmed, ground the control gate lines of the memory cells not associated with the memory word to be programmed, ground the word line, apply a positive voltage to the source line, and ground the inner substrate.

4. The memory of claim 3, wherein the positive voltage applied to the bit line of the memory cell of the memory word to be programmed is about 9.5 V, wherein the positive voltage applied to the source line is about 9.5 V, and wherein the negative voltage applied to the control gate line of the memory cell associated with the memory word to be programmed is about -9.5 V. wherein the positive voltage applied to the bit line of the memory cell not to be programmed is about 3.3 V, wherein the negative voltage applied to the control gate line of the memory cell associated with the memory word to be programmed is about -3.3 V, wherein the positive voltage applied to the control gate line of the memory cell in the same column as the memory cell of the memory word to be programmed is about 6 V, and wherein the positive voltage applied to the source line is about 3.3 V.

5. The memory of claim 1, further comprising: Circuitry for reading a memory word, configured to: apply a positive voltage to the bit line of the memory cell of the memory word to be read; apply a positive voltage to the control gate line of the memory cell of the memory word to be read; ground the control gate line of the memory cell not associated with the memory word to be read; apply a positive voltage to the word line of the memory cell of the row associated with the memory word to be read; ground the word line of the memory cell not on the row associated with the memory word to be read, ground the source line, and ground the internal substrate.

6. The memory of claim 5, wherein the positive voltage applied to the bit line of the memory cell of the memory word to be read is about 1 V, wherein the positive voltage applied to the control gate line of the memory cell of the memory word to be read is about 0.5 V, and wherein the positive voltage applied to the word line of the memory cell of the row associated with the memory word to be read is VDD.

7. A memory of the electrically erasable programmable read-only memory type, arranged in and on a semiconductor substrate, the memory comprising: a plurality of memory cells organized in a memory plane arranged in rows and columns in a matrix, each memory cell comprising: a state transistor comprising a source region, a drain region, an implantation window, a control gate, and a floating gate, the implantation window being located on one side of the drain; and an isolation transistor having a source region, a drain region, and a gate; and an isolation barrier comprising: a buried layer; and at least one wall extending from the buried layer to a surface of the substrate, wherein the at least one wall is perpendicular to the buried layer, and wherein the isolation barrier forms an internal substrate that surrounds at least one of the memory cells and isolates the at least one memory cell from the rest of the substrate; wherein the control gate of the state transistor is connected to a control gate line of the memory, wherein the source region of the isolation transistor is connected to a source line of the memory, wherein the gate of the isolation transistor is connected to a word line of the memory, and wherein the drain region of the state transistor is connected to a bit line; wherein the isolation barrier is configured to isolate together all the memory cells belonging to a column of the memory plane; wherein the positive voltage applied to the bit line of the memory cell not to be programmed is about 3.3 V, wherein the negative voltage applied to the control gate line of the memory cell associated with the memory word to be programmed is about -3.3 V, wherein the positive voltage applied to the control gate line of the memory cell in the same column as the memory cell of the memory word to be programmed is about 6 V, and wherein the positive voltage applied to the source line is about 3.3 V. The memory further includes circuitry for erasing a memory word, configured to: float the bit lines, apply a second positive voltage to the control gate lines associated with the memory cells of the memory word to be erased, ground the control gate lines of the memory cells not associated with the memory word to be erased, ground the word lines, apply a first negative voltage to the source lines, and apply the first negative voltage to the internal substrate.

8. The memory of claim 7, wherein a voltage difference between the second positive voltage and the first negative voltage effects a Fowler-Nordheim effect by injecting a charge of electrons into the floating gate of the pass transistor.

9. The memory of claim 7, further comprising: Circuitry for programming a memory word, configured to: apply a positive voltage to the bit lines of the memory cells of the memory word to be programmed, apply a positive voltage to the bit lines of the memory cells not to be programmed, the positive voltage applied to the bit lines of the memory cells not to be programmed being less than the positive voltage applied to the bit lines of the memory cells to be programmed, apply a negative voltage to the control gate lines of the memory cells associated with the memory word to be programmed, apply a positive voltage to the control gate lines of the memory cells on the same column as the memory word to be programmed, ground the control gate lines of the memory cells not associated with the memory word to be programmed, ground the word lines, apply a positive voltage to the source lines, and ground the internal substrate.

10. The memory of claim 9, wherein the positive voltage applied to the bit lines of the memory cells of the memory word to be programmed is approximately 9.5 V, wherein the positive voltage applied to the bit lines of the memory cells not to be programmed is approximately 3.3 V, wherein the negative voltage applied to the control gate lines of the memory cells associated with the memory word to be programmed is approximately -3.3 V, wherein the positive voltage applied to the control gate lines of the memory cells on the same column as the memory cells of the memory word to be programmed is approximately 6 V, and wherein the positive voltage applied to the source lines is approximately 3.3 V.

11. The memory of claim 7, further comprising: Circuitry for reading a memory word, configured to: apply a positive voltage to the bit lines of the memory cells of the memory word to be read; apply a positive voltage to the control gate lines of the memory cells of the memory word to be read; ground the control gate lines of the memory cells not associated with the memory word to be read; apply a positive voltage to the word lines of the memory cells of the row associated with the memory word to be read; ground the word lines of the memory cells not on the row associated with the memory word to be read, ground the source lines, and ground the internal substrate.

12. The memory of claim 11, wherein the positive voltage applied to the bit line of the memory cell of the memory word to be read is about 1 V, wherein the positive voltage applied to the control gate line of the memory cell of the memory word to be read is about 0.5 V, and wherein the positive voltage applied to the word line of the memory cell of the row associated with the memory word to be read is VDD.

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