Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present application relate to a semiconductor device and a manufacturing method thereof. The semiconductor device of the embodiments includes a first chip provided with a memory cell array, and a second chip bonded to the first chip and provided with a control circuit that controls the memory cell array. The first chip has a substrate, a bump, a first structure, and a second structure. The substrate is disposed on the opposite side of a bonding surface of the second chip, and includes a first surface provided with the memory cell array between the opposite bonding surface, a second surface on the opposite side of the first surface, and an opening portion reaching from the second surface to the first surface in a first region. The bump is disposed in the opening portion. The first structure is disposed between the first surface and the bonding surface, and is electrically connected to the bump. The second structure is disposed between the first surface and the bonding surface in the first region.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2020-150749 (filed on September 8, 2020). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Technology

[0004] In recent years, hybrid bonding technology, which involves attaching two wafers containing semiconductor elements, has been introduced into CMOS (Complementary Metal Oxide Semiconductor) image sensors or non-volatile semiconductor memories. In this case, the electrode pads used for wire bonding for external connections are formed, for example, after the substrate is thinned, so that they are exposed on the top layer of the chip.

[0005] However, the mechanical stress during wire bonding may damage semiconductor components or wiring. Summary of the Invention

[0006] The embodiments provide a semiconductor device and a method for manufacturing the same, which are capable of suppressing the effects of stress generated by wire bonding.

[0007] The semiconductor device of this embodiment includes: a first chip having a memory cell array disposed thereon; and a second chip bonded to the first chip and having control circuitry for controlling the memory cell array disposed thereon. The first chip has a substrate, solder pads, a first structure, and a second structure. The substrate is disposed on the opposite side of the bonding surface of the second chip and includes: a first surface having the memory cell array disposed between it and the opposing bonding surface; a second surface opposite to the first surface; and an opening extending from the second surface to the first surface in a first region. Solder pads are disposed within the opening. The first structure is disposed between the first surface and the bonding surface and is electrically connected to the solder pads. The second structure is disposed between the first surface and the bonding surface in a first region. Attached Figure Description

[0008] Figure 1 This is a cross-sectional view illustrating an example of the construction of a semiconductor device.

[0009] Figure 2 This is a cross-sectional view showing an example of the structure of a columnar section.

[0010] Figure 3 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0011] Figure 4This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0012] Figure 5 This is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment.

[0013] Figure 6 This is a top-view view showing the configuration of the structure and plug holes in the first embodiment.

[0014] Figures 7-14 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0015] Figure 15 This is a cross-sectional view showing the configuration of a comparative example semiconductor device.

[0016] Figure 16 This is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment.

[0017] Figure 17 This is a top-view view showing the configuration of the structure and plug holes in the second embodiment.

[0018] Figure 18 This is a cross-sectional view showing the configuration of the semiconductor device according to the third embodiment.

[0019] Figure 19 This is a top-view view showing the configuration of the structure and plug holes in the third embodiment.

[0020] Figure 20 This is a cross-sectional view showing the configuration of the semiconductor device according to the fourth embodiment.

[0021] Figure 21 This is a cross-sectional view showing the configuration of the semiconductor device according to the fifth embodiment.

[0022] Figures 22-27 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the fifth embodiment. Detailed Implementation

[0023] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments are not intended to limit the present invention. In the following embodiments, the vertical direction of the semiconductor substrate refers to the relative direction with the surface on which the semiconductor element is disposed as the top, and may sometimes differ from the vertical direction based on gravitational acceleration. The accompanying drawings are schematic diagrams or conceptual diagrams, and the proportions of the parts may not be the same as in reality. In the specification and drawings, elements already mentioned in the drawings above are labeled with the same symbols, and detailed descriptions are omitted where appropriate.

[0024] (First Embodiment)

[0025] Figure 1This is a cross-sectional view illustrating an example of the construction of a semiconductor device. Figure 1 The semiconductor device is a three-dimensional memory formed by bonding an array chip 1 and a circuit chip 2. The array chip 1 is an example of the first chip, and the circuit chip 2 is an example of the second chip.

[0026] The array chip 1 includes: a memory cell array 11 comprising multiple memory cells, an insulating film 12 on the memory cell array 11, and an interlayer insulating film 13 under the memory cell array 11. The insulating film 12 is, for example, a silicon oxide film or a silicon nitride film. The interlayer insulating film 13 is, for example, a silicon oxide film, or a laminated film comprising a silicon oxide film and other insulating films.

[0027] Circuit chip 2 is disposed below array chip 1. The symbol S indicates the bonding surface between array chip 1 and circuit chip 2. The bonding surface S is an example of the first bonding surface. Circuit chip 2 includes an interlayer insulating film 14 and a substrate 15 under the interlayer insulating film 14. The interlayer insulating film 14 is, for example, a silicon oxide film, or a multilayer film including a silicon oxide film and other insulating films. The substrate 15 is, for example, a semiconductor substrate such as a silicon substrate.

[0028] Figure 1 The X and Y directions, which are parallel to and perpendicular to the surface of substrate 15, and the Z direction, which is perpendicular to the surface of substrate 15, are shown. In this specification, the +Z direction is considered the upward direction, and the -Z direction is considered the downward direction. The -Z direction may or may not be aligned with the direction of gravity.

[0029] The array chip 1 has multiple word lines WL and source lines SL as electrode layers within the memory cell array 11. Figure 1 The stepped structure 21 of the memory cell array 11 is shown. Each word line WL is electrically connected to the word wiring layer 23 via a contact plug 22. Each columnar portion CL passing through multiple word lines WL is electrically connected to the bit line BL via a plug hole 24, and is also electrically connected to the source line SL. The source line SL includes a first layer SL1 as a semiconductor layer and a second layer SL2 as a metal layer.

[0030] The circuit chip 2 includes a plurality of transistors 31. Each transistor 31 includes: a gate electrode 32 disposed on a substrate 15 through a gate insulating film; and a source diffusion layer and a drain diffusion layer (not shown) disposed within the substrate 15. In addition, the circuit chip 2 includes: a plurality of contact plugs 33 disposed on the gate electrode 32, source diffusion layer, or drain diffusion layer of these transistors 31; a wiring layer 34 disposed on these contact plugs 33 and including a plurality of wirings; and a wiring layer 35 disposed on the wiring layer 34 and including a plurality of wirings.

[0031] The circuit chip 2 also includes: a wiring layer 36 disposed on the wiring layer 35 and containing multiple wirings; multiple vias 37 disposed on the wiring layer 36; and multiple metal pads 38 (second bonding pads) disposed on these vias 37. The metal pads 38 are, for example, Cu (copper) layers or Al (aluminum) layers. The circuit chip 2 functions as a control circuit (logic circuit) that controls the operation of the array chip 1. This control circuit includes transistors 31, etc., and is electrically connected to the metal pads 38.

[0032] The array chip 1 includes: a plurality of metal pads 41 (first bonding pads) disposed on metal pads 38, and a plurality of vias 42 disposed on the metal pads 41. Additionally, the array chip 1 includes: a wiring layer 43 disposed on the vias 42 and including a plurality of wirings; and a wiring layer 44 disposed on the wiring layer 43 and including a plurality of wirings. The metal pads 41 are, for example, Cu layers or Al layers.

[0033] The array chip 1 also includes: a plurality of vias 45 disposed on the wiring layer 44, metal pads 46 (connection terminals) disposed on these vias 45 or on the insulating film 12, and a passivation film 47 disposed on the metal pads 46 or on the insulating film 12. The metal pads 46 are, for example, a Cu layer or an Al layer, serving as... Figure 1 The external bonding pads (bonding pads) of the semiconductor device function as bonding pads. The passivation film 47 is an insulating film, such as a silicon oxide film, and has an opening P (connection terminal area) that exposes the upper surface of the metal bonding pad 46. The metal bonding pad 46 can be connected to the mounting substrate or other devices through the opening P via bonding wires, solder balls, metal bumps, etc.

[0034] Figure 2 This is a cross-sectional view showing an example of the construction of the columnar section CL.

[0035] like Figure 2 As shown, the memory cell array 11 has alternating layers of interlayer insulating film 13. Figure 1 The device contains multiple word lines WL and multiple insulating layers 51. The word lines WL are, for example, a W (tungsten) layer. The insulating layers 51 are, for example, a silicon oxide film.

[0036] The columnar portion CL sequentially comprises a barrier insulating film 52, a charge accumulation layer 53, a tunnel insulating film 54, a channel semiconductor layer 55, and a core insulating film 56. The charge accumulation layer 53, for example, is a silicon nitride film, formed on the side of the word line WL and the insulating layer 51, separating it from the barrier insulating film 52. The charge accumulation layer 53 can be a semiconductor layer such as a polysilicon layer. The channel semiconductor layer 55, for example, is a polysilicon layer, formed on the side of the charge accumulation layer 53, separating it from the tunnel insulating film 54. The barrier insulating film 52, the tunnel insulating film 54, and the core insulating film 56 are, for example, silicon oxide films or metal insulating films.

[0037] Figure 3 and Figure 4 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0038] Figure 3 An array wafer W1 containing multiple array chips 1 and a circuit wafer W2 containing multiple circuit chips 2 are shown. The array wafer W1 is also referred to as a "memory wafer", and the circuit wafer W2 is also referred to as a "CMOS wafer". The array wafer W1 is an example of a first wafer, and the circuit wafer W2 is an example of a second wafer.

[0039] Please note Figure 3 The orientation of the array wafer W1 and Figure 1 The array chip 1 is oriented in opposite directions. In this embodiment, a semiconductor device is manufactured by bonding the array wafer W1 to the circuit wafer W2. Figure 3 This shows an array of wafers W1 that have been flipped so that they are facing forward in order to be bonded. Figure 1 The image shows the array chip 1 after being reversed for bonding and cutting.

[0040] exist Figure 3 In the diagram, symbol S1 represents the upper surface of array wafer W1, and symbol S2 represents the upper surface of circuit wafer W2. Note that array wafer W1 has a substrate 16 disposed under insulating film 12. Substrate 16 is, for example, a semiconductor substrate such as a silicon substrate.

[0041] In this embodiment, firstly, as Figure 3 As shown, a memory cell array 11, an insulating film 12, an interlayer insulating film 13, a stepped structure portion 21, and a metal pad 41 are formed on the substrate 16 of the array wafer W1, and an interlayer insulating film 14, a transistor 31, and a metal pad 38 are formed on the substrate 15 of the circuit wafer W2. For example, vias 45, wiring layers 44 and 43, vias 42, and metal pads 41 are sequentially formed on the substrate 16. Additionally, contact plugs 33, wiring layers 34, 35, and 36, vias 37, and metal pads 38 are sequentially formed on the substrate 15. Next, as... Figure 4 As shown, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure. This bonds the interlayer insulating film 13 and the interlayer insulating film 14 together. Next, the array wafer W1 and the circuit wafer W2 are annealed at 400°C. This bonds the metal pad 41 and the metal pad 38 together.

[0042] Subsequently, substrate 15 is thinned using CMP (Chemical Mechanical Polishing), and substrate 16 is removed using CMP. Then, array wafer W1 and circuit wafer W2 are diced into multiple chips. This process is used to manufacture... Figure 1 Semiconductor devices. Figure 1 The diagram shows a circuit chip 2 including metal pads 38, and an array chip 1 including metal pads 41 disposed on the metal pads 38. Furthermore, the metal pads 46 and passivation film 47 are formed on the insulating film 12, for example, after thinning the substrate 15 and removing the substrate 16.

[0043] Furthermore, although the array wafer W1 is bonded to the circuit wafer W2 in this embodiment, it is also possible to bond the array wafer W1 to each other instead. (See reference...) Figures 1 to 4 Based on the content mentioned above and references Figures 5 to 20 The content described below can also be applied to the bonding of array wafers W1 to each other.

[0044] in addition, Figure 1 The interfaces between interlayer insulating films 13 and 14, and between metal pads 41 and 38, are shown, but these interfaces are generally not observable after the annealing process. However, the locations of these interfaces can be estimated, for example, by detecting the slope of the sides of metal pads 41 and 38, or the positional deviation between the sides of metal pads 41 and 38.

[0045] Furthermore, the semiconductor device of this embodiment can be cut into multiple chips. Figure 1 It can become a trading object in a certain state, or it can be before being cut into multiple chips. Figure 4 In a certain state, it becomes a trading object. Figure 1 A semiconductor device showing the state of a chip. Figure 4 A semiconductor device in wafer form is shown. In this embodiment, a single wafer-shaped semiconductor device ( Figure 4 Manufacturing multiple chip-shaped semiconductor devices Figure 1 ).

[0046] The following is for reference Figures 5 to 20 The array chip 1 of this embodiment will be described in detail, and specifically, the structure of the metal pad 46 and its surrounding area will be described in detail. The following description also applies to the circuit wafer W2 of this embodiment.

[0047] Figure 5 This is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment.

[0048] exist Figure 5 In, with Figure 1 Compared to the configuration shown, Figure 4 The substrate 16 shown was not completely removed, but rather thinned. Additionally, Figure 1 The insulating film 12 and source line SL shown are not shown. Figure 5 In addition, at Figure 5The array also includes a structure 18 and insulating layers 61 and 62. Symbol 111 represents the stacked body of the memory cell array 11, and symbol 112 represents the columnar portion of the memory cell array 11.

[0049] like Figure 5 As shown, the array chip 1 includes a substrate 16, metal pads 46, vias 45, a structure 18, and insulating layers 61 and 62.

[0050] Substrate 16 is disposed on the opposite side of the bonding surface (joint surface) S of circuit chip 2. Substrate 16 also includes surface F3 and surface F4 opposite to surface F3. Surface F3 faces the bonding surface S, and a memory cell array 11 is disposed between surface F3 and the bonding surface S. Furthermore, substrate 16 includes an opening 16a in region A1 extending from surface F4 to surface F3. As explained below, region A1 is the region where wiring is formed by wire bonding WB.

[0051] Metal pad 46 is disposed within the opening 16a. Furthermore, the metal pad 46 is electrically connected in region A1 via wire bonding WB. Figure 5 In the example shown, two metal pads 46 are provided. However, the number of metal pads 46 is not limited to this. The material of the metal pads 46 is, for example, aluminum (Al).

[0052] A plug hole 45 is disposed between surface F1 of the insulating layer 61 and the mating surface S, and is electrically connected to the metal solder pad 46. Additionally, as... Figure 5 As shown, the via 45 is connected to a transistor 31, which is part of the control circuit. That is, the via 45 is electrically connected to the control circuitry disposed on the circuit chip 2. The via 45 is, for example, connected to the columnar portion 112 of the memory cell array 11 (e.g., Figure 1 The contact plug 22 is formed approximately simultaneously with the contact plug 22. Therefore, the material of the plug hole 45 is the same as the material of the contact plug 22, for example, tungsten. Furthermore, the plug hole 45 is not limited to a columnar portion, but may be a structure with other shapes. This structure may also include a wiring layer or the like connected to the plug hole 45.

[0053] The structure 18 is disposed in region A1 between the surface F1 of the insulating layer 61 and the bonding surface S.

[0054] As described above, one method for connecting a semiconductor device to an external mounting substrate or device is known to form wiring for a metal pad 46 by wire bonding (WB). Regarding wire bonding (WB), a load is applied to the metal pad 46 for a certain period of time using a bonding tool such as a solder pin. Therefore, stress is applied to the semiconductor device during wire bonding. Here, as shown in region A1, the substrate 16 is removed, and a metal pad 46 electrically connected to the transistor 31 is provided. Therefore, the strength of region A1 is reduced. For example, the memory cell array 11, transistor 31, via 45, or wiring layer disposed directly below or around the opening 16a may be mechanically damaged by stress.

[0055] Therefore, in the first embodiment, a structure 18, which functions as a stress-resistant film during wire bonding, is provided directly below the opening 16a. The structure 18 has, for example, a high rigidity or robust construction. This improves load resistance and impact resistance. Consequently, the effects of stress applied to the semiconductor device during wire bonding can be mitigated.

[0056] exist Figure 5 In the example shown, the construct 18 is a stacked stack corresponding to the stacked stack 111 of the memory cell array 11. Figure 2 As explained, the memory cell array 11 has a stacked body 111, which includes a plurality of word lines WL (conductive layers) and a plurality of insulating layers 51 alternately stacked along the Z direction perpendicular to the surface F1 of the insulating layer 61. Therefore, the structure 18 has a stacked body 181 containing two types of insulating layers 181a and 181b, which are alternately stacked in a manner corresponding to the stacked body 111. This is because, during the formation step of the memory cell array 11, the structure 18 (stacked body 181) is formed approximately simultaneously with the memory cell array 11. Therefore, the position and thickness of the insulating layer 181a from the surface F1 of the insulating layer 61 are approximately the same as those of the word lines WL. Furthermore, the position and thickness of the insulating layer 181b from the surface F1 of the insulating layer 61 are approximately the same as those of the insulating layer 51.

[0057] Furthermore, either of the two insulating layers 181a and 181b of the laminate 181 is the same as the insulating layer 51 of the laminate 111. Figure 5 In the example shown, insulating layer 181b is, for example, a silicon oxide film. Therefore, the material of insulating layer 181b is the same as that of insulating layer 51. On the other hand, insulating layer 181a is, for example, a silicon nitride film. Silicon nitride (SiN) has higher strength than silicon oxide (SiO2) of interlayer insulating film 13. As a result, structure 18 has high strength.

[0058] Here, as a method for forming the stacked body 111 of the memory cell array 11, a known method is as follows: the sacrificial layer is selectively removed from the stacked body containing the sacrificial layer and the insulating layer 51, and the resulting cavity is filled with a metal such as tungsten. This sacrificial layer corresponds to the insulating layer 181a. Therefore, in the steps of forming the memory cell array 11 until the sacrificial layer is replaced with the word line WL, the stacked body 181 is formed approximately simultaneously with the memory cell array 11.

[0059] Figure 6 This is a top-view view showing the configuration of the structure 18 and the plug hole 45 in the first embodiment. Figure 6 From Figure 5 A diagram showing the opening 16a viewed in the Z direction. Figure 6 In the example shown, for one metal pad 46, plug holes 45 are arranged in 2 rows and 2 columns.

[0060] like Figure 6 As shown, the structure 18 is configured not to contact the plugging hole 45. That is, an interlayer insulating film 13 is provided between the insulating layers 181a and 181b of the structure 18 and the plugging hole 45. The structure 18 is formed, for example, by forming an opening around the periphery of the plugging hole 45.

[0061] In addition, Figure 6 In the example shown, the structure 18 is disposed within the area of ​​the metal pad 46. However, it is not limited to this and may also be disposed outside the area of ​​the metal pad 46. From a strength point of view, the structure 18 is preferably disposed more widely, but it may also be varied depending on the configuration of other components within the array chip 1.

[0062] like Figure 5 As shown, the insulating layer 61 is disposed within the opening 16a such that at least a portion of the metal pad 46 in region A1 is exposed on the surface F4 side of the substrate 16. The insulating layer 61 is, for example, a silicon oxide film. The insulating layer 61 includes surface F1 and surface F2 opposite to surface F1. Figure 5 In the example shown, face F1 is approximately parallel to face F3, and face F2 is approximately parallel to face F4.

[0063] An insulating layer 62 is disposed on the sides of the array chip 1 and the circuit chip 2 to cover the connection portion between the array chip 1 and the circuit chip 2. Figure 5 In the example shown, the metal pads 38 and 41 used to bond the array chip 1 to the circuit chip 2 are exposed from the interlayer insulating films 13 and 14. By covering the metal pads 38 and 41 with the insulating layer 62, contamination of the metal pads 38 and 41 caused by impurities during the manufacturing process can be suppressed. The insulating layer 61 is, for example, a silicon oxide film. More specifically, the material of the insulating layer 62 is the same as that of the insulating layer 61. This is because, as explained below, the insulating layers 61 and 62 are formed together. Furthermore, in... Figure 5 In this configuration, the sides of the array chip 1 and circuit chip 2, which are provided with insulating layer 62, correspond to the outer peripheral side of the wafer. On the other hand, in... Figure 5 In the middle, the side opposite to the side where the insulating layer 62 is provided is a continuous arbitrary cross-section.

[0064] Next, the manufacturing method of the semiconductor device will be explained.

[0065] Figures 7-14 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0066] First, such as Figure 7 As shown, a memory cell array 11 and vias 45 are formed on surface F3 of a substrate 16 that includes surface F3 and surface F2F4 opposite to surface F3, and a structure 18 is formed in region A1 on surface F3. Furthermore, please note... Figure 7 The orientation of the array wafer W1 and Figure 5 The array chip 1 is oriented in the opposite direction. In addition, more specifically, as described above, the structure 18 is formed simultaneously with the formation of the memory cell array 11.

[0067] In addition, such as Figure 3 As explained, transistors 31 and wiring are formed on substrate 15.

[0068] Next, as Figure 8 As shown, the array wafer W1 and the circuit wafer W2 are bonded together. That is, the array wafer W1, which has a substrate 16, is bonded to the circuit wafer W2, on which the control circuit for the control memory cell array 11 is formed. Furthermore, the substrate 16 is ground by back grinding. Additionally, the side surfaces Ws of the array wafer W1 and the circuit wafer W2 are ground, for example, by trimming. The side surfaces Ws refer to the outer peripheral surfaces of the wafers. By grinding the side surfaces Ws, in… Figure 8 In the example shown, the metal pads 38 and 41 at the joint interface are exposed.

[0069] Next, as Figure 9 As shown, an opening 16a is formed in region A1, extending from surface F4 of substrate 16 to surface F3. For example, the opening 16a is formed by forming a silicon oxide film on surface F4 of substrate 16 and performing RIE (Reactive Ion Etching) using a resist mask. At the bottom of this opening 16a, a plug hole 45 is exposed from the interlayer insulating film 13.

[0070] Next, as Figure 10As shown, an aluminum film 46a is formed at surface F4 and opening 16a. The aluminum film 46a is formed along the bottom of opening 16a, the side surface of substrate 16, and surface F4.

[0071] Next, as Figure 11 As shown, an aluminum film 46a is processed using a photoresist mask to form a metal pad 46 that is electrically connected to the plug hole 45 inside the opening 16a.

[0072] Next, as Figure 12 As shown, an insulating layer 63 is formed covering the surface F4, opening 16a, metal pad 46, and side surface Ws of the substrate 16. Thus, the insulating layer 63 can cover the metal pads 38 and 41 of the bonding interface exposed from the side surface Ws, as well as the upper surface and side surface of the substrate 16, approximately simultaneously. The insulating layer 63 is, for example, a silicon oxide film. For example, TEOS (Tetraethoxysilane) is used to form the insulating layer 63.

[0073] Next, as Figure 13 As shown, the upper surface of the insulating layer 63 is polished using CMP until surface F4 of the substrate 16 is exposed. This separates the insulating layer 63 into an insulating layer 61 and an insulating layer 62. That is, an insulating layer 61 is formed within the opening 16a, and an insulating layer 62 is formed on the side surface Ws. The insulating layer 62 is provided on the side surface Ws to cover the connection between the array wafer W1 and the circuit wafer W2. In other words, the metal pads 38 and 41 remain covered by the insulating layer 62 even after CMP polishing.

[0074] Next, as Figure 14 As shown, a passivation film 47 is formed on surface F4 and the upper surface (surface F2) of insulating layer 61. For example, a thick-film resist such as PI (polyimide) is coated, followed by exposure, development, and RIE processing. This forms an opening P that exposes the metal solder pad 46. Subsequently, it is monolithically processed, thereby... Figure 5 The semiconductor device is completed.

[0075] As described above, according to the first embodiment, the metal pad 46 is disposed within the opening 16a of the substrate 16 in the wire bonding region A1. Furthermore, the structure 18 is disposed in region A1 between the surface F1 of the insulating layer 61 and the bonding surface S. The structure 18 has high strength and can suppress the influence of mechanical stress applied to the semiconductor device during wire bonding. Therefore, even when wire bonding is performed on the metal pad 46 directly above the plug hole 45, the influence of mechanical stress on the plug hole 45, etc., can be suppressed. In addition, since stress during wire bonding does not need to be considered, the design freedom of semiconductor components or wiring can be improved. Furthermore, after wire bonding, the opening P or the wire bonding area can be covered with a protective film such as polyimide or resin.

[0076] Furthermore, the structure 18 is formed approximately simultaneously with the memory cell array 11 during the formation step. Therefore, it is possible to suppress the increase in the number of steps used to form the structure 18. In addition, the structure 18 does not necessarily have to be formed through the steps used to form the memory cell array 11. For example, the stacked body 181 may be formed as a robust stacked body, different from the memory cell array 11.

[0077] Figure 15 This is a cross-sectional view showing the configuration of a comparative example semiconductor device.

[0078] As a method to suppress the influence of stress when no construct 18 is set, consider the following method: Figure 15 As shown, the metal pad 46 is placed along... Figure 15 The chip is configured with its leads extended laterally (horizontally). In this case, wire bonding (WB) is performed in the opening P, which is separated from the opening 16a directly above the via 45. However, it is necessary to ensure the distance L between the opening 16a and the opening P. That is, extra space is required to bring out the metal pads 46, which hinders the reduction of chip size.

[0079] In contrast, in the first embodiment, wiring can be formed directly at the opening P in region A1 by wire bonding WB, without having to extend the metal pad 46 laterally. As a result, the chip area can be reduced.

[0080] In addition, Figure 15 In the comparative example shown, the metal pads 46 near the sidewall of the opening 16a are formed with a high aspect ratio. Therefore, the metal pads 46 may break at the edge of the opening 16a, resulting in poor connection. Furthermore, forming multiple layers such as the metal pads 46 and insulating layers 61a and 61b to expose the metal pads 46 due to the step difference generated by the substrate 16 complicates the process. Additionally, the insulating layers 61a and 61b are, for example, silicon oxide films. Figure 6In the structure shown, it is difficult to form an insulating layer 62 as a protective film on the side of the chip in terms of manufacturing process.

[0081] In contrast, in the first embodiment, the metal pad 46 can be provided along surface F1 (flat surface) within the opening 16a. The metal pad 46 does not need to extend laterally; therefore, it is provided between surface F1 and surface F2 (between surface F3 and surface F4). This suppresses the breakage of the metal pad 46 caused by a high aspect ratio. Furthermore, the insulating layer 61 extends from surface F1 to surface F2 within the opening 16a. That is, the lower surface (surface F1) and upper surface (surface F2) of the insulating layer 61 are respectively provided on the same plane as surfaces F3 and F4 of the substrate 16. Therefore, the metal pad 46 and the insulating layer 61 can be formed more easily without using complex multilayer films. Additionally, the insulating layer 62 can be formed together with the insulating layer 61, making the steps common. As a result, the insulating layer 62 can be formed more easily.

[0082] (Second Implementation)

[0083] Figure 16 This is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment. The second embodiment differs from the first embodiment in that the structure 18 is configured to contact the plug hole 45.

[0084] Compared with the first embodiment Figure 5 In comparison, Figure 16 In the example shown, structure 18 is continuously provided across region A1. Additionally, plug hole 45 is provided in a manner that penetrates structure 18.

[0085] Figure 17 This is a top-view view showing the configuration of the structure 18 and the plug hole 45 in the second embodiment.

[0086] like Figure 17 As shown, the laminate 181 is disposed in contact with the via 45. The insulating layers 181a and 182b are insulators; therefore, even when in contact with the via 45, a short circuit will not occur between the vias 45. Thus, the operation of the control circuit containing the transistor 31 will not be affected. Furthermore, the arrangement area of ​​the structure 18 can be increased, improving the robustness of the structure 18. Additionally, the structure 18 can directly support the via 45, further suppressing the influence of stress on the via 45. As a result, the influence of stress during wire bonding can be further suppressed.

[0087] Furthermore, in the second embodiment, the method described in the first embodiment is not provided. Figure 6 The opening of the structure 18 around the plug hole 45 is shown. Therefore, the stacked body 181 can be formed approximately uniformly, similar to the stacked body 111 of the memory cell array 11. As a result, the structure 18 can be formed more easily than in the first embodiment.

[0088] The other configurations of the semiconductor device in the second embodiment are the same as those of the corresponding configuration of the semiconductor device in the first embodiment; therefore, detailed descriptions thereof are omitted. The semiconductor device in the second embodiment can achieve the same effects as the semiconductor device in the first embodiment.

[0089] (Third Implementation)

[0090] Figure 18 This is a cross-sectional view showing the configuration of the semiconductor device according to the third embodiment. The third embodiment differs from the first embodiment in that the multilayer of the structure 18 does not include a metal layer.

[0091] The structure 18 has a stacked body 182, which is stacked alternately in a manner corresponding to the stacked body 111, and includes a plurality of metal layers 182a and a plurality of insulating layers 182b electrically cut from the plug hole 45. This is because the structure 18 (stacked body 182) is formed approximately simultaneously with the formation step of the memory cell array 11. Therefore, the position and thickness of the metal layer 182a relative to the plane F1 are approximately the same as those of the word line WL. Similarly, the position and thickness of the insulating layer 182b relative to the plane F1 are approximately the same as those of the insulating layer 51.

[0092] Furthermore, the material of metal layer 182a is the same as the material of the word line WL of the laminate 111, for example, tungsten. The strength of tungsten in metal layer 182a is higher than that of silicon oxide in interlayer insulating film 13. As a result, structure 18 has high strength. Additionally, the material of insulating layer 182b is the same as the material of insulating layer 51 in laminate 111. Insulating layer 182b is, for example, a silicon oxide film.

[0093] In the third embodiment, the insulating layer 181a, which serves as a sacrificial layer in the first embodiment, is replaced with a metal layer 182a. Therefore, in the formation step of the memory cell array 11, which also includes the replacement step, the stacked body 182 is formed approximately simultaneously with the memory cell array 11.

[0094] Figure 19 This is a top-view view showing the configuration of the structure 18 and the plug hole 45 in the third embodiment.

[0095] like Figure 19 As shown, the structure 18 is configured not to contact the plugging orifice 45. That is, an interlayer insulating film 13 is provided between the metal layer 182a of the structure 18 and the plugging orifice 45. This suppresses short circuits between the plugging orifices 45. The metal layer 182a is, for example, electrically floating. The structure 18 is formed, for example, by forming an opening around the periphery of the plugging orifice 45.

[0096] The other configurations of the semiconductor device in the third embodiment are the same as those of the corresponding configuration of the semiconductor device in the first embodiment; therefore, detailed descriptions thereof are omitted. The semiconductor device of the third embodiment can achieve the same effects as that of the first embodiment.

[0097] (Fourth implementation)

[0098] Figure 20 This is a cross-sectional view showing the configuration of the semiconductor device according to the fourth embodiment. The fourth embodiment differs from the first embodiment in that the structure 18 is not a laminate.

[0099] exist Figure 20 In the example shown, the structure 18 is a columnar portion 183 provided in a manner corresponding to the columnar portion 112 of the memory cell array 11. The memory cell array 11 has a columnar portion 112 provided along the Z direction in a manner connected to the stack 111. The columnar portion 112 is, for example, Figure 1 The contact plug 22 is shown. However, it is not limited to this; the columnar portion 112 may also be other contact plugs within the memory cell array 11. The structure 18 has a plurality of columnar portions 183 arranged along the Z direction. That is, the columnar portions 183 are arranged in a manner substantially parallel to the columnar portions 112. Figure 19 As shown, the columnar portion 183 differs from the plug hole 45 and is not connected to the wiring layer 44. Therefore, the columnar portion 183 is in an electrically floating state.

[0100] Furthermore, the columnar portion 183 is not limited to metal and can also be an insulator. In this case, the material of the columnar portion 112, which is formed approximately simultaneously with the columnar portion 183, can be, for example, the same as... Figure 1 The columnar portion CL shown is made of the same material as the columnar portion provided to support the stepped structure portion 21 when replaced. Furthermore, the structure 18 does not necessarily have to be formed using the steps for forming the memory cell array 11. The columnar portion 183 may, for example, be formed as a sturdy columnar portion, different from the memory cell array 11.

[0101] The other configurations of the semiconductor device in the fourth embodiment are the same as those of the corresponding configuration of the semiconductor device in the first embodiment, therefore, detailed descriptions are omitted. The semiconductor device in the fourth embodiment can achieve the same effects as the first embodiment. Furthermore, the semiconductor devices of the first to third embodiments and the fourth embodiment can be combined. In this case, the structure 18 may have both laminates 181 and 182 and columnar portions 183.

[0102] (5th embodiment)

[0103] Figure 21 This is a cross-sectional view showing the configuration of the semiconductor device according to the fifth embodiment. (e.g.) Figure 21As shown, unlike the first embodiment, the array chip 1 has a pad opening P in the insulating layer of the interlayer insulating film 13, and the pad 46 is disposed on the interlayer insulating film 13.

[0104] Figure 21 and Figure 5 Compared to the configuration shown, Figure 5 The substrate 16 shown was completely removed. Additionally, in Figure 21 In the middle, the insulating layer 61 covers the upper surface of the interlayer insulating film 13.

[0105] like Figure 21 As shown, the array chip 1 includes a metal pad 46, a via 45, a structure 18, and insulating layers 61 and 62.

[0106] An insulating layer 61 is disposed on the opposite side of the bonding surface (joint surface) S of the circuit chip 2. Furthermore, the insulating layer 61 includes a surface F1 and a surface F2 opposite to surface F1. Surface F1 is the surface facing the bonding surface S, and a memory cell array 11 is disposed between surface F1 and the bonding surface S. Additionally, the insulating layer 61 also includes a pad opening P in region A1 extending from surface F2 to surface F1. As explained below, region A1 is the region where wiring is formed by wire bonding WB.

[0107] Metal pad 46 is disposed within the pad opening P. Furthermore, the metal pad 46 is electrically connected in region A1 via wire bonding WB. Figure 21 In the example shown, two metal pads 46 are provided. However, the number of metal pads 46 is not limited to this. The material of the metal pads 46 is, for example, aluminum (Al).

[0108] A plug hole 45 is located between surface F1 and mating surface S, and is electrically connected to the metal solder pad 46. Additionally, as... Figure 21 As shown, the via 45 is connected to a transistor 31, which is part of the control circuit. That is, the via 45 is electrically connected to the control circuitry disposed on the circuit chip 2. The via 45 is, for example, connected to the columnar portion 112 of the memory cell array 11 (e.g., Figure 1 The contact plug 22 is formed approximately simultaneously with the contact plug 22. Therefore, the material of the plug hole 45 is the same as the material of the contact plug 22, for example, tungsten. Furthermore, the plug hole 45 is not limited to a columnar portion, but may be a structure with other shapes. This structure may also include a wiring layer or the like connected to the plug hole 45.

[0109] The structure 18 is positioned in region A1 between surface F1 and mating surface S.

[0110] As described above, one method for connecting a semiconductor device to an external mounting substrate or device is known to form wiring for a metal pad 46 by wire bonding (WB). Regarding wire bonding (WB), a load is applied to the metal pad 46 for a certain period of time using a bonding tool such as a solder pin. Therefore, stress is applied to the semiconductor device during wire bonding. Here, as shown in region A1, the insulating layer 61 is removed to provide the metal pad 46 electrically connected to the transistor 31. Therefore, the strength of region A1 is reduced. For example, the memory cell array 11, transistor 31, via 45, or wiring layer disposed directly below or around the pad opening P may be mechanically damaged by stress.

[0111] Therefore, in the fifth embodiment, a structure 18, which functions as a stress-resistant film during wire bonding, is provided directly below the pad opening P. The structure 18 has, for example, a high rigidity or robust construction. This improves load-bearing capacity and impact resistance. Consequently, the effects of stress applied to the semiconductor device during wire bonding can be mitigated.

[0112] exist Figure 21 In the example shown, the construct 18 is a stacked stack corresponding to the stacked stack 111 of the memory cell array 11. Figure 2 As explained, the memory cell array 11 has a stacked body 111, which includes multiple word lines WL (conductive layers) and multiple insulating layers 51 alternately stacked along the Z direction perpendicular to the surface F1. Therefore, the structure 18 has a stacked body 181 containing two types of insulating layers 181a and 181b, which are alternately stacked in a manner corresponding to the stacked body 111. This is because, during the formation step of the memory cell array 11, the structure 18 (stacked body 181) is formed approximately simultaneously with the memory cell array 11. Therefore, the position and thickness of the insulating layer 181a from the surface F1 are approximately the same as those of the word lines WL. Furthermore, the position and thickness of the insulating layer 181b from the surface F1 are approximately the same as those of the insulating layer 51.

[0113] Furthermore, either of the two insulating layers 181a and 181b of the laminate 181 is the same as the insulating layer 51 of the laminate 111. Figure 21 In the example shown, insulating layer 181b is, for example, a silicon oxide film. Therefore, the material of insulating layer 181b is the same as that of insulating layer 51. On the other hand, insulating layer 181a is, for example, a silicon nitride film. Silicon nitride (SiN) has higher strength than silicon oxide (SiO2) of interlayer insulating film 13. As a result, structure 18 has high strength.

[0114] Here, as a method for forming the stacked body 111 of the memory cell array 11, a known method is as follows: the sacrificial layer is selectively removed from the stacked body containing the sacrificial layer and the insulating layer 51, and the resulting cavity is filled with a metal such as tungsten. This sacrificial layer corresponds to the insulating layer 181a. Therefore, in the steps of forming the memory cell array 11 until the sacrificial layer is replaced with the word line WL, the stacked body 181 is formed approximately simultaneously with the memory cell array 11.

[0115] like Figure 21 As shown, the insulating layer 61 is provided in the pad opening P such that at least a portion of the metal pad 46 in region A1 is exposed on the F2 side of the insulating layer 61. The insulating layer 61 is, for example, a silicon oxide film.

[0116] An insulating layer 62 is disposed on the sides of the array chip 1 and the circuit chip 2 to cover the connection portion between the array chip 1 and the circuit chip 2. Figure 21 In the example shown, the metal pads 38 and 41 used to bond the array chip 1 to the circuit chip 2 are exposed from the interlayer insulating films 13 and 14. By covering the metal pads 38 and 41 with the insulating layer 62, contamination of the metal pads 38 and 41 caused by impurities during the manufacturing process can be suppressed. The insulating layer 61 is, for example, a silicon oxide film. More specifically, the material of the insulating layer 62 is the same as that of the insulating layer 61. This is because, as explained below, the insulating layers 61 and 62 are formed together. Furthermore, in... Figure 21 In the diagram, the two insulating layers 61 and 62 are separated by a dotted line. However, as explained below, insulating layers 61 and 62 are integrally formed in a single step. Furthermore, in... Figure 21 In this configuration, the sides of the array chip 1 and circuit chip 2, which are provided with insulating layer 62, correspond to the outer peripheral side of the wafer. On the other hand, in... Figure 21 In the middle, the side opposite to the side where the insulating layer 62 is provided is a continuous arbitrary cross-section.

[0117] Next, the manufacturing method of the semiconductor device according to the fifth embodiment will be described. Figures 22-27 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the fifth embodiment.

[0118] arrive Figure 7 Up to this point, it has been manufactured using the same method as in the first embodiment. Next, as follows... Figure 8 As shown, the array wafer W1 and the circuit wafer W2 are bonded together. That is, the array wafer W1, which has a substrate 16, is bonded to the circuit wafer W2, on which the control circuit for the control memory cell array 11 is formed. Furthermore, as... Figure 22As shown, the substrate 16 is ground by back-side grinding until the interlayer insulating film 13 is exposed. The plug via 45 is exposed on the upper surface of the interlayer insulating film 13. Additionally, the side surfaces Ws of the array wafer W1 and the circuit wafer W2 are ground, for example, by trimming. The side surfaces Ws refer to the outer peripheral side surfaces of the wafers. By grinding the side surfaces Ws, in... Figure 22 In the example shown, the metal pads 38 and 41 (attached pads) at the joint interface are exposed.

[0119] Next, as Figure 23 As shown, an aluminum film 46a is formed on the interlayer insulating film 13. Next, as... Figure 24 As shown, an aluminum film 46a is processed using a photoresist mask to form a metal pad 46 electrically connected to the plug hole 45 in region A1.

[0120] Next, as Figure 25 As shown, an insulating layer 63 is formed covering the interlayer insulating film 13, the metal pads 46, and the side surfaces Ws. Thus, the insulating layer 63 can cover the metal pads 38 and 41 of the bonding interface exposed from the side surfaces Ws, as well as the upper surface and side surfaces of the interlayer insulating film 13, approximately simultaneously. The insulating layer 63 is, for example, a silicon oxide film. For example, TEOS (Tetraethoxysilane) is used to form the insulating layer 63.

[0121] Next, as Figure 26 As shown, the upper surface of the insulating layer 63 is ground using CMP until the thickness of the insulating layer 61 reaches the desired thickness. In the fifth embodiment, unlike the first embodiment, the insulating layer 63 is not separated into insulating layer 61 and insulating layer 62. That is, in the fifth embodiment, both the insulating layer 61 disposed on the interlayer insulating film 13 and the insulating layer 62 disposed on the side surface Ws are formed simultaneously. The insulating layer 62 is disposed on the side surface Ws in such a way that it covers the connection portion between the array wafer W1 and the circuit wafer W2. That is, after the metal pads 38 and 41 are ground by CMP, they remain covered by the insulating layer 62.

[0122] Next, as Figure 27 As shown, a passivation film 47 is formed on the upper surface of the insulating layer 61, i.e., surface F2. For example, a thick-film resist such as PI (Polyimide) is coated, followed by exposure, development, and RIE processing. This forms an opening P that exposes the metal solder pad 46. Subsequently, it is monolithically processed, thereby... Figure 21 The semiconductor device is completed.

[0123] As described above, according to the fifth embodiment, the metal solder pad 46 is disposed within the solder pad opening P of the insulating layer 61 in the wire bonding region A1. Furthermore, the structure 18 is disposed in region A1 between the surface F1 and the mating surface S. The structure 18 has high strength and can suppress the influence of mechanical stress applied to the semiconductor device during wire bonding. Therefore, even when wire bonding is performed on the metal solder pad 46 directly above the plug hole 45, the influence of mechanical stress on the plug hole 45, etc., can be suppressed. In addition, since stress during wire bonding does not need to be considered, the design freedom of semiconductor components or wiring can be increased. Furthermore, after wire bonding, the opening P or the wire bonding area can be covered with a protective film such as polyimide or resin.

[0124] This embodiment includes the following forms.

[0125] A semiconductor device includes: a first chip having a memory cell array; and a second chip connected to the first chip and having a control circuit for controlling the memory cell array.

[0126] The first chip has:

[0127] The first insulating layer is disposed on the opposite side of the bonding surface of the second chip, and includes a first surface, a second surface opposite to the first surface, and a connection terminal area in the first region. The memory cell array is disposed between the first surface and the opposite bonding surface.

[0128] A connection terminal is provided in the connection terminal area with at least a portion exposed.

[0129] The first structure is disposed between the first surface and the mating surface, and is electrically connected to the connecting terminal;

[0130] A second structure is disposed in the first region between the first surface and the mating surface; and

[0131] An interlayer insulating film is disposed between the first laminate and the first structure;

[0132] The second structure and the interlayer insulating film are made of different materials.

[0133] The connection terminal electrically connects the external power supply to the first chip.

[0134] The storage cell array has:

[0135] The first laminate comprises a plurality of conductive layers and a plurality of insulating layers alternately laminated along a first direction perpendicular to the first surface; and

[0136] The first columnar portion is disposed along the first direction in a manner that connects it to the first laminate;

[0137] The second structure has a plurality of second columnar portions arranged along the first direction.

[0138] Several embodiments of the present invention have been described, but these embodiments are merely examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device, characterized by It comprises: a first chip having a memory cell array; and a second chip connected to the first chip and having a control circuit for controlling the memory cell array; The first chip has: The first insulating layer is disposed on the opposite side of the bonding surface of the second chip, and includes a first surface, a second surface opposite to the first surface, and a connection terminal area in the first region. The memory cell array is disposed between the first surface and the opposite bonding surface. A connection terminal is provided in the connection terminal area with at least a portion exposed. The first structure is disposed between the first surface and the mating surface, and is electrically connected to the connecting terminal; A second structure is disposed in the first region between the first surface and the mating surface; and An interlayer insulating film is disposed between the first stack and the first structure, wherein the first stack is present in the memory cell array; The connecting terminal and the second structure have a portion that overlaps when viewed from above. The second structure and the interlayer insulating film are made of different materials. The connection terminal electrically connects the external components to the first chip. A plurality of the first structures are disposed below the connection terminal, and a second structure is disposed between the plurality of the first structures. The memory cell array has the first stacked layer, which includes a plurality of conductive layers and a plurality of insulating layers alternately stacked along a first direction perpendicular to the first plane. The second structure has a third laminate, which is stacked alternately in a manner corresponding to the first laminate, and includes multiple metal layers and multiple insulating layers that are insulated from the first structure. It also has a bonding line that connects to the connecting terminal in the first region.

2. The semiconductor device according to claim 1, wherein: The first chip has a first bonding pad located on the bonding surface, and the second chip has a second bonding pad located on the bonding surface. The first bonding pad and the second bonding pad are electrically connected.

3. The semiconductor device according to claim 2, wherein: The first structure is positioned at a location that overlaps with the connecting terminal and the second bonding pad when viewed from above.

4. The semiconductor device according to claim 1, wherein: The first chip further has a substrate disposed on the opposite side of the bonding surface of the second chip, and includes: a third surface on which the memory cell array is disposed between the bonding surface and the opposite surface; a fourth surface on the opposite side of the third surface; and an opening in the first region extending from the fourth surface to the third surface, and having the first insulating layer disposed therein.

5. The semiconductor device according to claim 1, wherein: The material of the metal layer of the third laminate is the same as the material of the conductive layer of the first laminate. The insulating layer of the third laminate is made of the same material as the insulating layer of the first laminate.

6. The semiconductor device according to claim 4, wherein: The first insulating layer extends from the third surface within the opening to the fourth surface.

7. The semiconductor device according to claim 4, wherein: The first chip is disposed within a first wafer, and the second chip is disposed within a second wafer. A second insulating layer is also provided on the sides of the first and second wafers, the second insulating layer being disposed to cover the connection portion between the first and second wafers. The material of the second insulating layer is the same as that of the first insulating layer, and the first insulating layer is disposed in the opening such that at least a portion of the connection terminal in the first region is exposed on the fourth surface side of the substrate.

8. The semiconductor device according to claim 4, characterized in that: The connecting terminal is disposed along the third surface within the opening.

9. The semiconductor device according to claim 4, characterized in that: The connecting terminal is disposed between the third surface and the fourth surface.

10. A method of manufacturing a semiconductor device, characterized by The method comprises the following steps: forming a first stacked body in a memory cell array region on a substrate including a third surface and a fourth surface opposite to the third surface, and forming a first structure and a second structure as a second stacked body in a first region on the third surface; The first wafer having the substrate is joined with the second wafer having a control circuit for controlling the memory cell array. An opening is formed in the first region, extending from the fourth surface of the substrate to the third surface; A connection terminal electrically connected to the first structure is formed within the opening; and A third insulating layer is formed covering the fourth surface of the substrate, the opening, and the side surfaces of the first wafer and the second wafer, and the third insulating layer is polished until the fourth surface of the substrate is exposed, thereby forming the first insulating layer and the second insulating layer in the opening and the side surfaces, respectively. The second structure is formed simultaneously with the formation of the first stacked layer of the memory cell array; A bonding line is also formed in the first region to connect with the connecting terminal.

11. The method for manufacturing a semiconductor device according to claim 10, wherein It also includes the following steps: before forming the third insulating layer, grinding the sides of the first wafer and the second wafer. The first insulating layer and the second insulating layer are formed in the opening and on the side of the connection between the first wafer and the second wafer, respectively, and cover the connection between the first wafer and the second wafer.

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