Display substrate and manufacturing method thereof, and display device

Abstract

The present disclosure provides a display substrate, a method for manufacturing the same, and a display device. The display substrate includes a first electrode, a blocking electrode, and a second electrode sequentially arranged on a substrate. The second electrode is connected to the first electrode via a connecting via. The orthographic projection of the blocking electrode on the substrate at least partially overlaps the orthographic projection of the connecting via on the substrate. The blocking electrode is configured to provide a stepped structure to the hole wall of the connecting via. By providing a blocking electrode, the present disclosure configures the connecting via connecting the first electrode and the second electrode into a stepped structure, thereby improving the quality of film deposition within the via, effectively resolving the low yield rate and other issues of existing manufacturing processes, and improving the yield rate.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, display devices using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] The inventors of the present application have discovered through research that the existing manufacturing processes for OLED or QLED display devices have problems such as low yield. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by the present disclosure is to provide a display substrate and a preparation method thereof, and a display device, so as to solve the problems of low yield rate and the like existing in the existing preparation process.

[0006] The present disclosure provides a display substrate, comprising a first electrode, a blocking electrode, and a second electrode sequentially arranged on a substrate, wherein the second electrode is connected to the first electrode via a connecting via, the orthographic projection of the blocking electrode on the substrate at least partially overlaps with the orthographic projection of the connecting via on the substrate, and the blocking electrode is configured to provide a hole wall of the connecting via with a stepped structure.

[0007] In an exemplary embodiment, the display substrate further includes: a first composite insulating layer disposed between the first electrode and the blocking electrode, and a second composite insulating layer disposed between the blocking electrode and the second electrode; the connecting via includes a first sub-hole, a second sub-hole, and a third sub-hole that are interconnected, the first sub-hole being a via hole disposed on the first composite insulating layer, the second sub-hole being a via hole disposed on the blocking electrode, and the third sub-hole being a via hole disposed on the second composite insulating layer.

[0008] In an exemplary embodiment, the orthographic projection of the first sub-aperture on the substrate is within the range of the orthographic projection of the second sub-aperture on the substrate, and the orthographic projection of the second sub-aperture on the substrate is within the range of the orthographic projection of the third sub-aperture on the substrate.

[0009] In an exemplary embodiment, a step is formed at a junction of the second sub-hole and the third sub-hole, and the third sub-hole exposes a surface of the second sub-hole and the blocking electrode away from the substrate.

[0010] In an exemplary embodiment, in a plane perpendicular to the substrate, the cross-sectional shapes of the first sub-hole, the second sub-hole, and the third sub-hole are inverted trapezoidal shapes.

[0011] In an exemplary embodiment, the third sub-hole has a greater wall slope angle than the first sub-hole, which is greater than the second sub-hole. The wall slope angle is the angle between the inner wall of the hole and the base plane.

[0012] In an exemplary embodiment, the slope angle of the hole wall of the first sub-hole is 55° to 75°.

[0013] In an exemplary embodiment, the slope angle of the hole wall of the second sub-hole is 25° to 45°.

[0014] In an exemplary embodiment, the slope angle of the hole wall of the third sub-hole is 55° to 80°.

[0015] In an exemplary embodiment, in a plane parallel to the substrate, the blocking electrode has a circular ring shape, an elliptical ring shape, a rectangular ring shape, a pentagonal ring shape, or a hexagonal ring shape.

[0016] In an exemplary embodiment, in a plane perpendicular to the substrate, the cross-sectional shape of the blocking electrode is trapezoidal, and the side slope angle of the blocking electrode located outside the ring is 25° to 45°, and the side slope angle is the angle between the side of the blocking electrode and the substrate plane.

[0017] In an exemplary embodiment, the display substrate includes a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a fourth conductive layer sequentially arranged on a base, the first electrode is arranged in the first conductive layer, the second electrode is arranged in the fourth conductive layer, and the blocking electrode is arranged in the second conductive layer and / or the third conductive layer.

[0018] In an exemplary embodiment, the first electrode is a shielding electrode, and the second electrode is a source electrode of a transistor.

[0019] The present disclosure also provides a display device, comprising the aforementioned display substrate.

[0020] The present disclosure also provides a method for preparing a display substrate, comprising:

[0021] A first electrode, a blocking electrode, and a second electrode are sequentially formed on a substrate, the second electrode being connected to the first electrode through a connecting via, the orthographic projection of the blocking electrode on the substrate at least partially overlapping with the orthographic projection of the connecting via on the substrate, and the blocking electrode being configured to make the hole wall of the connecting via a step structure.

[0022] The exemplary embodiments of the present disclosure disclose a display substrate, a method for preparing the same, and a display device. By setting a blocking electrode, the connecting via hole connecting the first electrode and the second electrode is set into a step structure, thereby improving the quality of film deposition in the via hole, effectively solving the problem of low yield rate in the existing preparation process, and improving the yield rate.

[0023] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0025] Figure 1 is a structural schematic diagram of a display device;

[0026] Figure 2 A schematic diagram of the planar structure of a display substrate;

[0027] Figure 3 A schematic diagram of the cross-sectional structure of a display substrate;

[0028] Figure 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0029] Figure 5 This is a working timing diagram of a pixel driving circuit;

[0030] Figure 6 A schematic cross-sectional structure diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0031] Figure 7 This is a schematic diagram of an exemplary embodiment of the present disclosure after forming a first conductive layer pattern;

[0032] Figure 8This is a schematic diagram of an exemplary embodiment of the present disclosure after a semiconductor pattern is formed;

[0033] Figure 9 This is a schematic diagram of an exemplary embodiment of the present disclosure after forming a second conductive layer pattern;

[0034] Figure 10 A schematic diagram of a planar structure of a blocking electrode according to an exemplary embodiment of the present disclosure;

[0035] Figure 11 is a schematic cross-sectional structure diagram of a blocking electrode according to an exemplary embodiment of the present disclosure;

[0036] Figure 12 This is a schematic diagram of an exemplary embodiment of the present disclosure after forming a third conductive layer pattern;

[0037] Figure 13 This is a schematic diagram of an exemplary embodiment of the present disclosure after forming a fourth insulation layer pattern;

[0038] Figure 14 is a schematic cross-sectional structural diagram of a third via hole according to an exemplary embodiment of the present disclosure;

[0039] Figure 15 This is a schematic diagram of an exemplary embodiment of the present disclosure after forming a fourth conductive layer pattern;

[0040] Figure 16 This is a schematic structural diagram of a source electrode connected to a shielding electrode according to an exemplary embodiment of the present disclosure;

[0041] Figure 17 is a schematic cross-sectional structure diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0042] Figure 18 is a schematic cross-sectional structure diagram of another third via hole according to an exemplary embodiment of the present disclosure;

[0043] Figure 19 is a schematic cross-sectional structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0044] Figure 20 FIG. 4 is a schematic cross-sectional structure diagram of another third via hole according to an exemplary embodiment of the present disclosure.

[0045] Description of the accompanying drawings:

[0046] 10—substrate; 11—first insulating layer; 12—second insulating layer;

[0047] 13—third insulating layer; 14—fourth insulating layer; 21—shielding electrode;

[0048] 22—active layer; 23—gate electrode; 24—source electrode;

[0049] 25—drain electrode; 30—blocking electrode; 30A—first blocking electrode;

[0050] 30B—second blocking electrode; 31—first side; 32—second side;

[0051] 41—first electrode plate; 42—second electrode plate; 51—first sublayer;

[0052] 52—second sublayer; 53—third sublayer; 101—transistor;

[0053] 101A—storage capacitor; 102—driving circuit layer; 103—light-emitting structure layer;

[0054] 104—encapsulation structure layer; 301—anode; 302—pixel definition layer;

[0055] 303—organic light-emitting layer; 304—cathode; 401—first encapsulation layer;

[0056] 401—second encapsulation layer; 403—third encapsulation layer. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0058] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0059] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0060] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0061] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0062] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0063] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0064] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0065] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0066] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0067] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0068] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0069] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0070] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, a display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver, respectively. The data driver is connected to a plurality of data signal lines (D1 to Dn), the scan driver is connected to a plurality of scan signal lines (S1 to Sm), and the light-emitting driver is connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include at least one scan signal line, at least one data signal line, at least one light-emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel row basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register and may generate an emission signal in a manner such that an emission stop signal provided in the form of an off-level pulse is sequentially transmitted to a next-stage circuit under the control of a clock signal. o may be a natural number.

[0071] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, a display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and a third subpixel P3 that emits a third color light. The first subpixel P1, the second subpixel P2, and the third subpixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to the pixel driving circuit of the subpixel. The light-emitting devices are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the subpixel.

[0072] In an exemplary embodiment, the first subpixel P1 may be a red subpixel emitting red (R) light, the second subpixel P2 may be a blue subpixel emitting blue (B) light, and the third subpixel P3 may be a green subpixel emitting green (G) light. In an exemplary embodiment, the subpixels in a pixel unit may be rectangular, diamond, pentagonal, or hexagonal, and may be arranged horizontally, vertically, or in a triangular pattern.

[0073] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, a square arrangement, or a diamond arrangement, etc., which is not limited in the present disclosure.

[0074] Figure 3 This is a schematic diagram of the cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. Figure 3 As shown, in a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 10, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 10, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 10. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in this disclosure.

[0075] In an exemplary embodiment, the substrate 10 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit. Figure 3In the figure, only a pixel driving circuit including a transistor 101 and a storage capacitor 101A is used as an example. The light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303 and a cathode 304. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via, the organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of corresponding color under the drive of the anode 301 and the cathode 304. The encapsulation structure layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402 and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0076] In an exemplary embodiment, the organic light-emitting layer 303 may include a light-emitting layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking electrode (EBL), a hole blocking electrode (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking electrode, hole blocking electrode, electron transport layer, and electron injection layer of all sub-pixels may be a common layer connected together, and the light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0077] Figure 4 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure. Figure 4 As shown, the pixel driving circuit may include 7 transistors (transistor T1 to seventh transistor T7), 1 storage capacitor C, and the pixel driving circuit may be connected to 7 signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light-emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS).

[0078] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, the second node N2 is respectively connected to the second electrode of the transistor, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and the second end of the storage capacitor C, and the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6.

[0079] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .

[0080] The control electrode of the transistor T1 is connected to the second scan signal line S2, the first electrode of the transistor T1 is connected to the initialization signal line INIT, and the second electrode of the transistor is connected to the second node N2. When an on-level scan signal is applied to the second scan signal line S2, the transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3, thereby initializing the charge amount of the control electrode of the third transistor T3.

[0081] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0082] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between the control electrode and the first electrode.

[0083] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When an on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D to the pixel driving circuit.

[0084] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When an on-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power line VDD and the second power line VSS, causing the light-emitting device to emit light.

[0085] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initialization signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When the on-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting device to initialize or release the charge accumulated in the first electrode of the light-emitting device.

[0086] In an exemplary embodiment, the second electrode of the light-emitting device is connected to a second power line VSS. The signal on the second power line VSS is a low-level signal, while the signal on the first power line VDD is a continuously high-level signal. The first scan signal line S1 is a scan signal line in the pixel driving circuit of the current display row, and the second scan signal line S2 is a scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n-1). The second scan signal line S2 of the current display row is the same as the first scan signal line S1 in the pixel driving circuit of the previous display row. This can reduce the number of signal lines on the display panel and achieve a narrow bezel on the display panel.

[0087] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the transistors T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0088] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is made of oxide (Oxide). Low-temperature polysilicon thin film transistors have advantages such as high mobility and fast charging, while oxide thin film transistors have advantages such as low leakage current. In an exemplary embodiment, low-temperature polysilicon thin film transistors and oxide thin film transistors can be integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, which can take advantage of the advantages of both, achieve high resolution (Pixel Per Inch, PPI), low-frequency driving, reduce power consumption, and improve display quality.

[0089] In an exemplary embodiment, the first and second scan signal lines S1 and S2 , the emission signal line E, and the initial signal line INIT may extend in a horizontal direction, and the second and first power lines VSS and VDD and the data signal line D may extend in a vertical direction.

[0090] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0091] Figure 5 This is a working timing diagram of a pixel driving circuit. Figure 4 The operation process of the pixel driving circuit of the example illustrates an exemplary embodiment of the present disclosure. Figure 4 The pixel driving circuit includes 7 transistors (transistor T1 to the seventh transistor T7) and 1 storage capacitor C, and all the 7 transistors are P-type transistors.

[0092] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0093] The first phase A1, known as the reset phase, is characterized by a low-level signal on the second scan signal line S2, and a high-level signal on the first scan signal line S1 and the light-emitting signal line E. The low-level signal on the second scan signal line S2 turns on transistor T1, and the signal on the initialization signal line INIT is supplied to the second node N2, initializing the storage capacitor C and clearing the existing data voltage in the storage capacitor. The high-level signals on the first scan signal line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this phase, the OLED does not emit light.

[0094] In the second phase A2, also known as the data writing phase or threshold compensation phase, the signal on the first scan signal line S1 is a low-level signal, the signals on the second scan signal line S2 and the light-emitting signal line E are high-level signals, and the data signal line D outputs a data voltage. During this phase, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The low-level signal on the first scan signal line S1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The conduction of the second transistor T2 and the fourth transistor T4 causes the data voltage output by the data signal line D to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is then charged into the storage capacitor C. The voltage at the second end of the storage capacitor C (the second node N2) is Vd-|Vth|, where Vd is the data voltage output by the data signal line D and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, so that the initial voltage of the initialization signal line INIT is supplied to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED and clearing the pre-stored voltage within it, completing the initialization and ensuring that the OLED does not emit light. The signal of the second scanning signal line S2 is a high-level signal, turning off the transistor T1. The signal of the light-emitting signal line E is a high-level signal, turning off the fifth transistor T5 and the sixth transistor T6.

[0095] In the third phase A3, known as the light-emitting phase, the signal on the light-emitting signal line E is a low-level signal, while the signals on the first scan signal line S1 and the second scan signal line S2 are high-level signals. The low-level signal on the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0096] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0097] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0098] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0099] The inventors of this application have found that the existing preparation process has problems such as low yield, which is to a certain extent caused by the large depth of the via hole connecting the two electrodes. For example, for a dual-gate structure transistor with a shielding electrode, since the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer are provided between the source electrode and the shielding electrode, the via hole connecting the source electrode and the shielding electrode is a deep hole. Due to the large depth of the via hole, the via hole depth is about greater than 1μm, and the slope angle of the via hole sidewall is large, about 75° to 85°, which makes the deposition effect of the conductive material in the via hole poor, resulting in a reduced yield. The inventors of this application have further found that for the first source and drain metal layer of the three-layer structure, the poor deposition effect is mainly reflected in the following aspects: (1) the top layer deposited in the deep hole cannot completely cover the middle layer, and there is a risk of oxidation and corrosion due to the exposure of the middle layer, resulting in unqualified display substrates; (2) the thickness of the middle layer on the side wall and the bottom of the deep hole is small, and there is a risk of puncture due to burrs in the hole, resulting in unqualified display substrates.

[0100] To address issues such as low yield rates in existing manufacturing processes, exemplary embodiments of the present disclosure provide a display substrate. In exemplary embodiments, the display substrate may include a first electrode, a blocking electrode, and a second electrode sequentially disposed on a substrate. The second electrode is connected to the first electrode via a connecting via. The orthographic projection of the blocking electrode on the substrate at least partially overlaps the orthographic projection of the connecting via on the substrate. The blocking electrode is configured to provide a stepped structure on the wall of the connecting via. By forming a stepped structure in the connecting via, exemplary embodiments of the present disclosure improve the quality of film deposition within the via, effectively addressing issues such as low yield rates in existing manufacturing processes and improving the yield rate.

[0101] Figure 6 FIG. 1 is a schematic cross-sectional view of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a transistor and a storage capacitor. Figure 6 As shown, in a plane perpendicular to the display substrate, the display substrate may include a base 10 and a first conductive layer, a first insulating layer 11, a semiconductor layer, a second insulating layer 12, a second conductive layer, a third insulating layer 13, a third conductive layer, a fourth insulating layer 14, and a fourth conductive layer sequentially disposed on the base 10. The first conductive layer may include a shielding electrode 21 serving as a first electrode of the present disclosure, the semiconductor layer may include an active layer 22, the second conductive layer may include a gate electrode 23, a blocking electrode 30, and a first electrode plate 41, the third conductive layer may include a second electrode plate 42, and the fourth conductive layer may include a drain electrode 25 and a source electrode 24 serving as a second electrode of the present disclosure. The source electrode 24 may be connected to the active layer 22 and the shielding electrode 21 via a first via and a third via, respectively, and the drain electrode 25 may be connected to the active layer 22 via a second via.

[0102] In an exemplary embodiment, a first insulating layer 11 and a second insulating layer 12 are arranged between the blocking electrode 30 and the shielding electrode 21 serving as the first electrode. The first insulating layer 11 and the second insulating layer 12 can serve as the first composite insulating layer of the present disclosure. A third insulating layer 13 and a fourth insulating layer 14 are arranged between the blocking electrode 30 and the source electrode 24 serving as the second electrode. The third insulating layer 13 and the fourth insulating layer 14 can serve as the second composite insulating layer of the present disclosure. The third via connecting the source electrode 24 and the shielding electrode 21 can serve as the connecting via of the present disclosure.

[0103] In an exemplary embodiment, the third via hole connecting the source electrode 24 and the blocking electrode 21 may include a first sub-hole, a second sub-hole, and a third sub-hole that are interconnected, the first sub-hole being a via hole that passes through the first insulating layer 11 and the second insulating layer 12, the second sub-hole being a via hole arranged on the blocking electrode 30, and the third sub-hole being a via hole that passes through the third insulating layer 13 and the fourth insulating layer 14.

[0104] In an exemplary embodiment, the orthographic projection of the first sub-hole on the substrate may be within the range of the orthographic projection of the second sub-hole on the substrate, and the orthographic projection of the second sub-hole on the substrate may be within the range of the orthographic projection of the third sub-hole on the substrate.

[0105] In an exemplary embodiment, a step is formed at the junction of the second sub-hole and the third sub-hole, and the third sub-hole exposes the second sub-hole and a surface of the barrier electrode 30 away from the substrate.

[0106] In an exemplary embodiment, in a plane perpendicular to the substrate, the cross-sectional shapes of the first sub-hole, the second sub-hole, and the third sub-hole may be inverted trapezoids.

[0107] In an exemplary embodiment, in a plane parallel to the substrate, the shape of the barrier electrode 30 may be a circular ring, an elliptical ring, a rectangular ring, a pentagonal ring, or a hexagonal ring.

[0108] In an exemplary embodiment, the cross-sectional shape of the barrier electrode 30 in a plane perpendicular to the substrate may be a trapezoidal shape.

[0109] In an exemplary embodiment, the fourth conductive layer may have a multilayer composite structure including a stacked first sublayer, a second sublayer, and a third sublayer. In an exemplary embodiment, the first and third sublayers may be made of titanium (Ti), and the second sublayer may be made of aluminum (Al), forming a Ti / Al / Ti three-layer structure with a bottom and top layer of titanium and a middle layer of aluminum.

[0110] In an exemplary embodiment, the blocking electrode 30 is disposed in the same layer as the gate electrode 23 of the transistor and is formed simultaneously through the same patterning process.

[0111] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0112] In an exemplary embodiment, a process of preparing a display substrate may include the following operations.

[0113] (1) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive film on the substrate 10, patterning the first conductive film through a patterning process, and forming a first conductive layer pattern disposed on the substrate 10, wherein the first conductive layer pattern includes at least a shielding electrode 21, such as Figure 7 shown.

[0114] In the exemplary embodiment, the shielding electrode 21 is configured to serve as a shielding electrode of a transistor on the one hand, and as a gate of a lower transistor on the other hand.

[0115] In an exemplary embodiment, the first conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, etc. The first conductive layer can be called a shielding (LS) layer.

[0116] (2) Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: depositing a first insulating film and a semiconductor film in sequence on a substrate having the aforementioned pattern formed thereon, patterning the semiconductor film through a patterning process to form a first insulating layer 11 covering the first conductive layer pattern, and a semiconductor layer pattern disposed on the first insulating layer 11, wherein the semiconductor layer pattern includes at least an active layer 22, the position of the active layer 22 corresponds to the position of the shielding electrode 21, and the orthographic projection of the active layer 22 on the substrate is within the range of the orthographic projection of the shielding electrode 21 on the substrate, such as Figure 8 shown.

[0117] In exemplary embodiments, the semiconductor thin film may be made of single crystal silicon, polycrystalline silicon, or oxide, which is not limited in the present disclosure.

[0118] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second insulating film and a second conductive film in sequence on the substrate having the aforementioned pattern, patterning the second conductive film through a patterning process to form a second insulating layer 12 covering the semiconductor layer pattern, and a second conductive layer pattern disposed on the second insulating layer 12, such as Figure 9 shown.

[0119] In exemplary embodiments, the second conductive layer pattern includes at least the gate electrode 23 , the barrier electrode 30 , and the first electrode 41 .

[0120] In an exemplary embodiment, the position of the gate electrode 23 corresponds to the position of the active layer 22 , and the orthographic projection of the gate electrode 23 on the substrate is within the range of the orthographic projection of the active layer 22 on the substrate.

[0121] In an exemplary embodiment, the position of the blocking electrode 30 corresponds to the position of a third via hole to be formed subsequently. The orthographic projection of the blocking electrode 30 on the substrate is within the range of the orthographic projection of the shielding electrode 21 on the substrate. The orthographic projection of the blocking electrode 30 on the substrate does not overlap with the orthographic projection of the active layer 22 on the substrate. In an exemplary embodiment, the third via hole is a via hole connecting the source electrode and the shielding electrode.

[0122] In an exemplary embodiment, the first electrode plate 41 is disposed on a side of the second insulating layer 12 away from the substrate, and the first electrode plate 41 is configured to serve as a plate of a storage capacitor in the pixel driving circuit.

[0123] Figure 10 FIG. 1 is a schematic diagram of a planar structure of a blocking electrode according to an exemplary embodiment of the present disclosure. Figure 10 As shown, in an exemplary embodiment, in a plane parallel to the substrate, the blocking electrode 30 may be in the shape of a circular ring. In some possible embodiments, the blocking electrode 30 may also be in the shape of an elliptical ring, a rectangular ring, a pentagonal ring, or a hexagonal ring.

[0124] Figure 11 FIG. 1 is a schematic diagram of a cross-sectional structure of a blocking electrode according to an exemplary embodiment of the present disclosure. Figure 11 As shown, in an exemplary embodiment, the cross-sectional shape of the barrier electrode 30 in a plane perpendicular to the substrate may be a trapezoidal shape.

[0125] In an exemplary embodiment, the trapezoidal blocking electrode 30 may include a lower side close to the substrate, an upper side away from the substrate, and side edges between the lower and upper sides, and the side edges may include a first side edge 31 located inside the ring and a second side edge 32 located outside the ring.

[0126] In an exemplary embodiment, a dry etching process can be used to form a second conductive layer pattern, so that the side slope angle α of the first side 31 can be approximately 25° to 45°, and the side slope angle α can be the angle between the side of the blocking electrode 30 and the substrate plane. The side slope angle α is configured to control the hole wall slope angle of the subsequently formed third via hole.

[0127] In an exemplary embodiment, the side slope angle α of the first side 31 may be approximately 30° to 40°. For example, the side slope angle α may be approximately 35°.

[0128] In an exemplary embodiment, the side slope angle of the second side 32 may be the same as or similar to the side slope angle α of the first side 31 .

[0129] In an exemplary embodiment, the second conductive layer may be made of a metal material, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo). The second conductive layer may be referred to as a first gate metal (GATE1) layer. For example, the second conductive layer may be made of molybdenum.

[0130] In an exemplary embodiment, after this patterning process, the semiconductor layer can be conductorized by utilizing the shielding of the second conductive layer. The semiconductor layer not shielded by the second conductive layer is conductorized to form a conductorized source region and a conductorized drain region. The source region and the drain region are configured to connect to the source electrode and the drain electrode formed subsequently.

[0131] In some possible implementations, this process can simultaneously pattern the second insulating film and the second conductive film through a patterning process, so that the patterns of the second conductive layer and the second insulating layer are substantially the same, which is not limited in the present disclosure.

[0132] (4) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third insulating film and a third conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the third conductive film through a patterning process to form a third insulating layer 13 covering the second conductive layer pattern, and a third conductive layer pattern disposed on the third insulating layer 13, such as Figure 12 shown.

[0133] In an exemplary embodiment, the third conductive layer pattern includes at least a second electrode plate 42 , the position of the second electrode plate 42 corresponds to the position of the first electrode plate 41 , and the orthographic projection of the second electrode plate 42 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 41 on the substrate.

[0134] In an exemplary embodiment, the second plate 42 is disposed on a side of the third insulating layer 13 away from the substrate. The second plate 42 is configured to serve as another plate of a storage capacitor in the pixel driving circuit. The first plate 41 and the second plate 42 constitute a storage capacitor of the pixel driving circuit.

[0135] In an exemplary embodiment, the third conductive layer may be made of a metal material, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo). The third conductive layer may be referred to as a second gate metal (GATE2) layer. For example, the third conductive layer may be made of molybdenum.

[0136] In some possible implementations, this process may simultaneously pattern the third insulating film and the third conductive film through a patterning process, so that the patterns of the third conductive layer and the third insulating layer are substantially the same, which is not limited in the present disclosure.

[0137] (5) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film through a patterning process, and forming a fourth insulating layer 14 pattern covering the third conductive layer pattern, such as Figure 13 shown.

[0138] In an exemplary embodiment, the fourth insulation layer 14 pattern includes at least a first via hole K1 , a second via hole K2 , and a third via hole K3 .

[0139] In an exemplary embodiment, the orthographic projection of the first via K1 on the substrate can be located within the range of the orthographic projection of the source region of the active layer 22 on the substrate, and the fourth insulating layer 14, the third insulating layer 13 and the second insulating layer 12 in the first via K1 are etched away to expose the surface of the source region of the active layer 22. The first via K1 is configured to connect a subsequently formed source electrode to the source region of the active layer 22 through the via.

[0140] In an exemplary embodiment, the orthographic projection of the second via K2 on the substrate can be located within the range of the orthographic projection of the drain region of the active layer 22 on the substrate, and the fourth insulating layer 14, the third insulating layer 13 and the second insulating layer 12 in the second via K2 are etched away to expose the surface of the drain region of the active layer 22, and the second via K2 is configured to connect a subsequently formed drain electrode to the drain region of the active layer 22 through the via.

[0141] In an exemplary embodiment, the orthographic projection of the third via K3 on the substrate can be located within the range of the orthographic projection of the blocking electrode 21 on the substrate, and the fourth insulating layer 14, the third insulating layer 13, the second insulating layer 12 and the first insulating layer 11 in the third via K3 are etched away to expose the surface of the blocking electrode 21, and the third via K3 is configured to connect the subsequently formed source electrode to the blocking electrode 21 through the via.

[0142] Figure 14 FIG. 1 is a schematic cross-sectional view of a third via hole according to an exemplary embodiment of the present disclosure. Figure 14 As shown, in a plane perpendicular to the substrate, the third via hole may include a first sub-hole K11, a second sub-hole K12 and a third sub-hole K13 that are interconnected, and the first sub-hole K11, the second sub-hole K12 and the third sub-hole K13 constitute a third via hole with a stepped structure.

[0143] In an exemplary embodiment, the first sub-hole K11 can be a via hole opened on the second insulating layer 12 and the first insulating layer 11. The second insulating layer 12 and the first insulating layer 11 in the first sub-hole K11 are etched away to expose the surface of the blocking electrode 21. The first insulating layer 11 and the second insulating layer 12 can serve as the first composite insulating layer of this exemplary embodiment.

[0144] In an exemplary embodiment, the second sub-hole K12 may be a via hole provided on the blocking electrode 30 , the second sub-hole K12 exposes the first sub-hole K11 , and the orthographic projection of the first sub-hole K11 on the substrate may be within the range of the orthographic projection of the second sub-hole K12 on the substrate.

[0145] In an exemplary embodiment, the third sub-hole K13 can be a via hole opened on the fourth insulating layer 14 and the third insulating layer 13. The fourth insulating layer 14 and the third insulating layer 13 in the third sub-hole K13 are etched away, exposing the second sub-hole K12 and a portion of the surface of the blocking electrode 30 away from the substrate. The orthographic projection of the second sub-hole K12 on the substrate can be located within the range of the orthographic projection of the third sub-hole K13 on the substrate. The third insulating layer 13 and the fourth insulating layer 14 can serve as the second composite insulating layer of this exemplary embodiment.

[0146] In an exemplary embodiment, a step is formed at the junction of the second sub-hole K12 and the third sub-hole K13, and the third sub-hole K13 exposes the second sub-hole K12 and the surface of the blocking electrode 30 away from the substrate, that is, the step in the step structure is the surface of the blocking electrode 30 away from the substrate.

[0147] In an exemplary embodiment, in a plane perpendicular to the substrate, the cross-sectional shape of the first sub-hole K11 may be an inverted trapezoid, and the first hole wall slope angle θ1 of the hole wall of the first sub-hole K11 may be approximately 55° to 75°.

[0148] In an exemplary embodiment, in a plane perpendicular to the substrate, the cross-sectional shape of the second sub-hole K12 may be an inverted trapezoid, the hole wall of the second sub-hole K12 is the first side 31 of the blocking electrode 30, and the second hole wall slope angle θ2 of the hole wall of the second sub-hole K12 is the side slope angle α of the first side 31 of the blocking electrode 30. The second hole wall slope angle θ2 may be approximately 25° to 45°.

[0149] In an exemplary embodiment, the cross-sectional shape of the third sub-hole K13 in a plane perpendicular to the substrate may be an inverted trapezoid, and a third hole wall slope angle θ3 of the hole wall of the third sub-hole K13 may be approximately 55° to 80°.

[0150] In an exemplary embodiment, the hole wall slope angle may be an angle between an inner wall of the hole and a base plane.

[0151] In an exemplary embodiment, the third hole wall slope angle θ3 may be greater than the first hole wall slope angle θ1 , and the first hole wall slope angle θ1 may be greater than the second hole wall slope angle θ2 .

[0152] In an exemplary embodiment, the first hole wall slope angle θ1 may be approximately 55° to 70°. For example, the first hole wall slope angle θ1 may be approximately 60°.

[0153] In an exemplary embodiment, the second hole wall slope angle θ2 may be approximately 30° to 40°. For example, the second hole wall slope angle θ2 may be approximately 35°.

[0154] In an exemplary embodiment, the third hole wall slope angle θ3 may be approximately 60° to 80°. For example, the third hole wall slope angle θ3 may be approximately 70°.

[0155] In an exemplary embodiment, forming the fourth insulating layer pattern may include depositing a fourth insulating film on the substrate having the aforementioned pattern, applying a layer of photoresist, exposing the photoresist using a conventional mask, and developing the photoresist to form a photoresist pattern. The photoresist pattern includes exposed areas and unexposed areas, where the exposed areas are the areas where the first via K1, the second via K2, and the third via K3 are located. The photoresist in the exposed areas is removed to expose the surface of the fourth insulating film, while the photoresist in the unexposed areas remains. The exposed areas are then etched using a dry etching process to form the first via K1, the second via K2, and the third via K3, respectively. Finally, the remaining photoresist is stripped.

[0156] In an exemplary embodiment, during the formation of the third via hole K3, after etching away the fourth insulating film and the third insulating film, the blocking electrode 30 is exposed, forming a second sub-hole K12 and a third sub-hole K13. The second sub-hole K12 is located within the third sub-hole K13, and the orthographic projection of the second sub-hole K12 on the substrate is within the range of the orthographic projection of the third sub-hole K13 on the substrate. Subsequently, using the blocking electrode 30 as a hard mask, the second insulating layer 12 and the first insulating layer 11 in the second sub-hole K12 that are not blocked by the blocking electrode 30 are etched to form a first sub-hole K11 that exposes the blocking electrode 21. The first sub-hole K11 is located within the second sub-hole K12, and the orthographic projection of the first sub-hole K11 on the substrate is within the range of the orthographic projection of the second sub-hole K12 on the substrate, thereby forming a stepped structure third via hole K3.

[0157] In an exemplary embodiment, because a photoresist is used as a mask during the formation of the third sub-hole K13, the wall of the third sub-hole K13 etched using a dry etching process has a larger wall slope angle. Because the blocking electrode 30 is blocked during the formation of the second sub-hole K12, the extent of etching of the blocking electrode 30 is relatively small. Therefore, the wall slope angle of the second sub-hole K12 is substantially the same as or similar to the side slope angle of the first side 31 of the blocking electrode 30, forming a stepped platform, which is the surface of the blocking electrode 30 facing away from the substrate. Because the first side 31 of the blocking electrode 30 is used as a mask during the formation of the first sub-hole K11, and the side slope angle of the first side 31 is approximately 25° to 45°, the wall slope angle of the etched first sub-hole K11 is approximately 20° to 25° greater than the side slope angle. Therefore, the wall slope angle of the first sub-hole K11 can be approximately 55° to 75°, which is relatively small. Compared with the existing structure, the slope angle of the hole wall of the first sub-hole disclosed in the present invention can be reduced by about 15° to 25°, which is beneficial to the subsequent film deposition quality of the fourth conductive film and improves the yield rate.

[0158] (6) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film through a patterning process, and forming a fourth conductive layer pattern on the fourth insulating layer 14, such as Figure 15 In an exemplary embodiment, the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0159] In an exemplary embodiment, the fourth conductive layer pattern includes at least a source electrode 24 and a drain electrode 25. The source electrode 24 is connected to the source region of the active layer 22 through the first via K1 on the one hand, and is connected to the blocking electrode 21 through the third via K3 on the other hand. The drain electrode 25 is connected to the drain region of the active layer 22 through the second via K2.

[0160] Figure 16 FIG. 1 is a schematic diagram of a structure in which a source electrode and a shielding electrode are connected in an exemplary embodiment of the present disclosure. Figure 16 As shown, in an exemplary embodiment, the fourth conductive layer can adopt a multi-layer composite structure, including a stacked first sublayer 51, a second sublayer 52 and a third sublayer 53, the first sublayer 51 is arranged on the side of the fourth insulating layer 14 away from the substrate, the second sublayer 52 is arranged on the side of the first sublayer 51 away from the substrate, and the third sublayer 53 is arranged on the side of the second sublayer 52 away from the substrate.

[0161] In an exemplary embodiment, the first sub-layer 51 and the third sub-layer 53 may be made of titanium (Ti), and the second sub-layer 52 may be made of aluminum (Al), forming a three-layer structure of Ti / Al / Ti.

[0162] In this exemplary embodiment, because the third via has a stepped structure, which divides the third via into interconnected first, second, and third sub-holes, the deposition of the fourth conductive film is equivalent to depositing it separately in the first, second, and third sub-holes, minimizing the depth of deposition within the holes. In other words, the fourth conductive film is deposited separately in the first sub-hole of the first depth, the second sub-hole of the second depth, and the third sub-hole of the third depth, rather than depositing it in the via with the first, second, and third depths combined. This ensures the thickness of the aluminum layer at the bottom of the via, minimizing the risk of punctures caused by burrs within the hole.

[0163] In an exemplary embodiment, since the third via K3 is a step structure, the overall hole wall slope angle of the third via is effectively reduced, the first sub-layer can better cover the side walls of the first sub-hole, the second sub-hole and the third sub-hole, and the third sub-layer can better cover the aluminum layer, thereby achieving the coverage and encapsulation of the aluminum layer by the titanium layer, and minimizing the risk of oxidation and corrosion caused by the exposure of the aluminum layer.

[0164] At this point, a driving circuit layer including transistors and storage capacitors is formed on the substrate. The storage capacitor may include a first electrode 41 and a second electrode 42. The dual-gate transistor may include a lower transistor and an upper transistor with the same channel. The upper transistor may include an active layer 22, a gate electrode 23, a source electrode 24, and a drain electrode 25. The lower transistor may include an active layer 22, a shielding electrode 21, a source electrode 24, and a drain electrode 25. Since the signal voltage value of the gate (shielding electrode) of the lower transistor is less than the signal voltage value of the gate (gate electrode) of the upper transistor, the negative bias of the threshold voltage of the lower transistor is less than that of the upper transistor, which can reduce the overall negative bias of the transistor, ensure the stability of the transistor, and ensure the uniformity of the electrical characteristics of the transistor.

[0165] The subsequent preparation process may include forming a first planar layer, a second source / drain metal (SD2), a second planar layer, a light emitting structure layer and an encapsulation structure layer, etc., which will not be described in detail here.

[0166] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate. The rigid substrate may be glass or quartz. The flexible substrate may be a single-layer structure or a stacked-layer structure including a flexible material layer. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer may be referred to as a buffer layer, the second insulating layer and the third insulating layer may be referred to as a gate insulating layer (GI), and the fourth insulating layer may be referred to as an interlayer insulating layer (ILD).

[0167] It can be seen from the structure and preparation process of the substrate displayed in the exemplary embodiment of the present disclosure that the exemplary embodiment of the present disclosure sets the third via hole connecting the source electrode and the shielding electrode into a step structure by setting a blocking electrode, thereby reducing the hole wall slope angle of the third via hole as a whole, which not only ensures the thickness of the aluminum layer at the bottom of the via hole and minimizes the risk of puncture due to burrs in the hole, but also ensures the coverage and coating of the aluminum layer by the top titanium layer, minimizes the risk of oxidation and corrosion caused by the exposure of the aluminum layer, improves the film deposition quality in the via hole, effectively solves the problems of low yield in the existing preparation process, and improves the yield.

[0168] The exemplary embodiment of the present disclosure sets a blocking electrode in the second conductive layer. The blocking electrode and the gate electrode are set in the same layer and are formed synchronously through the same patterning process. Not only does no additional patterning process need to be added, but the preparation process is simple and has good process compatibility, which is conducive to ensuring process quality and reducing production costs.

[0169] Figure 17 FIG. 1 is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the present disclosure. Figure 18 FIG. 1 is a schematic cross-sectional view of another third via hole according to an exemplary embodiment of the present disclosure. Figure 17 and Figure 18 As shown, the main structure of the display substrate of this exemplary embodiment is similar to that of the previous embodiment. The display substrate may include a base 10 and a first conductive layer, a first insulating layer 11, a semiconductor layer, a second insulating layer 12, a second conductive layer, a third insulating layer 13, a third conductive layer, a fourth insulating layer 14, and a fourth conductive layer sequentially disposed on the base 10. Unlike the previous exemplary embodiment, the blocking electrode 30 of this exemplary embodiment is disposed in the third conductive layer.

[0170] In an exemplary embodiment, in a plane perpendicular to the substrate, the third via hole may include a first sub-hole K11, a second sub-hole K12, and a third sub-hole K13 connected to each other, which constitute a third via hole of a stepped structure.

[0171] In an exemplary embodiment, the first sub-hole K11 can be a via hole opened on the third insulating layer 13, the second insulating layer 12 and the first insulating layer 11. The third insulating layer 13, the second insulating layer 12 and the first insulating layer 11 in the first sub-hole K11 are etched away to expose the surface of the blocking electrode 21. The first insulating layer 11, the second insulating layer 12 and the third insulating layer 13 can serve as the first composite insulating layer of this exemplary embodiment.

[0172] In an exemplary embodiment, the second sub-hole K12 may be a via hole provided on the blocking electrode 30 , the second sub-hole K12 exposes the first sub-hole K11 , and the orthographic projection of the first sub-hole K11 on the substrate may be within the range of the orthographic projection of the second sub-hole K12 on the substrate.

[0173] In an exemplary embodiment, the third sub-hole K13 can be a via hole opened on the fourth insulating layer 14. The fourth insulating layer 14 in the third sub-hole K13 is etched away, exposing the second sub-hole K12 and a portion of the surface of the blocking electrode 30 away from the substrate. The orthographic projection of the second sub-hole K12 on the substrate can be located within the range of the orthographic projection of the third sub-hole K13 on the substrate. The fourth insulating layer 14 can serve as the second composite insulating layer of this exemplary embodiment.

[0174] In an exemplary embodiment, a step is formed at the junction of the second sub-hole K12 and the third sub-hole K13, and the third sub-hole K13 exposes the second sub-hole K12 and the surface of the blocking electrode 30 away from the substrate, that is, the step in the step structure is the surface of the blocking electrode 30 away from the substrate.

[0175] In an exemplary embodiment, parameters such as the cross-sectional shape and slope angle of the barrier electrode 30 , the first sub-hole K11 , the second sub-hole K12 , and the third sub-hole K13 may be substantially the same as or similar to those of the aforementioned embodiment.

[0176] In this exemplary embodiment, the manufacturing process of the display substrate can be substantially similar to that of the aforementioned embodiment. The difference is that the blocking electrode is not included in the second conductive layer pattern. Instead, the blocking electrode and the second electrode plate are formed simultaneously when forming the third conductive layer pattern. The position of the blocking electrode corresponds to the position of the subsequently formed third via. The orthographic projection of the blocking electrode on the substrate is within the range of the orthographic projection of the shielding electrode on the substrate, and the orthographic projection of the blocking electrode on the substrate does not overlap with the orthographic projection of the active layer on the substrate. When forming the fourth insulating layer pattern, the blocking electrode is used to form the third via with a stepped structure.

[0177] This exemplary embodiment demonstrates that the substrate can also improve the quality of film deposition within the vias, effectively resolving issues such as low yields in existing fabrication processes. Because the blocking electrode and the second plate are placed on the same layer and formed simultaneously through the same patterning process, not only does this eliminate the need for additional patterning steps, but the fabrication process is also simple and offers excellent process compatibility, ensuring process quality and reducing production costs.

[0178] Figure 19 FIG. 1 is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the present disclosure. Figure 20 FIG. 1 is a schematic cross-sectional view of another third via hole according to an exemplary embodiment of the present disclosure. Figure 19 and Figure 20 As shown, the main structure of the display substrate of this exemplary embodiment is similar to that of the previous embodiment. The display substrate may include a base 10 and a first conductive layer, a first insulating layer 11, a semiconductor layer, a second insulating layer 12, a second conductive layer, a third insulating layer 13, a third conductive layer, a fourth insulating layer 14, and a fourth conductive layer sequentially disposed on the base 10. Unlike the previous exemplary embodiment, this exemplary embodiment includes a first blocking electrode 30A disposed in the second conductive layer and a second blocking electrode 30B disposed in the third conductive layer.

[0179] In an exemplary embodiment, in a plane perpendicular to the substrate, the third via hole may include a first sub-hole K11, a second sub-hole K12, a fourth sub-hole K14, a fifth sub-hole K15 and a third sub-hole K13 that are interconnected, and the first sub-hole K11, the second sub-hole K12, the fourth sub-hole K14, the fifth sub-hole K15 and the third sub-hole K13 constitute a third via hole of a step structure.

[0180] In an exemplary embodiment, the first sub-hole K11 can be a via hole opened on the second insulating layer 12 and the first insulating layer 11. The second insulating layer 12 and the first insulating layer 11 in the first sub-hole K11 are etched away to expose the surface of the blocking electrode 21. The first insulating layer 11 and the second insulating layer 12 can serve as the first composite insulating layer of this exemplary embodiment.

[0181] In an exemplary embodiment, the second sub-hole K12 may be a via hole provided on the first barrier electrode 30A. The second sub-hole K12 exposes the first sub-hole K11 . The orthographic projection of the first sub-hole K11 on the substrate may be within the range of the orthographic projection of the second sub-hole K12 on the substrate.

[0182] In an exemplary embodiment, the fourth sub-hole K14 can be a via hole opened on the third insulating layer 13. The third insulating layer 13 in the fourth sub-hole K14 is etched away, exposing the second sub-hole K12 and a portion of the surface of the first blocking electrode 30A away from the substrate. The orthographic projection of the second sub-hole K12 on the substrate can be within the range of the orthographic projection of the fourth sub-hole K14 on the substrate.

[0183] In an exemplary embodiment, the fifth sub-hole K15 may be a via hole provided on the second barrier electrode 30B, the fifth sub-hole K15 exposes the fourth sub-hole K14 , and the orthographic projection of the fourth sub-hole K14 on the substrate may be within the range of the orthographic projection of the fifth sub-hole K15 on the substrate.

[0184] In an exemplary embodiment, the third sub-hole K13 can be a via hole opened on the fourth insulating layer 14. The fourth insulating layer 14 in the third sub-hole K13 is etched away, exposing the fifth sub-hole K15 and a portion of the surface of the second blocking electrode 30B away from the substrate. The orthographic projection of the fifth sub-hole K15 on the substrate can be located within the range of the orthographic projection of the third sub-hole K13 on the substrate. The fourth insulating layer 14 can serve as the second composite insulating layer of this exemplary embodiment.

[0185] In an exemplary embodiment, a step is formed at the junction of the second sub-hole K12 and the fourth sub-hole K14, and the fourth sub-hole K14 exposes the second sub-hole K12 and the surface of the first blocking electrode 30A away from the substrate, that is, one step in the step structure is the surface of the first blocking electrode 30A away from the substrate.

[0186] In an exemplary embodiment, another step is formed at the junction of the fifth sub-hole K15 and the third sub-hole K13, and the third sub-hole K13 exposes the fifth sub-hole K15 and a portion of the surface of the second blocking electrode 30B away from the substrate, that is, another step in the step structure is the surface of the second blocking electrode 30B away from the substrate.

[0187] In an exemplary embodiment, parameters such as the cross-sectional shape and slope angle of the first blocking electrode 30A and the second blocking electrode 30B may be substantially the same as or similar to those of the blocking electrodes in the aforementioned embodiment, and parameters such as the cross-sectional shape and slope angle of the first sub-hole K11, the second sub-hole K12, and the third sub-hole K13 may be substantially the same as or similar to those in the aforementioned embodiment.

[0188] In an exemplary embodiment, in a plane perpendicular to the substrate, the cross-sectional shape of the fourth sub-hole K14 and the fifth sub-hole K15 may be an inverted trapezoid, the fourth hole wall slope angle of the hole wall of the fourth sub-hole K14 may be approximately 55° to 75°, and the fifth hole wall slope angle of the hole wall of the fifth sub-hole K15 may be approximately 25° to 45°.

[0189] In an exemplary embodiment, the fourth hole wall slope angle may be smaller than the third hole wall slope angle, and the fourth hole wall slope angle may be greater than the first hole wall slope angle.

[0190] In an exemplary embodiment, the hole wall of the second sub-hole K12 may be a side edge of the first blocking electrode 30A, and the second hole wall slope angle of the hole wall of the second sub-hole K12 may be the side edge slope angle of the first blocking electrode 30A. The hole wall of the fifth sub-hole K15 may be a side edge of the second blocking electrode 30B, and the fifth hole wall slope angle of the hole wall of the fifth sub-hole K15 may be the side edge slope angle of the second blocking electrode 30B.

[0191] In an exemplary embodiment, the manufacturing process of the display substrate of this exemplary embodiment can be substantially similar to that of the aforementioned embodiment, except that a first blocking electrode is formed in the formed second conductive layer pattern, and a second blocking electrode is formed in the formed third conductive layer pattern. The positions of the first and second blocking electrodes correspond to the positions of the subsequently formed third via holes. The orthographic projections of the first and second blocking electrodes on the substrate are within the range of the orthographic projection of the blocking electrode on the substrate, and the orthographic projections of the first and second blocking electrodes on the substrate do not overlap with the orthographic projection of the active layer on the substrate. During the formation of the fourth insulating layer pattern, the first and second blocking electrodes are used to form a third via hole having a stepped structure.

[0192] This exemplary embodiment demonstrates that the substrate can also improve the quality of film deposition within the vias, effectively resolving issues such as low yields associated with existing fabrication processes. Because the first barrier electrode and gate electrode are co-located and formed simultaneously through the same patterning process, and the second barrier electrode and second plate are co-located and formed through the same patterning process, not only does this eliminate the need for additional patterning steps, but it also simplifies the fabrication process and improves process compatibility, ensuring process quality and reducing production costs.

[0193] The structure and preparation process shown in the exemplary embodiment of the present disclosure are merely exemplary descriptions. The corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit them herein.

[0194] The display substrate disclosed herein can be applied to a display device having a pixel driving circuit, such as OLED, QLED, light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc. It can also be applied to other display devices, such as liquid crystal display, plasma display or electrophoretic display, etc., which are not limited in the present disclosure.

[0195] The present disclosure also provides a method for preparing a display substrate. In an exemplary embodiment, the method may include:

[0196] A first electrode, a blocking electrode, and a second electrode are sequentially formed on a substrate, the second electrode being connected to the first electrode through a connecting via, the orthographic projection of the blocking electrode on the substrate at least partially overlapping with the orthographic projection of the connecting via on the substrate, and the blocking electrode being configured to make the hole wall of the connecting via a step structure.

[0197] The present disclosure also provides a display device comprising the display substrate of the aforementioned embodiment. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0198] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, characterized in that: The invention comprises a first electrode, a blocking electrode, and a second electrode sequentially arranged on a substrate, wherein the second electrode is connected to the first electrode through a connecting via hole, an orthographic projection of the blocking electrode on the substrate at least partially overlaps with an orthographic projection of the connecting via hole on the substrate, and the blocking electrode is configured to make a hole wall of the connecting via hole have a stepped structure; The display substrate further includes: a first composite insulating layer disposed between the first electrode and the blocking electrode, and a second composite insulating layer disposed between the blocking electrode and the second electrode; The connecting via includes a first sub-hole, a second sub-hole, and a third sub-hole that are interconnected, the first sub-hole being a via hole provided on the first composite insulating layer, the second sub-hole being a via hole provided on the blocking electrode, and the third sub-hole being a via hole provided on the second composite insulating layer; The wall slope angle of the third sub-hole is greater than the wall slope angle of the first sub-hole, and the wall slope angle of the first sub-hole is greater than the wall slope angle of the second sub-hole. The wall slope angle is the angle between the inner wall of the hole and the base plane. The slope angle of the hole wall of the first sub-hole is 55° to 75°, the slope angle of the hole wall of the second sub-hole is 25° to 45°, and the slope angle of the hole wall of the third sub-hole is 55° to 80°.

2. The display substrate according to claim 1, wherein: The orthographic projection of the first sub-hole on the substrate is within the range of the orthographic projection of the second sub-hole on the substrate, and the orthographic projection of the second sub-hole on the substrate is within the range of the orthographic projection of the third sub-hole on the substrate.

3. The display substrate according to claim 1, wherein A step is formed at the junction of the second sub-hole and the third sub-hole, and the third sub-hole exposes the second sub-hole and the surface of the blocking electrode away from the substrate.

4. The display substrate according to claim 1, wherein: In a plane perpendicular to the substrate, the cross-sectional shapes of the first sub-hole, the second sub-hole and the third sub-hole are inverted trapezoidal shapes.

5. The display substrate according to claim 1, wherein In a plane parallel to the substrate, the blocking electrode has a circular ring shape, an elliptical ring shape, a rectangular ring shape, a pentagonal ring shape, or a hexagonal ring shape.

6. The display substrate according to claim 5, wherein: In a plane perpendicular to the substrate, the cross-sectional shape of the blocking electrode is trapezoidal, and the side slope angle of the blocking electrode located outside the ring is 25° to 45°, and the side slope angle is the angle between the side of the blocking electrode and the substrate plane.

7. The display substrate according to any one of claims 1 to 6, characterized in that: The display substrate includes a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer and a fourth conductive layer arranged in sequence on a base, the first electrode is arranged in the first conductive layer, the second electrode is arranged in the fourth conductive layer, and the blocking electrode is arranged in the second conductive layer and / or the third conductive layer.

8. The display substrate according to claim 7, wherein: The first electrode is a shielding electrode, and the second electrode is a source electrode of a transistor.

9. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 8.

10. A method for preparing a display substrate, characterized in that: include: forming a first electrode, a blocking electrode, and a second electrode in sequence on a substrate, wherein the second electrode is connected to the first electrode through a connecting via, an orthographic projection of the blocking electrode on the substrate at least partially overlaps with an orthographic projection of the connecting via on the substrate, and the blocking electrode is configured to make a hole wall of the connecting via have a stepped structure; The display substrate further includes: a first composite insulating layer disposed between the first electrode and the blocking electrode, and a second composite insulating layer disposed between the blocking electrode and the second electrode; The connecting via includes a first sub-hole, a second sub-hole and a third sub-hole that are interconnected. The first sub-hole is a via provided on the first composite insulating layer, the second sub-hole is a via provided on the blocking electrode, and the third sub-hole is a via provided on the second composite insulating layer; the hole wall slope angle of the third sub-hole is greater than the hole wall slope angle of the first sub-hole, the hole wall slope angle of the first sub-hole is greater than the hole wall slope angle of the second sub-hole, and the hole wall slope angle is the angle between the inner wall of the hole and the base plane; the hole wall slope angle of the first sub-hole is 55° to 75°, the hole wall slope angle of the second sub-hole is 25° to 45°, and the hole wall slope angle of the third sub-hole is 55° to 80°.

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