Virtual system and method for ADC peripherals on a chip

Abstract

The present invention discloses a virtual system and method for an ADC peripheral on a chip, wherein the system includes a virtual chip and an analog quantity acquisition interface module. The virtual chip includes a virtual CPU and a virtual ADC peripheral, the virtual ADC peripheral includes a virtual ADC peripheral register that simulates the ADC peripheral register and an analog quantity conversion module for converting analog quantities to digital quantities, the virtual CPU can read and write data to the virtual ADC peripheral register, and the analog quantity acquisition interface module is used to provide a virtual electrical signal to the virtual ADC peripheral. According to the virtual system of the above technical solution, the virtual ADC peripheral cooperates with the analog quantity acquisition interface module to directly use physical quantities, providing an embedded target code with a simulation that is closer to the ADC peripheral on the real chip, so that the debugged target code can be directly delivered without the need for interface adaptation, thereby improving the convenience of debugging.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip virtual simulation, and in particular relates to a virtual system and method for ADC peripherals in a chip. Background Art

[0002] Compilers for embedded systems have integrated debugging capabilities. However, the interfaces within the debugging environment are low-level, and data variables observed are only viewed from a machine perspective, without direct access to physical data, making it inconvenient. Existing simulation software provides data to high-level language interfaces by reading data streams such as files. This requires the embedded software to adapt to the interface or provide variable addresses. With the former, the embedded software adds code beyond the control task; with the latter, addresses change with software iterations, requiring the variable addresses to be queried and updated in the new version of the software, impacting debugging efficiency. Summary of the Invention

[0003] Purpose of the invention: The purpose of the present invention is to propose a virtual system for on-chip ADC peripherals, which can realize the virtualization of on-chip virtual ADC peripherals that is closer to the real thing and improve the convenience of debugging.

[0004] Another object of the present invention is to propose a method implemented by a virtual system of the ADC peripheral in the above chip, which can ensure that the embedded software target code runs in the virtual chip in the same way as in the real chip, and the debugged target code can be directly delivered.

[0005] Technical solution: The virtual system of the ADC peripheral on a chip described in the present invention includes a virtual chip and an analog quantity acquisition interface module, wherein the virtual chip includes a virtual CPU and a virtual ADC peripheral, the virtual ADC peripheral includes virtual ADC peripheral registers that simulate ADC peripheral registers and an analog quantity conversion module for analog-to-digital conversion, the virtual CPU can read and write data in the virtual ADC peripheral registers, and the analog quantity acquisition interface module is used to provide virtual electrical signals to the virtual ADC peripheral.

[0006] Furthermore, it also includes a mathematical model, which is used to provide physical values ​​for the analog interface acquisition module. The mathematical model runs in parallel with the virtual chip and iteratively calculates the physical values. The analog acquisition interface module converts the physical values ​​into virtual electrical signals.

[0007] Furthermore, the virtual ADC peripheral also includes an operation command CFIFO and an acquisition conversion result RFIFO. The operation command CFIFO is used to store ADC operation commands, and the acquisition conversion result RFIFO is used to store the acquisition conversion results of the analog conversion module. The virtual ADC peripheral register includes a corresponding operation command CFIFO control register, an operation command CFIFO push register, an acquisition conversion result RFIFO pop-up register, and a FIFO and interrupt status register.

[0008] Furthermore, the virtual ADC peripheral register also includes a buffer zone for storing high-speed data using a circular queue.

[0009] Furthermore, the virtual CPU includes an instruction counter, and the instruction counter is used to record the number of instructions executed by the virtual CPU.

[0010] Furthermore, the virtual ADC peripheral device further includes a data processing clock, and the data processing clock is used to record the data processing task time of the virtual ADC peripheral device.

[0011] The method for virtualizing an ADC peripheral device within a chip according to the present invention comprises the following steps:

[0012] S1: Run the virtual chip and load the virtual ADC peripheral;

[0013] S2: Load the embedded software target code to be debugged into the virtual CPU for execution;

[0014] S3: Check whether the instruction counter increment reaches the instruction number corresponding to the data processing clock of the virtual ADC peripheral. If so, perform the data processing task of the virtual ADC peripheral.

[0015] S4: Determine whether there is an interrupt request and jump to the corresponding service program according to the interrupt request.

[0016] Furthermore, the S3 step further includes:

[0017] S3.1: If the value of the operation command CFIFO push register changes and the operation command CFIFO is not full, the value of the operation command CFIFO push register is stored in the operation command CFIFO register, and the number of CFIFO command entries in the FIFO and interrupt status registers is updated;

[0018] S3.2: The virtual ADC peripheral converts the virtual electrical signal received from the analog acquisition interface module into a digital quantity, stores it in the acquisition conversion result RFIFO, and updates the number of entries in the acquisition conversion result RFIFO in the FIFO and interrupt status register;

[0019] S3.3: Extract a command from the operation command CFIFO. If it is an ADC register read or write command, set the values ​​of the FIFO and interrupt status registers according to the value of the operation command CFIFO control register, set the scan mode and scan trigger mode of the virtual ADC peripheral, start the corresponding timer period task, write the time required for the virtual ADC peripheral configuration to convert one AD channel into the data processing clock, and update the CFIFO command entry number and next instruction pointer in the FIFO and interrupt status registers;

[0020] S3.4: Extract a command from the operation command CFIFO. If it is an ADC conversion command and the acquisition conversion result RFIFO is not empty, read a data from the acquisition conversion result RFIFO into the acquisition conversion result RFIFO pop register, and update the number of entries and the next data pointer of the acquisition conversion result RFIFO in the FIFO and interrupt status register.

[0021] S3.5: Check the values ​​of the FIFO and interrupt status registers, and clear the flag bits in the FIFO and interrupt status registers according to the value of the operation command CFIFO control register.

[0022] Beneficial effects: Compared with the existing technology, the present invention has the following advantages: it has a virtual ADC peripheral that runs consistently with the ADC peripheral in a real chip, and cooperates with an analog acquisition interface module that can provide virtual voltage values. Physical data can be used directly to provide a debugging environment for embedded target code that is closer to the real chip. The debugged embedded software target code can be kept consistent with that at the time of delivery, and no interface adaptation is required. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a system block diagram of a virtual system of an on-chip ADC peripheral according to an embodiment of the present invention;

[0024] Figure 2 Flowchart of a method for virtualizing an ADC peripheral on a chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0026] Reference Figure 1According to an embodiment of the present invention, a virtual system for an ADC peripheral in a chip includes a virtual chip and an analog quantity acquisition interface module. The virtual chip includes a virtual CPU and a virtual ADC peripheral, and the virtual ADC peripheral includes a virtual ADC peripheral register that simulates the ADC peripheral register and an analog quantity conversion module for converting analog quantities to digital quantities. The virtual CPU can access the virtual ADC peripheral register to configure the parameters of the virtual ADC peripheral register and synchronize the data in the virtual ADC peripheral register to the address of the loaded embedded target code. The analog quantity acquisition interface module is used to provide a virtual electrical signal to the analog quantity conversion module in the virtual ADC peripheral.

[0027] According to the virtual system of the ADC peripheral in the chip of the above technical solution, through the analog quantity acquisition interface module and the virtual ADC peripheral, it is possible to provide an ADC peripheral simulation close to the real chip for the embedded target code to be debugged loaded on the virtual chip, thereby verifying the function of the embedded software to obtain external analog quantities. When debugging the embedded target code through the above virtual system, there is no need to write additional control task code. The virtual ADC peripheral is consistent with the ADC peripheral in the real chip, so the debugged target code can be delivered directly without the need for interface adaptation. In addition, by injecting fault signals between the analog quantity acquisition interface module and the virtual ADC peripheral, functions such as setting data step changes, disconnections, glitches, etc. can be simulated to verify the fault handling and identification function of the embedded software.

[0028] Reference Figure 1 In practice, the analog acquisition interface module can manually set the acquisition voltage or receive physical quantities calculated by the mathematical model. It then calibrates and converts these into corresponding virtual electrical signals and transmits them to the virtual ADC peripheral via pipe communication. The mathematical model runs in parallel with the virtual chip and automatically cycles, continuously iterating and calculating physical quantities. Because the virtual CPU processes slower than the real chip, the virtual ADC peripheral has a buffer that uses a circular queue to store data for high-speed data. The high-speed virtual electrical signals are first stored in the circular queue. The analog conversion module of the virtual ADC peripheral parses the latest data, places the virtual electrical signals into a global variable array based on the channel number, converts them into digital quantities, and stores them in the virtual ADC peripheral register.

[0029] In practice, the virtual CPU includes an instruction counter that tracks the number of instructions executed by the virtual CPU. The virtual ADC peripheral includes a data processing clock that tracks the duration of the virtual ADC peripheral's data processing tasks. Unless an interrupt request is received, the virtual CPU accesses the virtual ADC peripheral to perform data processing tasks at intervals specified by the data processing clock.

[0030] In practice, the register types in the virtual ADC peripheral registers can be determined based on the model of the actual on-chip ADC peripheral being simulated, and generally include control registers, data registers, and status registers. In this embodiment, the virtual ADC peripheral simulates an on-chip ADC peripheral designed using FIFO mode, including two FIFOs: the command CFIFO and the conversion result RFIFO. The virtual ADC peripheral registers include the command CFIFO control register EQADC_CFCRn, the command CFIFO push register EQADC_CFPRn, the conversion result RFIFO pop register EQADC_RFPRn, the conversion result FIFO, and the interrupt status register EQADC_FISRn. The operation command CFIFO control register EQADC_CFCRn is used to configure the parameters of the virtual ADC peripheral, such as interrupt enable, receive enable, resolution and working mode, acquisition conversion time, acquisition channel, etc. The operation command CFIFO push register EQADC_CFPRn is used to store the operation instructions that need to be stored in the operation command CFIFO register. The acquisition conversion result RFIFO pop-up register EQADC_RFPRn is used to store the digital quantity that needs to be extracted from the acquisition conversion result RFIFO to the embedded target code address. The FIFO and interrupt status register EQADC_FISRn includes various flag bits, the number of entries in the operation command CFIFO register and the acquisition conversion result RFIFO, the current extraction position, and the pointer information that should be extracted next time.

[0031] Reference Figure 2 According to the on-chip ADC peripheral virtualization system of the embodiment of the present invention, the on-chip ADC peripheral can be virtualized by the following method:

[0032] S1: Run the virtual chip and load the virtual ADC peripheral;

[0033] S2: Load the embedded software target code to be debugged into the virtual CPU for execution;

[0034] S3: Check whether the instruction counter increment reaches the instruction number corresponding to the data processing clock of the virtual ADC peripheral. If so, perform the data processing task of the virtual ADC peripheral.

[0035] S4: Determine whether there is an interrupt request and jump to the corresponding service program according to the interrupt request.

[0036] If the embedded target code involves multi-channel ADC conversion, multiple virtual ADC peripherals can be loaded, and the channel number of each virtual ADC peripheral can be configured and bound to the channel number set by the analog acquisition interface module.

[0037] The virtual ADC peripheral, analog acquisition interface module and virtual CPU run in parallel. The virtual ADC peripheral converts the virtual electrical signal transmitted by the analog acquisition interface module into a digital signal and stores it in the acquisition conversion result RFIFO.

[0038] In step S3, when the value in the operation command CFIFO push register EQADC_CFPRn changes, it indicates that a new operation command needs to enter the operation command CFIFO queue. The operation command comes from the project software's operation on the ADC, such as collecting a certain channel. First, determine whether the command CFIFO not full CFFF in the FIFO and interrupt status register EQADC_FISRn is 0. If it is 0, calculate the command filling position based on the next instruction pointer TNXTPTR and the CFIFO command entry number CFCTR in the register EQADC_FISRn. Then, fill the value in EQADC_CFPRn into the command filling position in the operation command CFIFO, and modify CFCTR by 1. If CFCTR is equal to the command CFIFO depth, set the command CFIFO not full CFFF in the register EQADC_FISRn to 1.

[0039] Each time the virtual ADC peripheral performs data processing, it first calculates the location of the next instruction based on the next instruction pointer (TNXTPTR) in the EQADC_FISRn register. It then reads the corresponding instruction from the command CFIFO register and completes the virtual ADC peripheral register read or write or ADC conversion task based on the instruction content. Upon completion, the value of TNXTPTR is incremented by 1 and the value of CFCTR is decremented by 1.

[0040] When the operation instruction is an ADC register read or write command, the flags in the FIFO and interrupt status registers EQADC_FISRn are set according to the value of the operation command CFIFO control register EQADC_CFCRn, and the parameters of the virtual ADC peripheral are set. For example, if the single-channel scan flag SSEn in the EQADC_CFCRn register is set to 1, the single-channel scan status flag SSSn in the EQADC_FISRn register is set to 1. If the command CFIFO invalidation flag CFINVn is set to 1, the command entry count CFCTR and the next instruction pointer TNXTPTR are set to 0, and the command CFIFO not full flag is set to 1. The scan mode can also be set to rising edge triggered single channel scan, falling edge triggered single channel scan, or continuous scan, based on the value of the signal scan mode MODE.

[0041] When the operation instruction is an ADC conversion command and the number of entries (RFCTR) in the acquisition conversion result RFIFO in the FIFO and interrupt status register EQADC_FISRn is greater than 0, the position of the digital data to be read is calculated based on the next data pointer (POPNXTPTR) popped out of the acquisition conversion result RFIFO in the EQADC_FISRn register. The data at that position is read from the acquisition conversion result RFIFO and stored in the acquisition conversion result RFIFO pop-up register EQADC_RFPRn. RFCTR is then decremented by 1 and POPNXTPTR is incremented by 1. If RFCTR is 0, RFDF in the acquisition conversion result RFIFO register EQADC_FISRn is set to 0. The virtual CPU reads the value in the EQADC_RFPRn register into the address of the embedded software.

[0042] Each time a data processing task is completed, the relevant bits in the flag bits of the FIFO and interrupt status register EQADC_FISRn are cleared to 0 according to the value of the operation command CFIFO control register EQADC_CFCRn.

[0043] During implementation, the time required to convert one AD channel is calculated based on the ADC configuration and converted into the number of instruction entries specified by the virtual CPU to set the timing period. For example, if the ADC acquisition and conversion frequency is 1MHz, this is equivalent to 1us. If the chip system clock is 100MHz, this means that the ADC acquisition and conversion is performed once every 100 instructions. If the value in the CFIFO control register is set for single-channel scanning according to the operation command, the task is terminated after converting to one channel. If continuous scanning is used, each channel is processed in sequence until the queue end EOQ bit in the FIFO and interrupt status register EQADC_FISRn is valid, at which point the task is terminated.

Claims

1. A method for virtualizing an ADC peripheral on a chip, characterized in that: The ADC peripherals in the virtual chip include a virtual chip and an analog quantity acquisition interface module, wherein the virtual chip includes a virtual CPU and a virtual ADC peripheral, the virtual ADC peripheral includes a virtual ADC peripheral register that simulates the ADC peripheral register and an ADC for analog-to-digital conversion, the virtual CPU can read and write data to the virtual ADC peripheral register, and the analog quantity acquisition interface module is used to provide a virtual electrical signal to the virtual ADC peripheral; The virtual ADC peripheral also includes an operation command CFIFO and an acquisition conversion result RFIFO, wherein the operation command CFIFO is used to store the ADC operation command, and the acquisition conversion result RFIFO is used to store the acquisition conversion result of the analog conversion module. The virtual ADC peripheral register includes a corresponding operation command CFIFO control register, an operation command CFIFO push register, an acquisition conversion result RFIFO pop register, and a FIFO and interrupt status register; The method for virtualizing an ADC peripheral device within a chip comprises the following steps: S1: Run the virtual chip and load the virtual ADC peripheral; S2: Load the embedded software target code to be debugged into the virtual CPU for execution; S3: Check whether the instruction counter increment in the virtual CPU reaches the instruction number corresponding to the data processing clock of the virtual ADC peripheral. If so, perform the data processing task of the virtual ADC peripheral. The S3 step includes: S3.1: If the value of the operation command CFIFO push register changes and the operation command CFIFO is not full, the value of the operation command CFIFO push register is stored in the operation command CFIFO control register, and the number of CFIFO command entries in the FIFO and interrupt status registers is updated; S3.2: The virtual ADC peripheral converts the virtual electrical signal received from the analog acquisition interface module into a digital quantity, stores it in the acquisition conversion result RFIFO, and updates the number of entries in the acquisition conversion result RFIFO in the FIFO and interrupt status register; S3.3: Extract a command from the operation command CFIFO. If it is a virtual ADC peripheral register read or write command, set the values ​​of the FIFO and interrupt status registers according to the value of the operation command CFIFO control register, set the scan mode and scan trigger mode of the virtual ADC peripheral, start the corresponding timer period task, write the time required for the virtual ADC peripheral to convert one AD channel into the data processing clock, and update the CFIFO command entry number and next instruction pointer in the FIFO and interrupt status registers; S3.4: Extract a command from the operation command CFIFO. If it is an ADC operation command and the acquisition conversion result RFIFO is not empty, read a data from the acquisition conversion result RFIFO into the acquisition conversion result RFIFO pop register, and update the number of entries and the next data pointer of the acquisition conversion result RFIFO in the FIFO and interrupt status register. S3.5: Check the values ​​of the FIFO and interrupt status registers, and clear the flag bits in the FIFO and interrupt status registers according to the value of the operation command CFIFO control register.

2. The method for virtualizing an ADC peripheral on a chip according to claim 1, wherein: The ADC peripheral in the virtual chip also includes a mathematical model, which is used to provide physical values ​​for the analog interface acquisition module. The mathematical model runs periodically in parallel with the virtual chip to iteratively calculate the physical values, and the analog acquisition interface module converts the physical values ​​into virtual electrical signals.

3. The method for virtualizing an ADC peripheral on a chip according to claim 1, wherein: The virtual ADC peripheral register also includes a buffer area that uses a circular queue to store high-speed data.

4. The method for virtualizing an ADC peripheral on a chip according to claim 1, wherein: The instruction counter is used to record the number of instructions executed by the virtual CPU.

5. The method for virtualizing an ADC peripheral on a chip according to claim 1, wherein: The data processing clock is used to record the data processing task time of the virtual ADC peripheral.

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