Thread scheduling methods, processors, and electronic devices

Abstract

A thread scheduling method, a processor, and an electronic device are disclosed. The thread scheduling method includes: performing a pre-release operation of shared memory resources for a first thread group. Performing the pre-release operation of shared memory resources for the first thread group includes: when it is determined that the thread subgroup currently running in the processing unit is the last thread subgroup in the first thread group, releasing the shared memory resources occupied and available for release by the first thread group. This thread scheduling method can release the shared memory resources occupied by the current thread group while it is still running, thereby allowing the released resources to be allocated to other thread groups, achieving the purpose of pre-allocating resources, thus improving running efficiency and shortening the overall task completion time.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a thread scheduling method, a processor, and an electronic device. Background Technology

[0002] A Graphics Processing Unit (GPU), also known as a display core, visual processor, or display chip, is a microprocessor specifically designed for performing image and graphics-related calculations in personal computers, workstations, game consoles, and some mobile devices (such as tablets and smartphones). The GPU converts and drives the display information required by the computer system and provides line scanning signals to the monitor, thereby controlling the monitor to display correctly. The GPU is a crucial component connecting the monitor and the computer motherboard (which includes the central processing unit), and is also one of the essential devices for enabling human-computer interaction. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a thread scheduling method, including: performing an early release operation of shared storage resources of a first thread group, including: when it is determined that the thread subgroup currently running in the processing unit is the last thread subgroup in the first thread group, releasing the shared storage resources occupied and releasable by the first thread group.

[0004] For example, at least one embodiment of the thread scheduling method provided in this disclosure further includes: allocating previously occupied and releasable shared storage resources to a second thread group that is currently making a resource allocation request.

[0005] For example, in the thread scheduling method provided in at least one embodiment of this disclosure, while the shared storage resources that were previously occupied by the first thread group and are releasable are allocated to the second thread group, the last thread subgroup in the first thread group is still running.

[0006] For example, at least one embodiment of the thread scheduling method provided in this disclosure further includes: responding to an early release instruction for shared storage resources of a first thread group to perform an early release operation for shared storage resources of the first thread group.

[0007] For example, in the thread scheduling method provided in at least one embodiment of this disclosure, responding to an early release instruction for shared storage resources of a first thread group includes: obtaining the status information of the thread subgroup currently running in the processing unit; and determining, based on the status information, whether the thread subgroup currently running in the processing unit is the last thread subgroup in the first thread group.

[0008] For example, in the thread scheduling method provided in at least one embodiment of this disclosure, the status information of the thread subgroup includes indication information and identification information. The indication information indicates whether the thread subgroup is the last thread subgroup in the first thread group, and the identification information indicates the resource identifier corresponding to the thread subgroup.

[0009] For example, in the thread scheduling method provided in at least one embodiment of this disclosure, releasing the shared storage resources occupied and releasable by the first thread group includes: obtaining information about the shared storage resources that need to be released based on the identification information, and releasing the shared storage resources occupied and releasable by the first thread group based on the information about the shared storage resources.

[0010] For example, in the thread scheduling method provided in at least one embodiment of this disclosure, releasing the shared storage resources occupied and available for release by the first thread group according to the information of the shared storage resources includes: obtaining a mask table corresponding to the shared storage resources from the resource mask matrix, and updating the state of the shared storage resources in the mask table to an available state.

[0011] For example, in the thread scheduling method provided in at least one embodiment of this disclosure, the information of the shared storage resource includes the address and size of the shared storage resource.

[0012] For example, the thread scheduling method provided in at least one embodiment of this disclosure, after performing the early release operation of shared storage resources, further includes: performing the termination operation of the first thread group to release the private storage resources occupied by the first thread group.

[0013] For example, in the thread scheduling method provided in at least one embodiment of this disclosure, performing the termination operation of the first thread group includes: responding to a thread group termination instruction for the first thread group and terminating the operation of the first thread group.

[0014] At least one embodiment of this disclosure provides a processor, including: a processing unit configured to execute at least one thread group, wherein the thread group includes at least one thread subgroup; and a resource manager configured to release shared storage resources occupied and releasable by the thread group to which it belongs when it is determined that the thread subgroup currently running in the processing unit is the last thread subgroup in the thread group to which it belongs.

[0015] For example, in a processor provided in at least one embodiment of this disclosure, the processing unit includes: a control unit configured to receive a shared storage resource early release instruction, and to provide the status information of the thread subgroup currently running in the processing unit and the shared storage resource early release instruction to a resource manager, wherein the resource manager is further configured to, based on the status information and the shared storage resource early release instruction, release the shared storage resources occupied and releasable by the thread group to which it belongs, if it is determined that the thread subgroup currently running in the processing unit is the last thread subgroup in its respective thread group.

[0016] For example, in the processor provided in at least one embodiment of this disclosure, the processing unit further includes multiple vector processing units and shared memory; each vector processing unit includes a vector register and a scalar register, which are provided as private storage resources to each thread subgroup; the shared memory is provided as a shared storage resource to the thread group.

[0017] At least one embodiment of this disclosure provides an electronic device including a processor provided in at least one embodiment of this disclosure. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0019] Figure 1 This is a schematic diagram of the structure of a shader processing unit;

[0020] Figure 2A This is a schematic diagram of a vector register mask matrix;

[0021] Figure 2B A schematic diagram of a scalar register mask matrix;

[0022] Figure 2C A schematic diagram of a mask matrix for shared storage resources;

[0023] Figure 3A A timing diagram illustrating thread allocation and kernel program execution is shown.

[0024] Figure 3B A timing diagram illustrating thread allocation and kernel program execution provided in at least one embodiment of this disclosure is shown.

[0025] Figure 4A A flowchart of a thread scheduling method provided in at least one embodiment of this disclosure is shown;

[0026] Figure 4B A flowchart illustrating an exemplary thread scheduling method is shown.

[0027] Figure 5 A schematic diagram of a processor provided in at least one embodiment of the present disclosure is shown;

[0028] Figure 6A A schematic diagram of an electronic device provided for at least one embodiment of this disclosure; and

[0029] Figure 6B A schematic diagram of another electronic device provided for at least one embodiment of this disclosure. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0031] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0032] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and known components have been omitted.

[0033] Figure 1 This is a schematic diagram of the structure of a shader processing unit (SPU) 100.

[0034] like Figure 1 As shown, the SPU 100 is used to execute tasks such as GPU kernel programs, and may include multiple Vector Execution Units (VEUs) 101, Thread Cluster Shared Memory (TCSM) 102, Shader Control Units (SCUs) 103, Shader Resource Managers (SRMs) (not shown in the figure), and Command Interface (CI) modules (not shown in the figure). It should be noted that... Figure 1Four VEU 101s are illustrated, but this does not constitute a limitation on the embodiments of this disclosure. The number of VEU 101s can be any number, such as two, three, five, etc., which can be determined according to actual needs.

[0035] In parallel computing within the kernel, computational tasks are typically executed through multiple threads. A thread is the smallest unit of execution in GPU computation, capable of performing a single logically meaningful operation. A Thread Cluster (TC) is the smallest thread group unit issued by the Thread Integration Center (CI), containing a maximum of 2048 threads. A Thread Platoon (TP) is the smallest thread group unit processed by the Thread Management Replication (SRM), containing a maximum of 64 threads. The GPU kernel executes within a VEU101. Each VEU101 includes a Vector Register (VR) and a Scalar Register (SR). Each VR contains 64 32-bit registers, each individual 32-bit register used by one thread within a TP. A TP can request multiple VRs as needed. Each SR is a 32-bit register, used by all threads within a TP. A TP can also request multiple SRs as needed. Different TPs belonging to the same TC can share data through a TCSM, which acts as a cache for a TC.

[0036] The SCU 103, acting as the control unit of the SPU 100, is responsible for tasks such as instruction fetching and decoding during the execution of the GPU kernel program. The CI (Computer Interface) is responsible for unpacking the issued tasks, thereby scheduling the unpacked TCs and related information to different SRMs for splitting. The SRM is used to split the TCs sent by the CI into individual TPs, allocate each TP to a different VEU, and allocate corresponding hardware resources for each TP. The GPU kernel program fetches and decodes instructions through the SCU, and then the SRM obtains TPs by splitting the TCs sent by the CI, executing the TP as the smallest unit on the VEU within the SPU. Only after the SRM has allocated the hardware resources for the selected SPU and VEU that meet the TP's hardware resource requirements and notified the SCU that the hardware resource allocation is complete can the kernel program for that TP be fetched, decoded, and executed by the SCU from memory.

[0037] Hardware resources include private storage resources and shared storage resources. Private storage resources belonging to a TP include VR, SR, etc., while shared storage resources belonging to all TPs within the same TC include TCSM, etc. Each VEU stores its own private mask table in the SRM to record the usage of its private storage resources. Multiple mask tables recording the usage of private storage resources for multiple VEUs form a mask matrix. Figure 2A The mask matrix for VR in private storage resources is shown. Figure 2B The mask matrix of SR in private storage resources is shown. For example... Figure 2A and Figure 2B As shown, N-1 VEUs correspond to N-1 VR mask tables and N-1 SR mask tables. The N-1 VR mask tables form a VR mask matrix, and the N-1 SR mask tables form an SR mask matrix. Here, N ≥ 2 and is an integer. Similarly, each SPU also has its own private mask table to record the usage of shared storage resources belonging to that SPU. Multiple mask tables also form a mask matrix. Figure 2C The mask matrix for TCSM in shared storage resources is shown. For example... Figure 2C As shown, M-1 SPUs correspond to M-1 TCSM mask tables, and these M-1 TCSM mask tables form a TCSM mask matrix. Here, M ≥ 2 and is an integer.

[0038] exist Figure 2A , Figure 2B , Figure 2C In the mask matrix, the vertical axis represents the SPU / VEU number. For example, if the vertical axis is VEU_0, it means that the row with the vertical axis VEU_0 stores the mask table of the private storage resources corresponding to the VEU with the number VEU_0. When a TP's resource request receives a response from the SRM, all hardware resources allocated to that TP are marked as in use in the corresponding resource mask table of the VEU allocated to that TP. That is, the status of the corresponding resource is marked as in use in the mask table. In this way, subsequent TPs cannot use the occupied resources, thereby avoiding resource conflicts and duplicate allocation. For example, in one example, assuming each VEU has 100 VRs, the first TP is allocated 20 VRs, and subsequent TPs can only allocate from the remaining 80 VRs.

[0039] When a TP requests hardware resources from the SRM, the SRM iterates through the mask matrices of all hardware resources (e.g., the mask matrices of VR, SR, and TCSM). The SRM only responds to the TP's hardware resource request if all available hardware resources can meet its requirements. Once the TP's hardware resource request is responded to, the SRM assigns a VEU on an SPU that meets its hardware resource requirements to execute the kernel program, and selects the shared memory resource number allocated to the SPU and the private memory resource number allocated to the VEU. Simultaneously, the SRM stores the hardware resource attributes (address and size of the hardware resources) used by the TP in a memory location.

[0040] Shared storage resources are hardware resources belonging to the SPU and shared by all TPs within a TC. Therefore, all TPs in this TC must be allocated to the same SPU to ensure that shared storage resources can be used. When searching for all VEUs that meet the criteria, the needs of subsequent TPs in the same TC must be considered, not just the currently allocated TPs, to prevent subsequent TPs from not having enough free resources. Therefore, from the SRM's perspective, the first TP in a TC has the largest hardware resource requirement. As long as there are available VEUs and SPUs to meet the first TP's needs, all TPs in the entire TC can be allocated sequentially; conversely, the splitting of the entire TC will be paused until the TPs allocated to the previous TC finish execution and release sufficient hardware resources before allocation continues.

[0041] When the SCU retrieves an instruction from memory and performs decoding, and determines that the instruction is the last instruction of the kernel program (i.e., the END instruction) based on the decoding result, the SCU will notify the SRM to release all resources occupied by the TP after the END instruction is executed. After receiving the SPU number, VEU number, and TP number allocated to the TP from the SCU, the SRM saves the memory location of the hardware resources used by the TP based on these three numbers, obtains the hardware resource attributes used by the TP, and then releases the hardware resources according to the hardware resource attributes and updates the hardware resource mask matrix (i.e., sets the corresponding hardware resources in the mask table of the resource mask matrix to unused). For shared memory resources, the SRM will only release the shared memory resources according to the hardware resource attributes stored in memory when the SCU notifies the SRM that the currently completed TP is the last TP in the entire TC. All TPs in a TC can be allocated consecutively if all the hardware resources required by the first TP meet the conditions. If any resource does not meet the conditions, all TPs in the entire TC cannot be allocated.

[0042] In the typical execution method, private and shared memory resources are only released after the last process node (TP) in the task manager (TC) has completed its kernel program execution. This significantly reduces task parallelism and increases the total execution time of all tasks.

[0043] At least one embodiment of this disclosure provides a thread scheduling method, including: performing an early release operation of shared storage resources for a first thread group. Performing the early release operation of shared storage resources for the first thread group includes: when it is determined that the thread subgroup currently running in the processing unit is the last thread subgroup in the first thread group, releasing the shared storage resources occupied and available for release by the first thread group.

[0044] At least one embodiment of this disclosure also provides a processor to which the above-described thread scheduling method is applied and an electronic device including the processor.

[0045] The thread scheduling method provided in the above embodiments of this disclosure can release the shared storage resources occupied by the current thread group while it is still running, so that the released resources can be allocated to other thread groups. This achieves the purpose of pre-allocating resources, thereby improving running efficiency and shortening the overall task completion time. For example, in some examples, since the last TP of a Task Manager (TC) does not need to share data with other TPs when executing the kernel program, the shared storage resources are released in advance after the data is loaded. The released resources can be allocated to other thread groups, thereby improving the parallelism of the task.

[0046] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, but this disclosure is not limited to these specific embodiments.

[0047] Figure 3A A timing diagram illustrating TP allocation and kernel program execution is shown.

[0048] like Figure 3A As shown, the horizontal axis represents time, and the vertical axis represents the executed task. In this example, there are a total of 2 TCs (TC0 and TC1). TC0 contains 3 TPs (TC0_TP0, TC0_TP1, and TC0_TP2), and TC1 contains 3 TPs (TC1_TP0, TC1_TP1, and TC1_TP2). Each TP executes its corresponding kernel program. First, TC0_TP0 is created and allocated. When the creation and allocation of TC0_TP0 is complete, TC0_TP0 begins executing its kernel program, while TC0_TP1 is created and allocated simultaneously. When the creation and allocation of TC0_TP1 is complete, TC0_TP1 begins executing its kernel program, while TC0_TP2 is created and allocated simultaneously. When the creation and allocation of TC0_TP2 is complete, TC0_TP2 begins executing its kernel program. For the shared storage resource TCSM, the TCSM data is loaded at the beginning of the kernel program execution in the last TP (i.e., TC0_TP2) of TC0. After the kernel program execution in TC0_TP2 is completed, the TCSM resource is released, and then TC1_TP0 is created and allocated. The timing of the execution tasks of the three TPs in TC1 is similar to that of the three TPs in TC0, and will not be repeated here.

[0049] exist Figure 3A In this context, the data in TCSM is already loaded at the very beginning of the kernel program execution in TC0_TP2. As mentioned above, the last TP of a TC does not need to share data with other TPs when executing the kernel program, so TCSM can be released after loading the data in it.

[0050] By employing the thread scheduling method provided in this embodiment, the TCSM is released after loading the TCSM data, thus obtaining a new timing diagram. The new timing diagram... Figure 3B As shown in the image.

[0051] Figure 3B A timing diagram illustrating TP allocation and kernel program execution provided in at least one embodiment of this disclosure is shown.

[0052] like Figure 3B As shown, the process begins with the creation and allocation of TC0_TP0. Once TC0_TP0 is created and allocated, it begins executing its kernel program, while simultaneously creating and allocating TC0_TP1. When TC0_TP1 is created and allocated, it begins executing its kernel program, and simultaneously creates and allocates the last TP (TC0_TP2) within TC0. After TC0_TP2 is created and allocated, it begins executing its kernel program. At the beginning of TC0_TP2's kernel program execution, the TCSM data is loaded. Immediately after loading the TCSM data, the TCSM resources are released. For example, the released TCSM resources can be used for the early allocation of the next TC. Therefore, upon completion of the TCSM resource release, the first TP of TC1 (i.e., TC1_TP0) can begin creation and allocation, and the subsequent process... Figure 3A Similarly, I will not go into details here.

[0053] contrast Figure 3A and Figure 3B As shown in the timing diagram, by releasing unnecessary TCSM resources in advance, the next TC can be allocated in advance, thereby shortening the overall task completion time. The time saved is shown in the diagram. Regarding... Figure 3B The corresponding thread scheduling methods will be explained further below.

[0054] Figure 4A A flowchart of a thread scheduling method provided in at least one embodiment of the present disclosure is shown.

[0055] like Figure 4A As shown, the thread scheduling method includes steps S401 to S403.

[0056] Step S401: Respond to the early release instruction for the shared storage resources of the first thread group to perform the early release operation of the shared storage resources of the first thread group.

[0057] For example, the shared storage resource can be the aforementioned TCSM, and the shared storage resource early release instruction (e.g., represented as TCSM_EARLY_RELEASE) can be obtained from the memory. For example, the memory can be Dynamic Random Access Memory (DRAM), or other types of memory; the embodiments of this disclosure are not limited to this. Furthermore, the shared storage resource is not limited to the aforementioned TCSM; it can be any other type of storage resource, as long as it is shared by the same TC.

[0058] In some embodiments of this disclosure, in step S401, responding to the early release instruction for the shared storage resources of the first thread group may include: obtaining the status information of the thread subgroup currently running in the processing unit; and determining, based on the status information, whether the thread subgroup currently running in the processing unit is the last thread subgroup in the first thread group.

[0059] For example, the processing unit can be Figure 1 The SPU 100 shown can have its first thread group as follows: Figure 3A and Figure 3B As shown in TC0, the thread subgroups in the first thread group can be TC0_TP0, TC0_TP1, and TC0_TP2, and the last thread subgroup can be TC0_TP2. The first thread group can run on one VEU 101 in SPU 100.

[0060] For example, the status information of a thread subgroup includes indication information and identification information. The indication information indicates whether the thread subgroup is the last thread subgroup in the first thread group, and the identification information indicates the resource identifier corresponding to the thread subgroup.

[0061] For example, the identification information includes the SPU and VEU numbers where the thread subgroup is located, as well as the number of the thread subgroup.

[0062] After performing step S401, step S402 can be performed.

[0063] Step S402: Perform the early release operation of shared storage resources for the first thread group.

[0064] In some embodiments of this disclosure, step S402 may include: if it is determined that the thread subgroup currently running in the processing unit is the last thread subgroup in the first thread group, releasing the shared storage resources occupied and releasable by the first thread group.

[0065] The shared storage resources occupied by the first thread group and available for release are available when the last thread subgroup of the first thread group has finished loading the shared storage resources and the shared storage resources occupied by the first thread group are in a releaseable state.

[0066] In some embodiments of this disclosure, releasing the shared storage resources occupied and releasable by the first thread group may include: obtaining information about the shared storage resources to be released based on identification information, and releasing the shared storage resources occupied and releasable by the first thread group based on the information about the shared storage resources.

[0067] For example, information about shared storage resources includes the address and size of the shared storage resource (e.g., TCSM).

[0068] For example, the address and size of a shared storage resource (e.g., TCSM) can be obtained by using the SPU and VEU numbers of the thread subgroup and the thread subgroup number index to store the memory with allocated thread subgroup attributes.

[0069] For example, releasing the shared storage resources occupied and available for release by the first thread group based on the information of the shared storage resources includes: obtaining the mask table corresponding to the shared storage resources from the resource mask matrix, and updating the status of the shared storage resources in the mask table to the available status.

[0070] For example, the resource mask matrix can be Figure 2C The TCSM mask matrix shown uses the SPU number to obtain the mask table corresponding to the shared storage resources from the TCSM mask matrix. Based on the address and size of the TCSM, the TCSM space that needs to be released is set to an available state in the mask table.

[0071] After performing step S402, step S403 can be performed.

[0072] Step S403: Allocate the previously occupied and releasable shared storage resources to the second thread group that is currently making the resource allocation request.

[0073] In some embodiments of this disclosure, while the previously occupied and releasable shared storage resources of the first thread group are allocated to the second thread group, the last thread subgroup in the first thread group is still running.

[0074] For example, the first thread group can be Figure 3A and Figure 3B As shown in TC0, the second thread group can be Figure 3A and Figure 3B As shown in TC1. Figure 3BAs shown, after the last thread subgroup (TC0_TP2) in the first thread group finishes loading the data of the shared memory resource TCSM, the TCSM resource is released. At this time, the shared memory resource TCSM previously occupied by TC0 is allocated to TC1. At this time, the last thread subgroup TC0_TP2 in the first thread group is still executing the kernel program.

[0075] In some embodiments of this disclosure, after the shared storage resource is released early, the thread scheduling method may further include: performing a termination operation on the first thread group and releasing the private storage resources occupied by the first thread group.

[0076] At this point, only private storage resources need to be released, not shared storage resources. This is because shared storage resources that originally belonged to the first thread group (such as TCSM resources) have already been released, so there is no need to release them again. For example, previously released shared storage resources may have already been allocated to subsequent thread groups.

[0077] In some embodiments of this disclosure, performing a termination operation on the first thread group includes: responding to a thread group termination command for the first thread group and terminating the operation of the first thread group.

[0078] For example, the thread group termination instruction (e.g., the END instruction) is an instruction in the kernel assembler. This thread group termination instruction and the aforementioned shared memory resource early release instruction (TCSM_EARLY_RELEASE) can have the same instruction format to reduce changes to the hardware design. Of course, the embodiments of this disclosure are not limited to this; the thread group termination instruction and the shared memory resource early release instruction can also use different instruction formats to improve design flexibility, which can be determined according to actual needs.

[0079] Figure 4B A flowchart illustrating an exemplary thread scheduling method provided by some embodiments of this disclosure is shown.

[0080] like Figure 4B As shown, first, the SCU fetches instructions from memory (e.g., DRAM) and performs a decoding operation.

[0081] Next, the SCU determines whether the acquired instruction is a shared memory resource early release instruction (TCSM_EARLY_RELEASE instruction) based on the decoding result. If the decoding determines that the instruction is a TCSM_EARLY_RELEASE instruction, it sends TCSM release information to the SRM. At the same time, the SCU still needs to send the SPU and VEU numbers where the TP is located, as well as the TP number, to the SRAM. All of the above information is packaged in a set of data and transmitted to the SRM through a preset bus protocol.

[0082] Next, the SRM receives the TCSM release information sent by the SCU.

[0083] Next, the SRM unpacks the information data and determines whether the TP currently executing the kernel program is the last TP in the TC and notifies the SRM of this information. If it is not the last TP, the TCSM release information sent by the SCU is ignored. If it is determined that the TP currently executing the kernel program is the last TP in its TC, the memory with allocated TP attributes is stored using the SPU, VEU, and TP number index obtained from the information data, thereby obtaining the address and size of the TCSM. Then, the TCSM mask matrix is ​​updated; that is, the mask table corresponding to the TCSM occupied by that SPU is retrieved from the TCSM mask matrix using the SPU number, and the TCSM space that needs to be released is set to available in the mask table.

[0084] At this point, because the TP has not yet completed the execution of the kernel program, the remaining hardware resources occupied by the TP cannot be released. If the TC to be allocated next cannot be allocated only because the TCSM resources are insufficient, then the TCSM released in advance may meet its resource requirements and be allocated in advance.

[0085] After the shared storage resource is released early, the first thread group terminates, releasing the private storage resources it occupies. Specifically, if the instruction retrieved by the SCU is decoded as an END instruction, the SCU sends resource release information. The SRM receives this information and uses the SPU, VEU, and TP numbers obtained from the information data to index the memory storing the allocated TP attribute, thereby obtaining the addresses and sizes of other hardware resources besides TCSM. Next, the mask matrix of other hardware resources besides TCSM is updated. Specifically, the mask tables corresponding to other hardware resources in the mask matrix of other hardware resources (e.g., VR mask matrix, SR mask matrix) are retrieved using the VEU and TP numbers, and the spaces of other hardware resources that need to be released are set to available in the mask table. Here, since TCSM has already been released early, only the mask matrix of other hardware resources besides TCSM needs to be updated at this point.

[0086] In the thread scheduling method provided in this embodiment, the resource release process is broken down into two steps: first, shared storage resources are released in advance, and then private storage resources are released. This allows for the early allocation of the next set of task processors (TPs) by releasing unnecessary resources, thereby shortening the total task completion time. Because shared storage resources are released in advance, the next task processor (TC) can be allocated earlier than in the conventional method. This allows for time overlap with the previous TC's kernel program execution, increasing task parallelism and further shortening the total task execution time.

[0087] It should be noted that in the embodiments of this disclosure, the above thread scheduling method may include more or fewer steps, and is not limited to the steps described above. The execution order of each step is not restricted and can be determined according to actual needs.

[0088] Figure 5 A schematic diagram of a processor 500 provided in at least one embodiment of the present disclosure is shown.

[0089] like Figure 5 As shown, the processor 500 includes a processing unit 501 and a resource manager 502.

[0090] Processing unit 501 is configured to execute at least one thread group, wherein the thread group includes at least one thread subgroup. Processing unit 501 includes a control unit 503, multiple vector processing units 504, and shared memory 505. Control unit 503 is configured to receive a shared memory resource early release instruction and provide the status information of the thread subgroup currently running in processing unit 501, along with the shared memory resource early release instruction, to resource manager 502. Each vector processing unit 504 includes VR and SR, which are provided as private storage resources to the thread subgroup. Shared memory 505 is provided as shared storage resources to the thread group.

[0091] Resource Manager 502 is configured to release the shared storage resources occupied by the thread group that are available for release when it is determined that the thread subgroup currently running in processing unit 501 is the last thread subgroup in its respective thread group. Resource Manager 502 is also configured to release the shared storage resources occupied by the thread group that are available for release when it is determined that the thread subgroup currently running in processing unit 501 is the last thread subgroup in its respective thread group, based on the status information of the thread subgroup running in processing unit 501 and the shared storage resource early release instruction.

[0092] Processing unit 501 is, for example, Figure 1 The SPU 100 shown, the resource manager 502 is, for example, the SRM mentioned above, and the control unit 503 is, for example, Figure 1The SCU 103 shown contains multiple vector processing units 504, for example... Figure 1 The VEU 101 shown has a shared memory 505, for example, Figure 1 The TCSM 102 is shown. Detailed descriptions of each unit or module can be found in the preceding text and will not be repeated here. For example, processor 500 can be any type of processor such as a CPU or GPU. Processor 500 may also include more units and modules to implement processing and computing functions. The technical effects of processor 500 can be found in the description of the thread scheduling method above and will not be repeated here.

[0093] The following is combined Figure 5 An embodiment of the thread scheduling method provided in at least one embodiment of this disclosure will be briefly described.

[0094] Resource Manager 502 is used to split thread groups into individual thread subgroups and assign each thread subgroup to a different vector processing unit 504, while also allocating corresponding hardware resources to each thread subgroup. The GPU kernel program is fetched and decoded by Control Unit 503, and then executed by Resource Manager 502 on the vector processing unit 504 in Processing Unit 501, with the thread subgroup as the smallest unit. Control Unit 503 determines whether the fetched instruction is a shared memory resource early release instruction based on the decoding result. If the decoding determines that the instruction is a shared memory resource early release instruction, it sends shared memory resource release information to Resource Manager 502. At the same time, Control Unit 503 still needs to send the numbers of Processing Unit 501 and Vector Processing Unit 504 to which the thread subgroup belongs, as well as the number of the thread subgroup, to Resource Manager 502. All of the above information is packaged in a set of information data.

[0095] Next, the resource manager 502 receives the shared memory resource release information sent by the control unit 503. Then, the resource manager 502 unpacks the information data and determines whether the currently executing kernel program's thread subgroup is the last thread subgroup in the thread group. If it is the last thread subgroup, it uses the processing unit 501, vector processing unit 504, and the thread subgroup's number index memory obtained from the information data to retrieve the address and size of the shared memory resource, and finally updates the TCSM mask matrix. After the shared memory resource early release operation, the thread group termination operation is performed, releasing the private memory resources (such as VR and SR resources) occupied by the thread group.

[0096] Figure 6A This is a schematic diagram of the structure of an electronic device 600 provided for at least one embodiment of the present disclosure.

[0097] like Figure 6A As shown, the electronic device 600 includes Figure 5The processor 500 shown. Figure 6A The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments disclosed herein.

[0098] Figure 6B This is a schematic diagram of the structure of another electronic device 700 provided in at least one embodiment of the present disclosure. The electronic device 700 in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle terminals (e.g., vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 6B The electronic device 700 shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments disclosed herein.

[0099] For example, such as Figure 6B As shown, in some examples, electronic device 700 includes a processing unit (e.g., a central processing unit, graphics processor, etc.) 601, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 602 or a program loaded from storage device 608 into random access memory (RAM) 603. For example, processing unit 601 can be the aforementioned processor 500. Various programs and data required for the operation of the computer system are also stored in RAM 603. Processing unit 601, ROM 602, and RAM 603 are connected via bus 604. Input / output (I / O) interface 605 is also connected to bus 604.

[0100] For example, the following components can be connected to I / O interface 605: input devices 606 such as touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 607 such as liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 608 such as magnetic tapes, hard disks, etc.; and communication devices 609 including network interface cards such as LAN cards, modems, etc. Communication device 609 allows electronic device 700 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 610 is also connected to I / O interface 605 as needed. Removable media, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 610 as needed so that computer programs read from them can be installed into storage device 608 as needed. Although Figure 6B An electronic device 700 including various means is shown; however, it should be understood that implementation or inclusion of all the means shown is not required. More or fewer means may be implemented or included alternatively.

[0101] For example, the electronic device 700 may further include a peripheral interface (not shown). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 609 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0102] For example, electronic device 700 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, etc., or any combination of electronic devices and hardware. The embodiments disclosed herein do not limit this.

[0103] It should be noted that the computer-readable medium described above in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In embodiments of this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In embodiments of this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0104] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0105] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0106] The following points should be noted regarding this disclosure:

[0107] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0108] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0109] The above description is only a specific embodiment of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A thread scheduling method, comprising: Respond to the instruction to release shared storage resources early for the first thread group. Perform an early release operation on the shared storage resources of the first thread group. The step of performing the early release operation of shared storage resources of the first thread group includes: If it is determined that the thread subgroup currently running in the processing unit is the last thread subgroup in the first thread group, the shared memory resources occupied and releasable by the first thread group are released, wherein the shared memory resources include hardware resources belonging to the shader processing unit (SPU). The method further includes: Allocate the previously occupied and releasable shared storage resources to the second thread group that is currently making the resource allocation request; While allocating the previously occupied and releasable shared storage resources to the second thread group, the last thread subgroup in the first thread group is still running.

2. The thread scheduling method according to claim 1, wherein, Responding to the instruction to prematurely release shared storage resources for the first thread group includes: Obtain the status information of the thread subgroup currently running in the processing unit; Based on the status information, it is determined whether the thread subgroup currently running in the processing unit is the last thread subgroup in the first thread group.

3. The thread scheduling method according to claim 2, wherein, The status information of the thread subgroup includes indication information and identification information. The indication information indicates whether the thread subgroup is the last thread subgroup in the first thread group. The identification information indicates the resource identifier corresponding to the thread subgroup.

4. The thread scheduling method according to claim 3, wherein, Releasing the shared storage resources that are occupied and can be released by the first thread group includes: Based on the identification information, obtain information about the shared storage resources that need to be released, and release the shared storage resources occupied by the first thread group that are available for release based on the information about the shared storage resources.

5. The thread scheduling method according to claim 4, wherein, Releasing the shared storage resources occupied and available for release by the first thread group based on the information of the shared storage resources includes: Obtain the mask table corresponding to the shared storage resource from the resource mask matrix, and update the status of the shared storage resource in the mask table to an available status.

6. The thread scheduling method according to claim 4, wherein, The information about the shared storage resource includes its address and size.

7. The thread scheduling method according to any one of claims 1-6, further comprising, after performing the shared storage resource early release operation: Perform the termination operation on the first thread group and release the private storage resources occupied by the first thread group.

8. The thread scheduling method according to claim 7, wherein, Performing the termination operation for the first thread group includes: Respond to the thread group termination instruction for the first thread group and terminate the operation of the first thread group.

9. A processor, comprising: A processing unit is configured to execute at least one thread group, wherein the thread group includes at least one thread subgroup; a resource manager is configured to release shared storage resources occupied and releasable by the first thread group when it is determined that the thread subgroup currently running in the processing unit is the last thread subgroup in the first thread group, wherein the shared storage resources include hardware resources belonging to the shader processing unit (SPU). The resource manager is further configured to allocate the previously occupied and releasable shared storage resources to the second thread group that is currently making the resource allocation request; wherein, while allocating the previously occupied and releasable shared storage resources to the second thread group, the last thread subgroup in the first thread group is still running; The processing unit includes: The control unit is configured to receive a shared storage resource early release instruction and provide the resource manager with the status information of the thread subgroup currently running in the processing unit and the shared storage resource early release instruction. The resource manager is further configured to, based on the status information and the shared storage resource early release instruction, release the shared storage resource occupied and available for release by the first thread group when it is determined that the thread subgroup currently running in the processing unit is the last thread subgroup in the first thread group.

10. The processor according to claim 9, wherein, The processing unit also includes multiple vector processing units and a shared memory; Each vector processing unit includes a vector register and a scalar register, which are provided as private storage resources to each thread subgroup; The shared memory is provided to the thread group as a shared storage resource.

11. An electronic device comprising the processor according to claim 9 or 10.

Images