Interface IP core control method, interface IP core, device and medium

Abstract

The present application discloses an interface IP core control method, an interface IP core, a device and a medium, and relates to the field of data exchange. After receiving and caching first data information sent by a master device, the interface IP core converts the received first data information into an AHB protocol standard format, and sends the format-converted first data information to a slave device. The interface IP core control method provided by the present application outputs data information in an AHB protocol standard format, and does not need to configure AHB protocol conversion for each interface IP core separately.

Description

Technical Field

[0001] The present application relates to the field of data exchange, and in particular to an interface IP core control method, an interface IP core, a device and a medium. Background Art

[0002] In the design of System On Chip (SOC), on-chip bus design is the most critical issue. Among them, Advanced High Performance Bus (AHB) is mainly used for the connection between high-performance modules, such as Central Processing Unit (CPU), Direct Memory Access (DMA), Digital Signal Processor (DSP), etc. As the on-chip system bus of SOC, it includes the following features: single clock edge operation; non-three-state implementation; support burst transmission; support segmented transmission; support multiple master controllers; configurable 32-bit to 128-bit bus width; support byte, half-word and word transmission. According to the AHB bus protocol, the AHB bus uses a dedicated memory controller IP (Intellectual Property) core to complete the access to the off-chip memory in the data exchange system. Existing, when the interface IP core is used to connect the AHB bus, it is necessary to configure the AHB protocol conversion for each interface IP core separately.

[0003] Therefore, it can be seen that providing an interface IP core to reduce the need to configure AHB protocol conversion on the interface IP core alone is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0004] The purpose of this application is to provide an interface IP core to reduce the need to configure the AHB protocol conversion for the interface IP core alone.

[0005] In order to solve the above technical problems, the present application provides an interface IP core control method, comprising:

[0006] Receiving first data information stored in a FIFO memory, wherein the first data information is sent to the FIFO memory by a master device;

[0007] Converting the first data information into an AHB protocol standard format;

[0008] The converted first data information is sent to the slave device.

[0009] Preferably, in the above interface IP core control method, after sending the converted first data information to the slave device, it also includes:

[0010] receiving second data information stored in the FIFO memory, the second data information being returned by the slave device to the FIFO memory;

[0011] The second data information is sent to the master device.

[0012] Preferably, in the above interface IP core control method, the first data information includes: read instructions and read control information;

[0013] Correspondingly, the second data information includes read data and a read response signal;

[0014] The sending the second data information to the master device includes: when the read FIFO is not empty, reading out the read data and the read response signal and returning them to the master device.

[0015] Preferably, in the above interface IP core control method, the first data information includes: write instructions, write control information and write data;

[0016] Correspondingly, sending the converted first data information to the slave device includes:

[0017] When the write FIFO is not empty, the write data is read out and sent to the slave device; when the write FIFO is empty, the write data is read out and sent to the slave device after waiting for the write FIFO to be not empty.

[0018] Preferably, in the above interface IP core control method, the step of sending the converted first data information to the slave device comprises:

[0019] The converted first data information is sent to the JPEG module.

[0020] The present application also provides an interface IP core, characterized in that it includes:

[0021] FIFO memory,controller;

[0022] The FIFO memory is used to receive and buffer the first data information sent by the master device;

[0023] The controller is used to receive the first data information stored in the FIFO memory, convert the first data information into an AHB protocol standard format, and send the converted first data information to a slave device.

[0024] Preferably, in the above interface IP core, the FIFO memory is further used to: receive and cache the second data information returned by the slave device;

[0025] The controller is further configured to: receive the second data information stored in the FIFO memory, and send the second data information to the master device.

[0026] The present application also provides an interface IP core control device, characterized in that it includes:

[0027] A receiving module, used for receiving first data information stored in the FIFO memory, wherein the first data information is sent to the FIFO memory by the master device;

[0028] A conversion module, used for converting the first data information into an AHB protocol standard format;

[0029] A sending module is used to send the converted first data information to the slave device.

[0030] The present application also provides an interface IP core control device, characterized in that it includes:

[0031] Memory for storing computer programs;

[0032] A processor is used to implement the steps of the above-mentioned interface IP core control method when executing the computer program.

[0033] The present application also provides a computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the above-mentioned interface IP core control method are implemented.

[0034] The interface IP core control method provided by the present application receives and caches the first data information sent by the master device, converts the received first data information into the AHB protocol standard format, and sends the format-converted first data information to the slave device. The interface IP core control method provided by the present application outputs data information in the AHB protocol standard format, and does not need to configure the interface IP core separately for AHB protocol conversion.

[0035] In addition, the present application also provides an interface IP core, a device and a medium, which are applied to the above-mentioned interface IP core control method, and the effect is the same as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 A flow chart of an interface IP core control method provided in an embodiment of the present application;

[0038] Figure 2 A schematic diagram of an interface IP core provided in an embodiment of the present application;

[0039] Figure 3 A schematic diagram of a FIFO memory provided in an embodiment of the present application;

[0040] Figure 4 A timing diagram of a write operation performed by a master device provided in this application;

[0041] Figure 5 A timing diagram of a read operation performed by a master device provided in this application;

[0042] Figure 6 A structural diagram of an interface IP core control device provided in an embodiment of the present application

[0043] Figure 7 A structural diagram of an interface IP core control device provided in another embodiment of the present application. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0045] The core of the present application is to provide an interface IP core control method to reduce the need to configure AHB protocol conversion for the interface IP core alone.

[0046] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0047] Figure 1 A flow chart of an interface IP core control method provided in an embodiment of the present application; Figure 1 As shown, the present application provides an interface IP core control method, including:

[0048] S10: receiving first data information stored in the FIFO memory 22, the first data information is sent from the master device 21 to the FIFO memory 22;

[0049] S11: Convert the first data information into an AHB protocol standard format;

[0050] S12: Send the converted first data information to the slave device 24.

[0051] First In First Out (FIFO), the FIFO memory 22 mentioned in this embodiment is a first-in first-out data buffer. In system design, the FIFO memory 22 is widely used for the purpose of increasing data transmission rate, processing large amounts of data streams, and matching systems with different transmission rates, thereby improving system performance. The FIFO memory 22 is a first-in first-out dual-port buffer, that is, the first data entering it is the first to be removed, one of which is the input port of the memory and the other is the output port of the memory. The FIFO memory 22 is divided into a dedicated write area and a dedicated read area. The read operation and the write operation can be performed asynchronously, and the data written in the write area is read out from the area at the read end in the order of writing.

[0052] In addition, the FIFO memory 22 may be divided into different areas for storing different data types, which is not specifically limited in this embodiment.

[0053] This embodiment does not limit the specific forms of the master device 21 and the slave device 24, such as DSP, CPU, Field-Programmable Gate Array (FPGA), Graphics Processing Unit (GPU), etc. Any device may be used as the master device 21, and any device may be used as the slave device 24. This embodiment does not make specific restrictions, and can be designed according to actual conditions. When the slave device 24 and the interface IP core are connected through the AHB bus, the data received by the AHB should comply with the AHB protocol specification, and the data that complies with the AHB protocol specification is transmitted to the slave device 24 through the AHB bus. In addition, this embodiment does not limit the connection method between the master device 21 and the interface IP core.

[0054] This embodiment does not limit the specific information type of the first data information, such as read instructions, write instructions, write data and other information.

[0055] Specifically, after the master device 21 sends the first data information to the FIFO memory 22 , the FIFO memory 22 caches the received first data information, and the controller 23 converts the first data information received by the FIFO memory 22 into the AHB bus protocol standard format and transmits it to the slave device 24 .

[0056] In addition, after the first data information is transmitted to the slave device 24, if the slave device 24 needs to return the data information to the master device 21, this embodiment provides a preferred implementation scheme. In the above interface IP core control method, after sending the converted first data information to the slave device 24, it also includes:

[0057] receiving second data information stored in the FIFO memory 22, the second data information being returned to the FIFO memory 22 by the slave device 24;

[0058] The second data information is sent to the master device 21 .

[0059] The second data information mentioned in this embodiment refers to the data information returned after the slave device 24 receives the first data information. This embodiment does not limit the specific information type of the second data information.

[0060] Specifically, after receiving the first data information, the slave device 24 returns the second data information, the FIFO memory 22 receives and caches the second data information, and the controller 23 reads out the second data information and sends it to the master device 21 .

[0061] This embodiment provides a preferred solution, in which the interface IP core receives the second data information returned from the device 24 and completes the data information return operation.

[0062] The interface IP core control method provided by the present application receives and caches the first data information sent by the master device 21, converts the received first data information into the AHB protocol standard format, and sends the format-converted first data information to the slave device 24. The interface IP core control method provided by the present application outputs data information in the AHB protocol standard format, and does not need to configure the interface IP core separately for AHB protocol conversion.

[0063] According to the above embodiment, this embodiment provides a preferred solution when the interface IP core performs a read operation. In the above interface IP core control method, the first data information includes: a read instruction and read control information;

[0064] Correspondingly, the second data information includes read data and a read response signal;

[0065] Sending the second data information to the master device 21 includes: when the read FIFO 223 is not empty, reading out the read data and the read response signal and returning them to the master device 21 .

[0066] It should be noted that the read FIFO 223 refers to a portion of storage space in the FIFO memory 22 for storing read data and read response signals.

[0067] Specifically, the master device 21 sends a read instruction and read control information to the FIFO memory 22, the controller 23 converts the read instruction and read control information into the AHB protocol standard format and sends it to the slave device 24, the slave device 24 receives the read instruction and read control information, returns the read data and read response signal, the FIFO memory 22 receives and stores the read data and read response signal, and when the read FIFO223 is not empty, the controller 23 reads out the read data and read response signal and returns it to the master device 21.

[0068] This embodiment provides a specific solution for performing a read operation. The controller 23 converts the read instruction and the read control information into the AHB protocol standard format and sends them to the slave device 24, avoiding the need for the ordinary interface IP core to configure the AHB protocol conversion separately for the interface IP core.

[0069] According to the above embodiment, when a write operation is performed, in the above interface IP core control method, the first data information includes: a write instruction, write control information and write data;

[0070] Correspondingly, sending the converted first data information to the slave device 24 includes:

[0071] When the write FIFO 222 is not empty, the write data is read out and sent to the slave device 24; when the write FIFO 222 is empty, the write data is read out and sent to the slave device 24 after waiting for the write FIFO 222 to be not empty.

[0072] It should be noted that the write FIFO 222 refers to a portion of storage space in the FIFO memory used for writing data.

[0073] Specifically, the master device 21 sends write instructions, write control information and write data to the FIFO memory 22. After the controller 23 converts the write data into the AHB protocol standard format, when the controller 23 determines that the current data FIFO is not empty, the controller 23 reads the write data and sends it to the slave device 24; when the write FIFO222 is empty, the controller 23 waits for the write FIFO222 to be non-empty and then reads the write data and sends it to the slave device 24.

[0074] This embodiment provides a specific solution for performing a write operation. The controller 23 converts the write data into the AHB protocol standard format and sends it to the slave device 24, avoiding the need for a common interface IP core to separately configure the interface IP core for AHB protocol conversion.

[0075] According to the above embodiment, this embodiment provides a preferred embodiment, the interface IP core is connected to the JPEG module of the slave device 24 through the AHB bus, and in the above interface IP core control method, the converted first data information is sent to the slave device 24, including:

[0076] The converted first data information is sent to the JPEG module.

[0077] When the JPEG module needs to be debugged on FPGA, the JPEG module registers are read and written through the interface IP core provided by this application to complete the JPEG configuration. Since there is no need to configure the AHB protocol conversion for the interface IP core separately, the debugging speed is accelerated, labor is saved, and the debugging cycle is shortened.

[0078] Figure 2 A schematic diagram of an interface IP core provided in an embodiment of the present application; Figure 2 As shown, the present application also provides an interface IP core, including:

[0079] FIFO memory 22, controller 23;

[0080] The FIFO memory 22 is used to receive and buffer the first data information sent by the master device 21;

[0081] The controller 23 is used to receive the first data information stored in the FIFO memory 22 , convert the first data information into the AHB protocol standard format, and send the converted first data information to the slave device 24 .

[0082] The FIFO memory 22 mentioned in this embodiment is a first-in, first-out data buffer. In system design, the FIFO memory 22 is widely used for the purpose of increasing data transmission rate, processing large amounts of data streams, and matching systems with different transmission rates, thereby improving system performance. The FIFO memory 22 is a first-in, first-out dual-port buffer, that is, the first data entering it is the first to be removed, one of which is the input port of the memory and the other is the output port of the memory. The FIFO memory 22 is divided into a dedicated write area and a dedicated read area. The read operation and the write operation can be performed asynchronously, and the data written in the write area is read out from the area at the read end in the order of writing.

[0083] This embodiment does not limit what specific device the controller 23 is, such as a CPU, an MCU, etc. This embodiment does not impose any specific limitation.

[0084] This embodiment does not limit the specific forms of the master device 21 and the slave device 24, such as DSP, CPU, Field-Programmable Gate Array (FPGA), Graphics Processing Unit (GPU), etc. Any device may be used as the master device 21, and any device may be used as the slave device 24. This embodiment does not make specific restrictions, and can be designed according to actual conditions. When the slave device 24 and the interface IP core are connected through the AHB bus, the data received by the AHB should comply with the AHB protocol specification, and the data that complies with the AHB protocol specification is transmitted to the slave device 24 through the AHB bus. In addition, this embodiment does not limit the connection method between the master device 21 and the interface IP core.

[0085] After the master device 21 sends the first data information to the FIFO memory 22, the FIFO memory 22 is used to receive and cache the first data information sent by the master device 21; the controller 23 receives the first data information stored in the FIFO memory 22, converts the first data information into the AHB protocol standard format, and sends the converted first data information to the slave device 24.

[0086] In addition, after the first data information is transmitted to the slave device 24, if the slave device 24 needs to return the data information to the master device 21, this embodiment provides a preferred solution.

[0087] The FIFO memory 22 is also used to: receive and buffer the second data information returned from the device 24;

[0088] The controller 23 is further configured to receive the second data information stored in the FIFO memory 22 , and send the second data information to the master device 21 .

[0089] When the slave device 24 returns the second data information to the FIFO memory 22 , the FIFO storage receives and caches the second data information returned by the slave device 24 ; the controller 23 receives the second data information stored in the FIFO memory 22 , and sends the second data information to the master device 21 .

[0090] This embodiment provides a preferred solution, in which the interface IP core receives the second data information returned from the device 24 and completes the data information return operation.

[0091] The interface IP core provided in the present application receives and caches the first data information sent by the master device 21 through the FIFO memory 22, and the controller 23 converts the received first data information into the AHB protocol standard format, and sends the format-converted first data information to the slave device 24. The interface IP core provided in the present application outputs data information in the AHB protocol standard format, and there is no need to configure the interface IP core separately for AHB protocol conversion.

[0092] According to the above embodiment, when the interface IP core performs a read operation, this embodiment provides a preferred solution: Figure 3 A schematic diagram of a FIFO memory provided in an embodiment of the present application; Figure 3 As shown, the FIFO memory 22 includes: a read FIFO 223, a control information FIFO 221;

[0093] The control information FIFO 221 is used to receive and cache read instructions and read control information;

[0094] The read FIFO 223 is used to receive and buffer the read data and the read response signal;

[0095] The controller 23 is used to: when the read FIFO 223 is not empty, read the read data and the read response signal from the read FIFO 223 and return them to the master device 21.

[0096] The read FIFO 223 is used to cache the read data and response signals returned by the slave device 24 ; the control information FIFO 221 is used to cache the read instructions and read control information sent by the master device 21 .

[0097] When the master device 21 sends a read instruction and read control information to the interface IP core, the control information FIFO 221 receives and caches the read instruction and read control information, and the controller 23 FIFO converts the read instruction and read control information into the AHB protocol standard format according to the AHB protocol and transmits it to the slave device 24; the slave device 24 returns the read data and read response signal, and the read FIFO 223 receives and caches the read data and read response signal. When the read FIFO 223 is not empty, the controller 23 reads the read data and read response signal from the read FIFO 223 and returns it to the master device 21.

[0098] This embodiment provides an interface IP core, and the controller 23 converts the read instruction and the read control information into the AHB protocol standard format and sends them to the slave device 24, thereby avoiding the need for the ordinary interface IP core to separately configure the AHB protocol conversion for the interface IP core.

[0099] According to the above embodiment, when the interface IP core is used to perform a write operation, this embodiment provides a preferred solution, the FIFO memory 22 includes: a write FIFO 222;

[0100] The control information FIFO 221 is also used to: receive and cache write instructions and write control information;

[0101] Write FIFO 222 is used to receive and cache write data;

[0102] The controller 23 is used to: when the write FIFO 222 is not empty, read the write data and send it to the slave device 24; when the write FIFO 222 is empty, wait for the write FIFO 222 to be not empty and then read the write data and send it to the slave device 24.

[0103] The write FIFO 222 is used to receive and buffer the write data information sent by the master device 21 .

[0104] When a write operation is required, the master device 21 sends write instructions, write control information and write data to the interface IP core, the control information FIFO221 receives and caches the write instructions and write control information; the write FIFO222 receives and caches the write data; the controller 23 converts the write data into the AHB protocol standard format according to the AHB protocol; when the write FIFO222 is not empty, the write data is read out and sent to the slave device 24; when the write FIFO222 is empty, the write data is read out and sent to the slave device 24 when the write FIFO222 is empty.

[0105] This embodiment provides an interface IP core when performing a write operation. The controller 23 converts the write data into the AHB protocol standard format and sends it to the slave device 24, avoiding the need for the ordinary interface IP core to configure the AHB protocol conversion separately for the interface IP core.

[0106] According to the above embodiment, this embodiment provides a preferred embodiment, the interface IP core is connected to the slave device 24 JPEG module via the AHB bus,

[0107] The controller 23 is connected to the JPEG module and is used to send the converted first data information to the JPEG module.

[0108] When the JPEG module needs to be debugged on FPGA, the JPEG module registers are read and written through the interface IP core provided by this application to complete the JPEG configuration. Since there is no need to configure the AHB protocol conversion for the interface IP core separately, the debugging speed is accelerated, labor is saved, and the debugging cycle is shortened.

[0109] In addition, it should be noted that the controller 23 mentioned in this embodiment is mainly implemented through a state machine, including 6 states: FIDLE, BUSREQ, ADDR, RD_DATA, WR_DATA, and FRETRY.

[0110] The status is described as follows:

[0111] FIDLE: Idle state, the default state after the interface IP core is reset. When the master device 21 does not send any instructions or all instructions sent by the master device 21 are executed, it returns to this state; when the master device 21 sends instructions and the control FIFO is not full, it enters the BUSREQ state;

[0112] BUSREQ: Request bus status, apply for bus control to the arbiter through the m_hbusreq signal, and enter the ADDR state after obtaining bus control;

[0113] ADDR: address segment state, sending the starting address and control signal to the slave device 24. When the master device 21 sends a read command and the read FIFO 223 is not full, it enters the RD_DATA state. When the master device 21 sends a write command and the write FIFO 222 is not empty, it enters the WR_DATA state.

[0114] RD_DATA: Read data state. According to the received control information, control the address and htrans changes, receive the data and response from the slave end. When the last data of the instruction is received, it enters the FIDLE state. When the slave device responds with RETRY, it enters the FRETRY state.

[0115] WR_DATA: write data state, according to the received control information, control address and htrans changes, send data to the slave end, when the last data of the instruction is sent, enter the FIDLE state, when the slave device responds to RETRY, enter the FRETRY state;

[0116] FRETRY: Retry state. In this state, the data at the RETRY address will be re-read and written. After two clock cycles, the bus transmission operation will be restarted and the RD_DATA state or WR_DATA state will be entered.

[0117] The main signals of the master device 21-side interface are as follows:

[0118]

[0119] Figure 4 The timing diagram of the master device performing a write operation provided in this application is as follows: Figure 4 As shown, the control information FIFO 221 and the write FIFO 222 use independent full signals. When the control information is valid and the control information FIFO 221 is not full, the control information (l_addr, l_burst, l_size, l_length) on the master device 21 side is placed in the control information FIFO 221. When the data is valid and the write data FIFO is not full, the data to be sent by the master device 21 side is placed in the write data FIFO in sequence.

[0120] Figure 5 The timing diagram of the master device performing a read operation provided by this application is as follows: Figure 5 As shown, the master device 21 only needs to send control information for the read operation. The l_resp signal is a read response signal returned to the master device 21, which is output after being cached by the read data FIFO and is synchronized with the returned data l_rdata. One data on the AHB bus corresponds to one response signal.

[0121] In the above embodiments, the interface IP core control method is described in detail, and the present application also provides an embodiment corresponding to the interface IP core control device. It should be noted that the present application describes the embodiments of the device part from two perspectives, one is based on the functional module perspective, and the other is based on the hardware perspective.

[0122] Figure 6 This is a structural diagram of an interface IP core control device provided in an embodiment of the present application. The present application also provides an interface IP core control device, including:

[0123] The receiving module 61 is used to receive the first data information stored in the FIFO memory, and the first data information is sent to the FIFO memory by the master device;

[0124] A conversion module 62, configured to convert the first data information into an AHB protocol standard format;

[0125] The sending module 63 is used to send the converted first data information to the slave device.

[0126] The receiving module 61 receives the first data information stored in the FIFO memory, and the first data information is sent from the master device to the FIFO memory; the converting module 62 converts the first data information into the AHB protocol standard format; and the sending module 63 sends the converted first data information to the slave device.

[0127] The interface IP core control device provided in the present application outputs data information in the AHB protocol standard format, and there is no need to configure the interface IP core separately for AHB protocol conversion.

[0128] Since the embodiments of the apparatus part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the apparatus part, which will not be repeated here.

[0129] Figure 7 A structural diagram of an interface IP core control device provided in another embodiment of the present application is shown in FIG. Figure 7 As shown, the interface IP core control device includes: a memory 70 for storing computer programs;

[0130] The processor 71 is used to implement the steps of the method for obtaining user operation habit information in the above embodiment (interface IP core control method) when executing a computer program.

[0131] The interface IP core control device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer, or a desktop computer.

[0132] Among them, the processor 71 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 71 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 71 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 71 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 71 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0133] The memory 70 may include one or more computer-readable storage media, which may be non-transitory. The memory 70 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 70 is at least used to store the following computer program 701, wherein, after the computer program is loaded and executed by the processor 71, it can implement the relevant steps of the XXXXXXX method disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 70 may also include an operating system 702 and data 703, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 702 may include Windows, Unix, Linux, etc. Data 703 may include but is not limited to data involved in implementing the interface IP core control method, etc.

[0134] In some embodiments, the interface IP core control device may also include a display screen 72 , an input / output interface 73 , a communication interface 74 , a power supply 75 , and a communication bus 76 .

[0135] Those skilled in the art will understand that Figure 7 The structure shown in the figure does not constitute a limitation on the interface IP core control device, and may include more or fewer components than those shown in the figure.

[0136] The interface IP core control device provided in the embodiment of the present application includes a memory and a processor. When the processor executes the program stored in the memory, it can implement the following method: the interface IP core control method receives and caches the first data information sent by the master device 21, converts the received first data information into the AHB protocol standard format, and sends the format-converted first data information to the slave device 24. Because the output data information is in the AHB protocol standard format, there is no need to configure the interface IP core separately for AHB protocol conversion.

[0137] Finally, the present application also provides an embodiment corresponding to a computer-readable storage medium. A computer program is stored on the computer-readable storage medium, and when the computer program is executed by the processor, the steps described in the above method embodiment (which may be a method corresponding to the server side, a method corresponding to the diagnostic device side, or a method corresponding to both the server side and the diagnostic device side) are implemented.

[0138] It is understandable that if the method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0139] The computer-readable storage medium provided in this embodiment stores a computer program, and when the processor executes the program, the following method can be implemented: the interface IP core control method receives and caches the first data information sent by the master device 21, converts the received first data information into the AHB protocol standard format, and sends the format-converted first data information to the slave device 24. Because the output data information is in the AHB protocol standard format, there is no need to configure the interface IP core separately for AHB protocol conversion.

[0140] The above is a detailed introduction to an interface IP core control method, an interface IP core, a device and a medium provided by the present application. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can refer to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0141] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. An interface IP core control method, characterized in that: The interface IP core includes a FIFO memory, a controller, a master device and a slave device are connected through the interface IP core, and the slave device and the interface IP core are connected through an AHB bus; the FIFO memory includes a control information FIFO, a write FIFO and a read FIFO; Interface IP cores are used in data exchange systems; including: Receiving first data information stored in a FIFO memory, wherein the first data information is sent to the FIFO memory by a master device; Converting the first data information into an AHB protocol standard format; Sending the converted first data information to the slave device; The first data information includes: read instructions and read control information; The master device sends a read instruction and read control information to the FIFO memory, and the controller converts the read instruction and read control information into the AHB protocol standard format and sends it to the slave device; The first data information includes: write instructions, write control information and write data; The master device sends write instructions, write control information and write data to the FIFO memory, and the controller converts the write data into the AHB protocol standard format; Correspondingly, sending the converted first data information to the slave device includes: When the write FIFO is not empty, the converted write data is read out and sent to the slave device; when the write FIFO is empty, the write data is read out and sent to the slave device when the write FIFO is not empty; After sending the converted first data information to the slave device, the method further includes: receiving second data information stored in the FIFO memory, the second data information being returned by the slave device to the FIFO memory; Sending the second data information to the master device; The second data information includes read data and a read response signal; The sending the second data information to the master device comprises: when the read FIFO is not empty, reading out the read data and the read response signal and returning them to the master device; Among them, the controller is implemented through a state machine, including 6 states: FIDLE, BUSREQ, ADDR, RD_DATA, WR_DATA, FRETRY; The FIDLE state represents the idle state, which is the default state after the interface IP core is reset. When the master device does not send any instructions or all the instructions sent by the master device are executed, it returns to this state; when the master device sends instructions and the control FIFO is not full, it enters the BUSREQ state; The BUSREQ state is used to indicate the request bus state. The arbiter is requested to control the bus through the m_hbusreq signal. After obtaining the bus control, the ADDR state is entered. The ADDR state is used to represent the address segment state, sending the starting address and control signal to the slave device. When the master device sends a read command and the read FIFO is not full, it enters the RD_DATA state. When the master device sends a write command and the write FIFO is not empty, it enters the WR_DATA state. The RD_DATA state is used to represent the read data state. According to the received control information, the control address and htrans change, the slave end data and response are received. When the last data of the instruction is received, the FIDLE state is entered. When the slave end responds with RETRY, the FRETRY state is entered. The WR_DATA state is used to represent the write data state. According to the received control information, the control address and htrans change, data is sent to the slave end. When the last data of the instruction is sent, it enters the FIDLE state. When the slave device responds with RETRY, it enters the FRETRY state. The FRETRY state is used to represent the retry state. In this state, the data at the RETRY address will be re-read and written. After two clock cycles, the bus transmission operation will be restarted and the RD_DATA state or WR_DATA state will be entered. When the master device performs a write operation, the control information FIFO and the write FIFO use independent full signals. When the control information is valid and the control information FIFO is not full, the control information of the master device is placed in the control information FIFO. When the data is valid and the write data FIFO is not full, the data to be sent by the master device is placed in the write data FIFO in sequence. The control information of the master device includes: instruction operation address, burst transmission type signal, number of bytes transmitted at one time, and length of write / read data. When the master device performs a read operation, the master device only needs to send control information. The l_resp signal is the read response signal returned to the master device. It is output after being cached by the read data FIFO and is synchronized with the returned data l_rdata. One data on the AHB bus corresponds to one response signal.

2. The interface IP core control method according to claim 1, characterized in that: The step of sending the converted first data information to a slave device includes: The converted first data information is sent to the JPEG module.

3. An interface IP core, characterized in that: The interface IP core contains FIFO memory and controller. The master device and the slave device are connected through the interface IP core, and the slave device and the interface IP core are connected through the AHB bus. Interface IP cores are used in data exchange systems; including: FIFO memory, controller; the FIFO memory includes a control information FIFO, a write FIFO and a read FIFO; The FIFO memory is used to receive and buffer the first data information sent by the master device; The controller is used to receive the first data information stored in the FIFO memory, convert the first data information into an AHB protocol standard format, and send the converted first data information to the slave device; the first data information includes: write instructions, write control information and write data; The first data information includes: read instructions and read control information; The master device sends a read instruction and read control information to the FIFO memory, and the controller converts the read instruction and read control information into the AHB protocol standard format and sends it to the slave device; The master device sends write instructions, write control information and write data to the FIFO memory, and the controller converts the write data into the AHB protocol standard format; Correspondingly, sending the converted first data information to the slave device includes: When the write FIFO is not empty, the converted write data is read out and sent to the slave device; when the write FIFO is empty, the write data is read out and sent to the slave device when the write FIFO is not empty; The FIFO memory is also used to: receive and cache the second data information returned by the slave device; The controller is further configured to: receive the second data information stored in the FIFO memory, and send the second data information to the master device; The second data information includes read data and a read response signal; The sending the second data information to the master device comprises: when the read FIFO is not empty, reading out the read data and the read response signal and returning them to the master device; Among them, the controller is implemented through a state machine, including 6 states: FIDLE, BUSREQ, ADDR, RD_DATA, WR_DATA, FRETRY; The FIDLE state represents the idle state, which is the default state after the interface IP core is reset. When the master device does not send any instructions or all the instructions sent by the master device are executed, it returns to this state; when the master device sends instructions and the control FIFO is not full, it enters the BUSREQ state; The BUSREQ state is used to indicate the request bus state. The arbiter is requested to control the bus through the m_hbusreq signal. After obtaining the bus control, the ADDR state is entered. The ADDR state is used to represent the address segment state, sending the starting address and control signal to the slave device. When the master device sends a read command and the read FIFO is not full, it enters the RD_DATA state. When the master device sends a write command and the write FIFO is not empty, it enters the WR_DATA state. The RD_DATA state is used to represent the read data state. According to the received control information, the control address and htrans change, the slave end data and response are received. When the last data of the instruction is received, the FIDLE state is entered. When the slave end responds with RETRY, the FRETRY state is entered. The WR_DATA state is used to represent the write data state. According to the received control information, the control address and htrans change, data is sent to the slave end. When the last data of the instruction is sent, it enters the FIDLE state. When the slave device responds with RETRY, it enters the FRETRY state. The FRETRY state is used to represent the retry state. In this state, the data at the RETRY address will be re-read and written. After two clock cycles, the bus transmission operation will be restarted and the RD_DATA state or WR_DATA state will be entered. When the master device performs a write operation, the control information FIFO and the write FIFO use independent full signals. When the control information is valid and the control information FIFO is not full, the control information of the master device is placed in the control information FIFO. When the data is valid and the write data FIFO is not full, the data to be sent by the master device is placed in the write data FIFO in sequence. The control information of the master device includes: instruction operation address, burst transmission type signal, number of bytes transmitted at one time, and length of write / read data. When the master device performs a read operation, the master device only needs to send control information. The l_resp signal is the read response signal returned to the master device. It is output after being cached by the read data FIFO and is synchronized with the returned data l_rdata. One data on the AHB bus corresponds to one response signal.

4. An interface IP core control device, characterized in that: The interface IP core includes a FIFO memory, a controller, a master device and a slave device are connected through the interface IP core, and the slave device and the interface IP core are connected through an AHB bus; the FIFO memory includes a control information FIFO, a write FIFO and a read FIFO; Interface IP cores are used in data exchange systems; including: A receiving module, used for receiving first data information stored in the FIFO memory, wherein the first data information is sent to the FIFO memory by the master device; A conversion module, used for converting the first data information into an AHB protocol standard format; A sending module, used for sending the converted first data information to a slave device; The first data information includes: write instructions, write control information and write data; The first data information includes: read instructions and read control information; The master device sends a read instruction and read control information to the FIFO memory, and the controller converts the read instruction and read control information into the AHB protocol standard format and sends it to the slave device; The master device sends write instructions, write control information and write data to the FIFO memory, and the controller converts the write data into the AHB protocol standard format; Correspondingly, the sending module is specifically used for, when the write FIFO is not empty, reading out the converted write data and sending it to the slave device; when the write FIFO is empty, waiting for the write FIFO to be not empty and then reading out the write data and sending it to the slave device; After sending the converted first data information to the slave device, the method further includes: receiving second data information stored in the FIFO memory, the second data information being returned by the slave device to the FIFO memory; Sending the second data information to the master device; The second data information includes read data and a read response signal; The sending the second data information to the master device comprises: when the read FIFO is not empty, reading out the read data and the read response signal and returning them to the master device; Among them, the controller is implemented through a state machine, including 6 states: FIDLE, BUSREQ, ADDR, RD_DATA, WR_DATA, FRETRY; The FIDLE state represents the idle state, which is the default state after the interface IP core is reset. When the master device does not send any instructions or all the instructions sent by the master device are executed, it returns to this state; when the master device sends instructions and the control FIFO is not full, it enters the BUSREQ state; The BUSREQ state is used to indicate the request bus state. The arbiter is requested to control the bus through the m_hbusreq signal. After obtaining the bus control, the ADDR state is entered. The ADDR state is used to represent the address segment state, sending the starting address and control signal to the slave device. When the master device sends a read command and the read FIFO is not full, it enters the RD_DATA state. When the master device sends a write command and the write FIFO is not empty, it enters the WR_DATA state. The RD_DATA state is used to represent the read data state. According to the received control information, the control address and htrans change, the slave end data and response are received. When the last data of the instruction is received, the FIDLE state is entered. When the slave end responds with RETRY, the FRETRY state is entered. The WR_DATA state is used to represent the write data state. According to the received control information, the control address and htrans change, data is sent to the slave end. When the last data of the instruction is sent, it enters the FIDLE state. When the slave device responds with RETRY, it enters the FRETRY state. The FRETRY state is used to represent the retry state. In this state, the data at the RETRY address will be re-read and written. After two clock cycles, the bus transmission operation will be restarted and the RD_DATA state or WR_DATA state will be entered. When the master device performs a write operation, the control information FIFO and the write FIFO use independent full signals. When the control information is valid and the control information FIFO is not full, the control information of the master device is placed in the control information FIFO. When the data is valid and the write data FIFO is not full, the data to be sent by the master device is placed in the write data FIFO in sequence. The control information of the master device includes: instruction operation address, burst transmission type signal, number of bytes transmitted at one time, and length of write / read data. When the master device performs a read operation, the master device only needs to send control information. The l_resp signal is the read response signal returned to the master device. It is output after being cached by the read data FIFO and is synchronized with the returned data l_rdata. One data on the AHB bus corresponds to one response signal.

5. An interface IP core control device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the interface IP core control method as claimed in claim 1 or 2 when executing the computer program.

6. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the interface IP core control method according to claim 1 or 2 are implemented.

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