Memristor array structure and method of operating the same, neural network sparsification apparatus

Abstract

The disclosure provides a memristor array structure and an operating method thereof and a neural network sparsification device. The memristor array structure comprises a plurality of structure sub-arrays, each of the plurality of structure sub-arrays comprises a plurality of memristor units, a plurality of first transistor units and a plurality of second transistor units. The plurality of memristor units are arranged in a distributed manner to form a memristor array, the plurality of first transistor units are respectively connected to the plurality of memristor units at both ends of the memristor array in a first direction, and the plurality of second transistor units are respectively connected to the plurality of memristor units at the other two ends of the memristor array in a second direction. In the first direction, the plurality of first transistor units are respectively connected to the adjacent memristor arrays at both ends of the memristor array, and in the second direction, the plurality of second transistor units are respectively connected to the adjacent memristor arrays at the other two ends of the memristor array.

Description

Technical Field

[0001] This disclosure relates to the fields of semiconductor devices and integrated circuits, and in particular to a highly integrated memristor array structure suitable for sparse matrix multiplication and addition operations, its operation method, and a neural network sparsification device. Background Technology

[0002] In-memory computing, a non-von Neumann architecture, significantly reduces the amount of data moved during logic operations by utilizing the in-memory computing capabilities of devices or circuits. This improves hardware efficiency and reduces power consumption, and it is widely considered a hardware acceleration method for deep learning algorithms. Memristors are fundamental functional devices for implementing in-memory computing architectures, possessing characteristics such as low power consumption and high computational density. The cross-array structure based on memristors enables highly parallel vector-matrix multiplication-addition (VMM) operations, forming the hardware foundation for accelerating deep learning algorithms. Summary of the Invention

[0003] (a) Technical problems to be solved

[0004] To address at least one of the technical problems existing in the implementation of sparse deep neural networks in the prior art, this disclosure provides a memristor array structure and its operation method for sparse matrix multiplication and addition operations, as well as a neural network sparsification device.

[0005] (II) Technical Solution

[0006] One aspect of this disclosure provides a memristor array structure, comprising multiple structural subarrays, each subarray including multiple memristor units, multiple first transistor units, and multiple second transistor units. The multiple memristor units are distributed and arranged to form a memristor array. The multiple first transistor units are respectively connected in a first direction to multiple memristor units at both ends of the memristor array; the multiple second transistor units are respectively connected in a second direction to multiple memristor units at the other ends of the memristor array; wherein, in the first direction, the multiple first transistor units are respectively connected to adjacent memristor arrays at both ends of the memristor array; and in the second direction, the multiple second transistor units are respectively connected to adjacent memristor arrays at the other ends of the memristor array.

[0007] According to embodiments of this disclosure, a memristor array includes a plurality of first subarrays or a plurality of second subarrays. The plurality of first subarrays are arranged sequentially in a second direction; the plurality of second subarrays are arranged sequentially in a first direction; wherein the number of memristor cells in the plurality of first subarrays, the number of memristor cells in the plurality of second subarrays, and the number of memristor cells in the memristor array are equal.

[0008] According to embodiments of this disclosure, each of a plurality of memristor cells includes a top electrode, a bottom electrode, and a dielectric layer. The top electrode is connected to a first word line of a corresponding first subarray in a first direction; the bottom electrode is connected to a first word line of a corresponding second subarray in a second direction; the dielectric layer is located between the top electrode and the bottom electrode to realize resistive switching of each memristor cell.

[0009] According to embodiments of this disclosure, each of the plurality of first transistor units includes a gate, a source, and a drain. The gate is connected to a second word line of a corresponding first subarray in a first direction; the source is connected to a first word line of a corresponding first subarray in a first direction, or to another first word line of a corresponding first subarray in an adjacent memristor array in a first direction; the drain is connected to another first word line of a corresponding first subarray in an adjacent memristor array in a first direction, or to a first word line of a corresponding first subarray in a first direction.

[0010] According to embodiments of this disclosure, each of the plurality of second transistor units includes a gate, a source, and a drain. The gate is connected to a second bit line of a corresponding second subarray in a second direction; the source is connected to a first bit line of a corresponding second subarray in a second direction, or to another first bit line of a corresponding second subarray in an adjacent memristor array in a second direction; the drain is connected to another first bit line of a corresponding second subarray in an adjacent memristor array in a second direction, or to a first bit line of a corresponding second subarray in a second direction.

[0011] Another aspect of this disclosure provides a method for operating the above-described memristor array structure, comprising: selecting at least one memristor cell in the memristor array; performing a read operation or a write operation on the selected at least one memristor cell to control at least one memristor cell to undergo resistance change.

[0012] According to embodiments of the present disclosure, in at least one memristor cell in a gated memristor array, the method includes: applying an enable voltage to a second word line and a second bit line where the at least one memristor cell is located, and grounding the other second word line and second bit line.

[0013] According to embodiments of this disclosure, before performing a read or write operation on at least one selected memristor cell, the method further includes: applying a read signal or a write signal to the first word line and the first bit line where the at least one memristor cell is located, and placing the other first word line and the first bit line in a floating state.

[0014] According to embodiments of this disclosure, performing a read or write operation on at least one selected memristor cell includes: applying a read voltage to a first word line where at least one memristor cell is located, and reading a current value or voltage value corresponding to the read voltage through the first word line where the cell is located; or applying a read voltage to the first word line where at least one memristor cell is located, and reading a current value or voltage value corresponding to the read voltage through the first word line where the cell is located.

[0015] According to embodiments of this disclosure, performing a read or write operation on at least one selected memristor cell includes: applying a first programming voltage to a first word line where the at least one memristor cell is located, and grounding the first word line; or applying a second programming voltage to the first word line where the at least one memristor cell is located, and grounding the first word line; wherein the first programming voltage and the second programming voltage are opposite in direction and equal in magnitude.

[0016] Another aspect of this disclosure provides a neural network sparsification device, wherein the device is implemented based on the memristor array structure described above.

[0017] (III) Beneficial Effects

[0018] This disclosure provides a memristor array structure and its operation method for sparse matrix multiplication and addition operations, as well as a neural network sparsification device. The memristor array structure includes multiple subarrays, each subarray comprising multiple memristor units, multiple first transistor units, and multiple second transistor units. The multiple memristor units are distributed to form a memristor array. The multiple first transistor units are connected in a first direction to the memristor units at both ends of the memristor array, respectively. The multiple second transistor units are connected in a second direction to the memristor units at the other ends of the memristor array, respectively. Specifically, in the first direction, the multiple first transistor units are connected to adjacent memristor arrays at both ends of the memristor array; in the second direction, the multiple second transistor units are connected to adjacent memristor arrays at the other ends of the memristor array. Based on the embodiments of this disclosure, the above-described memristor array structure can adapt to multiplication and addition operations of coefficient matrices and vectors with low local crosstalk characteristics while ensuring the operational accuracy of sparse matrix multiplication and addition operations. Furthermore, it improves the integration density of the memristor array by reducing the number of gated transistors within the array. Attached Figure Description

[0019] Figure 1A A schematic diagram illustrating the composition of a memristor array structure according to an embodiment of the present disclosure is shown.

[0020] Figure 1B The diagram schematically illustrates a configuration of a memristor array according to an embodiment of the present disclosure (with one memristor cell selected);

[0021] Figure 1C The diagram schematically illustrates another compositional diagram of a memristor array according to an embodiment of the present disclosure (four memristor cells are selected);

[0022] Figure 2 A flowchart illustrating an operation method of a memristor array structure according to an embodiment of the present disclosure is shown schematically.

[0023] Figure 3 This diagram illustrates an application scenario of the weight mapping process for a memristor array structure according to an embodiment of the present disclosure.

[0024] Figure 4 A flowchart illustrating a method for generating a neural network weight matrix using a memristor array structure according to embodiments of the present disclosure is shown; and

[0025] Figure 5 The illustration shows a corresponding embodiment of the present disclosure. Figure 4 The diagram shows a sparse matrix of a neural network. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0027] It should be noted that implementations not illustrated or described in the accompanying drawings or the main text of the specification are all forms known to those skilled in the art and are not described in detail. Furthermore, the definitions of the various elements and methods described above are not limited to the specific structures, shapes, or methods mentioned in the embodiments, and those skilled in the art can easily modify or substitute them.

[0028] It should also be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings and are not intended to limit the scope of protection of this disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure.

[0029] Furthermore, the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are merely illustrative of embodiments of this disclosure. Additionally, any reference numerals placed between parentheses in the claims should not be construed as limiting the scope of the claims.

[0030] Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0031] The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify the corresponding elements does not in itself imply that the element has any ordinal number, nor does it represent the order of one element with another element or the order of manufacturing methods. The use of these ordinal numbers is only to enable a named element to be clearly distinguished from another element with the same name.

[0032] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose. Furthermore, in the unit claims enumerating several means, several of these means may be embodied by the same hardware item.

[0033] Similarly, it should be understood that, in order to simplify this disclosure and aid in understanding one or more of the various aspects of the disclosure, in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof. However, this approach to disclosure should not be construed as reflecting an intention that the claimed disclosure requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, the aspects of the disclosure consist of fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the disclosure.

[0034] When implementing sparse deep neural networks, existing technical solutions mainly have two major problems: First, although the 1R cross-array has the high integration advantage of 4F2, due to its crosstalk problem, the read / write accuracy and computation accuracy are difficult to guarantee, making it difficult to achieve large-scale matrix operations; Second, since each memristor requires a separate transistor to be selected, the integration of the 1T1R cross-array is not high, affecting the surface efficiency of the in-memory computing system.

[0035] To address at least one of the technical problems in existing sparse deep neural network implementations—namely, the crosstalk problem caused by 1R cross arrays and the limitation on matrix operation scale and low in-memory computing system efficiency due to the need for individual transistors for each memristor—this disclosure provides a memristor array structure and its operation method for sparse matrix multiplication and addition operations, as well as a neural network sparsification device. It provides a highly integrated memristor array structure capable of implementing sparse matrix multiplication and addition operations, and a neural network sparsification device adaptable to highly integrated memristor array structures.

[0036] like Figures 1A-1C As shown, one aspect of this disclosure provides a memristor array structure 100, which includes a plurality of structure subarrays, each of the plurality of structure subarrays including a plurality of memristor cells, a plurality of first transistor cells and a plurality of second transistor cells.

[0037] Multiple memristor cells are arranged in a distributed manner to form a memristor array.

[0038] Multiple first transistor units are respectively connected to multiple memristor units at both ends of the memristor array in a first direction;

[0039] Multiple second transistor units are respectively connected in the second direction to multiple memristor units at the other two ends of the memristor array;

[0040] In the first direction, multiple first transistor units are connected to adjacent memristor arrays at both ends of the memristor array; in the second direction, multiple second transistor units are connected to adjacent memristor arrays at the other two ends of the memristor array.

[0041] like Figure 1A The memristor array structure shown includes multiple structural subarrays A, B, C, and D, each of which can have the same number of memristor cells.

[0042] Taking the structure subarray A as an example, such as Figures 1A-1C As shown, the structural subarray A includes multiple memristor units M. 11 -M nn There are a total of n×n memristor cells. These memristor cells can be interconnected through corresponding word lines WL and bit lines BL, and are distributed in an array to form a memristor cell array, i.e., a memristor array.

[0043] In the first direction X, multiple first transistor units T 21 -T 2n Multiple memristor units M at one end of memristor array A 11 -M n1 One-to-one correspondence; simultaneously, multiple first transistor units T31 -T 3n Multiple memristor units M at the other end of the memristor array A 1n -M nn One-to-one correspondence.

[0044] In the second direction Y, multiple second transistor units T 11 -T 1n Multiple memristor units M at one end of memristor array A 11 -M 1n One-to-one connection; simultaneously, multiple second transistor units T 41 -T 4n Multiple memristor units M at the other end of the memristor array A n1 -M nn One-to-one correspondence.

[0045] Furthermore, in the first direction X, two adjacent memristor arrays A and B can share a column of first transistor cells T. 31 -T 3n Meanwhile, in the second direction Y, two adjacent memristor arrays A and C can share a column of second transistor units T. 41 -T 4n .

[0046] Therefore, based on the above-described memristor array structure of the present disclosure, the weight mapping matrix can be uniformly divided into sub-blocks of equal size. In the local space of the sub-block, there is only one non-zero element in the same row, thereby avoiding the read / write crosstalk problem caused by the 1R structure. Thus, some transistors in the 1T1R array can be omitted in the local space, greatly improving the integration of the memristor array.

[0047] Clearly, by utilizing the aforementioned memristor array structure, and by eliminating transistors within the memristor array while simultaneously reusing transistor units in the same column from adjacent memristor arrays, the number of gated transistor units within the array structure can be significantly reduced, thereby greatly improving the integration density of the memristor array. Furthermore, the aforementioned memristor array structure can simultaneously retain the original functionality of the transistor units and ensure the computational accuracy of the array structure, making it suitable for multiplying and adding sparse matrices and vectors with low local crosstalk characteristics. Therefore, the memristor array structure disclosed herein can achieve high integration density for sparse matrix multiplying and adding operations, and is suitable for neural network sparsification devices with high integration density memristor array structures.

[0048] like Figures 1A-1C As shown, according to embodiments of the present disclosure, the memristor array includes a plurality of first subarrays or a plurality of second subarrays.

[0049] Multiple first subarrays are arranged sequentially in the second direction; or

[0050] Multiple second subarrays are arranged sequentially in the first direction;

[0051] The number of memristor units in the multiple first subarrays, the number of memristor units in the multiple second subarrays, and the number of memristor units in the memristor array are all equal.

[0052] For memristor array A, in the second direction Y, the first subarray M 11 -M 1n First subarray M 21 -M 2n ...first subarray M n1 -M nn They are arranged sequentially to form a memristor array. Similarly, in the first direction X, the second subarray M... 11 -M n1 The second subarray M 12 -M n2 ...second subarray M 1n -M nn These elements are arranged sequentially to form a memristor array. The multiple first subarrays and multiple second subarrays are actually partitions of the memristor array according to different directions. Therefore, the number of memristor cells in the multiple first subarrays, the multiple second subarrays, and the memristor array itself are all equal, namely n×n memristor cells.

[0053] like Figures 1A-1C As shown, according to embodiments of the present disclosure, each of the plurality of memristor cells includes a top electrode, a bottom electrode, and a dielectric layer.

[0054] The top electrode is connected to the first word line of a corresponding first subarray in a first direction;

[0055] The bottom electrode is connected to the first line of a corresponding second subarray in the second direction;

[0056] The dielectric layer is located between the top and bottom electrodes and is used to achieve resistance switching for each memristor unit.

[0057] For a memristor cell M among multiple memristor cells in memristor array A 11 Specifically, its top electrode a is connected to a first word line WL1 disposed in the first direction X, and the first word line WL1 is used to connect the first subarray M in series. 11 -M 1n Each memristor cell in the array, and the first subarray M 11 -M 1nThe transistors T at both ends 21 and T 31 It is also connected to the first word line WL1.

[0058] Furthermore, the memristor unit M 11 The bottom electrode c is connected to the first line BL1 arranged in the second direction Y, and the first line BL1 is used to connect the second subarray M in series. 11 -M n1 Each memristor cell in the array, and the first subarray M 11 -M n1 The transistors T at both ends 11 and T 41 It is also connected to the first line BL1.

[0059] The memristor unit M 11 The dielectric layer b is disposed between the top electrode a and the bottom electrode c, when the memristor unit M 11 When a voltage signal is applied to the top electrode a and / or bottom electrode c, the memristor unit M 11 The dielectric layer b can undergo resistance changes, producing high and low resistance states, thereby realizing the memristor unit M. 11 The resistance change.

[0060] like Figures 1A-1C As shown, according to embodiments of the present disclosure, each of the plurality of first transistor units includes a gate, a source, and a drain.

[0061] The gate is connected to the second word line of a corresponding first subarray in a first direction;

[0062] The source is connected to the first word line of a corresponding first subarray in a first direction, or to another first word line of a corresponding first subarray in an adjacent memristor array in a first direction.

[0063] The drain is connected to another first word line in the first direction of a corresponding first subarray in an adjacent memristor array, or to the first word line in the first direction of a corresponding first subarray in a plurality of first subarrays.

[0064] For the first transistor unit, multiple first transistor units T 21 -T 2n With T 31 -T 3n A first transistor unit T 21 In terms of the first transistor unit T 21 The gate can be connected to a second word line WG1 disposed in the first direction X, the second word line WG1 being disposed corresponding to the first word line WL1, that is, connected to the first subarray M.11 -M 1n Correspondingly.

[0065] The first transistor unit T 21 The source is connected to the first subarray M 11 -M 1n On the first word line WL1 in the first direction X, or connected to another first word line in the first direction X of the corresponding first subarray in the adjacent memristor array. Figures 1A-1C (Not shown).

[0066] The first transistor unit T 21 The drain serves as the corresponding connection terminal to the source, and this drain is connected to another first word line of the corresponding first subarray in the adjacent memristor array in the first direction X. Figures 1A-1C (not shown), or connected to the first subarray M 11 -M 1n On the first word line WL1 in the first direction X.

[0067] In this way, in the first direction X, two adjacent memristor arrays can reuse a column of transistor cells located between them. That is, a first transistor cell between the first subarray of a memristor array and the corresponding first subarray of an adjacent memristor array can be shared by two adjacent first subarray memristor cells simultaneously. Therefore, the first transistor cell array between adjacent memristor arrays in the first direction X can simultaneously serve as the boundary between two memristor arrays. In other words, the number of gating transistor cells within the array structure is greatly reduced, thereby significantly improving the integration density of the array composed of memristor cells.

[0068] like Figures 1A-1C As shown, according to an embodiment of the present disclosure, each of the plurality of second transistor units includes a gate, a source, and a drain.

[0069] The gate is connected to the second bit line of a corresponding second subarray in a second direction;

[0070] The source is connected to the first line of a corresponding second subarray in the second direction, or to the other first line of a corresponding second subarray in the second direction in an adjacent memristor array.

[0071] The drain is connected to the first line of the corresponding second subarray in the second direction in the adjacent memristor array, or to the first line of the corresponding second subarray in the second direction in the second direction among multiple second subarrays.

[0072] For multiple second transistor units T of the second transistor unit 11 -T1n With T 41 -T 4n A second transistor unit T 11 Regarding the second transistor unit T 11 The gate can be connected to a second bit line BG1 disposed in the second direction Y, which corresponds to the first bit line BL1, i.e., is connected to the second subarray M. 11 -M n1 Correspondingly.

[0073] The first transistor unit T 11 The source is connected to the second subarray M 11 -M n1 On the first line BL1 in the second direction Y, or connected to the other first line of the corresponding second subarray in the adjacent memristor array in the second direction Y. Figures 1A-1C (Not shown).

[0074] The second transistor unit T 11 The drain serves as the corresponding connection terminal to the source, and this drain is connected to the other first line of the corresponding second subarray in the adjacent memristor array in the second direction Y. Figures 1A-1C (not shown), or connected to the second subarray M 11 -M n1 On the first line BL1 in the second direction Y.

[0075] Thus, in the second direction Y, adjacent memristor arrays can reuse a column of transistor cells located between them. Specifically, a second transistor cell between the second subarray of one memristor array and the corresponding second subarray of an adjacent memristor array can be shared by two adjacent second subarray memristor cells simultaneously. Therefore, the second transistor cell array between adjacent memristor arrays in the second direction can simultaneously serve as the boundary between two memristor arrays. This further significantly reduces the number of gating transistor cells within the array structure, thereby greatly improving the integration density of the memristor cell array.

[0076] Therefore, the memristor array structure described in this embodiment mainly consists of memristor units and transistor units. Locally, the 1R memristor units are arranged in an array, with electrodes at both ends of the memristor units led out. The top electrodes of memristor units in the same row are connected to each other via word lines WL, and the bottom electrodes of memristor units in the same column are connected via bit lines BL, thus forming a 1R cross-array structure. The word lines WL and bit lines BL led out from multiple 1R cross-array structures can also be connected to each other via the source and drain terminals of transistor units. The gate terminals of transistor units on the same word line WL (or bit line BL) are connected to each other and led out, forming a gating structure parallel to the word line WL (or bit line BL), corresponding to the word line WG (or bit line BG), thereby constituting a memristor-based array structure with large-scale expansion potential. The memristor units can be used to implement storage and computation functions, while the transistor units can be used to implement device gating and crosstalk suppression functions.

[0077] Since the integration level of the memristor array structure is an important performance indicator for evaluating memristor-type in-memory computing systems, by adopting the novel memristor array structure proposed in this invention, the memristor-type in-memory computing system can adapt to the multiplication and addition operations of sparse matrices and vectors with local low crosstalk characteristics while ensuring computational accuracy. This is achieved by reducing the number of gating transistors in the array and improving the integration level of the memristor array.

[0078] like Figure 2 As shown, another aspect of this disclosure provides a method for operating the above-described memristor array structure, which includes steps S201-S202.

[0079] In step S201, at least one memristor cell in the memristor array is selected;

[0080] In step S202, a read operation or a write operation is performed on at least one selected memristor cell to control at least one memristor cell to undergo a resistance change.

[0081] like Figure 1A As shown, the aforementioned memristor array structure 100 structurally utilizes memristor cells to locally construct a 1R cross array structure. Then, the rows (WL1-WL) of multiple 1R cross arrays are arranged... m ) and columns (BL1-BL m Multiple 1R cross arrays are interconnected using the source and drain terminals of transistor cells. The gate terminals of transistor cells in the same row or column with connected source and drain are interconnected and brought out, forming a row selector (WG1-WG). m ) and column gates (BG1-BG m )structure.

[0082] Based on the memristor array structure 100 described above, such as Figure 1B and Figure 1C As shown, using row selection (WG1-WG) m ) and column gates (BG1-BG m The structure selects and positions at least one memristor cell device, grounds the other unselected row and column select structures (i.e. connects to GND), applies read / write signals to the word line WL and bit line BL of the corresponding selected memristor cell device, and sets the other unselected word line WL and bit line BL to a floating state (i.e. connects to float), thereby realizing read and write operations on at least one memristor cell device.

[0083] This allows for read / write operations on at least one memristor cell.

[0084] like Figure 1A , Figure 1B and Figure 2 As shown, according to an embodiment of this disclosure, at least one memristor cell in a gated memristor array includes:

[0085] An enable voltage is applied to the second word line and the second bit line where at least one memristor cell is located, and the other second word lines and the second bit line are grounded.

[0086] First, the memristor cell to be operated needs to be selected.

[0087] Specifically, such as Figure 1B As shown, if we want to target the memristor unit M 2n Gating is performed in memristor unit M. 2n WG2 and BG in the same row and column n Simultaneously apply an on-state voltage (i.e., V) gae ), to turn on the memristor unit M 2n Transistor cell T in the row and column 22 T 32 T 1n and T 4n and WG1, WG3-WG in other columns n and BG1-BG n-1 Place it on ground (i.e., connect it to GND).

[0088] Accordingly, such as Figure 1C As shown, if we want to target the memristor unit M 11 M 12 M 21 and M 22 If gating is performed, then in memristor unit M 11 M 12 M 21 and M 22 A turn-on voltage (i.e., V) is simultaneously applied to WG1, WG2 and BG1, BG2 in the same row and column. gate), to turn on the memristor unit M 11 M 12 M 21 and M 22 Transistor cell T in the row and column 21 T 22 T 31 T 32 and T 11 T 12 T 41 T 42 and the other WG3-WG n and BG3-BG n Place it on ground (i.e., connect it to GND).

[0089] like Figure 1A , Figure 1B and Figure 2 As shown, according to embodiments of this disclosure, the method further includes performing a read or write operation on at least one selected memristor cell before:

[0090] A read signal or write signal is applied to the first word line and the first bit line where at least one memristor cell is located, and the other first word lines and the first bit line are placed in a floating state.

[0091] Then, read / write the memristor device.

[0092] Specifically, such as Figure 1B As shown, in the selected memristor unit M 2n A read signal or write signal (such as read voltage V) is applied to the word line WL2 of the corresponding row and the bit line BLn of the corresponding column. read At the same time, change the word lines WL1, WL3-WL in other rows and columns. n and bit line BL1-BL n-1 Place it in a floating state (i.e., connect it to float).

[0093] Similarly, such as Figure 1C As shown, for memristor unit M 11 M 12 M 21 and M 22 Read or write signals are applied to the corresponding word lines and bit lines, while other word lines and bit lines are placed in a floating state to prepare the read / write device. This should be understood by those skilled in the art, and will not be elaborated further.

[0094] like Figure 1A , Figure 1B and Figure 2 As shown, according to embodiments of this disclosure, performing a read or write operation on at least one selected memristor cell includes:

[0095] A read voltage is applied to the first word line containing at least one memristor cell, and the current or voltage value corresponding to the read voltage is read through the first bit line; or

[0096] A read voltage is applied to the first bit line of at least one memristor cell, and the current or voltage value corresponding to the read voltage is read through the first word line.

[0097] For read operations, such as Figure 1B As shown, in the selected memristor unit M 2n A read voltage signal (i.e., connected to V) is applied to the word line WL2 where the device is located. read ), and at the same time utilize this bit line BL n Read the memristor unit M 2n The current or voltage signal value of the device.

[0098] Additionally, for read operations, such as Figure 1B As shown, it can also be done in the selected memristor unit M. 2n Bit line BL where the device is located n Apply a read voltage signal (i.e., connect to V) read Simultaneously, the memristor unit M is read using the word line WL2. 2n The current or voltage signal value of the device.

[0099] Furthermore, such as Figure 1C As shown, for memristor unit M 11 M 12 M 21 and M 22 To perform a read operation, you can refer to the above description regarding the selected memristor unit M. 2n The device read operation is performed. This read process can be considered as utilizing the in-memory computing capabilities of the memristor array to perform vector-matrix multiplication operations on the array. Those skilled in the art should understand this, and further details are omitted.

[0100] The current signal value or voltage signal value is used to determine the memristor unit M. 2n The resistance of the device. Specifically, based on Kirchhoff's laws and Ohm's law, the vector-matrix product and result applied to this memristor array structure can be obtained.

[0101] like Figure 1A , Figure 1B and Figure 2 As shown, according to embodiments of this disclosure, performing a read or write operation on at least one selected memristor cell includes:

[0102] A first programming voltage is applied to the first word line containing at least one memristor cell, and the first bit line containing it is grounded; or

[0103] A second programming voltage is applied to the first bit line of at least one memristor cell, and the first word line is grounded.

[0104] The first programming voltage and the second programming voltage are opposite in direction and equal in magnitude.

[0105] For write operations, such as Figure 1B As shown, a programming signal (i.e., V) is applied to the word line WL2 where the selected memristor cell M2n is located. program Simultaneously, the corresponding bit line BLn is connected to GND, thereby forming the programmed memristor unit M. 2n The potential difference of the device controls the memristor unit M. 2n The device undergoes a resistance change.

[0106] Additionally, for write operations, such as Figure 1B As shown, in the selected memristor unit M 2n Bit line BL where the device is located n Apply another programming signal with the same value but opposite direction (i.e., -V) program Simultaneously, the word line WL2 is connected to GND, which also constitutes the memristor unit M that was programmed. 2n The potential difference of the device is used to control the memristor unit M. 2n The device undergoes a resistance change.

[0107] Furthermore, such as Figure 1C As shown, for memristor unit M 11 M 12 M 21 and M 22 To perform a write operation, you can refer to the above description regarding the selected memristor cell M. 2n The write operation to the device is performed. This should be understood by those skilled in the art, and will not be elaborated further.

[0108] As can be seen, by applying transistor turn-on voltage to the word line WG corresponding to the parallel input signal and the bit line BG corresponding to the parallel output, and applying the input signal to the word line WL, the current / voltage signal can be read on the output bit line BL to obtain the result of vector-matrix multiplication and addition operation.

[0109] Therefore, programming signals and GND are applied to the word line WL and bit line BL of the selected device, respectively, to form a potential difference that can be programmed for the memristor, thereby controlling the resistance change of the memristor and enabling precise operation of each memristor cell in the memristor array.

[0110] like Figures 1A-5 As shown, another aspect of this disclosure provides a neural network sparsification device, wherein the device is implemented based on the memristor array structure 100 described above.

[0111] like Figure 3 As shown, this neural network sparsification device realizes the process of neural network sparsification and sparse matrix weight mapping.

[0112] The first step is to divide the three-dimensional weight matrix Z (rows, columns, channels C) of the neural network into element groups R (including w) with fixed step sizes according to the row vectors. 21 -W 24 The different channels C of the weight matrix Z are independent of each other. The number of elements in the element group R must not exceed the number of rows in the submatrix of the memristor matrix.

[0113] The second step is to perform random sparsification on the element set R, so that the element set r1 contains at most one non-zero element w. 23 For example, sparsification in step S301.

[0114] The third step is to expand the three-dimensional weight matrix z1 into a two-dimensional matrix z2 along the row vectors, and then expand the column vector group r2 of the two-dimensional matrix z2 into a two-dimensional matrix z2. 23 The row vectors come from the same channel C but from different channels, as in step S302 for dimensionality reduction.

[0115] The fourth step is to map the two-dimensional matrix z2 into the memristor array structure 100, where the element group r2 corresponds to the column vector of the local 1R cross structure, thereby ensuring that within the same 1R cross array, the column vector contains at most one non-zero element, as in step S303.

[0116] Therefore, by using this neural network sparsification device based on the aforementioned memristor array structure, and employing multiple sparsity, format judgment, and retraining processes, the dense original weight matrix of the neural network can be sparsified to the point where no more than one non-zero element exists in the same column of local sub-blocks, while ensuring neural network performance. Thus, as... Figure 4 As shown, the neural network sparsification process of the neural network sparsification device in this embodiment of the present disclosure can be as follows:

[0117] The first step is to train the neural network based on the dense weight matrix structure and obtain the original weight matrix distribution. Specifically, the neural network structure and weight matrix can be initialized according to the rules of the deep learning algorithm and the actual task requirements. Then, the neural network is trained using the deep learning algorithm to obtain the original weight matrix, as shown in steps S401-S402.

[0118] The second step is randomized balanced sparsity, which involves randomly sparsifying a fixed number of matrix elements with a fixed step size, such as sparsifying 50% of the matrix elements. Specifically, the elements of the original weight matrix can be adjusted according to the above... Figure 3 The mapping rules shown are used to group elements with equal step sizes and then randomly sparsify them (e.g., 50% sparsification) within each element group to obtain the transition matrix, as shown in steps S402-S403.

[0119] The third step is to retrain the sparsed neural network to improve its performance. Specifically, the neural network based on the transition matrix is ​​retrained. By correcting the values ​​of the non-zero elements in the transition matrix, the performance loss caused by sparsity is reduced, as shown in steps S403-S404.

[0120] The fourth step is to determine the sparsity of the matrix to ensure that the sparse matrix, after being mapped to the 1R cross array (i.e., the memristor array structure 100 mentioned above), does not form a crosstalk loop. For sparse matrices that do not meet the requirements, steps S402-S404 are repeated until the sparsity requirement is met, thus completing the neural network sparsification process, as shown in step S405. To ensure adaptation to the memristor array structure, the sparsity step size must remain unchanged throughout the sparsification process. Specifically, in step S405, it is determined whether the transition matrix meets the sparsity requirement of having at most a single non-zero element within a group of elements. If it does, the sparse weight matrix is ​​output (as shown in steps S405-S406); otherwise, the transition matrix is ​​used as the original weight matrix, and steps S402-S404 are repeated.

[0121] like Figure 5 As shown, the neural network sparsification device based on the aforementioned memristor array structure can be adapted to a sparse matrix composed of multiple equal-sized two-dimensional matrix sub-blocks. The sub-blocks are located in the same column of the matrix, and each column within a sub-block contains at most one non-zero element, the positions of which can be randomly distributed. Furthermore, the column elements of this matrix represent the same weight matrix of the neural network, while the rows represent different weight matrices. Therefore, the sub-blocks correspond to a local 1R cross-array in the memristor array structure.

[0122] The embodiments of this disclosure have now been described in detail with reference to the accompanying drawings.

[0123] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A memristor array structure, wherein, It includes multiple structural subarrays, each of which includes: Multiple memristor units are arranged in a distributed manner to form a memristor array. Multiple first transistor units are respectively connected in a first direction to multiple memristor units at both ends of the memristor array; Multiple second transistor units are respectively connected in a second direction to multiple memristor units at the other two ends of the memristor array; In the first direction, the plurality of first transistor units are correspondingly connected to the adjacent memristor arrays at both ends of the memristor array; in the second direction, the plurality of second transistor units are correspondingly connected to the adjacent memristor arrays at the other two ends of the memristor array. The memristor array includes: a plurality of first subarrays arranged sequentially in the second direction; or a plurality of second subarrays arranged sequentially in the first direction; wherein the number of memristor units in the plurality of first subarrays, the number of memristor units in the plurality of second subarrays, and the number of memristor units in the memristor array are equal. Each of the plurality of first transistor units includes: a gate, connected to a second word line of a corresponding first subarray in a first direction; a source, connected to a first word line of a corresponding first subarray in a first direction, or connected to another first word line of a corresponding first subarray in a first direction in an adjacent memristor array; and a drain, connected to another first word line of a corresponding first subarray in a first direction in an adjacent memristor array, or connected to a first word line of a corresponding first subarray in a first direction in a first direction. Each of the plurality of second transistor units includes: a gate, connected to a second bit line of a corresponding second subarray in a second direction; a source, connected to a first bit line of a corresponding second subarray in a second direction, or connected to another first bit line of the corresponding second subarray in a second direction in an adjacent memristor array; and a drain, connected to another first bit line of the corresponding second subarray in a second direction in an adjacent memristor array, or connected to a first bit line of the corresponding second subarray in a second direction.

2. The memristor array structure according to claim 1, wherein, Each of the plurality of memristor units includes: The top electrode is connected to the first word line of a corresponding first subarray in the first direction; The bottom electrode is connected to the first line of a corresponding second subarray in the second direction; A dielectric layer, located between the top electrode and the bottom electrode, is used to realize the resistance switching of each memristor unit.

3. A method of operating a memristor array structure according to any one of claims 1-2, wherein, include: Select at least one memristor cell in the memristor array; Perform a read operation or a write operation on the selected memristor cell to control the resistance of the at least one memristor cell to change.

4. The operating method according to claim 3, wherein, At least one memristor cell in the gated memristor array includes: An enable voltage is applied to the second word line and the second bit line where the at least one memristor cell is located, and the other second word lines and the second bit lines are grounded.

5. The operating method according to claim 3, wherein, Before performing a read or write operation on the selected at least one memristor cell, the method further includes: A read signal or write signal is applied to the first word line and the first bit line where the at least one memristor cell is located, and the other first word lines and the first bit line are placed in a floating state.

6. The operating method according to claim 5, wherein, The process of performing a read or write operation on the selected at least one memristor cell includes: A read voltage is applied to the first word line containing the at least one memristor cell, and the current or voltage value corresponding to the read voltage is read through the first bit line; or A read voltage is applied to the first bit line of the at least one memristor unit, and the current or voltage value corresponding to the read voltage is read through the first word line.

7. The operating method according to claim 5, wherein, The process of performing a read or write operation on the selected at least one memristor cell includes: A first programming voltage is applied to the first word line containing the at least one memristor cell, and the first bit line is grounded; or A second programming voltage is applied to the first bit line where the at least one memristor cell is located, and the first word line where it is located is grounded; The first programming voltage and the second programming voltage are opposite in direction and equal in magnitude.

8. A neural network sparsification device, wherein, The device is implemented based on the memristor array structure according to any one of claims 1-2.

Images