Defect repair circuit and defect repair method

Abstract

The embodiment of the present application relates to a defect repair circuit and a defect repair method, wherein the defect repair circuit includes: a test module, which is used to perform a defect test on a memory cell array in a test mode to determine a defect memory cell, and output a test address information and a defect identification signal corresponding to the memory cell; a defect information storage module, which is connected to the test module, and is used to store defect address information in response to a defect identification signal, wherein the defect address information is the test address information of the defect memory cell, and is also used to output a first address information in response to an externally input repair selection signal, wherein the first address information is one of a plurality of defect address information; and a repair module, which is connected to the defect information storage module, and is used to repair the corresponding defect memory cell according to the received first address information. In this embodiment, the defect repair circuit can be compatible with a chip with a smaller area, and has higher convenience and reliability.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor device technology, and in particular, to a defect repair circuit and a defect repair method. Background Art

[0002] Memory is one of the most important memory storage components today. Due to its multiple functions and low manufacturing cost, it is widely used in computers, communications, home appliances and other fields.

[0003] Data storage reliability is a key performance of memory. Therefore, it is necessary to test the storage performance of the storage unit in the memory and repair the defective storage unit to ensure the storage performance of the memory. However, currently, it is necessary to rely on external test machine support to test and repair the storage unit, which leads to insufficient convenience and flexibility of repair. Summary of the invention

[0004] Based on this, it is necessary to provide a defect repair circuit and a defect repair method to address the problem of insufficient convenience and flexibility in repair.

[0005] A defect repair circuit, comprising:

[0006] A test module, used to perform a defect test on the memory cell array in a test mode to determine a defective memory cell, and output test address information and a defect identification signal corresponding to the memory cell;

[0007] a defect information storage module connected to the test module, and configured to store defect address information in response to the defect identification signal, wherein the defect address information is the test address information of the defect storage unit, and further configured to output first address information in response to an externally input repair selection signal, wherein the first address information is one of the plurality of defect address information;

[0008] A repair module is connected to the defect information storage module and is used to repair the corresponding defective storage unit according to the received first address information.

[0009] In one of the embodiments, the repair module is further used to receive second address information input from the outside, and repair the defective storage unit corresponding to the first address information or the second address information.

[0010] In one embodiment, it also includes:

[0011] The first selection circuit is connected to the defect information storage module and the repair module respectively, and is used to receive the first address information, the second address information and the repair selection signal, and generate target address information in response to the repair selection signal, and the target address information is one of the first address information and the second address information.

[0012] In one embodiment, the defect information storage module includes:

[0013] The identification bit storage unit is connected to the test module and the repair module respectively, and is used to generate and store corresponding identification bit information for the defect storage unit in response to the defect identification signal.

[0014] In one of the embodiments, the first selection circuit synchronously receives the first address information and the identification bit information corresponding to the defective storage unit.

[0015] In one of the embodiments, the defect information storage module further includes:

[0016] The address storage unit comprises N levels of address buffer memories, the N levels of address buffer memories are numbered from a first level address buffer memory to an Nth level address buffer memory in sequence, a clock end of the address buffer memory is used to receive the defect identification signal, a data input end of the first level address buffer memory is used to receive the test address information, an output end of the N-1th level address buffer memory is connected to a data input end of the Nth level address buffer memory, and N is an integer greater than or equal to 2;

[0017] The identification bit storage unit includes N levels of identification buffer memories, which are numbered in sequence from a first-level identification buffer memory to an N-th-level identification buffer memory, a clock end of the identification buffer memory receives the defect identification signal, a data input end of the first-level identification buffer memory is used to connect a preset level signal, and an output end of the N-1-th-level identification buffer memory is connected to a data input end of the N-th-level address buffer memory.

[0018] In one of the embodiments, the defect information storage module further includes:

[0019] a second selection circuit, wherein a control end of the second selection circuit is used to receive the repair selection signal, N input ends of the second selection circuit are connected to output ends of the N-level address buffer memory in a one-to-one correspondence, and an output end of the second selection circuit is used to output the first address information;

[0020] The third selection circuit, the control end of the third selection circuit is used to receive the repair selection signal, the N input ends of the third selection circuit are connected one-to-one with the output ends of the N-level identification buffer memory, and the output end of the third selection circuit is used to output the identification bit information.

[0021] A defect repair method, comprising:

[0022] Enter test mode;

[0023] The test module performs a defect test on the memory cell array to determine the defective memory cell, and outputs the test address information and the defect identification signal corresponding to the memory cell;

[0024] The defect information storage module stores defect address information in response to the defect identification signal, wherein the defect address information is test address information of the defect storage unit;

[0025] Exit the test mode and enter the repair mode;

[0026] The defect information storage module outputs first address information in response to an externally input repair selection signal, wherein the first address information is one of the plurality of defect address information;

[0027] A repair module repairs the corresponding defective storage unit according to the received first address information;

[0028] Exit the repair mode.

[0029] In one embodiment, before repairing the corresponding defective storage unit according to the received first address information, the method further includes:

[0030] Receiving second address information input from outside;

[0031] The repairing the corresponding defective storage unit according to the received first address information includes:

[0032] Repair the defective storage unit corresponding to the first address information or the second address information.

[0033] In one embodiment, the repairing the defective storage unit corresponding to the first address information or the second address information includes:

[0034] receiving the first address information, the second address information and the repair selection signal;

[0035] generating target address information in response to the repair selection signal, the target address information being one of the first address information and the second address information;

[0036] The defective storage unit is repaired according to the target address information.

[0037] In one embodiment, the outputting of the first address information in response to the externally input repair selection signal, wherein the first address information is one of the plurality of defect address information, further comprises:

[0038] In response to the defect identification signal, corresponding identification bit information is generated for the defective storage unit.

[0039] In one embodiment, the outputting of first address information in response to an externally input repair selection signal, wherein the first address information is one of a plurality of defect address information, includes:

[0040] The second selection circuit outputs the first address information in response to the repair selection signal;

[0041] The third selection circuit outputs the identification bit information in response to the repair selection signal;

[0042] Wherein, the first address information and the identification bit information are output synchronously.

[0043] The above-mentioned defect repair circuit and defect repair method, the defect repair circuit includes: a test module, which is used to perform defect test on the memory cell array in the test mode to determine the defect memory cell, and output the test address information and defect identification signal corresponding to the memory cell; a defect information storage module, which is connected to the test module, and is used to store defect address information in response to the defect identification signal, the defect address information is the test address information of the defect memory cell, and is also used to output first address information in response to an externally input repair selection signal, the first address information is one of the multiple defect address information; a repair module, which is connected to the defect information storage module, and is used to repair the corresponding defect memory cell according to the received first address information. Through the built-in test module and repair module in the memory, the repair operation can be performed based on its own hardware structure. Moreover, the repair module in the defect repair circuit of this embodiment can reuse the structure and function of the packaged repair circuit, and automatically store the wrong address through the added test module, so as to perform intelligent repair together. In this embodiment, the defect repair circuit has few newly added circuit structures, so it can be compatible with chips with smaller areas, and the tester and controller are not required to store the addresses of defective storage units, thereby enhancing the convenience and reliability of the defect repair circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a schematic structural diagram of a defect repair circuit according to a first embodiment;

[0045] Figure 2 is a schematic structural diagram of a defect repair circuit according to a second embodiment;

[0046] Figure 3 is a schematic structural diagram of a defect repair circuit according to a third embodiment;

[0047] Figure 4 is a schematic structural diagram of a defect repair circuit according to a fourth embodiment;

[0048] Figure 5 is a schematic structural diagram of a defect repair circuit according to a fifth embodiment;

[0049] Figure 6 A schematic diagram of the structure of an address storage unit and a flag bit storage unit according to an embodiment;

[0050] Figure 7 is a schematic structural diagram of a defect repair circuit according to a sixth embodiment;

[0051] Figure 8 is a schematic structural diagram of a second selection circuit according to an embodiment;

[0052] Fig. 9 is a schematic structural diagram of a third selection circuit according to an embodiment;

[0053] Fig.10 is a flow chart of a defect repair method according to an embodiment;

[0054] Fig.11 A flowchart of a defect repair method according to another embodiment;

[0055] Fig.12 is a flow chart of step S610 of an embodiment;

[0056] Fig.13 FIG. 5 is a flow chart of step S500 of an embodiment.

[0057] Component number description:

[0058] Test module: 100; defect information storage module: 200; address storage unit: 210; address buffer memory: 211; identification bit storage unit: 220; identification buffer memory: 221; second selection circuit: 230; third selection circuit: 240; repair module: 300; storage unit array: 400; first selection circuit: 500 DETAILED DESCRIPTION

[0059] In order to facilitate understanding of the embodiments of the present application, the embodiments of the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the embodiments of the present application are given in the drawings. However, the embodiments of the present application can be implemented in many different forms and are not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the embodiments of the present application more thorough and comprehensive.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the technical field of the embodiments of the present application. The terms used herein in the specification of the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present application. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0061] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, the first address information may be referred to as the second address information, and similarly, the second address information may be referred to as the first address information. Both the first address information and the second address information are address information, but they are not the same address information.

[0062] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0063] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0064] Figure 1 FIG. 1 is a schematic diagram of the structure of the defect repair circuit of the first embodiment, referring to FIG. Figure 1In this embodiment, the defect repair circuit includes a test module 100, a defect information storage module 200 and a repair module 300. The defect repair circuit of the embodiment of the present application is used to test the storage unit in the memory to determine the defective storage unit and repair it. Among them, the memory can be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. The memory includes a plurality of storage blocks, each storage block includes a plurality of storage cell arrays 400, each storage cell array 400 includes a plurality of storage cells arranged in an array, and each storage cell can store data, so that the storage function of the memory is realized by a plurality of storage cells.

[0065] The test module 100 is used to perform a defect test on the memory cell array 400 in a test mode to determine defective memory cells and output test address information and a defect identification signal corresponding to the memory cells.

[0066] Among them, the test module 100 is connected to the memory cell array 400 to test the connected memory cell array 400 in the test mode, that is, when the memory is in the test mode, the test module 100 performs the corresponding test function. The memory switches to the test mode in response to the test trigger signal. Exemplarily, the memory can automatically generate a test trigger signal to switch to the test mode each time it is powered on. The memory can also switch to the test mode in response to an externally input test trigger signal. The test trigger signal can, for example, be a signal input by a user through an electronic device connected to the memory. The memory can also switch to the test mode in response to a test trigger signal output by a built-in controller. The controller can output a test trigger signal after each preset time of the memory operation to achieve regular monitoring of the memory cell array 400.

[0067] The defect test method can be that the test module 100 automatically generates one or more test data in response to a test trigger signal, and writes the test data to each storage unit to be tested, and reads data from the storage unit after a certain period of time, and compares the read data with the automatically generated test data to determine whether the storage function of the storage unit is normal. If the data read from a storage unit is different from the written data, the storage unit is a defective storage unit.

[0068] When the test module 100 tests a defective memory cell, a pulse signal (fail pulse) in the defect identification signal can be generated accordingly. That is, if the memory cell currently being tested is not a defective memory cell, there is no need to generate a pulse signal, and the state of the defect identification signal is 0, thereby reducing unnecessary operations; if the memory cell currently being tested is a defective memory cell, a pulse signal in the defect identification signal is synchronously generated. When the test module 100 completes the detection of each memory cell, the test address information and the defect identification signal of the memory cell that has completed the test are synchronously sent to the defect information storage module 200, thereby storing the defect information.

[0069] The defect information storage module 200 is connected to the test module 100, and is used to store defect address information in response to the defect identification signal, wherein the defect address information is the test address information of the defect storage unit, and is also used to output first address information in response to an externally input repair selection signal, wherein the first address information is one of the multiple defect address information.

[0070] Among them, the defect information storage module 200 is configured with a clock end, and the clock end of the defect information storage module 200 is connected to the test module 100, so that the defect information storage module 200 stores the test address information in response to the pulse signal in the defect identification signal. For example, the defect information storage module 200 can store the test address information in response to the rising edge of the pulse signal. It can be understood that if the tested storage unit is not a defective storage unit, the defect identification signal corresponding to the storage unit is a continuous low level, that is, it does not contain a rising edge. Although the test address information of the storage unit is sent to the defect information storage module 200, it will not be stored; if the storage unit is a defective storage unit, the test address information of the defective storage unit (i.e., the defective address information) will be stored in response to the rising edge of the pulse signal, thereby realizing the storage function of the defect information.

[0071] It should be noted that the defect information may not be limited to the aforementioned defect address information, but since the defect address information is necessary information for executing the repair process, the description in this embodiment focuses on the defect address information. It is understandable that other defect information can be stored in a similar storage method to the defect address information, so it will not be repeated in this embodiment and other embodiments. Exemplarily, the other defect information can be defect level information determined based on the test results, and the test module 100 can send the defect level information to the defect information storage module 200 for storage, so that when repairing, the storage unit with a higher defect level can be repaired first to improve the reliability of the repair.

[0072] The externally input repair selection signal is used to instruct the defect information storage module 200 to output different first address information in a time-sharing manner. It can be understood that, through defect testing, if multiple defective storage units are determined, multiple defective address information can be output in a time-sharing manner, so that the repair module 300 can accurately receive each defective address information with a smaller number of interfaces and perform corresponding repairs. Furthermore, the "external" in the externally input repair selection signal refers to the outside of the defect repair circuit. For example, the repair selection signal can be issued by a controller in the memory, that is, this embodiment does not require an external tester or controller, and can realize automatic storage and automatic repair of defective address information based on the internal structure of the memory.

[0073] The repair module 300 is connected to the defect information storage module 200, and is used to repair the corresponding defective storage unit according to the received first address information.

[0074] Among them, repair means replacing the defective storage unit with a redundant storage unit when reading and writing data, and performing the data reading and writing functions that the defective storage unit should perform, while the defective storage unit is still set at the original address, but it is not required to perform the reading and writing operations. Exemplarily, repair may include row repair and / or column repair, row repair means replacing the row address corresponding to the defective storage unit with the row address of the redundant storage unit, and column repair means replacing the column address corresponding to the defective storage unit with the column address of the redundant storage unit.

[0075] Specifically, the repair module 300 stores redundant address information of multiple redundant storage units internally. Therefore, after obtaining the first address information, a mapping relationship between the first address information and the redundant address information can be established according to internal preset rules, thereby realizing the repair of the defective storage unit.

[0076] In this embodiment, the defect repair circuit includes: a test module 100, which is used to perform defect test on the memory cell array 400 in the test mode to determine the defective memory cell and output the test address information and defect identification signal corresponding to the memory cell; a defect information storage module 200, which is connected to the test module 100, and is used to store defect address information in response to the defect identification signal, the defect address information is the test address information of the defective memory cell, and is also used to output first address information in response to an externally input repair selection signal, the first address information is one of the plurality of defect address information; a repair module 300, which is connected to the defect information storage module 200, and is used to repair the corresponding defective memory cell according to the received first address information. By using the built-in test module 100 and repair module 300 in the memory, the repair operation can be performed based on its own hardware structure. Moreover, the repair module 300 in the defect repair circuit of this embodiment can reuse the structure and function of the packaged repair circuit, and automatically store the wrong address through the added test module 100, so as to perform intelligent repair together. In this embodiment, the defect repair circuit has few newly added circuit structures, so it can be compatible with chips with smaller areas, and the tester and controller are not required to store the addresses of defective storage units, thereby enhancing the convenience and reliability of the defect repair circuit.

[0077] Figure 2 FIG. 1 is a schematic diagram of the structure of the defect repair circuit of the second embodiment, referring to FIG. Figure 2 In this embodiment, the repair module 300 is also used to receive the second address information input from the outside, and repair the defective storage unit corresponding to the first address information or the second address information. Specifically, the first address information is automatically obtained by the test module 100 through defect testing, and the second address information may be obtained and saved by the memory supplier through post-packaging testing after completing the packaging, that is, the first address information may be built into the memory before the memory leaves the factory. The first address information may generally be a device hardware defect caused by the manufacturing process, and the first address information in this embodiment may also include defective address information corresponding to a defective storage unit generated during user use. Therefore, the repair module 300 of this embodiment can repair both the above-mentioned first address information and the second address information, thereby realizing a more flexible defect repair circuit.

[0078] Figure 3 FIG. 1 is a schematic diagram of the structure of the defect repair circuit of the third embodiment, referring to FIG. Figure 3 In this embodiment, the defect repair circuit includes a test module 100, a defect information storage module 200, a repair module 300 and a first selection circuit 500. The implementation methods of the test module 100, the defect information storage module 200 and the repair module 300 are similar to those of the first selection circuit 500. Figure 1 The implementation methods of the embodiments are similar and will not be described in detail here.

[0079] The first selection circuit 500 is connected to the defect information storage module 200 and the repair module 300, respectively, and is used to receive the first address information, the second address information and the repair selection signal, and generate target address information in response to the repair selection signal, and the target address information is one of the first address information and the second address information.

[0080] Specifically, the first selection circuit 500 can be a multiplexer, such as a two-to-one selector, and the first selection circuit 500 is configured with two transmission paths. Among them, the first transmission path is used to connect the defect information storage module 200 and the repair module 300 to transmit the first address information to the repair module 300; the second transmission path is used to receive the second address information to transmit the second address information to the repair module 300. The first selection circuit 500 is also configured with a control terminal, and the control terminal is used to input a repair identification signal to select one of the two transmission paths to be turned on. Exemplarily, when the repair identification signal is 1, the first transmission path can be turned on. Therefore, if the defective storage unit corresponding to the first address information needs to be repaired, the controller of the memory outputs a repair identification signal with a state of 1 to send the first address information as the target address information to the repair module 300, so as to perform the repair.

[0081] Figure 4 FIG. 1 is a schematic diagram of a defect repair circuit according to a fourth embodiment. Figure 4 In this embodiment, the defect information storage module 200 includes an identification bit storage unit 220 .

[0082] Specifically, the identification bit storage unit 220 is respectively connected to the test module 100 and the repair module 300, and is used to generate and store corresponding identification bit information for the defective storage unit in response to the defect identification signal. Each storage unit is configured with an identification bit information (fail flag), and the identification bit information is used to indicate whether the corresponding storage unit is a defective storage unit. Exemplarily, the identification bit information of the defective storage unit can be set to 1, and the identification bit information of other storage units can be set to 0. When performing other operations, it can be determined whether the corresponding storage unit is a defective storage unit based on the identification bit information, so as to more efficiently perform repair and other operations. Further, continue to refer to Figure 4 The defect information storage module 200 further includes an address storage unit 210. The address storage unit 210 is connected to the test module 100 and the repair module 300 respectively to store the defect address information of the defect storage unit, so as to facilitate selecting the first address information from the plurality of defect address information and outputting it to the repair module 300.

[0083] Figure 5 FIG. 1 is a schematic diagram of the structure of the defect repair circuit of the fifth embodiment, referring to FIG. Figure 5 In this embodiment, the defect storage circuit includes a test module 100, a defect information storage module 200, a first selection circuit 500 and a repair module 300. Among them, the address storage unit 210 is connected to the test module 100 and the first selection circuit 500 respectively, and the identification bit storage module is also connected to the test module 100 and the first selection circuit 500 respectively, and the address storage unit 210 and the identification bit storage unit 220 both store information in response to the defect identification signal. Further, the first selection circuit 500 synchronously receives the first address information and the identification bit information corresponding to the defective storage unit. Through the above-mentioned setting method, the address storage unit 210 and the identification bit storage unit 220 can synchronously store and output the information of the same defective storage unit, thereby improving the accuracy and reliability of storage.

[0084] Further, Figure 6 FIG. 2 is a schematic diagram of the structure of the address storage unit 210 and the identification bit storage unit 220 of an embodiment, referring to FIG. Figure 6 In this embodiment, the address storage unit 210 includes N-level address buffer memories 211, and the identification bit storage unit 220 includes N-level identification buffer memories 221, where N is an integer greater than or equal to 2.

[0085] Specifically, the N-level address buffer memory 211 is sequentially numbered as the first-level address buffer memory 211 to the N-th-level address buffer memory 211, the clock end of the address buffer memory 211 is used to receive the defect identification signal, the data input end of the first-level address buffer memory 211 is used to receive the test address information, and the output end of the N-1-th-level address buffer memory 211 is connected to the data input end of the N-level address buffer memory 211. The N-level identification buffer memory 221 is sequentially numbered as the first-level identification buffer memory 221 to the N-th-level identification buffer memory 221, the clock end of the identification buffer memory 221 receives the defect identification signal, the data input end of the first-level identification buffer memory 221 is used to connect the preset level signal, and the output end of the N-1-th-level identification buffer memory 221 is connected to the data input end of the N-level address buffer memory 211. The address latch and the identification bit latch set in pairs are used to latch the first address information or identification bit information of the same defective storage unit.

[0086] Furthermore, the address buffer memory 211 and the identification buffer memory 221 can both be D flip-flops and have the same hardware structure. Furthermore, the path length between the clock end and the defect identification signal input interface of each pair of the address buffer memory 211 and the identification buffer memory 221 is the same. Therefore, the pulse signal can synchronously arrive at the first-level address buffer memory 211 and the first-level identification buffer memory 221.

[0087] For example, when a defective memory cell is detected, a pulse signal is generated in the defect identification signal. Figure 6 When the previous pulse signal arrives, the first-level address buffer memory 211 samples the test address information inputted from the input terminal, thereby generating defect address information 0 <n:0>The first level identification buffer memory 221 samples the preset level signal input from the input end, thereby generating identification bit information 0 <n:0>Until the next pulse signal arrives, the information at the output of the first-level address buffer memory 211 and the first-level identification buffer memory 221 remains unchanged. When the next pulse signal arrives, the second-level address buffer memory 211 samples the signal received at its input end to generate defect address information 1 <n:0>, and the first-level address buffer memory 211 will also update the information of its output end according to the new test address information, thereby generating new defect address information 0 <n:0>Among them, the previous pulse signal and the next pulse signal are two pulses that are adjacent in time sequence. Similarly, every time a pulse signal arrives, the result of the previous level buffer memory will be sent to the next level for buffer storage, thereby realizing the storage function of the defect information storage module 200 for multiple defect address information and multiple identification bit information.

[0088] Figure 7 FIG. 1 is a schematic diagram of the structure of the defect repair circuit of the sixth embodiment, referring to FIG. Figure 7 In this embodiment, the defect information storage module 200 further includes a second selection circuit 230 and a third selection circuit 240 .

[0089] The second selection circuit 230, the control end of the second selection circuit 230 is used to receive the repair selection signal, the N input ends of the second selection circuit 230 are connected one-to-one with the output ends of the N-level address buffer memory 211, and the output end of the second selection circuit 230 is used to output the first address information. The second selection circuit 230 is connected to the defect information storage module 200 and the first selection circuit 500 respectively to determine the first address information from the multiple defect address information according to the repair selection signal.

[0090] Specifically, Figure 8 FIG. 2 is a schematic diagram of the structure of the second selection circuit 230 according to an embodiment of the present invention. Figure 8 , the second selection circuit 230 can be a multiplexer, the multiplexer is configured with multiple input terminals, and the number of input terminals is the same as the number of address buffer memories 211, and the input terminals of multiple multiplexers are connected to multiple address buffer memories 211 in a one-to-one correspondence to obtain multiple defect address information. In this embodiment, multiple control terminals are also configured, and the control terminals correspond to the input terminals in a one-to-one correspondence. At the same time, at most one of the multiple control terminals is enabled to be effective, thereby ensuring that one of the multiple defect address information is selected as the first address information for output. Among them, each control terminal can be used to input two signals, which are a repair selection signal and an inverted signal of the repair selection signal, that is, when any one of the two signals can turn on the corresponding transistor, the signal path can be turned on, thereby improving the operation speed of the second selection circuit 230.

[0091] The third selection circuit 240, the control end of the third selection circuit 240 is used to receive the repair selection signal, the N input ends of the third selection circuit 240 are connected to the output ends of the N-level identification buffer memory 221 in a one-to-one correspondence, and the output end of the third selection circuit 240 is used to output the identification bit information. The third selection circuit 240 is connected to the defect information storage module 200 and the first selection circuit 500 respectively to determine the first identification information from the multiple identification bit information according to the repair selection signal.

[0092] Specifically, Fig. 9 FIG. 2 is a schematic diagram of the structure of the third selection circuit 240 according to an embodiment of the present invention. Fig. 9 , the third selection circuit 240 can be a multiplexer, the multiplexer is configured with multiple input terminals, and the number of input terminals is the same as the number of identification buffer memories 221, and the input terminals of multiple multiplexers are connected to multiple identification buffer memories 221 in a one-to-one correspondence to obtain multiple identification bit information. In this embodiment, multiple control terminals are also configured, and the control terminals correspond to the input terminals in a one-to-one correspondence. At the same time, at most one of the multiple control terminals is enabled to be effective, thereby ensuring that one of the multiple identification bit information is selected as the first identification information for output. Among them, each control terminal can be used to input two signals, which are a repair selection signal and an inverted signal of the repair selection signal, that is, when any one of the two signals can turn on the corresponding transistor, the signal path can be turned on, thereby improving the operation speed of the third selection circuit 240.

[0093] Fig.10 is a flowchart of a defect repair method according to an embodiment, referring to Fig.10 In this embodiment, the defect repair method includes S100 to S700.

[0094] S100: Enter test mode;

[0095] S200: the test module 100 performs a defect test on the memory cell array 400 to determine a defective memory cell, and outputs test address information and a defect identification signal corresponding to the memory cell;

[0096] S300: the defect information storage module 200 stores defect address information in response to the defect identification signal, where the defect address information is the test address information of the defective storage unit;

[0097] S400: exit the test mode and enter the repair mode;

[0098] S500: the defect information storage module 200 outputs first address information in response to an externally input repair selection signal, where the first address information is one of the plurality of defect address information;

[0099] S600: The repair module 300 repairs the corresponding defective storage unit according to the received first address information;

[0100] S700: Exit the repair mode.

[0101] In this embodiment, a defect repair method with good reliability and convenience is implemented through steps S100 to S700. It can be understood that the specific implementation methods can refer to the implementation methods of the corresponding defect repair circuits, which will not be described in detail here.

[0102] Fig.11 is a flowchart of a defect repair method according to another embodiment. Fig.11 In this embodiment, before step S600, the following steps are also included:

[0103] S800: receiving second address information input from the outside;

[0104] Furthermore, step S600 includes:

[0105] Step S610: repairing the defective storage unit corresponding to the first address information or the second address information.

[0106] Fig.12 is a flowchart of step S610 of an embodiment, refer to Fig.12 , step S610 includes steps S611 to S613.

[0107] S611: receiving the first address information, the second address information and the repair selection signal;

[0108] S612: generating target address information in response to the repair selection signal, where the target address information is one of the first address information and the second address information;

[0109] S613: Repair the defective storage unit according to the target address information.

[0110] In one of the embodiments, before step S500, the method further includes: generating corresponding identification bit information for the defective storage unit in response to the defect identification signal.

[0111] Fig.13 is a flowchart of step S500 of an embodiment, refer to Fig.13 , step 500 includes steps S510 to S520.

[0112] S510: the second selection circuit 230 outputs the first address information in response to the repair selection signal;

[0113] S520: The third selection circuit 240 outputs the identification bit information in response to the repair selection signal;

[0114] Wherein, the first address information and the identification bit information are output synchronously.

[0115] It should be understood that, although the steps in each flowchart are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in each flowchart may include a plurality of sub-steps or a plurality of stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0116] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] The above-described embodiments only express several implementation methods of the embodiments of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the embodiments of the present application, and these all belong to the protection scope of the embodiments of the present application. Therefore, the protection scope of the patent of the embodiments of the present application shall be subject to the attached claims.

Claims

1. A defect repair circuit, characterized in that: include: A test module, used to perform a defect test on the memory cell array in a test mode to determine a defective memory cell, and output test address information and a defect identification signal corresponding to the memory cell; a defect information storage module connected to the test module, and configured to store defect address information in response to the defect identification signal, wherein the defect address information is the test address information of the defect storage unit, and further configured to output first address information in response to an externally input repair selection signal, wherein the first address information is one of the plurality of defect address information; a repair module, connected to the defect information storage module, and configured to repair the corresponding defective storage unit according to the received first address information; The defect information storage module also includes: an identification bit storage unit, connected to the test module and the repair module respectively, and used to generate and store corresponding identification bit information for the defect storage unit in response to the defect identification signal; The address storage unit comprises N levels of address buffer memories, the N levels of address buffer memories are numbered from a first level address buffer memory to an Nth level address buffer memory in sequence, a clock end of the address buffer memory is used to receive the defect identification signal, a data input end of the first level address buffer memory is used to receive the test address information, an output end of the N-1th level address buffer memory is connected to a data input end of the Nth level address buffer memory, and N is an integer greater than or equal to 2; Among them, the identification bit storage unit includes N levels of identification buffer memories, and the N levels of identification buffer memories are numbered in sequence as the first-level identification buffer memory to the N-th-level identification buffer memory, the clock end of the identification buffer memory receives the defect identification signal, the data input end of the first-level identification buffer memory is used to connect a preset level signal, and the output end of the N-1-th level identification buffer memory is connected to the data input end of the N-th level address buffer memory.

2. The defect repair circuit according to claim 1, characterized in that: The repair module is further used to receive second address information input from the outside, and repair the defective storage unit corresponding to the first address information or the second address information.

3. The defect repair circuit according to claim 2, characterized in that: Also includes: The first selection circuit is connected to the defect information storage module and the repair module respectively, and is used to receive the first address information, the second address information and the repair selection signal, and generate target address information in response to the repair selection signal, and the target address information is one of the first address information and the second address information.

4. The defect repair circuit according to claim 3, characterized in that: The first selection circuit synchronously receives the first address information and the identification bit information corresponding to the defective storage unit.

5. The defect repair circuit according to claim 1, characterized in that: The defect information storage module also includes: a second selection circuit, wherein a control end of the second selection circuit is used to receive the repair selection signal, N input ends of the second selection circuit are connected to output ends of the N-level address buffer memory in a one-to-one correspondence, and an output end of the second selection circuit is used to output the first address information; The third selection circuit, the control end of the third selection circuit is used to receive the repair selection signal, the N input ends of the third selection circuit are connected one-to-one with the output ends of the N-level identification buffer memory, and the output end of the third selection circuit is used to output the identification bit information.

6. A defect repair method, characterized in that: include: Enter test mode; The test module performs a defect test on the memory cell array to determine the defective memory cell, and outputs the test address information and the defect identification signal corresponding to the memory cell; The defect information storage module stores defect address information in response to the defect identification signal, wherein the defect address information is test address information of the defect storage unit; Exit the test mode and enter the repair mode; The defect information storage module outputs first address information in response to an externally input repair selection signal, wherein the first address information is one of the plurality of defect address information; A repair module repairs the corresponding defective storage unit according to the received first address information; exiting the repair mode; The defect information storage module also includes: an identification bit storage unit, connected to the test module and the repair module respectively, and used to generate and store corresponding identification bit information for the defect storage unit in response to the defect identification signal; The address storage unit comprises N levels of address buffer memories, the N levels of address buffer memories are numbered from a first level address buffer memory to an Nth level address buffer memory in sequence, a clock end of the address buffer memory is used to receive the defect identification signal, a data input end of the first level address buffer memory is used to receive the test address information, an output end of the N-1th level address buffer memory is connected to a data input end of the Nth level address buffer memory, and N is an integer greater than or equal to 2; Among them, the identification bit storage unit includes N levels of identification buffer memories, and the N levels of identification buffer memories are numbered in sequence as the first-level identification buffer memory to the N-th-level identification buffer memory, the clock end of the identification buffer memory receives the defect identification signal, the data input end of the first-level identification buffer memory is used to connect a preset level signal, and the output end of the N-1-th level identification buffer memory is connected to the data input end of the N-th level address buffer memory.

7. The defect repair method according to claim 6, characterized in that: Before repairing the corresponding defective storage unit according to the received first address information, the method further includes: Receiving second address information input from outside; The repairing the corresponding defective storage unit according to the received first address information includes: Repair the defective storage unit corresponding to the first address information or the second address information.

8. The defect repair method according to claim 7, characterized in that: The repairing the defective storage unit corresponding to the first address information or the second address information includes: receiving the first address information, the second address information and the repair selection signal; generating target address information in response to the repair selection signal, the target address information being one of the first address information and the second address information; The defective storage unit is repaired according to the target address information.

9. The defect repair method according to claim 7, characterized in that: The method further comprises: outputting first address information in response to an externally input repair selection signal, wherein the first address information is one of the plurality of defect address information; In response to the defect identification signal, corresponding identification bit information is generated for the defective storage unit.

10. The defect repair method according to claim 9, characterized in that: The outputting of first address information in response to an externally input repair selection signal, wherein the first address information is one of the plurality of defect address information, comprises: The second selection circuit outputs the first address information in response to the repair selection signal; The third selection circuit outputs the identification bit information in response to the repair selection signal; Wherein, the first address information and the identification bit information are output synchronously.

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