Electrostatic Discharge Protection Structure and Method for Forming the Same

Abstract

An electrostatic discharge protection structure and a method for forming the same, comprising: a substrate including a first region and a plurality of second regions; a first well region located in the first region, having a first doping ion in the first well region; a second well region located in the second region, having a second doping ion in the second well region; a first gate structure located on the first region; a second gate structure located on the second region; a first doping layer and a second doping layer respectively located in the substrate on both sides of the second gate structure, having a first doping ion in the first doping layer and the second doping layer, the first doping layer and the second doping layer are respectively located in the second well region, and the first doping layer is further in contact with the first well region. By forming a reverse-biased junction at the junction of the first well region and the second well region, since the first gate structure is connected in series with the reverse-biased junction, the resistance value of the branch formed by the first gate structure and the reverse-biased junction is increased, thereby reducing the risk of the first gate structure being broken down, and thus improving the performance of the finally formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technologies, and particularly to an electrostatic discharge protection structure and a method for forming the same. Background Art

[0002] Integrated circuits are vulnerable to electrostatic damage. Generally, protection circuits are designed at the input / output terminals or power protection devices of the circuit to prevent the internal circuit from being damaged by static electricity.

[0003] In existing integrated circuit designs, an electrostatic discharge (ESD) protection structure is often adopted to reduce electrostatic damage. The existing electrostatic discharge protection structures mainly include: a gate grounded N-type field effect transistor (Gate Grounded NMOS, hereinafter referred to as GGNMOS) protection circuit, a silicon controlled rectifier (hereinafter referred to as SCR) protection circuit, a lateral double diffused MOSFET (hereinafter referred to as LDMOS) protection circuit, a bipolar junction transistor (hereinafter referred to as BJT) protection circuit, etc.

[0004] Among them, GGNMOS is a widely used electrostatic discharge protection structure. Its working mechanism is as follows: Since the power consumption on the MOS transistor is the product of the passing current and the voltage drop, under a certain ESD static current, if the voltage drop on the MOS transistor can be reduced, and then the junction temperature of the MOS transistor can be reduced, so as to achieve the purpose of protecting the MOS transistor. As an ESD device, GGNMOS relies on the parasitic NPN BJT to discharge the ESD current in the forward direction. The NPN is composed of the N+ active region of the drain, the P-type substrate, and the N+ active region of the source; the path for discharging the ESD current in the reverse direction is composed of a PN diode and an NMOS diode with the gate-source connected. The PN diode is composed of the P-type substrate and the N+ active region. In the ESD network of the entire chip, when the ESD time comes, GGNMOS may conduct in both the forward and reverse directions, which is determined by the potential ESD path. The ESD current always flows to the low-resistance path. Therefore, when designing, the forward and reverse ESD performances of GGNMOS need to be considered to ensure the reliability of the integrated circuit. As a BJT, GGNMOS has a breakdown device working mechanism, and relies on the avalanche breakdown between the drain and the substrate to trigger and form a low-resistance path to discharge the ESD current.

[0005] However, the performance of the electrostatic discharge protection structure formed by the prior art needs to be improved. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide an electrostatic discharge protection structure and a method for forming the same, which can effectively improve the performance of the electrostatic discharge protection structure.

[0007] To solve the above problems, the present invention provides an electrostatic discharge protection structure, including: a substrate, the substrate includes a first region and a plurality of second regions arranged in a first direction, and the first region is located between adjacent second regions; a first well region located in the first region, the first well region having a first doping ion; a second well region located in the second region, the second well region having a second doping ion, and the second doping ion has a different conductivity type from the first doping ion; a first gate structure located on the first region; a second gate structure located on the second region; a first doping layer and a second doping layer respectively located in the substrate on both sides of the second gate structure, the first doping layer and the second doping layer having the first doping ion, the first doping layer and the second doping layer are respectively located in the second well region, and the first doping layer is also in contact with the first well region.

[0008] Optionally, the first doping ion includes an N-type ion; the first doping ion includes: phosphorus or arsenic.

[0009] Optionally, the second doping ion includes a P-type ion; the second doping ion includes: boron or indium.

[0010] Optionally, the substrate includes: a substrate and fins located on the substrate, the fins having the first well region and the second well region, and the first doping layer and the second doping layer are located in the fins.

[0011] Optionally, it further includes: an isolation structure located in the fins.

[0012] Optionally, the substrate includes: a substrate and a first fin and a second fin located on the substrate, the first fin having the first well region and the second well region, and the first doping layer and the second doping layer are located in the first fin, and the second fin has the second well region.

[0013] Optionally, it further includes: an isolation structure located between the first fin and the second fin.

[0014] Optionally, it further includes: a heavily doped region formed in the second well region, the isolation structure is located between the heavily doped region and the second doping layer, the heavily doped region has a third doping ion, the third doping ion has the same electrical type as the second doping ion, and the concentration of the third doping ion in the heavily doped region is greater than the concentration of the second doping ion in the second well region.

[0015] Optionally, the first doped layer is connected to an electrostatic output terminal; the second doped layer, the second gate structure, and the heavily doped region are connected to an electrostatic input terminal.

[0016] Optionally, it further includes: first conductive plugs respectively located on the first doped layer, the first conductive plugs being connected to the electrostatic output terminal; second conductive plugs respectively located on the second doped layer, the second gate structure, and the heavily doped region, the second conductive plugs being connected to the electrostatic input terminal.

[0017] Optionally, the first gate structure includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer.

[0018] Optionally, the first conductive plug and the first gate structure have a first pitch dimension along the first direction, the first conductive plug and the second gate structure have a second pitch dimension along the first direction, and the second pitch dimension is greater than the first pitch dimension.

[0019] Optionally, the first doped layer has a first width dimension along the first direction, the second doped layer has a second width dimension along the first direction, and the first width dimension is greater than the second width dimension.

[0020] Correspondingly, the present invention further provides a method for forming an electrostatic discharge protection structure, including: providing a substrate, the substrate including a first region and a plurality of second regions arranged along a first direction, the first region being located between adjacent second regions; forming a first well region in the first region, the first well region having first doping ions; forming a second well region in the second region, the second well region having second doping ions, the electrical type of the second doping ions being different from that of the first doping ions; forming a first gate structure on the first region; forming a second gate structure on the second region; forming a first doped layer and a second doped layer in the substrate on both sides of the second gate structure respectively, the first doped layer and the second doped layer having the first doping ions, the first doped layer and the second doped layer being respectively located in the second well region, and the first doped layer further being in contact with the first well region.

[0021] Optionally, the method for forming the first well region and the second well region includes: forming a first patterned layer on the substrate, the first patterned layer exposing the top surface of the first region; using the first patterned layer as a mask, performing an implantation process of a first doping ion on the first region to form the first well region in the first region; after forming the first well region, removing the first patterned layer; forming a second patterned layer on the substrate, the second patterned layer exposing the top surface of the second region; using the second patterned layer as a mask, performing an implantation process of a second doping ion on the second region to form the second well region in the second region.

[0022] Optionally, the first doping ion includes an N-type ion; the first doping ion includes: phosphorus or arsenic.

[0023] Optionally, the second doping ion includes a P-type ion; the second doping ion includes: boron or indium.

[0024] Optionally, the substrate includes: a substrate and fins located on the substrate, the first well region and the second well region are within the fins, and the first doping layer and the second doping layer are located within the fins.

[0025] Optionally, further includes: forming an isolation structure, the isolation structure is located within the fins.

[0026] Optionally, the substrate includes: a substrate and a first fin and a second fin located on the substrate, the first well region and the second well region are within the first fin, and the first doping layer and the second doping layer are located within the first fin, the second well region is within the second fin.

[0027] Optionally, further includes: forming an isolation structure, the isolation structure is located between the first fin and the second fin.

[0028] Optionally, the method for forming the fins and the isolation structure includes: providing an initial substrate; forming a third patterned layer on the initial substrate, the third patterned layer exposing a part of the top surface of the initial substrate; etching the initial substrate using the third patterned layer as a mask to form a substrate and fins located on the substrate, etching a part of the fins to form an isolation opening within the fins; forming the isolation structure within the isolation opening.

[0029] Optionally, the method for forming the first fin portion, the second fin portion, and the isolation structure includes: providing an initial substrate; forming a third patterned layer on the initial substrate, the third patterned layer exposing a top surface of a portion of the initial substrate; etching the initial substrate using the third patterned layer as a mask to form a base and a first fin portion and a second fin portion on the base, with an isolation opening between the first fin portion and the second fin portion; and forming the isolation structure in the isolation opening.

[0030] Optionally, after forming the isolation structure, the method further includes: forming a heavily doped region in the second well region, the isolation structure being located between the heavily doped region and the second doped layer, the heavily doped region having a third doping ion, the third doping ion having the same electrical type as the second doping ion, and the concentration of the third doping ion in the heavily doped region being greater than the concentration of the second doping ion in the second well region.

[0031] Optionally, after forming the heavily doped region, the method further includes: connecting the first doped layer to an electrostatic output terminal; connecting the second doped layer, the second gate structure, and the heavily doped region to an electrostatic input terminal.

[0032] Optionally, the method for connecting the first doped layer to the electrostatic output terminal includes: forming a first conductive plug on the first doped layer, the first conductive plug connecting to the electrostatic output terminal.

[0033] Optionally, the method for connecting the second doped layer, the second gate structure, and the heavily doped region to the electrostatic input terminal includes: forming second conductive plugs on the second doped layer, the second gate structure, and the heavily doped region respectively, the second conductive plugs connecting to the electrostatic input terminal.

[0034] Optionally, the first gate structure includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer.

[0035] Optionally, the first conductive plug has a first spacing dimension from the first gate structure in the first direction, and the first conductive plug has a second spacing dimension from the second gate structure in the first direction, the second spacing dimension being greater than the first spacing dimension.

[0036] Optionally, the first doped layer has a first width dimension in the first direction, and the second doped layer has a second width dimension in the first direction, the first width dimension being greater than the second width dimension.

[0037] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0038] In the structure of the technical solution of the present invention, through the first well region located in the first region, the first well region has a first doping ion; the second well region located in the second region, the second well region has a second doping ion, and the electrical type of the second doping ion is different from that of the first doping ion, so that a reverse-biased junction is formed at the junction of the first well region and the second well region. Since the first gate structure and the reverse-biased junction are connected in series through the first well region, the resistance value of the branch formed by the first gate structure and the reverse-biased junction increases. During the electrostatic discharge process, the branch formed by the first gate structure and the reverse-biased structure is equivalent to an open circuit state. Therefore, the risk of the first gate structure being broken down is reduced, thereby improving the performance of the finally formed semiconductor structure.

[0039] Further, the first conductive plug and the first gate structure have a first spacing dimension along the first direction, the first conductive plug and the second gate structure have a second spacing dimension along the first direction, and the second spacing dimension is greater than the first spacing dimension. By increasing the spacing between the first conductive plug and the second gate structure, the second gate structure is prevented from being broken down by discharge, so as to improve the protection ability of the device.

[0040] Further, the first doping layer has a first width dimension along the first direction, the second doping layer has a second width dimension along the first direction, and the first width dimension is greater than the second width dimension. By increasing the width dimension of the first doping layer along the first direction, the spacing between the first conductive plug and the second gate structure is further increased, so as to prevent the second gate structure from being broken down by discharge and improve the protection ability of the device.

[0041] In the formation method of the technical solution of the present invention, by forming a first well region in the first region, the first well region has a first doping ion; forming a second well region in the second region, the second well region has a second doping ion, and the conduction type of the second doping ion is different from that of the first doping ion, so that a reverse-biased junction is formed at the junction of the first well region and the second well region. Since the first gate structure and the reverse-biased junction are connected in series through the first well region, the resistance value of the branch formed by the first gate structure and the reverse-biased junction increases. During the electrostatic discharge process, the branch formed by the first gate structure and the reverse-biased structure is equivalent to an open circuit state. Therefore, the risk of the first gate structure being broken down is reduced, thereby improving the performance of the finally formed semiconductor structure.

[0042] Further, the first conductive plug and the first gate structure have a first spacing dimension in the first direction, and the first conductive plug and the second gate structure have a second spacing dimension in the first direction. The second spacing dimension is greater than the first spacing dimension. By increasing the spacing between the first conductive plug and the second gate structure, the second gate structure is prevented from being discharged and broken down, so as to improve the protection ability of the device.

[0043] Further, the first doped layer has a first width dimension in the first direction, the second doped layer has a second width dimension in the first direction, and the first width dimension is greater than the second width dimension. By increasing the width dimension of the first doped layer in the first direction, the spacing between the first conductive plug and the second gate structure is further increased, so as to prevent the second gate structure from being discharged and broken down, and improve the protection ability of the device. Description of the Drawings

[0044] Figure 1 and Figure 2 is a schematic structural diagram of a semiconductor structure;

[0045] Figures 3 to 14 is a schematic structural diagram of each step in an embodiment of the method for forming the semiconductor structure of the present invention. Detailed Embodiments

[0046] As described in the background art, the performance of the electrostatic discharge protection structure formed by the prior art needs to be improved. The following will be specifically described with reference to the drawings.

[0047] Please refer to Figure 1 , a substrate 100 is provided; a first well region 101 is formed in the substrate 100, and the first well region 101 has first doping ions; a first gate structure 102 and a plurality of second gate structures 103 are formed on the substrate 100, and the first gate structure 102 is located between adjacent second gate structures 103; a first epitaxial doped layer 104 and a second epitaxial doped layer 105 are respectively formed in the substrate 100 on both sides of the second gate structure 103. The first epitaxial doped layer 104 and the second epitaxial doped layer 105 have second doping ions, and the second doping ions are different from the first doping ions. The first epitaxial doped layer 104 is also located on both sides of the first gate structure 102.

[0048] Please refer to Figure 2, a doped region 106 is formed in the first well region 101, the first doped ions are present in the doped region 106, and the concentration of the first doped ions in the doped region 106 is greater than the concentration of the first doped ions in the first well region 101; first conductive plugs 107 are respectively formed on the first epitaxial doped layer 104, and the first conductive plugs 107 are electrically connected to each other; second conductive plugs 108 are formed on the doped region 106, the second gate structure 103 and the second epitaxial doped layer 105, and the second conductive plugs 108 are electrically connected to each other.

[0049] In this embodiment, the first conductive plug 107 needs to be arranged at a position far from the second gate structure 103 to improve the protection ability of the device. However, when the spacing dimension D1 between the first conductive plug 107 and the second gate structure 103 is large, the spacing dimension D2 between the first conductive plug 107 and the first gate structure 102 is small. At this time, the first gate structure 102 is easily damaged by breakdown, becoming a weak point of the device, and reducing the overall electrostatic tolerance of the finally formed semiconductor structure.

[0050] On this basis, the present invention provides an electrostatic discharge protection structure and a forming method thereof. By forming a first well region in the first region, the first well region has first doped ions; a second well region is formed in the second region, the second well region has second doped ions, and the second doped ions have a different conduction type from the first doped ions, so that a reverse-biased junction is formed at the junction of the first well region and the second well region. Since the first gate structure and the reverse-biased junction are connected in series through the first well region, the resistance value of the branch formed by the first gate structure and the reverse-biased junction is increased. During the electrostatic discharge process, the branch formed by the first gate structure and the reverse-biased structure is equivalent to an open circuit state, so the risk of the first gate structure being broken down is reduced, thereby improving the performance of the finally formed semiconductor structure.

[0051] To make the above objects, features and advantages of the present invention more obvious and understandable, the following specifically describes the specific embodiments of the present invention with reference to the accompanying drawings.

[0052] Figures 3 to 14 is a schematic structural diagram of the forming process of a semiconductor structure according to an embodiment of the present invention.

[0053] Please refer to Figure 3 , a substrate is provided, the substrate includes a first region I and a plurality of second regions II arranged along a first direction X, and the first region I is located between adjacent second regions II.

[0054] In this embodiment, the material of the substrate is silicon; in other embodiments, the material of the substrate may also be single crystal germanium, silicon germanium, silicon carbide, or may be silicon on insulator (SOI), germanium on insulator (GOI); alternatively, the substrate may also be made of other materials, such as ternary - pentary compounds like gallium arsenide.

[0055] In this embodiment, the substrate includes: a substrate 200, a first fin portion 201 and a second fin portion 202 located on the substrate 200; in other embodiments, the substrate may also include: a substrate and fin portions located on the substrate.

[0056] In this embodiment, the forming method of the first fin portion 201 and the second fin portion 202 includes: providing an initial substrate (not shown); forming a third patterned layer (not shown) on the initial substrate, the third patterned layer exposing a part of the top surface of the initial substrate; etching the initial substrate using the third patterned layer as a mask to form the substrate 200, the first fin portion 201 and the second fin portion 202 located on the substrate 200.

[0057] In other embodiments, provide an initial substrate; form a third patterned layer on the initial substrate, the third patterned layer exposing a part of the top surface of the initial substrate; etch the initial substrate using the third patterned layer as a mask to form a substrate and fin portions located on the substrate.

[0058] Please refer to Figure 4 , after forming the first fin portion 201 and the second fin portion 202, an isolation structure 203 is formed between the first fin portion 201 and the second fin portion 202.

[0059] In this embodiment, the material of the isolation structure 203 is silicon oxide; in other embodiments, the material of the isolation structure may also be silicon oxynitride.

[0060] In other embodiments, the forming method of the isolation structure may also include: etching part of the fin portions to form isolation openings in the fin portions; forming the isolation structure in the isolation openings.

[0061] Please refer to Figure 5 , after forming the isolation structure 203, a first well region 204 is formed in the first region I, and the first well region 204 has first doping ions.

[0062] In this embodiment, the method for forming the first well region 204 includes: forming a first patterned layer (not shown) on the substrate, the first patterned layer exposing the top surface of the first region I; using the first patterned layer as a mask, performing an implantation process of a first doping ion on the first region I to form the first well region 204 within the first region I.

[0063] The first doping ion includes an N-type ion; the first doping ion includes: phosphorus or arsenic. In this embodiment, the first doping ion is phosphorus.

[0064] In this embodiment, after forming the first well region 204, the first patterned layer is removed.

[0065] In this embodiment, the first well region 204 is within the first fin 201.

[0066] In other embodiments, the first well region is within the fin.

[0067] Please refer to Figure 6 , a second well region 205 is formed within the second region II, the second well region 205 having a second doping ion, the second doping ion being of a different electrical type from the first doping ion.

[0068] In this embodiment, the method for forming the second well region 205 includes: forming a second patterned layer (not shown) on the substrate, the second patterned layer exposing the top surface of the second region II; using the second patterned layer as a mask, performing an implantation process of a second doping ion on the second region II to form the second well region 205 within the second region II.

[0069] In this embodiment, after forming the second well region 205, the second patterned layer is removed.

[0070] The second doping ion includes a P-type ion; the second doping ion includes: boron or indium. In this embodiment, the second doping ion is boron.

[0071] In other embodiments, the second well region may be formed first, and after forming the second well region, the first well region is formed.

[0072] In this embodiment, the second well region 205 is respectively within the first fin 201 and the second fin 202.

[0073] In other embodiments, the second well region is within the fin.

[0074] Please refer to Figure 7, after forming the first well region 204 and the second well region 205, an isolation layer 218 is formed on the substrate. The isolation layer 218 covers part of the first fin 201 and the second fin 202, and the top surface of the isolation layer 218 is lower than the top surfaces of the first fin 201 and the second fin 202.

[0075] In this embodiment, the method for forming the isolation layer 218 includes: forming an initial isolation layer (not shown) on the substrate; etching away part of the initial isolation layer to form the isolation layer 218, and the top surface of the isolation layer 218 is lower than the top surfaces of the first fin 201 and the second fin 202.

[0076] The material of the isolation layer 218 is an insulating material, and the insulating material includes silicon oxide or silicon oxynitride; in this embodiment, the material of the isolation layer 218 is silicon oxide.

[0077] After forming the isolation layer 218, it further includes: forming a first gate structure on the first region I; forming a second gate structure on the second region II; forming a first doping layer and a second doping layer in the substrate on both sides of the second gate structure respectively. The first doping layer and the second doping layer contain the first doping ions. The first doping layer and the second doping layer are respectively located in the second well region 205, and the first doping layer is also in contact with the first well region 204. For the specific formation process, please refer to Figures 8 to 12 。

[0078] Please refer to Figure 8 , forming a first dummy gate structure 206 on the first region I; forming a second dummy gate structure 207 on the second region II.

[0079] In this embodiment, the method for forming the first dummy gate structure 206 includes: forming a first dummy gate dielectric layer on the isolation layer 218 and the first well region 204; forming a first dummy gate layer on the first dummy gate dielectric layer; forming a first sidewall (not labeled) on the sidewalls of the first dummy gate dielectric layer and the first dummy gate layer.

[0080] In this embodiment, the material of the first dummy gate dielectric layer is silicon oxide; in other embodiments, the material of the first dummy gate dielectric layer can also be silicon oxynitride.

[0081] In this embodiment, the material of the first dummy gate layer is silicon.

[0082] In this embodiment, the method for forming the second dummy gate structure 207 includes: forming a second dummy gate dielectric layer on the isolation layer 218 and the second well region 205; forming a second dummy gate layer on the second dummy gate dielectric layer; forming a second sidewall (not labeled) on the sidewalls of the second dummy gate dielectric layer and the second dummy gate layer.

[0083] In this embodiment, the materials of the second dummy gate dielectric layer and the first dummy gate dielectric layer are the same, and the materials of the second dummy gate layer and the first dummy gate layer are also the same.

[0084] In this embodiment, the first dummy gate structure 206 and the second dummy gate structure 207 are formed simultaneously, which can effectively improve production efficiency.

[0085] Please refer to Figure 9 , the first doped layer 208 and the second doped layer 209 are formed in the substrate. The first doped layer 208 and the second doped layer 209 contain the first doping ions. The first doped layer 208 and the second doped layer 209 are respectively located in the second well region 205, and the first doped layer 208 is also in contact with the first well region 204.

[0086] In this embodiment, the method for forming the first doped layer 208 and the second doped layer 209 includes: etching the first fin 201 using the first dummy gate structure 206 and the second dummy gate structure 207 as masks to form a first doping opening and a second doping opening (not labeled) in the first fin 201; forming the first doped layer 208 in the first doping opening; forming the second doped layer 209 in the second doping opening.

[0087] In this embodiment, the method for forming the first doped layer 208 and the second doped layer 209 includes: using an epitaxial growth process to form a first epitaxial layer in the first doping opening and a second epitaxial layer (not shown) in the second doping opening; performing in-situ doping on the first epitaxial layer and the second epitaxial layer during the epitaxial growth process, and doping the first doping ions into the first epitaxial layer and the second epitaxial layer to form the first doped layer 208 and the second doped layer 209.

[0088] In other embodiments, the first doped layer and the second doped layer can also be formed by a first doped ion implantation process.

[0089] In this embodiment, the first doped layer 208 and the second doped layer 209 are located in the first fin 201.

[0090] In other embodiments, the first doped layer and the second doped layer are located in the fin.

[0091] In this embodiment, the first doped layer 208 has a first width dimension d1 along the first direction X, the second doped layer 209 has a second width dimension d2 along the first direction X, and the first width dimension d1 is greater than the second width dimension d2.

[0092] By increasing the width dimension of the first doped layer 208 along the first direction X, the spacing between the subsequently formed first conductive plug and the second gate structure is increased, preventing the second gate structure from being discharged and broken down, so as to improve the protection ability of the device.

[0093] Please refer to Figure 10 , after forming the first doped layer 208 and the second doped layer 209, a dielectric layer 210 is formed on the substrate, and the dielectric layer 210 covers the sidewalls of the first dummy gate structure 206 and the second dummy gate structure 207.

[0094] In this embodiment, the material of the dielectric layer 210 is silicon oxide; in other embodiments, the material of the dielectric layer can also be a low-k dielectric material (referring to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-k dielectric material (referring to a dielectric material with a relative dielectric constant lower than 2.5).

[0095] Please refer to Figure 11 , after forming the dielectric layer 210, the first dummy gate structure 206 is removed, and a first opening 211 is formed in the dielectric layer 210, and the first opening 211 is located in the first region I; the second dummy gate structure 207 is removed, and a second opening 212 is formed in the dielectric layer 210, and the second opening 212 is located in the second region II.

[0096] In this embodiment, specifically, the first dummy gate dielectric layer and the first dummy gate layer of the first dummy gate structure 206 are removed; the second dummy gate dielectric layer and the second dummy gate layer of the second dummy gate structure 207 are removed.

[0097] Please refer to Figure 12 , the first gate structure 213 is formed in the first opening 211; the second gate structure 214 is formed in the second opening 212.

[0098] In this embodiment, the first gate structure 213 includes: a first gate dielectric layer and a first gate layer (not labeled) located on the first gate dielectric layer.

[0099] In this embodiment, the second gate structure 214 includes: a second gate dielectric layer and a second gate layer (not labeled) located on the second gate dielectric layer.

[0100] In this embodiment, a first well region 204 is formed in the first region I, and first doping ions are present in the first well region 204; a second well region 205 is formed in the second region II, and second doping ions are present in the second well region 205. The second doping ions have a conductivity type different from that of the first doping ions, so that a reverse-biased junction is formed at the junction of the first well region 204 and the second well region 205. Since the first gate structure 213 is serially connected to the reverse-biased junction through the first well region 204, the resistance value of the branch formed by the first gate structure 213 and the reverse-biased junction increases. During the electrostatic discharge process, the branch formed by the first gate structure 213 and the reverse-biased structure is equivalent to an open circuit state. Therefore, the risk of the first gate structure 213 being broken down is reduced, thereby improving the performance of the finally formed semiconductor structure.

[0101] Please refer to Figure 13 , a heavily doped region 215 is formed in the second well region 205. The isolation structure 203 is located between the heavily doped region 215 and the second doping layer 209. Third doping ions are present in the heavily doped region 215. The third doping ions have the same electrical type as the second doping ions, and the concentration of the third doping ions in the heavily doped region 215 is greater than the concentration of the second doping ions in the second well region 205.

[0102] In this embodiment, the purpose of forming the heavily doped region 215 with high-concentration doping in the second well region 205 is to reduce the contact resistance between the subsequently formed second conductive plug and the second well region 205 by using the heavily doped region 215 with high-concentration doping.

[0103] Please refer to Figure 14 , after forming the heavily doped region 215, the first doping layer 208 is connected to the electrostatic output terminal; the second doping layer 209, the second gate structure 214, and the heavily doped region 215 are connected to the electrostatic input terminal.

[0104] In this embodiment, the method of connecting the first doping layer 208 to the electrostatic output terminal includes: forming a first conductive plug 216 on the first doping layer 208, and the first conductive plug 216 is connected to the electrostatic output terminal.

[0105] In this embodiment, the first conductive plug 216 and the first gate structure 213 have a first spacing dimension s1 along the first direction X, and the first conductive plug 216 and the second gate structure 214 have a second spacing dimension s2 along the first direction X. The second spacing dimension s1 is greater than the first spacing dimension s2.

[0106] By increasing the spacing between the first conductive plug 216 and the second gate structure 214, the second gate structure 214 is prevented from being discharged and broken down, thereby improving the protection ability of the device.

[0107] In this embodiment, the method of connecting the second doped layer 209, the second gate structure 214, and the heavily doped region 215 to the electrostatic input terminal includes: forming second conductive plugs 217 on the second doped layer 209, the second gate structure 214, and the heavily doped region 215 respectively, and the second conductive plugs 217 are connected to the electrostatic input terminal.

[0108] In this embodiment, the materials of the first conductive plug 216 and the second conductive plug 217 are copper.

[0109] Correspondingly, the present invention also provides an electrostatic discharge protection structure. Please continue to refer to Figure 14 which includes: a substrate, the substrate includes a first region I and a plurality of second regions II arranged along the first direction X, the first region I is located between adjacent second regions II; a first well region 204 located in the first region I, the first well region 204 has first doping ions; a second well region 205 located in the second region II, the second well region 205 has second doping ions, and the conductivity type of the second doping ions is different from that of the first doping ions; a first gate structure 213 located on the first region I; a second gate structure 214 located on the second region II; a first doped layer 208 and a second doped layer 209 respectively located in the substrate on both sides of the second gate structure 214, the first doped layer 208 and the second doped layer 209 have the first doping ions, the first doped layer 208 and the second doped layer 209 are respectively located in the second well region 205, and the first doped layer 208 is also in contact with the first well region 204.

[0110] In this embodiment, through the first well region 204 located in the first region I, the first well region 204 has first doping ions; the second well region 205 located in the second region II, the second well region 205 has second doping ions, and the electrical type of the second doping ions is different from that of the first doping ions, so that a reverse-biased junction is formed at the junction of the first well region 204 and the second well region 205. Since the first gate structure 213 is connected in series with the reverse-biased junction through the first well region 204, the resistance value of the branch formed by the first gate structure 213 and the reverse-biased junction is increased. During the electrostatic discharge process, the branch formed by the first gate structure 213 and the reverse-biased structure is equivalent to an open circuit state. Therefore, the risk of the first gate structure 213 being broken down is reduced, thereby improving the performance of the finally formed semiconductor structure.

[0111] The first doping ion includes an N-type ion; the first doping ion includes: phosphorus or arsenic. In this embodiment, the first doping ion is phosphorus.

[0112] The second doping ion includes a P-type ion; the second doping ion includes: boron or indium. In this embodiment, the second doping ion is boron.

[0113] In this embodiment, the substrate includes: a substrate 200, a first fin 201 and a second fin 202 located on the substrate 200. The first fin 201 has the first well region 204 and the second well region 205, and the first doping layer 208 and the second doping layer 209 are located in the first fin 201. The second fin 202 has the second well region 205.

[0114] In other embodiments, the substrate includes: a substrate and fins located on the substrate. The fins have the first well region and the second well region, and the first doping layer and the second doping layer are located in the fins.

[0115] In this embodiment, it further includes: an isolation structure 203 located between the first fin 201 and the second fin 202.

[0116] In other embodiments, it further includes: an isolation structure located in the fins.

[0117] In this embodiment, it further includes: a heavily doped region 215 formed in the second well region 205. The isolation structure 203 is located between the heavily doped region 215 and the second doping layer 209. The heavily doped region 215 has a third doping ion. The third doping ion has the same electrical type as the second doping ion, and the concentration of the third doping ion in the heavily doped region 215 is greater than the concentration of the second doping ion in the second well region 205.

[0118] In this embodiment, the first doping layer 208 is connected to an electrostatic output terminal; the second doping layer 209, the second gate structure 214, and the heavily doped region 215 are connected to an electrostatic input terminal.

[0119] In this embodiment, it further includes: first conductive plugs 216 respectively located on the first doping layer 208. The first conductive plugs 216 are connected to the electrostatic output terminal; second conductive plugs 217 respectively located on the second doping layer 209, the second gate structure 214, and the heavily doped region 215. The second conductive plugs 217 are connected to the electrostatic input terminal.

[0120] In this embodiment, the first gate structure 213 includes a first gate dielectric layer and a first gate layer (not labeled) located on the first gate dielectric layer.

[0121] In this embodiment, the first conductive plug 216 and the first gate structure 213 have a first spacing dimension s1 along the first direction X, the first conductive plug 216 and the second gate structure 214 have a second spacing dimension s2 along the first direction X, and the second spacing dimension s2 is greater than the first spacing dimension s1. By increasing the spacing between the first conductive plug 216 and the second gate structure 214, the second gate structure 214 is prevented from being discharged and broken down, so as to improve the protection ability of the device.

[0122] In this embodiment, the first doped layer 208 has a first width dimension d1 along the first direction X, the second doped layer 209 has a second width dimension d2 along the first direction X, and the first width dimension d1 is greater than the second width dimension d2. By increasing the width dimension of the first doped layer 208 along the first direction X, the spacing between the first conductive plug 216 and the second gate structure 214 is further increased, so as to prevent the second gate structure 214 from being discharged and broken down, and improve the protection ability of the device.

[0123] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. An electrostatic discharge protection structure, characterized in that, Comprising: A substrate, the substrate including a first region and a plurality of second regions arranged in a first direction, the first region being located between adjacent second regions; A first well region located in the first region, the first well region having first doping ions; A second well region located in the second region, the second well region having second doping ions, the second doping ions having a different conductivity type from the first doping ions; A first gate structure located on the first region; A second gate structure located on the second region; A first doping layer and a second doping layer respectively located in the substrate on both sides of the second gate structure, the first doping layer and the second doping layer having the first doping ions, the first doping layer and the second doping layer being respectively located in the second well region, and the first doping layer also being in contact with the first well region.

2. The electrostatic discharge protection structure according to claim 1, wherein The first doping ions include N-type ions; the first doping ions include: phosphorus or arsenic.

3. The electrostatic discharge protection structure according to claim 1, wherein The second doping ions include P-type ions; The second doping ions include: boron or indium.

4. The electrostatic discharge protection structure according to claim 1, characterized in that, The substrate includes: a substrate and fins located on the substrate, the fins having the first well region and the second well region, and the first doping layer and the second doping layer being located in the fins.

5. The electrostatic discharge protection structure according to claim 4, wherein, Further comprising: An isolation structure located in the fins.

6. The electrostatic discharge protection structure according to claim 1, wherein, The substrate includes: a substrate and a first fin and a second fin located on the substrate, the first fin having the first well region and the second well region, and the first doping layer and the second doping layer being located in the first fin, the second fin having the second well region.

7. The electrostatic discharge protection structure according to claim 6, wherein, Further comprising: An isolation structure located between the first fin and the second fin.

8. The electrostatic discharge protection structure according to claim 5 or 7, characterized in that, Further comprising: A heavily doped region is formed in the second well region, the isolation structure is located between the heavily doped region and the second doping layer, the heavily doped region having third doping ions, the third doping ions having the same electrical type as the second doping ions, and the concentration of the third doping ions in the heavily doped region being greater than the concentration of the second doping ions in the second well region.

9. The electrostatic discharge protection structure according to claim 8, wherein The first doping layer is connected to an electrostatic output terminal; the second doping layer, the second gate structure, and the heavily doped region are connected to an electrostatic input terminal.

10. The electrostatic discharge protection structure according to claim 9, wherein, Further comprising: First conductive plugs respectively located on the first doping layer, the first conductive plugs being connected to the electrostatic output terminal; Second conductive plugs respectively located on the second doping layer, the second gate structure, and the heavily doped region, the second conductive plugs being connected to the electrostatic input terminal.

11. The electrostatic discharge protection structure according to claim 1, wherein, The first gate structure includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer.

12. The electrostatic discharge protection structure according to claim 10, wherein The first conductive plug and the first gate structure have a first spacing dimension in the first direction, the first conductive plug and the second gate structure have a second spacing dimension in the first direction, and the second spacing dimension is greater than the first spacing dimension.

13. The electrostatic discharge protection structure according to claim 12, wherein The first doping layer has a first width dimension in the first direction, the second doping layer has a second width dimension in the first direction, and the first width dimension is greater than the second width dimension.

14. A method for forming an electrostatic discharge protection structure, characterized in that, Comprising: Provide a substrate, the substrate including a first region and a plurality of second regions arranged in a first direction, the first region being located between adjacent second regions; Form a first well region in the first region, the first well region having first doping ions; Form a second well region in the second region, the second well region having second doping ions, the electrical type of the second doping ions being different from that of the first doping ions; Form a first gate structure on the first region; Form a second gate structure on the second region; Form a first doped layer and a second doped layer in the substrate on both sides of the second gate structure respectively, the first doped layer and the second doped layer having the first doping ions, the first doped layer and the second doped layer being respectively located in the second well region, and the first doped layer further contacting the first well region.

15. The method for forming the electrostatic discharge protection structure according to claim 14, wherein, The forming method of the first well region and the second well region includes: forming a first patterned layer on the substrate, the first patterned layer exposing the top surface of the first region; using the first patterned layer as a mask, performing an implantation process of first doping ions on the first region to form the first well region in the first region; after forming the first well region, removing the first patterned layer; forming a second patterned layer on the substrate, the second patterned layer exposing the top surface of the second region; using the second patterned layer as a mask, performing an implantation process of second doping ions on the second region to form the second well region in the second region.

16. The method for forming the electrostatic discharge protection structure according to claim 14, wherein, The first doping ions include N-type ions; the first doping ions include: phosphorus or arsenic.

17. The method for forming the electrostatic discharge protection structure according to claim 14, wherein, The second doping ions include P-type ions; The second doping ions include: boron or indium.

18. The method for forming the electrostatic discharge protection structure according to claim 14, wherein, The substrate includes: a substrate and fins located on the substrate, the fins having the first well region and the second well region, and the first doped layer and the second doped layer being located in the fins.

19. The method for forming the electrostatic discharge protection structure according to claim 18, wherein, Further include: Form an isolation structure, the isolation structure being located in the fins.

20. The method for forming the electrostatic discharge protection structure according to claim 14, wherein The substrate includes: a substrate and a first fin and a second fin located on the substrate, the first fin having the first well region and the second well region, and the first doped layer and the second doped layer being located in the first fin, the second fin having the second well region.

21. The method for forming the electrostatic discharge protection structure according to claim 20, wherein, Further include: Form an isolation structure, the isolation structure being located between the first fin and the second fin.

22. The method for forming the electrostatic discharge protection structure according to claim 19, wherein, The forming method of the fins and the isolation structure includes: providing an initial substrate; forming a third patterned layer on the initial substrate, the third patterned layer exposing a part of the top surface of the initial substrate; etching the initial substrate using the third patterned layer as a mask to form a substrate and fins located on the substrate; etching a part of the fins to form isolation openings in the fins; forming the isolation structure in the isolation openings.

23. The method for forming the electrostatic discharge protection structure according to claim 21, wherein, The forming method of the first fin portion, the second fin portion and the isolation structure includes: providing an initial substrate; forming a third patterned layer on the initial substrate, the third patterned layer exposing a top surface of a part of the initial substrate; etching the initial substrate using the third patterned layer as a mask to form a substrate and a first fin portion and a second fin portion located on the substrate, with an isolation opening between the first fin portion and the second fin portion; forming the isolation structure in the isolation opening.

24. The method for forming the electrostatic discharge protection structure according to claim 19 or 21, wherein, After forming the isolation structure, it further includes: forming a heavily doped region in the second well region, the isolation structure being located between the heavily doped region and the second doped layer, the heavily doped region having a third doping ion, the third doping ion having the same electrical type as the second doping ion, and the concentration of the third doping ion in the heavily doped region being greater than the concentration of the second doping ion in the second well region.

25. The method for forming the electrostatic discharge protection structure according to claim 24, wherein, After forming the heavily doped region, it further includes: connecting the first doped layer to an electrostatic output terminal; connecting the second doped layer, the second gate structure and the heavily doped region to an electrostatic input terminal.

26. The method for forming the electrostatic discharge protection structure according to claim 25, wherein, The method of connecting the first doped layer to the electrostatic output terminal includes: forming a first conductive plug on the first doped layer, the first conductive plug connecting to the electrostatic output terminal.

27. The method for forming the electrostatic discharge protection structure according to claim 25, wherein The method of connecting the second doped layer, the second gate structure and the heavily doped region to the electrostatic input terminal includes: forming second conductive plugs on the second doped layer, the second gate structure and the heavily doped region respectively, the second conductive plugs connecting to the electrostatic input terminal.

28. The method for forming the electrostatic discharge protection structure according to claim 14, wherein, The first gate structure includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer.

29. The method for forming the electrostatic discharge protection structure according to claim 26, wherein The first conductive plug and the first gate structure have a first spacing dimension along the first direction, the first conductive plug and the second gate structure have a second spacing dimension along the first direction, and the second spacing dimension is greater than the first spacing dimension.

30. The method for forming the electrostatic discharge protection structure according to claim 29, wherein, The first doped layer has a first width dimension along the first direction, the second doped layer has a second width dimension along the first direction, and the first width dimension is greater than the second width dimension.

Images