Semiconductor device

Abstract

Embodiments provide a semiconductor device capable of arranging a plurality of active regions at high density in a substrate. According to an embodiment, the semiconductor device includes a plurality of active regions provided in a substrate, a first active region, a second active region, a third active region, and a fourth active region each including a central portion, a first portion in a first direction of the central portion, a second portion on an opposite side of the first portion, a third portion in a second direction of the central portion, and a fourth portion on an opposite side of the third portion. Furthermore, an end portion of the first portion of the first active region faces a side portion of the fourth portion of the fourth active region, an end portion of the second portion of the second active region faces a side portion of the third portion of the third active region, an end portion of the third portion of the third active region faces a side portion of the first portion of the first active region, and an end portion of the fourth portion of the fourth active region faces a side portion of the second portion of the second active region.

Description

[0001] [Cross-reference to related applications]

[0002] This application claims priority to Japanese Patent Application No. 2020-151885 (filed on September 10, 2020). This application incorporates all contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device. Background Technology

[0004] When multiple active regions are formed within a substrate, the density of active regions on the substrate surface may sometimes be low depending on the planar shape of the active regions. To improve the integration of semiconductor devices, it is ideal to arrange the multiple active regions in a high density within the substrate. Summary of the Invention

[0005] The embodiments provide a semiconductor device capable of arranging multiple active regions in a high density within a substrate.

[0006] According to one embodiment, a semiconductor device includes: a substrate; a plurality of active regions disposed within the substrate; and a device separation region disposed within the substrate. Furthermore, the first, second, third, and fourth active regions among the plurality of active regions each include: a central portion; a first portion disposed in a first direction of the central portion; a second portion disposed on the opposite side of the first portion in the first direction of the central portion; a third portion disposed in a second direction of the central portion orthogonal to the first direction; and a fourth portion disposed on the opposite side of the third portion in the second direction of the central portion. Furthermore, the end of the first portion of the first active region faces the side of the fourth portion of the fourth active region, the end of the second portion of the second active region faces the side of the third portion of the third active region, the end of the third portion of the third active region faces the side of the first portion of the first active region, and the end of the fourth portion of the fourth active region faces the side of the second portion of the second active region. Attached Figure Description

[0007] Figure 1 This is a top view showing the structure of the semiconductor device according to the first embodiment.

[0008] Figure 2 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0009] Figure 3 This is a top view showing the structure of the semiconductor device of the comparative example of the first embodiment.

[0010] Figure 4 (a) and (b) are top views used to compare the semiconductor device of the comparative example with the semiconductor device of the first embodiment.

[0011] Figure 5 This is a top view showing the structure of the semiconductor device according to the second embodiment.

[0012] Figure 6 This is a top view used to provide a detailed description of the structure of the semiconductor device according to the second embodiment.

[0013] Figure 7 This is a top view showing an example of the wiring structure of the semiconductor device according to the first embodiment.

[0014] Figure 8 This is a top view showing an example of the wiring structure of the semiconductor device according to the second embodiment.

[0015] Figure 9 (a) to (d) are top views showing examples of the shape of the diffusion region of the semiconductor device according to the second embodiment. Detailed Implementation

[0016] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Figures 1 to 9 In Chinese, identical symbols are added to identical components, and repeated descriptions are omitted.

[0017] (First Embodiment)

[0018] Figure 1 This is a top view showing the structure of the semiconductor device according to the first embodiment.

[0019] The semiconductor device in this embodiment is, for example, a three-dimensional memory, which includes a memory cell array and a peripheral circuit section. The memory cell array includes cell transistors (memory cells) and select transistors. The peripheral circuit section includes peripheral transistors that control the operation of the memory cell array, such as LV (low voltage) transistors with thin gate insulating films and HV (high voltage) transistors with thick gate insulating films. Figure 1 The peripheral circuit section is shown, specifically, multiple peripheral transistors (e.g., HV transistors) Tr within the peripheral circuit section are shown. These transistors Tr are examples of control transistors.

[0020] like Figure 1As shown, the semiconductor device of this embodiment includes a substrate 1, multiple active regions 2, element separation regions 3, multiple gate electrodes 4, multiple diffusion regions 5, multiple contact plugs 6, multiple diffusion regions 7, multiple contact plugs 8, and multiple contact plugs 9. Diffusion region 5 is an example of a first diffusion region, and contact plug 6 is an example of a first plug. Diffusion region 7 is an example of a second diffusion region, and contact plug 8 is an example of a second plug. Contact plug 9 is an example of a third plug.

[0021] Substrate 1 is, for example, a semiconductor substrate such as a silicon (Si) substrate. Figure 1 The X and Y directions, which are parallel to and perpendicular to the surface (upper surface) of substrate 1, and the Z direction, which is perpendicular to the surface (upper surface) of substrate 1, are shown. In this specification, the +Z direction is considered the upward direction, and the -Z direction is considered the downward direction. The -Z direction may or may not be aligned with the direction of gravity. The ±Y direction is an example of the first direction, and the ±X direction is an example of the second direction.

[0022] The planar shape of the upper surface of substrate 1 is, for example, a square or rectangle having two sides parallel to the X direction and two sides parallel to the Y direction. The two sides parallel to the Y direction are examples of the first side. The two sides parallel to the X direction are examples of the second side. Figure 1 A portion of the upper surface of substrate 1 is shown. The shape of substrate 1 is, for example, a cuboid with an upper surface, a lower surface, and four side surfaces (end faces).

[0023] The plurality of active regions 2 are disposed within the substrate 1 as part of the substrate 1. Thus, the plurality of active regions 2 are formed, for example, from a semiconductor substrate such as a silicon substrate. The plurality of active regions 2 are also referred to as AA (Active Area).

[0024] Each active region 2 includes a protruding portion 2a, a protruding portion 2b, a protruding portion 2c, a protruding portion 2d, and a central portion 2e. The protruding portions 2a, 2b, 2c, and 2d are respectively positioned in the +Y, -Y, -X, and +X directions of the central portion 2e, protruding from the central portion 2e in these multiple directions. Thus, the planar shape of each active region 2 in this embodiment is a cross shape with the protruding portions 2a, 2b, 2c, and 2d arranged around the central portion 2e. The protruding portion 2b is located on the opposite side of the protruding portion 2a relative to the central portion 2e, and the protruding portion 2d is located on the opposite side of the protruding portion 2c relative to the central portion 2e. The protruding portions 2a, 2b, 2c, and 2d are examples of the first, second, third, and fourth portions, respectively.

[0025] The planar shapes of the protruding portions 2a to 2d and the central portion 2e are, for example, squares or rectangles. The protruding portions 2a to 2d each have an end point E1 that is the opposite side of the central portion 2e, and two side portions E2 that connect the central portion 2e to the end point E1. For example, in the protruding portion 2c, the side in the -X direction becomes the end point E1, and the side in the ±Y direction becomes the side portion E2. Furthermore, the planar shape of each active region 2 can be other than a cross shape, and the planar shapes of the protruding portions 2a to 2d and the central portion 2e can be other than squares or rectangles.

[0026] Component separation regions 3 are disposed within the substrate 1 and are formed by a component separation insulating film embedded in a component separation groove within the substrate 1. This component separation insulating film is, for example, a silicon insulating film. In this embodiment, the component separation regions 3 have a shape that surrounds each active region 2. Thus, the planar shape of each active region 2 is as follows: Figure 1 As shown, it forms a cross shape. The component separation insulating film 3 is also known as the STI (Shallow Trench Isolation) area.

[0027] The plurality of gate electrodes 4 are formed on the protrusions 2a to 2d of each active region 2, separated by a gate insulating film. Thus, four peripheral transistors Tr are disposed on each active region 2. The peripheral transistors Tr on the protrusions 2a to 2d are examples of the first to fourth transistors, respectively. The plurality of gate electrodes 4 includes a gate electrode 4a on the protrusion 2a, a gate electrode 4b on the protrusion 2b, a gate electrode 4c on the protrusion 2c, and a gate electrode 4d on the protrusion 2d. Each contact plug 9 is formed on the corresponding gate electrode 4.

[0028] Each diffusion region 5 is formed within the central portion 2e of each active region 2, and contains a high concentration of p-type or n-type impurities. The planar shape of the diffusion region 5 in this embodiment is, for example, rectangular or a similar rectangular shape. Each contact plug 6 is formed on the corresponding diffusion region 5.

[0029] Each diffusion region 7 is formed within any one of the protrusions 2a to 2d of each active region 2, and contains a high concentration of p-type or n-type impurities. Thus, each active region 2 contains four diffusion regions 7 within its protrusions 2a to 2d. The planar shape of the diffusion regions 7 in this embodiment is, for example, rectangular or similar. Each contact plug 8 is formed on its corresponding diffusion region 7.

[0030] Furthermore, the active regions 2 in this embodiment have the same shape. Moreover, these active regions 2 are periodically arranged within the substrate 1 along the X and Y directions. Furthermore, the arrangement of the gate electrodes 4 on these active regions 2, and the arrangement of the diffusion regions 5 and 7 within these active regions 2, are also identical between the active regions 2. However, in this embodiment, the active regions 2 may have different shapes, and the arrangements of the gate electrodes 4 and the diffusion regions 5 and 7 may also differ between the active regions 2. Furthermore, these active regions 2 may also be arranged non-periodically.

[0031] Figure 2 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0032] Figure 2 It is along Figure 1 The cross-sectional view of the straight line L shown. In addition to the aforementioned constituent elements, the semiconductor device of this embodiment also includes a plurality of source / drain regions 11, a plurality of gate insulating films 12, a plurality of cover insulating films 13, a plurality of sidewall insulating films 14, and an interlayer insulating film 15.

[0033] Figure 2 The location of an active region 2, and the locations of the protruding portions 2a, 2b, and central portion 2e within that active region 2 are indicated by dashed lines. Each active region 2 in this embodiment is shown as follows: Figure 1 The diagram shows multiple source / drain regions 11. Specifically, in this embodiment, each active region 2 includes five source / drain regions 11 within its protruding portions 2a-2d and central portion 2e, and each source / drain region 11 includes either a diffusion region 5 or a diffusion region 7. These source / drain regions 11 contain p-type or n-type impurities. In this embodiment, the active region 2 is, for example, a p-type impurity region, and the diffusion regions 5, 7, and source / drain regions 11 are, for example, n-type impurity regions.

[0034] Each peripheral transistor Tr includes, in sequence, a gate insulating film 12, a gate electrode 4, and a cover insulating film 13 on any protruding portion 2a-2d. Sidewall insulating films 14 are included on the sides of the gate insulating film 12, gate electrode 4, and cover insulating film 13. The gate insulating film 12, gate electrode 4, and cover insulating film 13 are arranged between two source / drain regions 11. The gate insulating film 12 is, for example, a silicon oxide film or a high-k (high dielectric constant) insulating film. The gate electrode 4 is, for example, a polysilicon layer or a metal layer. The cover insulating film 13 is, for example, a silicon oxide film or a silicon nitride film. The sidewall insulating film 14 is, for example, a laminated film comprising a silicon oxide film and a silicon nitride film. Figure 2The gate electrode 4a on the protrusion 2a and the gate electrode 4b on the protrusion 2b are shown. On each peripheral transistor Tr, a contact plug 9 is formed on the gate electrode 4 through and covering the insulating film 14.

[0035] An interlayer insulating film 15 is formed on the substrate 1, specifically, on each active region 2 and on the element separation insulating film 3, in a manner covering each peripheral transistor Tr. Contact plugs 6 and 8 are formed within the interlayer insulating film 15 on the diffusion regions 5 and 7. The interlayer insulating film 15 is, for example, a silicon oxide film.

[0036] Next, refer to again Figure 1 The structure of the semiconductor device in this embodiment will be further described in detail.

[0037] In the semiconductor device of this embodiment, four adjacent active regions 2 form a block. For example, four active regions 2, denoted by the symbols P1, P2, P3, and P4, form a block A. In the following description, the active regions 2 denoted by the symbols P1, P2, P3, and P4 will be referred to as active regions P1, P2, P3, and P4, respectively. Active regions P1, P2, P3, and P4 are examples of the first, second, third, and fourth active regions, respectively. Hereinafter, each block of this embodiment will be described in detail using block A as an example. The following description of block A also applies to other blocks of this embodiment.

[0038] Block A is formed by a protruding portion 2a of active region P1, a protruding portion 2b of active region P2, a protruding portion 2c of active region P3, and a protruding portion 2d of active region P4. In block A, the end point E1 of the protruding portion 2a of active region P1 faces the side portion E2 of the protruding portion 2d of active region P4. Furthermore, the end point E1 of the protruding portion 2b of active region P2 faces the side portion E2 of the protruding portion 2c of active region P3. Similarly, the end point E1 of the protruding portion 2c of active region P3 faces the side portion E2 of the protruding portion 2a of active region P1. Finally, the end point E1 of the protruding portion 2d of active region P4 faces the side portion E2 of the protruding portion 2c of active region P2.

[0039] Figure 1 The distances W1 between the protrusion 2a of active region P1 and the protrusion 2d of active region P4, W2 between the protrusion 2b of active region P2 and the protrusion 2c of active region P3, W3 between the protrusion 2c of active region P3 and the protrusion 2a of active region P1, and W4 between the protrusion 2d of active region P4 and the protrusion 2b of active region P2 are shown. Distances W1, W2, W3, and W4 are examples of the first, second, third, and fourth distances, respectively. In this embodiment, distances W1, W2, W3, and W4 are equal to each other (W1 = W2 = W3 = W4).

[0040] Figure 1 The width W of the protruding portions 2a to 2d is also shown. Width W represents the width of the protruding portions 2a and 2b in the X direction and the width of the protruding portions 2c and 2d in the Y direction. In this embodiment, the protruding portions 2a, 2b, 2c, and 2d have the same width W. In this embodiment, the distances W1, W2, W3, and W4 are shorter than the width W (W1, W2, W3, and W4 < W). Therefore, in block A of this embodiment, the protruding portions 2a of the active region P1, 2b of the active region P2, 2c of the active region P3, and 2d of the active region P4 are densely arranged.

[0041] Furthermore, the distances W1 to W4 can be unequal. Additionally, the protrusions 2a to 2d can also not have the same width. Furthermore, the distances W1 to W4 can be no shorter than the width W. However, in order to properly arrange multiple active regions 2 within the substrate 1, it is ideal that the distances W1 to W4 are equal, the protrusions 2a to 2d ideally have the same width, and the distances W1 to W4 ideally are shorter than the width W.

[0042] Figure 3 This is a top view showing the structure of the semiconductor device of the comparative example of the first embodiment.

[0043] Similar to the semiconductor device of this embodiment, the semiconductor device of this comparative example includes a substrate 1, multiple active regions 2, a device separation region 3, multiple gate electrodes 4, multiple diffusion regions 5, multiple contact plugs 6, multiple diffusion regions 7, multiple contact plugs 8, and multiple contact plugs 9. Figure 1 Similarly, Figure 3 The active regions P1, P2, P3, P4, and block A are shown. Figure 3 The distance W5 between protrusions 2a and 2b of adjacent active regions 2, and the distance W6 between protrusions 2c and 2d of adjacent active regions 2 are also shown.

[0044] In block A of this comparative example, the end E1 of the protruding portion 2a of active region P1 faces the side E2 of the protruding portion 2c of active region P3 and the side E2 of the protruding portion 2d of active region P4. Furthermore, the end E1 of the protruding portion 2b of active region P2 faces the side E2 of the protruding portion 2c of active region P3 and the side E2 of the protruding portion 2d of active region P4. Also, the end E1 of the protruding portion 2c of active region P3 faces the end E1 of the protruding portion 2d of active region P4.

[0045] In this comparative example, because the active regions 2 are arranged in this layout, the distance W5 between the protrusions 2a and 2b of adjacent active regions 2 becomes longer, resulting in a larger space between these protrusions 2a and 2b. Furthermore, the distance W6 between the protrusions 2c and 2d of adjacent active regions 2 also becomes longer, resulting in a larger space between these protrusions 2c and 2d. Compared to block A of this embodiment, in block A of this comparative example, the protrusions 2a of active region P1, 2b of active region P2, 2c of active region P3, and 2d of active region P4 are not densely packed.

[0046] Figure 4 This is a top view used to compare the semiconductor device of the comparative example with the semiconductor device of the first embodiment.

[0047] and Figure 3 Similarly, Figure 4 (a) indicates the semiconductor device of this comparative example. Figure 4 (a) shows blocks A, B, C, and D as four adjacent active regions 2. In this comparative example, the peripheral transistor Tr operates on a block-by-block basis. The semiconductor device of this comparative example includes multiple blocks A, multiple blocks B, multiple blocks C, and multiple blocks D. Figure 4 (a) shows a block A, a block B, a block C, and a block D as part of these blocks A to D.

[0048] and Figure 1 Similarly, Figure 4 (b) indicates the semiconductor device of this embodiment. Figure 4 (a) Similarly, Figure 4 (b) shows blocks A, B, C, and D as four adjacent active regions 2. In this embodiment, the peripheral transistor Tr also operates on a block-by-block basis. The semiconductor device of this embodiment includes multiple blocks A, multiple blocks B, multiple blocks C, and multiple blocks D. Figure 4 (b) shows a block A, a block B, a block C, and a block D as part of these blocks A to D.

[0049] In each block of this comparative example, protrusion 2b is disposed in the +Y direction of protrusion 2a, and protrusion 2d is disposed in the -X direction of protrusion 2c. In this comparative example, by adopting this configuration, the density of active region 2 on the surface of substrate 1 is reduced. For example, a larger space is generated near the side E2 of protrusions 2a to 2d in each block (see reference). Figure 3 (The distances W5 and W6). If such a large space exists, the integration density of the semiconductor device will decrease.

[0050] On the other hand, in each block of this embodiment, the protruding portion 2b is disposed in the inclined direction of the protruding portion 2a, and the protruding portion 2d is disposed in the inclined direction of the protruding portion 2c. Here, the former's inclined direction is approximately 45 degrees relative to the +Y direction, and the latter's inclined direction is approximately 45 degrees relative to the -X direction. As a result, the end E1 of the protruding portion 2a faces the side E2 of the protruding portion 2d, the end E1 of the protruding portion 2b faces the side E2 of the protruding portion 2c, the end E1 of the protruding portion 2c faces the side E2 of the protruding portion 2a, and the end E1 of the protruding portion 2d faces the side E2 of the protruding portion 2c. According to this embodiment, by adopting this configuration, the density of the active region 2 on the surface of the substrate 1 can be increased. As a result, the integration density of the semiconductor device can be improved.

[0051] Hereinafter, various differences between the semiconductor device of the comparative example and the semiconductor device of the first embodiment will be described.

[0052] In each block of this comparative example, the distances between protruding portions 2a and 2c, between protruding portions 2a and 2d, between protruding portions 2b and 2c, between protruding portions 2b and 2d, and between protruding portions 2c and 2d are shorter than the width W of the active region 2, but the distance between protruding portions 2a and 2b is greater than the width W of the active region 2. On the other hand, in each block of this embodiment, the distances between protruding portions 2a and 2c (W3), between protruding portions 2a and 2d (W1), between protruding portions 2b and 2c (W2), between protruding portions 2b and 2d (W4), between protruding portions 2c and 2d, and between protruding portions 2a and 2b are shorter than the width W of the active region 2.

[0053] Furthermore, in this comparative example, the protruding portions 2c and 2d of each active region 2 are disposed between the protruding portions 2a and 2b of the other two active regions 2. On the other hand, in this embodiment, the protruding portion 2c of each active region 2 is disposed between the protruding portions 2b and 2d of the other two active regions 2, and the protruding portion 2d of each active region 2 in this embodiment is disposed between the protruding portions 2a and 2c of the other two active regions 2.

[0054] Furthermore, the width of the component separation region 3 in this comparative example varies depending on its position. For example, the width of the component separation region 3 in this comparative example increases near the side E2 of the protruding portions 2a to 2d of each block. On the other hand, the width of the component separation region 3 in this embodiment is a constant width W regardless of its position.

[0055] As described above, in each block of this embodiment, the end E1 of the protruding portion 2a faces the side E2 of the protruding portion 2d, the end E1 of the protruding portion 2b faces the side E2 of the protruding portion 2c, the end E1 of the protruding portion 2c faces the side E2 of the protruding portion 2a, and the end E1 of the protruding portion 2d faces the side E2 of the protruding portion 2c. Therefore, according to this embodiment, a plurality of active regions 2 can be arranged in a high density within the substrate 1. This improves the integration density of the semiconductor device of this embodiment.

[0056] (Second Implementation)

[0057] Figure 5 This is a top view showing the structure of the semiconductor device according to the second embodiment.

[0058] like Figure 5 As shown, the semiconductor device of this embodiment has the same constituent elements as the semiconductor device of the first embodiment. Specifically, it includes a substrate 1, a plurality of active regions 2, a device separation region 3, a plurality of gate electrodes 4, a plurality of diffusion regions 5, a plurality of contact plugs 6, a plurality of diffusion regions 7, a plurality of contact plugs 8, and a plurality of contact plugs 9. Figure 4 (b) Similarly, Figure 5 Blocks A, B, C, and D are shown. However, Figure 5 The diagram shows one block A, two blocks B, one block C, and two blocks D.

[0059] Figure 5 The X' direction, which is tilted relative to the X direction, and the Y' direction, which is tilted relative to the Y direction, are also shown. Similar to the X and Y directions, the X' and Y' directions are parallel to and perpendicular to each other on the upper surface of substrate 1. The ±Y' direction is an example of the first direction, and the ±X' direction is an example of the second direction.

[0060] The planar shape of the upper surface of substrate 1 is, for example, a square or rectangle having two sides parallel to the X direction and two sides parallel to the Y direction, as described above. The two sides parallel to the Y direction are examples of the first side. The two sides parallel to the X direction are examples of the second side. Figure 5 A portion of the upper surface of substrate 1 is shown. The shape of substrate 1 is, for example, a cuboid with an upper surface, a lower surface, and four side surfaces (end faces), as described above.

[0061] Similar to the active regions 2 of the first embodiment, each active region 2 of this embodiment includes protruding portions 2a, 2b, 2c, 2d and a central portion 2e. However, in this embodiment, the protruding portions 2a, 2b, 2c, and 2d are respectively disposed in the +Y', -Y', -X', and +X' directions of the central portion 2e, protruding from the central portion 2e in these directions. The planar shape of the protruding portions 2a to 2d and the central portion 2e in the first embodiment is, for example, a square or rectangle having a side parallel to the X direction and a side parallel to the Y direction. In contrast, the planar shape of the protruding portions 2a to 2d and the central portion 2e in this embodiment is, for example, a square or rectangle having a side parallel to the X' direction and a side parallel to the Y' direction. The planar shape of the active region 2 in this embodiment is, for example, a cross shape inclined relative to the four sides of the upper surface of the substrate 1.

[0062] In each block of this embodiment, the end E1 of the protruding portion 2a faces the side E2 of the protruding portion 2d, the end E1 of the protruding portion 2b faces the side E2 of the protruding portion 2c, the end E1 of the protruding portion 2c faces the side E2 of the protruding portion 2a, and the end E1 of the protruding portion 2d faces the side E2 of the protruding portion 2c. Therefore, according to this embodiment, similar to the first embodiment, a plurality of active regions 2 can be arranged in the substrate 1 with high density. This improves the integration density of the semiconductor device of this embodiment.

[0063] Figure 5 The distance S1 in the Y direction and the distance S2 in the X direction between the contact plugs 8 on the protrusions 2a of adjacent active regions 2 are also shown. In this embodiment, the protrusions 2a of adjacent active regions 2 are arranged relative to each other in either the X or Y direction. The same applies to the protrusions 2b, 2c, 2d, and central portions 2e of adjacent active regions 2. This configuration of the active regions 2 can be achieved by tilting the X' direction at a specific angle relative to the X direction and tilting the Y' direction at the same specific angle relative to the Y direction. The method for calculating this specific angle will be referred to... Figure 6 As will be described below.

[0064] Figure 6 This is a top view used to provide a detailed description of the structure of the semiconductor device according to the second embodiment.

[0065] Figure 6 yes Figure 5 The enlarged top view shows the straight line L1 extending in the X direction, the straight line L2 extending in the Y direction, the straight line L3 extending in the X' direction, and the straight line L4 extending in the Y' direction. Figure 6 In the image, a right triangle formed by lines L1, L2, and L4 is also shown using thick solid lines. Figure 6 The diagram also shows the angle θ between lines L2 and L4. Angle θ represents the slope of the X' direction relative to the X direction and the slope of the Y' direction relative to the Y direction. The length of the hypotenuse of the right triangle is set to the distance in the Y' direction between the protruding parts 2a, and the length of the longer side of the right triangle is set to the distance in the Y direction between the protruding parts 2a (S1). The inverse cosine function of the ratio R of these distances is calculated, from which the angle θ (θ = cos...) can be calculated. -1 R).

[0066] According to this embodiment, by arranging the central portions 2e of adjacent active regions 2 in the Y direction, the wiring connecting the contact plugs 6 on these central portions 2e to each other can be appropriately configured. Hereinafter, reference will be made to... Figures 7 to 9 This configuration will be explained in detail. Specifically, please refer to [link / reference]. Figure 7 The wiring structure of the semiconductor device in the first embodiment will be explained, and then refer to... Figure 8 The wiring structure of the semiconductor device in this embodiment (the second embodiment) is described.

[0067] Figure 7 This is a top view showing an example of the wiring structure of the semiconductor device according to the first embodiment.

[0068] like Figure 7 As shown, the semiconductor device of the first embodiment includes multiple wirings 21, multiple wirings 22, and multiple wirings 23. Wirings 21 and wirings 23 are represented by dashed lines and dotted lines, respectively, to distinguish them from wirings 22, which are represented by solid lines. However, they are not broken lines in the form of dashed or dotted lines, but rather extend in the form of solid lines. Figure 7 The image also schematically shows a memory cell array 24 within the semiconductor device of the first embodiment. Figure 7 The diagram also shows blocks A to D of the protruding portions 2a to 2d, and blocks A to D within the storage cell array 24.

[0069] Each wiring 21 electrically connects the central portions 2e of multiple active regions 2 to each other, specifically, on contact plugs 6 formed on these central portions 2e. The wiring 21 of the first embodiment extends generally in a zigzag shape in the Y direction. The contact plug 6 is an example of a first plug, and the wiring 21 is an example of a first wiring.

[0070] Each wiring 22 electrically connects any one of the protrusions 2a to 2d of an active region 2 to the memory cell array 24. Specifically, each wiring 22 is formed on a contact plug 8 on the protrusion 2a, protrusion 2b, protrusion 2c, or protrusion 2d, extending linearly from the contact plug 8 to the memory cell array 24. The memory cell array 24 includes blocks A to D, each block A to D containing multiple cell transistors (memory cells) and multiple selection transistors. The contact plug 8 is an example of a second plug, and the wiring 22 is an example of a second wiring.

[0071] In the first embodiment, each wiring 22 electrically connects the contact plug 8 within a certain block to the same block within the memory cell array 24. For example, in the first embodiment, a wiring 22 electrically connects the contact plug 8 within block A to block A within the memory cell array 24. Thus, the peripheral transistor Tr within block A can control the operation of block A within the memory cell array 24. This is also true for blocks other than block A.

[0072] Each wiring 23 is formed on a plurality of contact plugs 9. These contact plugs 9 are formed on different gate electrodes 4. Thus, the different gate electrodes 4 are electrically connected to each other. The wiring 23 of the first embodiment has an annular shape extending in the X and Y directions. The contact plug 9 is an example of a third plug, and the wiring 23 is an example of a third wiring.

[0073] In the first embodiment, each wiring 23 is formed on the protruding portions 2a to 2d that form a block, and the contact plugs 9 on these protruding portions 2a to 2d are electrically connected to each other. For example, in the first embodiment, a certain wiring 23 electrically connects the four contact plugs 9 of block A to each other. As a result, the peripheral transistor Tr can be operated on a block-by-block basis. This is also the case for blocks other than block A.

[0074] Figure 8 This is a top view showing an example of the wiring structure of the semiconductor device according to the second embodiment.

[0075] Similar to the semiconductor device of the first embodiment, the semiconductor device of this embodiment includes multiple wirings 21, multiple wirings 22, multiple wirings 23, multiple contact plugs 9, and a memory cell array 24. Figure 8 The diagram also shows blocks A to D of the protruding portions 2a to 2d, and blocks A to D within the storage cell array 24.

[0076] Wiring 21 in the first embodiment ( Figure 7 The wiring 21 in this embodiment generally extends in a zigzag pattern in the Y direction. Figure 8The wiring 21 extends in a straight line in the Y direction. In this embodiment, since the central portions 2e of the active region 2 are arranged relative to each other in the Y direction, the wiring 21 can extend in the Y direction. Thus, for example, it is easy to arrange other components besides the wiring 21 and the contact plug 6 above the substrate 1, avoiding the wiring 21 and the contact plug 6.

[0077] Figure 9 This is a top view showing an example of the shape of the diffusion regions 5 and 7 of the semiconductor device in the second embodiment.

[0078] like Figure 9 (a)~ Figure 9 As shown in (d), the semiconductor device of this embodiment ( Figure 8 The device comprises diffusion regions 5 and 7 with a planar shape of either a square or a circle, and contact plugs 6 and 8 formed on these diffusion regions 5 and 7. The square can be a strictly square, or a square with rounded corners, etc., which differs from a strictly square. The same applies to the circle. For example, consider the case where, due to optical effects during the transfer of the pattern shape of the photomask to the resist film, the square of the photomask becomes a circle when transferred to the resist film. This change from square to circle also occurs, for example, when impurity atoms injected into the active region 2 to form the diffusion regions 5 and 7 diffuse.

[0079] When the planar shape of the diffusion regions 5 and 7 in this embodiment is rectangular or elliptical, if the diffusion regions 5 and 7 are tilted without corresponding to the slope of the active region 2, the diffusion regions 5 and 7 and the contact plugs 6 and 8 will hinder the arrangement of other components. However, when the diffusion regions 5 and 7 are also tilted according to the slope of the active region 2, the process of forming the diffusion regions 5 and 7 becomes complicated.

[0080] Therefore, in this embodiment, the planar shapes of the diffusion regions 5 and 7 are set to square or circular. When the planar shape of the diffusion regions 5 and 7 is square, even if the diffusion regions 5 and 7 are not tilted according to the slope of the active region 2, the diffusion regions 5 and 7 and the contact plugs 6 and 8 are unlikely to hinder the arrangement of other components. Furthermore, when the planar shape of the diffusion regions 5 and 7 is circular, the planar shape of the diffusion regions 5 and 7 is rotationally symmetric, so there is no need to tilt the diffusion regions 5 and 7 according to the slope of the active region 2. Thus, even if the diffusion regions 5 and 7 are not tilted according to the slope of the active region 2, the process of forming the diffusion regions 5 and 7 can be avoided from becoming cumbersome.

[0081] exist Figure 8In this embodiment, the diffusion regions 5 and 7 are circular in shape. Furthermore, the contact plugs 6 and 8 are positioned on the diffusion regions 5 and 7 without tilting them relative to the slope of the active region 2. According to this embodiment, by setting the planar shape of the diffusion regions 5 and 7 to a square or circular shape, the diffusion regions 5 and 7, and the contact plugs 6 and 8 can be easily formed while suppressing any obstruction to the arrangement of other components.

[0082] In addition, Figure 7 The shape of the diffusion regions 5 and 7 is set to be circular, but the shape of the diffusion regions 5 and 7 in the first embodiment can also be a shape other than square and circle, such as rectangle or ellipse.

[0083] As described above, in this embodiment, the active region 2 is arranged obliquely relative to the four sides of the upper surface of the substrate 1. Therefore, according to this embodiment, the central portions 2e of different active regions 2 can be arranged relative to each other in the X or Y direction, thereby allowing for the appropriate configuration of wiring 21 that connects the contact plugs 6 on these central portions 2e to each other.

[0084] The above description describes several embodiments, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. The novel device described herein can also be implemented in various other forms. Furthermore, various omissions, substitutions, and modifications can be made to the form of the device described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to encompass such forms and variations as contained in the scope and spirit of the invention.

[0085] [Explanation of Symbols]

[0086] 1: Substrate

[0087] 2: Active area

[0088] 2a, 2b, 2c, 2d: Prominent parts

[0089] 2e: Central Section

[0090] 3: Component separation area

[0091] 4, 4a, 4b, 4c, 4d: Gate electrodes

[0092] 5: Diffusion Area

[0093] 6: Contact plug

[0094] 7: Diffusion Area

[0095] 8: Contact plug

[0096] 9: Contact plug

[0097] 11: Source / Drain Region

[0098] 12: Gate insulating film

[0099] 13: Cover with insulating film

[0100] 14: Sidewall insulating film

[0101] 15: Interlayer insulating film

[0102] 21, 22, 23: Wiring

[0103] 24: Storage cell array.

Claims

1. A semiconductor device comprising: Substrate; A first active region is disposed within the substrate and has a first central portion and a first protruding portion, the first protruding portion protruding from the first central portion in a first orientation in a first direction; A second active region is disposed within the substrate and has a second central portion and a second protruding portion, the second protruding portion protruding from the second central portion toward a second orientation in the first direction; A third active region is disposed within the substrate and has a third central portion and a third protruding portion, the third protruding portion protruding from the third central portion toward a third orientation toward a second direction intersecting the first direction; and A fourth active region is disposed within the substrate and has a fourth central portion and a fourth protruding portion, the fourth protruding portion protruding from the fourth central portion toward a fourth orientation in the second direction; and The end of the first protruding portion in the protruding direction faces the side portion of the fourth protruding portion in the direction intersecting the protruding direction. The end of the second protruding portion in the protruding direction faces the side portion of the third protruding portion in the direction intersecting the protruding direction. The end of the third protruding portion in the protruding direction faces the side portion of the first protruding portion in the direction intersecting the protruding direction. The end of the fourth protruding portion in the protruding direction faces the side portion of the second protruding portion in the direction intersecting the protruding direction.

2. The semiconductor device according to claim 1, wherein The end of the first protruding portion in the protruding direction faces only the side portion of the fourth protruding portion in the direction intersecting the protruding direction. The end of the second protruding portion in the protruding direction faces only the side portion of the third protruding portion in the direction intersecting the protruding direction. The end of the third protruding portion in the protruding direction faces only the side portion of the first protruding portion in the direction intersecting the protruding direction. The end of the fourth protruding portion in the protruding direction faces only the side portion of the second protruding portion in the direction intersecting the protruding direction.

3. The semiconductor device according to claim 1 or 2, wherein The first distance between the first protruding portion and the fourth protruding portion, The second distance between the second protruding portion and the third protruding portion, The third distance between the third protruding portion and the first protruding portion, The fourth protrusion is at the same fourth distance from the second protrusion.

4. The semiconductor device according to claim 1 or 2, wherein The first distance between the first protruding portion and the fourth protruding portion, The second distance between the second protruding portion and the third protruding portion, The third distance between the third protruding portion and the first protruding portion, The fourth distance between the fourth protrusion and the second protrusion is shorter than the width of the first, second, third, and fourth protrusions.

5. The semiconductor device according to claim 1 or 2, wherein the planar shape of each of the first, second, third, and fourth active regions is a cross shape in which the first, second, third, and fourth protrusions are respectively provided around the central portions of the first, second, third, and fourth regions.

6. The semiconductor device according to claim 1 or 2, wherein the upper surface of the substrate has a first side and a second side. The first direction is parallel to the first side. The second direction is parallel to the second side.

7. The semiconductor device according to claim 1 or 2, wherein the upper surface of the substrate has a first side and a second side. The first direction is inclined relative to the first side. The second direction is inclined relative to the second side.

8. The semiconductor device according to claim 1 or 2, further comprising: The first diffusion region is respectively located within the central portions of the first, second, third, and fourth portions; and The first plug is disposed on the first diffusion region; The first diffusion region has a planar shape that is either square or circular.

9. The semiconductor device according to claim 1 or 2, further comprising: The second diffusion region is respectively disposed within the first, second, third, or fourth protruding portion; and The second plug is disposed on the second diffusion region; The planar shape of the second diffusion region is either square or circular.

10. The semiconductor device according to claim 1 or 2, further comprising first, second, third and fourth transistors, the plurality of transistors comprising a gate insulating film and a gate electrode respectively disposed on the first, second, third and fourth protrusions.

11. The semiconductor device of claim 10, wherein the first, second, third, and fourth transistors are control transistors for controlling a memory cell array.

12. The semiconductor device according to claim 10, further comprising: The first plug is respectively disposed on the central portions of the first, second, third and fourth portions; The second plug is respectively disposed on the first, second, third, or fourth protruding portion; The third plug is disposed on the gate electrode; The first wiring is installed on the first plug; The second wiring connects the second plug to the memory cell array. and The third wiring is installed on the third plug.

13. The semiconductor device of claim 12, wherein the first wiring has a straight shape.

14. The semiconductor device of claim 12, wherein the third wiring has a ring-shaped form.

15. The semiconductor device of claim 12, wherein the upper surface of the substrate has a first side and a second side, the first direction being inclined relative to the first side. The second direction is inclined relative to the second side.

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