Semiconductor device and method of manufacturing the same

Abstract

An embodiment of the present application provides a semiconductor device capable of improving the performance of a channel semiconductor layer and a manufacturing method thereof. According to an embodiment, the semiconductor device includes a substrate and a plurality of electrode layers disposed apart from each other in a first direction perpendicular to a surface of the substrate. Further, the device includes a first insulating film, a charge accumulation layer, a second insulating film, a first semiconductor region containing silicon, and a second semiconductor region containing silicon and carbon, which are sequentially disposed on side surfaces of the electrode layers, and an interface between the first semiconductor region and the second insulating film contains fluorine.

Description

[0001] [Related Application]

[0002] This application claims priority to Japanese Patent Application No. 2020-152316 (Filing date: September 10, 2020). This application incorporates by reference the entire contents of the base application. TECHNICAL FIELD

[0003] Embodiments of the present application relate to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0004] In a semiconductor memory such as a three-dimensional memory, it is desired to improve the performance of a channel semiconductor layer. SUMMARY

[0005] Embodiments provide a semiconductor device and a manufacturing method thereof capable of improving the performance of a channel semiconductor layer.

[0006] According to an embodiment, a semiconductor device has a substrate and a plurality of electrode layers disposed apart from each other in a first direction perpendicular to a surface of the substrate. Further, the device has a first insulating film, a charge accumulation layer, a second insulating film, a first semiconductor region containing silicon, and a second semiconductor region containing silicon and carbon, which are disposed in this order on side surfaces of the electrode layers; and an interface between the first semiconductor region and the second insulating film contains fluorine. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a cross-sectional view showing a structure of a semiconductor device of the first embodiment.

[0008] Figures 2-9 is a cross-sectional view showing a manufacturing method of a semiconductor device of the first embodiment.

[0009] Figure 10 is a cross-sectional view showing a structure of a semiconductor device of the second embodiment.

[0010] Figure 11 is an enlarged cross-sectional view showing a structure of a semiconductor device of the second embodiment.

[0011] Figure 12 is another enlarged cross-sectional view showing a structure of a semiconductor device of the second embodiment.

[0012] Figures 13-26 is a cross-sectional view showing a manufacturing method of a semiconductor device of the second embodiment.

[0013] Figure 27 is a cross-sectional view showing a structure of a semiconductor device of the third embodiment.

[0014] Figure 28 is another cross-sectional view showing the structure of the semiconductor device of the third embodiment.

[0015] Figure 29 , 30 is a cross-sectional view showing a manufacturing method of the semiconductor device of the fourth embodiment.

[0016] Figure 31 (a), (b) are cross-sectional views for comparing the manufacturing method of the semiconductor device of the first embodiment with the manufacturing method of the semiconductor device of the fourth embodiment.

[0017] Figure 32 is a table for describing the fluorine additive of the fourth embodiment.

[0018] Figure 33 (a) to (c) are structural formulas for describing partial structures of the fluorine additive of the fourth embodiment.

[0019] Figures 34-36 is a cross-sectional view showing a manufacturing method of the semiconductor device of the fifth embodiment. DETAILED DESCRIPTION

[0020] Embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, like elements are denoted by like reference symbols, and repeated description will be omitted. Figures 1-36

[0021] (First Embodiment)

[0022] Figure 1 is a cross-sectional view showing the structure of the semiconductor device of the first embodiment. Figure 1 The semiconductor device of the first embodiment is, for example, a three-dimensional memory.

[0023] Figure 1 The semiconductor device of the first embodiment has a substrate 1, a laminate film 2, a memory insulating film 11, a channel semiconductor layer 12, and a core insulating film 13. The laminate film 2 includes a plurality of electrode layers 2a and a plurality of insulating layers 2b. The memory insulating film 11 includes a barrier insulating film 11a, a charge accumulation layer 11b, and a tunnel insulating film 11c. The barrier insulating film 11a is an example of the first insulating film, and the tunnel insulating film 11c is an example of the second insulating film. The channel semiconductor layer 12 includes a semiconductor region 12a and a semiconductor region 12b. The semiconductor region 12a is an example of the first semiconductor region, and the semiconductor region 12b is an example of the second semiconductor region.

[0024] The substrate 1 is, for example, a semiconductor substrate such as a Si (silicon) substrate. Figure 1 ​The X direction and the Y direction which are parallel to the surface of the substrate 1 and perpendicular to each other, and the Z direction which is perpendicular to the surface of the substrate 1 are shown. In this specification, the +Z direction is regarded as the upward direction, and the -Z direction is regarded as the downward direction. The -Z direction can coincide with the direction of gravity, or can not coincide with the direction of gravity. The Z direction is an example of the first direction.

[0025] The laminated film 2 includes a plurality of electrode layers 2a and a plurality of insulating layers 2b which are alternately laminated above the substrate 1. These electrode layers 2a are alternately laminated with these insulating layers 2b, whereby they are separated from each other in the Z direction. These electrode layers 2a are used, for example, as word lines or selection lines for a three-dimensional memory. Each electrode layer 2a includes, for example, a metal layer such as a W (tungsten) layer. Each insulating layer 2b is, for example, a SiO2 film (silicon oxide film).

[0026] Figure 1 The semiconductor device of the present embodiment further includes a plurality of columnar portions CL which are formed in the laminated film 2 above the substrate 1, and have a columnar shape extending in the Z direction. Figure 1 One of these columnar portions CL is shown. The shape of each columnar portion CL is, for example, a cylindrical shape. Each columnar portion CL includes a memory insulating film 11, a channel semiconductor layer 12, and a core insulating film 13 which are sequentially formed in the laminated film 2, and constitutes a plurality of unit transistors (memory cells) and a plurality of selection transistors.

[0027] A barrier insulating film 11a is formed on the side surface of the laminated film 2, that is, the side surface of the electrode layer 2a and the insulating layer 2b. The barrier insulating film 11a is, for example, a SiO2 film.

[0028] A charge accumulation layer 11b is formed on the side surface of the barrier insulating film 11a. The charge accumulation layer 11b is, for example, an insulating film such as a SiN film (silicon nitride film), but can also be a semiconductor layer such as a polysilicon layer. The charge accumulation layer 11b can accumulate signal charges for a three-dimensional memory for each memory cell. Figure 1 The interface S1 of the barrier insulating film 11a and the charge accumulation layer 11b is shown.

[0029] A tunnel insulating film 11c is formed on the side surface of the charge accumulation layer 11b. The tunnel insulating film 11c is, for example, a SiON film (silicon oxynitride film). Figure 1 The interface S2 of the charge accumulation layer 11b and the tunnel insulating film 11c is shown.

[0030] A semiconductor region 12a is formed on the side surface of the tunnel insulating film 11c. The thickness of the semiconductor region 12a is, for example, 10 nm or less, and in this case, 3 nm or less. The semiconductor region 12a is, for example, a polysilicon layer. Figure 1 The interface S3 of the tunnel insulating film 11c and the semiconductor region 12a is shown.

[0031] The semiconductor region 12b is formed on a side surface of the semiconductor region 12a. The thickness of the semiconductor region 12b of the present embodiment is set to be thinner than the thickness of the semiconductor region 12a. The thickness of the semiconductor region 12b is, for example, 1 nm or less, and here, about 0.1 nm. The semiconductor region 12b is, for example, a SiC (silicon carbide) layer, and Si (silicon) atoms and C (carbon) atoms in the semiconductor region 12b form Si-C bonds. The concentration of C atoms in the semiconductor region 12b is, for example, 1.0 x 1020atoms / cm2or more and 1.0 x 1021atoms / cm2or less. The concentration of C atoms can be found using, for example, EDX (Energy-dispersive X-ray spectroscopy) or EELS (Electron energy loss spectroscopy). 22 cm -3 or less. The concentration of C atoms can be found using, for example, EDX (Energy-dispersive X-ray spectroscopy) or EELS (Electron energy loss spectroscopy). The semiconductor region 12b can also be a SiC region whose thickness is so thin that it cannot be called a SiC layer.

[0032] The core insulating film 13 is formed on a side surface of the semiconductor region 12b, at the center of each columnar portion CL. The core insulating film 13 is, for example, a SiO2 film.

[0033] Next, the semiconductor device of the present embodiment will be described in more detail. Figure 1

[0034] The columnar portion CL of the present embodiment contains F (fluorine) atoms. For example, the columnar portion CL can contain F atoms in the semiconductor region 12a and the tunnel insulating film 11c, and further contain F atoms in the charge accumulation layer 11b and the barrier insulating film 11a. In addition, F atoms can be contained in the interface S3 between the semiconductor region 12a and the tunnel insulating film 11c, and further contained in the interface S2 between the tunnel insulating film 11c and the charge accumulation layer 11b, or the interface S1 between the charge accumulation layer 11b and the barrier insulating film 11a. In addition, F atoms can be contained in the semiconductor region 12b, or in the interface between the semiconductor region 12b and the semiconductor region 12a, or in the core insulating film 13, or in the interface between the core insulating film 13 and the semiconductor region 12b.

[0035] ​According to this embodiment, by including F atoms in the semiconductor region 12a, the tunnel insulating film 11c, and the interface S3, the F atoms can be used to terminate defects and dangling bonds in the semiconductor region 12a, the tunnel insulating film 11c, and the interface S3. This improves the reliability of the semiconductor region 12a and the tunnel insulating film 11c. The F atoms, for example, form Si-F bonds with Si atoms in the semiconductor region 12a, the tunnel insulating film 11c, and the interface S3. Generally, the defects and dangling bonds targeted for termination are mostly located in the interface S3, therefore it is desirable for the interface S3 to contain a large number of F atoms. In this embodiment, the concentration of F atoms in the semiconductor region 12a, the tunnel insulating film 11c, and the interface S3 is, for example, 1.0 × 10⁻⁶. 22 cm -3 The concentration of F atoms can be determined, for example, using EDX or EELS.

[0036] This effect can also be achieved in other portions within each columnar section CL. For example, by including F atoms in interface S2 or interface S1, the F atoms can be used to terminate defects and dangling bonds in interface S2 or interface S1. In this embodiment, the concentration of F atoms in the charge accumulation layer 11b, the barrier insulating film 11a, interface S2, and interface S1 is, for example, 1.0 × 10⁻⁶. 22 cm -3 The F atoms, for example, form Si-F bonds with Si atoms in the charge accumulation layer 11b, the barrier insulating film 11a, interface S2, and interface S1. Furthermore, the F atoms in the semiconductor region 12b or its two interfaces form Si-F bonds or CF bonds with Si atoms or C atoms in the semiconductor region 12b or its two interfaces. In this embodiment, the concentration of F atoms in the semiconductor region 12b or its two interfaces is, for example, 1.0 × 10⁻⁶. 22 cm -3 the following.

[0037] In this embodiment, when forming the semiconductor region 12b on the side surface of the semiconductor region 12a, F atoms are introduced into each columnar portion CL. The following will refer to... Figures 2-9 Describe the process in detail.

[0038] Figures 2-9 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0039] First, a multilayer film 2' consisting of alternating sacrificial layers 2a' and insulating layers 2b is formed on top of substrate 1. Figure 2 As a result, these sacrificial layers 2a' are formed spaced apart from each other in the Z direction. Each sacrificial layer 2a' is, for example, a silicon nitride film with a thickness of about 50 nm. Each insulating layer 2b is, for example, a silicon oxide film as described above, with a thickness of about 50 nm. These sacrificial layers 2a' are examples of the first film.

[0040] Each of the sacrifice layers 2a' is formed by CVD (Chemical Vapor Deposition) using SiH2Cl2and NH3at 300 to 850°C and in a reduced pressure environment (2000 Pa or less) (H represents hydrogen, Cl represents chlorine, and N represents nitrogen), for example. Each of the insulating layers 2b is formed by CVD using TEOS (Tetraethyl orthosilicate) at 300 to 700°C and in a reduced pressure environment (2000 Pa or less), for example. The laminate film 2 of the present embodiment is formed over the substrate 1 with another film (such as an interlayer insulating film) interposed therebetween.

[0041] Next, a plurality of memory holes MH (see FIG. 2) are formed in the laminate film 2' by photolithography and RIE (Reactive Ion Etching), for example. Figure 3 ). Figure 3 One of these memory holes MH is shown. These memory holes MH are formed in a manner that penetrates the laminate film 2' using a resist film and a hard mask layer (such as a polysilicon layer) as a mask, for example.

[0042] Next, a barrier insulating film 11a, a charge accumulation layer 11b, a tunnel insulating film 11c, and a semiconductor region 12a are formed in this order in each of the memory holes MH (see FIG. 3). Figure 4 ). As a result, a barrier insulating film 11a, a charge accumulation layer 11b, a tunnel insulating film 11c, and a semiconductor region 12a are formed in this order on the side surface of the laminate film 2' in each of the memory holes MH. Thus, a memory insulating film 11 is formed in the memory hole MH. The semiconductor region 12a is a polysilicon layer, for example, as described above.

[0043] The barrier insulating film 11a is formed by ALD (atomic layer deposition) using TDMAS (Tris(dimethylamino)silane) and O3at 400 to 800°C and in a reduced pressure environment (2000 Pa or less) (O represents oxygen), for example. The charge accumulation layer 11b is formed by ALD using SiH2Cl2and NH3at 300 to 800°C and in a reduced pressure environment (2000 Pa or less), for example. The tunnel insulating film 11c is formed by ALD using HCD (hexachlorodisilane), NH3, and O2at 400 to 800°C and in a reduced pressure environment (2000 Pa or less), for example. The semiconductor region 12a is formed by CVD using SiH4at 400 to 800°C and in a reduced pressure environment (2000 Pa or less), for example.

[0044] Next, a polymer layer 21 is formed in each memory hole MH. Figure 5 As a result, the polymer layer 21 is formed on the side surface of the semiconductor region 12a in each memory hole MH. The polymer layer 21 is, for example, a CF polymer layer containing carbon (C) and fluorine (F), and has a thickness of about 5 nm. The polymer layer 21 is an example of the second film.

[0045] The polymer layer 21 is formed, for example, using C4F8 gas. The polymer layer 21 can be formed using a liquid instead of gas. x H y F z The gas contains carbon (C) and fluorine (F), and can contain hydrogen (H) or can not contain hydrogen (H). The polymer layer 21 of the present embodiment is formed using C4F8 gas. The polymer layer 21 can be formed using a liquid instead of gas. x H y F z The gas contains carbon (C) and fluorine (F), and can contain hydrogen (H) or can not contain hydrogen (H). The polymer layer 21 of the present embodiment is formed using C4F8 gas. The polymer layer 21 can be formed using a liquid instead of gas.

[0046] Next, the polymer layer 21, the semiconductor region 12a, the tunnel insulating film 11c, the charge accumulation layer 11b, the barrier insulating film 11a, and the like on the upper side of the substrate 1 are heated by thermal annealing (see FIG. 2B). As a result, a semiconductor region 12b is formed between the polymer layer 21 and the semiconductor region 12a. Thus, a channel semiconductor layer 12 is formed in the memory hole MH. The present embodiment forms a SiC layer as the semiconductor region 12b by Si atoms in the semiconductor region 12a and C atoms in the polymer layer 21. Further, the thermal annealing causes F atoms in the polymer layer 21 to diffuse into the semiconductor region 12b, the semiconductor region 12a, the tunnel insulating film 11c, the charge accumulation layer 11b, and the barrier insulating film 11a, and into the interfaces therebetween (for example, the interfaces S1, S2, S3 shown in FIG. 2B). Figure 6 ). As a result, a semiconductor region 12b is formed between the polymer layer 21 and the semiconductor region 12a. Thus, a channel semiconductor layer 12 is formed in the memory hole MH. The present embodiment forms a SiC layer as the semiconductor region 12b by Si atoms in the semiconductor region 12a and C atoms in the polymer layer 21. Further, the thermal annealing causes F atoms in the polymer layer 21 to diffuse into the semiconductor region 12b, the semiconductor region 12a, the tunnel insulating film 11c, the charge accumulation layer 11b, and the barrier insulating film 11a, and into the interfaces therebetween (for example, the interfaces S1, S2, S3 shown in FIG. 2B). Figure 1 The F atoms diffused in this manner are schematically shown. Figure 6 The F atoms diffused in this manner are schematically shown.

[0047] Figure 6 The thermal annealing of the process shown in FIG. 2B is performed, for example, at 900°C and under normal pressure for 30 minutes. The semiconductor region 12b can be formed in the semiconductor region 12a or in the polymer layer 21. Further, the semiconductor region 12b can be formed as a SiC region having a thickness so thin that it cannot be called a SiC layer instead of being formed as a SiC layer.

[0048] Next, the polymer layer 21 is removed (see FIG. 2C). As a result, the side surface of the semiconductor region 12b is exposed in each memory hole MH. The polymer layer 21 is removed, for example, by oxidation using O2 at 500°C and under normal pressure for 30 minutes. Figure 7 ). As a result, the side surface of the semiconductor region 12b is exposed in each memory hole MH. The polymer layer 21 is removed, for example, by oxidation using O2 at 500°C and under normal pressure for 30 minutes.

[0049] Next, a core insulating film 13 is formed within each memory hole MH. Figure 8 As a result, a core insulating film 13 is formed on the side of the semiconductor region 12b within each memory hole MH. Consequently, a columnar portion CL is formed within each memory hole MH.

[0050] The core insulating film 13 is formed, for example, by using TDMAS and O3 under a reduced pressure environment (below 2000 Pa) at 400–800°C. In this embodiment, the core insulating film 13 is formed in a manner that completely fills each memory via MH.

[0051] Next, each sacrificial layer 2a' within the stacked film 2' is replaced with one electrode layer 2a. Figure 9 As a result, a multilayer film 2, which alternately includes multiple electrode layers 2a and multiple insulating layers 2b, is formed above the substrate 1. Furthermore, a structure is achieved above the substrate 1 where each pillar CL penetrates within the multilayer film 2. In this way, multiple unit transistors (memory cells) and multiple selection transistors are formed in each pillar CL.

[0052] For example, it can be implemented in the following ways. Figure 9 The process is shown below. First, slits are formed within the multilayer film 2'. Through these slits, sacrificial layers 2a' within the multilayer film 2' are selectively removed using hot phosphoric acid. As a result, multiple recesses are formed between the insulating layers 2b within the multilayer film 2'. Next, a barrier insulating film, a barrier metal layer, and an electrode material layer are sequentially formed within these recesses. As a result, an electrode layer 2a containing both the barrier metal layer and the electrode material layer is formed within each recess. Furthermore, through... Figure 9 The barrier insulating film formed by the process shown and the passage Figure 4 The barrier insulating film 11a formed by the process shown constitutes the barrier insulating film of each memory cell.

[0053] exist Figure 9 In the process shown, the barrier insulating film is, for example, AlO₂. x The film (alumina film) is formed by ALD at 200–500°C under reduced pressure (below 2000 Pa) using TMA (trimethylaluminum) and O3. Furthermore, the barrier metal layer, such as a TiN film (titanium nitride film), is formed by CVD under reduced pressure using TiCl and NH3. Additionally, the electrode material layer, such as a W (tungsten) layer, is formed by CVD under reduced pressure using WF6.

[0054] In addition, Figure 2 In the process shown, a multilayer film 2 that alternately comprises multiple electrode layers 2a and multiple insulating layers 2b can be formed instead of forming a multilayer film 2' that alternately comprises multiple sacrificial layers 2a' and multiple insulating layers 2b. In this case, Figure 9In the process, the sacrificial layer 2a' is not replaced with the electrode layer 2a. The electrode layer 2a in this case is an example of the first film.

[0055] After that, various wiring layers, plug layers, interlayer insulating films, and the like are formed over the substrate 1. In this way, the semiconductor device of Figure 1 the present embodiment is manufactured.

[0056] Next, the manufacturing method of the semiconductor device of the present embodiment will be described in more detail.

[0057] The core insulating film 13 of the present embodiment is not formed directly on the side surface of the semiconductor region 12a (Si layer), but is formed on the side surface of the semiconductor region 12a through the semiconductor region 12b (SiC layer). In the case where the core insulating film 13 is formed directly on the side surface of the semiconductor region 12a, the semiconductor region 12a can be oxidized by O atoms used for forming the core insulating film 13. In this case, when the thickness of the semiconductor region 12a is thinned due to high integration of the semiconductor device, the oxidized portion of the semiconductor region 12a can penetrate the semiconductor region 12a, causing degradation of the performance of the channel semiconductor layer 12. On the other hand, in the case where the core insulating film 13 is formed on the side surface of the semiconductor region 12a through the semiconductor region 12b, the semiconductor region 12b is less likely to be oxidized than the semiconductor region 12a. Thus, according to the present embodiment, it is possible to suppress the problem caused by oxidation of the semiconductor region 12a.

[0058] Figure 9 The semiconductor region 12b remaining between the semiconductor region 12a and the core insulating film 13 is shown. In the case where the semiconductor region 12b is a SiC layer (or a SiC region), it is possible to increase a heat process at the time of forming the core insulating film 13. Thus, it is possible to diffuse F atoms further. The semiconductor device product of the present embodiment contains F atoms in the semiconductor region 12a, the tunnel insulating film 11c, the charge accumulation layer 11b, and the barrier insulating film 11a, and at the interfaces S1, S2, S3 therebetween, for example. There is a case where F atoms are further segregated at the interfaces S1, S2, S3 therebetween.

[0059] The F atoms in each columnar portion CL can terminate defects and dangling bonds, for example, and improve the electrical characteristics of each columnar portion CL. For example, the F atoms in the channel semiconductor layer 12 can improve the mobility of carriers, increase the storage cell current, and suppress the diffusion of p-type impurity atoms or n-type impurity atoms in the channel semiconductor layer 12 to the outside. Further, the F atoms in the tunnel insulating film 11c can suppress stress degradation of the tunnel insulating film 11c. Further, the F atoms in the charge accumulation layer 11b can increase the charge accumulation amount of the charge accumulation layer 11b. Further, the F atoms in the barrier insulating film 11a can repair defects and the like in the barrier insulating film 11a.

[0060] Furthermore, the F atoms near the interface between the core insulating film 13 and the channel semiconductor layer 12 can reduce carrier scattering at that interface and improve carrier mobility. In addition, the F atoms at the interface S3 between the channel semiconductor layer 12 and the tunnel insulating film 11c, the F atoms at the interface S2 between the tunnel insulating film 11c and the charge accumulation layer 11b, and the F atoms at the interface S1 between the charge accumulation layer 11b and the barrier insulating film 11a can repair defects in these interfaces S3, S2, and S1. The same applies to the F atoms at the interfaces between the barrier insulating film 11a and each electrode layer 2a.

[0061] Alternatively, the sacrificial layer 2a' can be a film other than SiN, as long as it can improve the etch selectivity with the insulating layer 2b. An example of such a sacrificial layer 2a' is a polysilicon layer. Furthermore, the barrier insulating film 11a can also be a film other than SiO2, for example, a multilayer film containing both SiO2 and SiN films, or a high-k film. Furthermore, the tunnel insulating film 11c can also be a film other than SiON, for example, a SiO2 film or a high-k film. Additionally, each electrode layer 2a can contain a barrier metal layer other than TiN (e.g., a TaN film (tantalum nitride film)) or an electrode material layer other than the W layer (e.g., a polysilicon layer, a silicide layer).

[0062] Furthermore, at least any one of the barrier insulating film 11a, charge accumulation layer 11b, tunnel insulating film 11c, semiconductor region 12a, and polymer layer 21 can be formed using gases other than those described above. For example, semiconductor region 12a can also be formed using SiH4 gas and Si2H6 gas alternately. Additionally, polymer layer 21 can also be formed using C3F6 gas.

[0063] As described above, the channel semiconductor layer 12 of this embodiment is formed to include a semiconductor region 12a containing silicon (Si) and a semiconductor region 12b containing both silicon (Si) and carbon (C). Therefore, according to this embodiment, the performance of the channel semiconductor layer 12 can be improved as described above. Furthermore, the performance of other portions within each columnar portion CL can also be improved as described above.

[0064] (Second Implementation)

[0065] Figure 10 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment. Figure 10 Semiconductor devices, for example, are three-dimensional memories.

[0066] and Figure 1 Similarly, semiconductor devices, Figure 10 The semiconductor device includes a substrate 1 and a multilayer film 2. Furthermore, Figure 10The semiconductor device of the present embodiment includes an interlayer insulating film 3, a source layer 4, an interlayer insulating film 5, a gate layer 6, and an interlayer insulating film 7. The laminate film 2 includes a plurality of electrode layers 2a and a plurality of insulating layers 2b. The source layer 4 includes a metal layer 4a, a lower semiconductor layer 4b, an intermediate semiconductor layer 4c, and an upper semiconductor layer 4d.

[0067] Figure 10 The semiconductor device of the present embodiment further includes a plurality of columnar portions CL. The columnar portions CL are formed in the same manner as the columnar portion CL of the semiconductor device of the first embodiment. Figure 1 Figure 10 Each of the columnar portions CL includes a memory insulating film 11, a channel semiconductor layer 12, and a core insulating film 13. In addition, the semiconductor device of the present embodiment includes a plurality of element separation insulating films 14. Figure 10

[0068] The substrate 1 is a semiconductor substrate such as a Si substrate, as described above. The interlayer insulating film 3, the source layer 4, the interlayer insulating film 5, and the gate layer 6 are formed in this order on the substrate 1. The interlayer insulating film 3 is, for example, a SiO2 film. The source layer 4 includes a metal layer 4a (for example, a W layer), a lower semiconductor layer 4b (for example, a polysilicon layer), an intermediate semiconductor layer 4c (for example, a polysilicon layer), and an upper semiconductor layer 4d (for example, a polysilicon layer), which are formed in this order on the interlayer insulating film 3. The interlayer insulating film 5 is, for example, a SiO2 film. The gate layer 6 is, for example, a polysilicon layer.

[0069] The laminate film 2 includes a plurality of electrode layers 2a and a plurality of insulating layers 2b, which are alternately laminated on the gate layer 6. Each of the electrode layers 2a includes a metal layer such as a W layer, as described above. Each of the insulating layers 2b is, for example, a SiO2 film, as described above. The interlayer insulating film 7 is formed on the laminate film 2. The interlayer insulating film 7 is, for example, a SiO2 film.

[0070] Each of the columnar portions CL includes the lower semiconductor layer 4b, the intermediate semiconductor layer 4c, the upper semiconductor layer 4d, the interlayer insulating film 5, the gate layer 6, the laminate film 2, and the interlayer insulating film 7, in which the memory insulating film 11, the channel semiconductor layer 12, and the core insulating film 13 are formed in this order, and has a columnar shape extending in the Z direction. The channel semiconductor layer 12 of the present embodiment is in contact with the intermediate semiconductor layer 4c, as shown in FIG. 2, and is electrically connected to the source layer 4. Figure 10

[0071] Each of the element separation insulating films 14 is formed in the upper semiconductor layer 4d, the interlayer insulating film 5, the gate layer 6, the laminate film 2, and the interlayer insulating film 7 in this order, and has a plate shape extending in the Z direction and the Y direction. Each of the element separation insulating films 14 is, for example, a SiO2 film.

[0072] Figure 11 FIG. 2 is an enlarged sectional view showing a structure of the semiconductor device of the second embodiment, and shows a region A of FIG. 1. Figure 10 FIG. 3 is an enlarged sectional view showing a structure of the semiconductor device of the second embodiment, and shows a region B of FIG. 1.​​​

[0073] Each columnar portion CL of the present embodiment includes, as shown in FIG. 1, a barrier insulating film 11a, a charge accumulation layer 11b, and a tunnel insulating film 11c of a memory insulating film 11, a semiconductor region 12a and a semiconductor region 12b of a channel semiconductor layer 12, and a core insulating film 13 in this order. The barrier insulating film 11a is, for example, a SiO2 film. The charge accumulation layer 11b is, for example, a SiN film. The tunnel insulating film 11c is, for example, a SiON film. The semiconductor region 12a is, for example, a polysilicon layer. The semiconductor region 12b is, for example, a SiC layer. The core insulating film 13 is, for example, a SiO2 film. The laminated film 2 includes a plurality of electrode layers 2a and a plurality of insulating layers 2b as described above, and these electrode layers 2a constitute, together with each columnar portion CL, a plurality of memory cells MC and the like. Figure 11

[0074] Figure 12 is another enlarged sectional view showing the structure of the semiconductor device of the second embodiment, and shows a region B of Figure 10 .

[0075] Each columnar portion CL of the present embodiment includes, as shown in FIG. 1, a barrier insulating film 11a, a charge accumulation layer 11b, and a tunnel insulating film 11c of a memory insulating film 11, a semiconductor region 12a and a semiconductor region 12b of a channel semiconductor layer 12, and a core insulating film 13 in this order. The barrier insulating film 11a is, for example, a SiO2 film. The charge accumulation layer 11b is, for example, a SiN film. The tunnel insulating film 11c is, for example, a SiON film. The semiconductor region 12a is, for example, a polysilicon layer. The semiconductor region 12b is, for example, a SiC layer. The core insulating film 13 is, for example, a SiO2 film. The laminated film 2 includes a plurality of electrode layers 2a and a plurality of insulating layers 2b as described above, and these electrode layers 2a constitute, together with each columnar portion CL, a plurality of memory cells MC and the like. Figure 12

[0076] As with each columnar portion CL of the first embodiment, each columnar portion CL of the present embodiment includes F atoms. For example, the F atoms in the impurity diffusion region R can suppress diffusion of impurities in the semiconductor region 12a in the Z direction. Thus, reduction of GIDL current due to impurity diffusion can be suppressed. At the same time, threshold value unevenness of the selection transistor due to impurity diffusion can be suppressed, and occurrence of short-circuit failure of the selection transistor due to impurity diffusion can be reduced, so that improvement of yield of the semiconductor device can be expected. Each columnar portion CL of the present embodiment includes C atoms in addition to the F atoms. Thus, diffusion of impurities can be further suppressed. The impurities are, for example, P (phosphorus) atoms.

[0077] ​​In this embodiment, the impurity concentration in the impurity diffusion region R has a variation along the Z direction. For example, the impurity concentration is high at the level of the middle semiconductor layer 4c, and the higher the level from the level of the middle semiconductor layer 4c, the lower the impurity concentration. On the other hand, the concentrations of C atoms and F atoms in the impurity diffusion region R have substantially no variation along the Z direction. For example, the concentrations of C atoms and F atoms in the impurity diffusion region R are substantially the same at the level of the lower semiconductor layer 4b, the level of the middle semiconductor layer 4c, and the level of the upper semiconductor layer 4d. Thus, the oxidation inhibition of the semiconductor region 12a by the C atoms and F atoms, and the termination of defects and dangling bonds of the columnar portion CL will not depend on the Z direction of the columnar portion CL, but will exert an effect on the entire columnar portion CL. According to this embodiment, in addition to being able to inhibit the oxidation of the semiconductor region 12a, and to terminate defects and dangling bonds of the columnar portion CL, it is also possible to maintain the impurity concentration in the impurity diffusion region R at the level of the middle semiconductor layer 4c at a high concentration by using such C atoms and F atoms. The concentration of P atoms in the impurity diffusion region R at the level of the middle semiconductor layer 4c is, for example, 1.0 x 1019atoms / cm2or higher. The concentration of P atoms in the impurity diffusion region R can be calculated, for example, from the resistance value of the impurity diffusion region R. 21 cm -3 The concentration of P atoms in the impurity diffusion region R can be calculated, for example, from the resistance value of the impurity diffusion region R.

[0078] Figures 13-26 is a cross-sectional view showing a manufacturing method of a semiconductor device according to the second embodiment.

[0079] First, an interlayer insulating film 3, a metal layer 4a, a lower semiconductor layer 4b, a lower protective film 22, a sacrificial layer 23, an upper protective film 24, an upper semiconductor layer 4d, an interlayer insulating film 5, and a gate layer 6 are formed in this order on a substrate 1. Figure 13 The lower protective film 22 is, for example, a SiO2film. The sacrificial layer 23 is, for example, a polysilicon layer. The upper protective film 24 is, for example, a SiO2film.

[0080] Next, on the gate layer 6, a laminated film 2' including a plurality of sacrificial layers 2a' and a plurality of insulating layers 2b in this order is formed, and an interlayer insulating film 7 is formed on the laminated film 2' (see FIG. 2). Figure 14 Each of the sacrificial layers 2a' is, for example, a SiN film as described above. These sacrificial layers 2a' are replaced with a plurality of electrode layers 2a by a process described later. Alternatively, in the case where a step of omitting this process is adopted, the electrode layers 2a are formed instead of the sacrificial layers 2a' in the process of forming the interlayer insulating film 7. Figure 14

[0081] Next, a plurality of memory holes MH are formed in the interlayer insulating film 7, the laminated film 2', the gate layer 6, the interlayer insulating film 5, the upper semiconductor layer 4d, the upper protective film 24, the sacrificial layer 23, the lower protective film 22, and the lower semiconductor layer 4b by photolithography and RIE.​Figure 15 ).

[0082] Next, within these memory holes MH, a memory insulating film 11, a channel semiconductor layer 12, and a core insulating film 13 are sequentially formed. Figure 16 As a result, multiple columnar portions CL are formed within these memory holes MH. Furthermore, the memory insulating film 11 is formed by sequentially forming the barrier insulating film 11a, the charge accumulation layer 11b, and the tunnel insulating film 11c within each memory hole MH. Additionally, the channel semiconductor layer 12 is formed by performing… Figures 4-7 The process shown is formed in a manner that sequentially includes the semiconductor region 12a and the semiconductor region 12b.

[0083] Next, through photolithography and RIE, multiple device separation trenches (slits) ST are formed in the interlayer insulating film 7, the stacked film 2', and the gate layer 6. Figure 17 and Figure 18 The RIE in Figure 17 The process shown is performed using the first etching gas, in Figure 18 The process shown uses a second etching gas, which is different from the first etching gas.

[0084] Next, the upper protective film 24 is removed from the bottom surface of the component separation tank ST by etching. Figure 19 A liner layer 25 is formed on the surface of the component separation groove ST. Figure 20 ), and remove the pad layer 25 from the bottom surface of the component separation groove ST by etching. Figure 21 As a result, the side surface of the component separation tank ST is protected by the padding layer 25, while the sacrificial layer 23 is exposed on the bottom surface of the component separation tank ST. The padding layer 25 is, for example, a SiN film.

[0085] Next, the sacrificial layer 23 is removed by wet etching using a component separation tank (ST). Figure 22 As a result, a cavity (air gap) C2 is formed between the lower protective film 22 and the upper protective film 24, thereby exposing the memory insulating film 11 on the side of the cavity C2.

[0086] Next, CDE (Chemical Dry Etching) is performed using a component separation tank (ST) to remove the lower protective film 22, the upper protective film 24, and the memory insulating film 11 exposed on the side of the cavity C2. Figure 23 As a result, the upper semiconductor layer 4d is exposed on the upper surface of cavity C2, the lower semiconductor layer 4b is exposed on the lower surface of cavity C3, and the channel semiconductor layer 12 is exposed on the side of cavity C2.

[0087] Next, an intermediate semiconductor layer 4c is formed on the surfaces of the upper semiconductor layer 4d, the lower semiconductor layer 4b, and the channel semiconductor layer 12 exposed in the cavity C2, thereby forming the intermediate semiconductor layer 4c in the cavity C2. Figure 24 As a result, the intermediate semiconductor layer 4c is formed between the upper semiconductor layer 4d and the lower semiconductor layer 4b, which is in contact with the upper semiconductor layer 4d, the lower semiconductor layer 4b, and the channel semiconductor layer 12. In addition, impurities in the intermediate semiconductor layer 4c are thermally diffused by heat treatment at the time of forming the intermediate semiconductor layer 4c or heat treatment in a subsequent process. According to the present embodiment, since the columnar portions CL contain F atoms and C atoms, the diffusion of impurities in the intermediate semiconductor layer 4c can be suppressed.

[0088] Next, the liner layer 25 in the element separation trench ST and each of the sacrificial layers 2a' in the laminate film 2' are removed by wet etching or dry etching using the element separation trench ST. Figure 25 As a result, a plurality of cavities (air gaps) C1 are formed between the insulating layers 2b in the laminate film 2'.

[0089] Next, a plurality of electrode layers 2a are formed in these cavities C1 by CVD. Figure 26 As a result, the laminate film 2 in which the plurality of electrode layers 2a and the plurality of insulating layers 2b are alternately included is formed between the gate layer 5 and the interlayer insulating film 7.

[0090] After that, an element separation insulating film 14 is formed in the element separation trench ST. Further, various plug layers, wiring layers, interlayer insulating films, and the like are formed on the substrate 1. In this way, the semiconductor device of Figure 10 is manufactured.

[0091] As described above, like the channel semiconductor layer 12 of the first embodiment, the channel semiconductor layer 12 of the present embodiment is formed to include the semiconductor region 12a containing silicon (Si) and the semiconductor region 12b containing silicon (Si) and carbon (C). Thereby, according to the present embodiment, the performance of the channel semiconductor layer 12 can be improved as described above. Further, the performance of the other portions in each of the columnar portions CL can also be improved as described above.

[0092] (Third Embodiment)

[0093] Figure 27 and Figure 28 is a cross-sectional view showing the structure of the semiconductor device of the third embodiment.

[0094] Figure 27 shows a longitudinal cross section (XZ cross section) of the semiconductor device of the present embodiment. Figure 28 shows a transverse cross section (XY cross section) of the semiconductor device of the present embodiment. Figure 27 shows a longitudinal cross section (XZ cross section) of the semiconductor device of the present embodiment. Figure 28a longitudinal cross section of the B-B' line of Figure 28 indicates a direction along Figure 27 a cross section of the A-A' line. The semiconductor device of the present embodiment is, for example, a three-dimensional memory.

[0095] Hereinafter, the structure of the semiconductor device of the present embodiment will be described mainly with reference to Figure 27 . In this description, reference will also be made to Figure 28 as appropriate.

[0096] As shown in Figure 27 , the semiconductor device of the present embodiment is provided with a substrate 31, an interlayer insulating film 32, a plurality of core insulating films 41, a plurality of channel semiconductor layers 42, a plurality of tunnel insulating films 43, a plurality of charge accumulation layers (floating gates) 44, a barrier insulating film 45, and a plurality of electrode layers (control gates) 46. Each channel semiconductor layer 42 includes semiconductor regions 42a, 42b. Each barrier insulating film 45 includes insulating films 45a, 45b, 45c. The barrier insulating film 45 is an example of a first insulating film, and the tunnel insulating film 43 is an example of a second insulating film. The semiconductor region 42a is an example of a first semiconductor region, and the semiconductor region 42b is an example of a second semiconductor region.

[0097] The substrate 31 is, for example, a semiconductor substrate such as a Si substrate. As with Figures 1-26 , Figure 27 , the X direction and the Y direction parallel to the surface of the substrate 31 and perpendicular to each other, and the Z direction perpendicular to the surface of the substrate 31 are shown. The Z direction is an example of a first direction. The Y direction is an example of a second direction.

[0098] The interlayer insulating film 32 is formed on the substrate 31. The interlayer insulating film 32 is, for example, a SiO2 film.

[0099] The core insulating film 41, the channel semiconductor layer 42, the tunnel insulating film 43, the charge accumulation layer 44, the barrier insulating film 45, and the electrode layer 46 are formed on the substrate 31 within the interlayer insulating film 32. The core insulating film 41 is, for example, a SiO2 film. The semiconductor regions 42a, 42b of the channel semiconductor layer 42 are, for example, a polysilicon layer and a SiC layer, respectively. The tunnel insulating film 43 is, for example, a SiO2 film. The charge accumulation layer 44 is, for example, a polysilicon layer. The insulating films 45a, 45b, 45c of the barrier insulating film 45 are, for example, a SiN film, a SiO2 film, and a SiN film, respectively. The electrode layer 46 is, for example, a metal layer including a W layer.

[0100] Each electrode layer 46 has a band-like shape extending along the Y direction Figure 27 and Figure 28 ). Figure 27A plurality of electrode layers 46 are arranged in a plurality of groups (2 groups in this example) of electrode layer arrays in the Z direction, and each electrode layer array includes a plurality of electrode layers 46 (4 in this example) arranged in a one-dimensional array in the Z direction with a space between the electrode layers. The number of electrode layers 46 in each electrode layer array is not limited to 4.

[0101] Each charge accumulation layer 44 is provided on the side of the corresponding electrode layer 46 with the corresponding barrier insulating film 45 interposed therebetween (and Figure 27 Figure 28 ). The insulating films 45c, 45b are sequentially formed on the upper surface, lower surface, and side of the corresponding electrode layer 46 as shown in Figure 27 Figure 27 . On the other hand, the insulating film 45a is formed on the upper surface, lower surface, and side of the corresponding charge accumulation layer 44 as shown in Figure 27 Figure 28 A plurality of charge accumulation layers 44 are arranged in a plurality of groups (2 groups in this example) of charge accumulation layer arrays in the Z direction and Y direction, and each charge accumulation layer array includes a plurality of charge accumulation layers 44 (16 in this example) arranged in a two-dimensional array in the Z direction and Y direction with a space between the charge accumulation layers. The number of charge accumulation layers 44 in each charge accumulation layer array is not limited to 16.

[0102] Each channel semiconductor layer 42 is provided on the side of the corresponding plurality of charge accumulation layers 44 with the corresponding tunnel insulating film 43 interposed therebetween (and Figure 27 Figure 28 ). The semiconductor regions 42a, 42b are sequentially formed on the side of the corresponding plurality of charge accumulation layers 44 with the corresponding tunnel insulating film 43 interposed therebetween. Each channel semiconductor layer 42 has a columnar shape extending in the Z direction as shown in Figure 27 Figure 28 . Figure 28 A plurality of channel semiconductor layers 42 are arranged in a plurality of groups (4 groups in this example) of channel semiconductor layer arrays in the Y direction, and each channel semiconductor layer array includes a plurality of channel semiconductor layers 42 (4 in this example) arranged in a one-dimensional array in the Y direction with a space between the channel semiconductor layers. The number of channel semiconductor layers 42 in each channel semiconductor layer array is not limited to 4.

[0103] Each core insulating film 41 is arranged between the corresponding 2 groups of channel semiconductor layer arrays and is provided on the side of each channel semiconductor layer 42 in these channel semiconductor layer arrays (and Figure 27 Figure 28 ). Each core insulating film 41 has a substantially plate shape extending in the Z direction and Y direction as shown in Figure 27 Figure 28 .

[0104] ​​​​​​​In this embodiment, each channel semiconductor layer 42 extends along the Z direction, and each electrode layer 46 extends along the Y direction. Furthermore, each charge accumulation layer 44 is disposed at the intersection of a corresponding channel semiconductor layer 42 and a corresponding electrode layer 46. This results in a two-dimensional matrix configuration of charge accumulation layers 44.

[0105] The semiconductor device of this embodiment can be manufactured using a method similar to that used in the semiconductor device of the first or second embodiment. For example, when forming the semiconductor regions 42a and 42b of the channel semiconductor layer 42, the process is the same as when forming the semiconductor regions 12a and 12b of the channel semiconductor layer 12. Figures 4-7 The process shown is as follows. This allows F atoms to be introduced into the channel semiconductor layer 42, the tunnel insulating film 43, the charge accumulation layer 44, the barrier insulating film 45, and the electrode layer 46, as well as into the interfaces between them.

[0106] As described above, similarly to the channel semiconductor layer 12 of the first and second embodiments, the channel semiconductor layer 42 of this embodiment is formed to include a semiconductor region 42a containing silicon (Si) and a semiconductor region 42b containing silicon (Si) and carbon (C). Therefore, according to this embodiment, similarly to the cases of the first and second embodiments, the performance of the channel semiconductor layer 42 and other portions can be improved.

[0107] (Fourth implementation)

[0108] Figure 29 and Figure 30 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the fourth embodiment.

[0109] First, in implementation Figures 2-4 After the process shown, fluorine additives are supplied to each memory hole MH. Figure 29 As a result, the fluorine additive adhered to the side surface of the semiconductor region 12a within each memory hole MH.

[0110] The fluorine additive can be a gaseous or liquid substance. In this embodiment, the fluorine additive is, for example, a liquid substance, coated onto the side surfaces of the semiconductor regions 12a within each memory hole MH. Furthermore, the fluorine additive in this embodiment is, for example, a substance containing at least fluorine (F) and carbon (C), having functional groups capable of forming chemical bonds with the surface of the semiconductor regions 12a. These functional groups are, for example, silane groups. In this embodiment, a silanizing agent incorporating fluorine through fluorine substitution is used as the fluorine additive. The fluorine and carbon content of the fluorine additive can be adjusted, for example, by changing the composition of the substituents.

[0111] In addition, the fluorine additive can have a functional group other than a silane group, such as a functional group capable of forming an ionic bond with the surface of the semiconductor region 12a. Examples of such a functional group include a sulfone group, an amino group, a carboxyl group, a mercaptan group, and the like. The fluorine additive of the present embodiment is made to become a cation or anion by causing hydrogen to bond to or dissociate from the molecule of the fluorine additive, thereby adsorbing on the surface of the semiconductor region 12a.

[0112] The semiconductor region 12a of the present embodiment is, for example, a polysilicon layer whose surface is oxidized by air. Thus, the silanization agent is chemically adsorbed on the side surface of the semiconductor region 12a in each memory hole MH. In addition, the silanization agent can be physically adsorbed on the side surface of the semiconductor region 12a instead of being chemically adsorbed on the side surface of the semiconductor region 12a.

[0113] Next, a core insulating film 13 is formed on the side surface of the semiconductor region 12a in each memory hole MH, and modification annealing of the core insulating film 13 and subsequent additional annealing are performed. Figure 30 As a result, a semiconductor region 12b is formed between the semiconductor region 12a and the core insulating film 13, and F atoms originating from the fluorine additive diffuse into the semiconductor region 12b, the semiconductor region 12a, the tunnel insulating film 11c, the charge accumulation layer 11b, and the barrier insulating film 11a, and into the interfaces therebetween. Figure 30 The F atoms diffused in this manner are schematically shown. In the present embodiment, a SiC layer is formed as the semiconductor region 12b by C atoms originating from the fluorine additive.

[0114] Before the modification annealing is performed, the silanization agent is present at the interface between the semiconductor region 12a and the core insulating film 13. The silanization agent is decomposed into C atoms and F atoms by the heat of the modification annealing and the additional annealing. As a result, the C atoms form the semiconductor region 12b as described above, and the F atoms diffuse as described above. Thus, the same effects as those brought about by the SiC layer and the F atoms in the first to third embodiments can be obtained.

[0115] Subsequently, various wiring layers, plug layers, interlayer insulating films, and the like are formed over the substrate 1. In this manner, the semiconductor device of the present embodiment is manufactured.

[0116] Figure 31 is a cross-sectional view for comparing the manufacturing method of the semiconductor device of the first embodiment with the manufacturing method of the semiconductor device of the fourth embodiment.

[0117] Figure 31 (a) shows the semiconductor region 12b formed using the method of the first embodiment. In the first embodiment, a polymer layer 21 is formed on the side surface of the semiconductor region 12a.Figure 5 ), and the semiconductor region 12b is formed using the polymer layer 21. In this case, if the aspect ratio of the memory hole MH is large, the thickness of each portion of the polymer layer 21 can change depending on the depth at which each portion is provided. For example, the thickness of the polymer layer 21 near the upper end of the memory hole MH can become thick, and the thickness of the polymer layer 21 near the lower end of the memory hole MH can become thin. As a result, the thickness of the semiconductor region 12b and the distribution of F atoms within each columnar portion CL can become uneven.

[0118] Figure 31 (b) shows the semiconductor region 12b formed using the method of the fourth embodiment. In the fourth embodiment, the semiconductor region 12b is formed by causing the fluorine additive to adhere to the side surface of the semiconductor region 12a. In this case, even if the aspect ratio of the memory hole MH is large, the fluorine additive can be caused to adhere uniformly to the side surface of the semiconductor region 12a. Thus, the thickness of the semiconductor region 12b and the distribution of F atoms within each columnar portion CL can be easily made uniform.

[0119] Figure 32 is a table for describing the fluorine additive of the fourth embodiment.

[0120] Figure 32 In Table 1, as specific examples of the fluorine additive of the present embodiment, HMDS (hexamethyldisilazane), TMSDMA (N-(Trimethylsilyl)dimethylamine), ODTS (octadecyl trichlorosilane), and perfluoroalkanesulfonic acid are shown. Figure 32 The structures and general forms of these substances are shown.

[0121] The fluorine content of the fluorine additive and the amount of diffusion of F atoms into each columnar portion CL can be adjusted, for example, by changing the composition of the substituents of the fluorine additive. For example, the alkyl group of the organic molecule such as HMDS or TMSDMA can be substituted with a fluoroalkyl group. Furthermore, the amount of diffusion of F atoms can be adjusted by introducing a reaction site to the substituents and adjusting the number of repetitions of the coating of the fluorine additive. At this time, the concentration of the fluorine additive adhering to the side surface of the semiconductor region 12a can also be adjusted by performing the coating process of the fluorine additive and the modification process using an oxidizing agent (e.g., ozone). Furthermore, the coating process of the fluorine additive and the modification process using an oxidizing agent can also be alternately repeated. Examples of the reaction site are functional groups such as a hydroxyl group (OH group), an amino group, a thiol group, a carboxyl group, and substituents containing an unsaturated bond such as an alkylene group and an alkyne group, and characteristic groups such as halogen.

[0122] Figure 33 This is a structural formula used to explain a portion of the structure of the fluorinated additive in the fourth embodiment. Specifically, Figure 33 It shows Figure 32 The structure of the R part in its general form is shown.

[0123] Figure 33 Example (a) shows a partial structure of a fluorinated additive (trifluoromethyl) in which all three H (hydrogen) atoms of the methyl group are replaced by F atoms. Figure 33 Example (b) illustrates a partial structure of a fluorinated additive in which 11 H atoms of the pentoxy group are replaced by F atoms (undecylfluoropentoxy). In this embodiment, the fluorine content of the fluorinated additive can be adjusted by changing the number of F atoms in the functional group (partial structure).

[0124] Figure 33 (c) shows a fluorinated additive containing an OH group as a reaction site. When a fluorinated additive molecule contains a reaction site, another molecule of the same fluorinated additive can bind to that reaction site. In this case, by adjusting the number of coating repetitions of the fluorinated additive, the amount of F atoms can be adjusted, thereby controlling the amount of F atom diffusion.

[0125] As described above, similar to the channel semiconductor layer 12 in the first embodiment, the channel semiconductor layer 12 in this embodiment is formed to include a semiconductor region 12a containing silicon (Si) and a semiconductor region 12b containing silicon (Si) and carbon (C). Therefore, according to this embodiment, similar to the cases in the first to third embodiments, the performance of the channel semiconductor layer 12 and other portions can be improved.

[0126] Furthermore, according to this embodiment, by using fluorine additives such as silanizing agents to form the semiconductor region 12b, it is possible to easily achieve a uniform thickness of the semiconductor region 12b and a uniform distribution of F atoms.

[0127] (Fifth Embodiment)

[0128] Figures 34-36 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the fifth embodiment.

[0129] First, in implementation Figures 2-4 After the process shown, fluorine additives are supplied to each memory hole MH. Figure 34 As a result, the fluorine additive adheres to the side surface of the semiconductor region 12a within each memory hole MH. The fluorine additive in this embodiment is, for example, the same as the fluorine additive in the fourth embodiment.

[0130] Next, insulating films 13a and 13b are sequentially formed on the side surfaces of the semiconductor regions 12a within each memory hole MH. Figure 35and Figure 36 ), and modification annealing of the insulating film 13b and subsequent additional annealing ( Figure 36 ) are performed. As a result, the semiconductor region 12b is formed between the semiconductor region 12a and the insulating film 13a, and F atoms originating from the fluorine additive diffuse into the semiconductor region 12b, the semiconductor region 12a, the tunnel insulating film 11c, the charge accumulation layer 11b, and the barrier insulating film 11a, and into interfaces between them. Figure 36 F atoms diffused in this way are schematically shown. In this embodiment, a SiC layer is formed as the semiconductor region 12b by C atoms originating from the fluorine additive.

[0131] Before the modification annealing is performed, a silanizing agent is present at the interface between the semiconductor region 12a and the insulating film 13a. This silanizing agent is decomposed into C atoms and F atoms by heat of the modification annealing and the additional annealing. As a result, the C atoms form the semiconductor region 12b as described above, and the F atoms diffuse as described above. Thus, the same effects as those brought about by the SiC layer and the F atoms in the first to fourth embodiments can be obtained.

[0132] In this embodiment, for example, the insulating film 13a is a SiN film, the insulating film 13b is a SiO2 film, and the core insulating film 13 is a laminate film including the insulating film 13a and the insulating film 13b. The insulating film 13a is an example of the third film.

[0133] Generally, the diffusion coefficient of F atoms in a SiN film is low. Thus, according to this embodiment, by forming the insulating film 13b on the side surface of the semiconductor region 12a through the insulating film 13a, it is possible to suppress the case where F atoms do not diffuse to the semiconductor region 12a side but diffuse to the insulating film 13b side. In addition, the insulating film 13a can be an insulating film other than a SiN film having a low diffusion coefficient of F atoms.

[0134] After that, various wiring layers, plug layers, interlayer insulating films, and the like are formed over the substrate 1. In this way, the semiconductor device of this embodiment is manufactured.

[0135] According to this embodiment, by forming the semiconductor region 12b using a fluorine additive such as a silanizing agent, it is possible to easily achieve uniform thickness of the semiconductor region 12b and uniform distribution of F atoms.

[0136] Further, according to this embodiment, by forming the insulating film 13a on the side surface of the semiconductor region 12a after the fluorine additive is attached to the side surface of the semiconductor region 12a, it is possible to suppress the case where F atoms do not diffuse to the semiconductor region 12a side but diffuse to the insulating film 13b side.

[0137] The above has described several embodiments, but these embodiments are merely presented as examples and are not intended to limit the scope of the application. The novel apparatus and method described in this specification can be implemented in other various forms. In addition, various omissions, substitutions, and changes can be made to the forms of the apparatus and method described in this specification without departing from the spirit of the application. The attached claims and their equivalent scope are intended to include such forms and variations.

[0138] [Explanation of symbols]

[0139] 1 substrate

[0140] 2 stacked film

[0141] 2' stacked film

[0142] 2a electrode layer

[0143] 2a' sacrificial layer

[0144] 2b insulating layer

[0145] 3 interlayer insulating film

[0146] 4 source electrode layer

[0147] 4a metal layer

[0148] 4b lower semiconductor layer

[0149] 4c intermediate semiconductor layer

[0150] 4d upper semiconductor layer

[0151] 5 interlayer insulating film

[0152] 6 gate electrode layer

[0153] 7 interlayer insulating film

[0154] 11 memory insulating film

[0155] 11a barrier insulating film

[0156] 11b charge accumulation layer

[0157] 11c tunnel insulating film

[0158] 12 channel semiconductor layer

[0159] 12a semiconductor region

[0160] 12b semiconductor region

[0161] 13 core insulating film

[0162] 13a insulating film

[0163] 13b insulating film

[0164] 14 element separation insulating film

[0165] 21 polymer layer

[0166] 22 lower protective film

[0167] 23 sacrificial layer

[0168] 24 upper protective film

[0169] 25 spacer layer

[0170] 31 substrate

[0171] 32 interlayer insulating film

[0172] 41 core insulating film

[0173] 42 channel semiconductor layer

[0174] 42a semiconductor region

[0175] 42b semiconductor region

[0176] 43 tunnel insulating film

[0177] 44 charge accumulation layer (floating gate)

[0178] 45 barrier insulating film

[0179] 45a insulating film

[0180] 45b insulating film

[0181] 45c insulating film

[0182] 46 electrode layer (control gate)

Claims

1. A semiconductor device comprising: a substrate; a plurality of electrode layers disposed apart from each other in a first direction perpendicular to a surface of the substrate; and a first insulating film, a charge accumulation layer, a second insulating film, a first semiconductor region containing silicon, a second semiconductor region containing silicon and carbon, and a third film containing silicon and nitrogen, which are sequentially disposed on side surfaces of the electrode layers. An interface of the first semiconductor region and the second insulating film contains fluorine. The first semiconductor region, the second insulating film, the charge accumulation layer, or the first insulating film contains fluorine. A thickness of the first semiconductor region is 3 nm or less.

2. The semiconductor device according to claim 1, wherein The concentration of carbon atoms in the second semiconductor region is 1.0 x 1018atoms / cm3or more. 22 cm -3 The following.

3. The semiconductor device according to claim 1, wherein A thickness of the second semiconductor region is thinner than a thickness of the first semiconductor region.

4. The semiconductor device according to claim 3, wherein The concentration of fluorine atoms in the first semiconductor region, in the second insulating film, in the charge accumulation layer, or in the first insulating film is 1.0 x 10 22 cm -3 below.

5. The semiconductor device according to any one of Claims 1 to 4, wherein 7. The semiconductor device according to any one of claims 1 to 4, further comprising a semiconductor layer disposed between the substrate and the plurality of electrode layers and in contact with the first semiconductor region.

6. The semiconductor device according to any one of Claims 1 to 4, wherein A third semiconductor region containing p-type impurity atoms or n-type impurity atoms is contained in a lower end portion of the first semiconductor region. A concentration of the p-type impurity atoms or the n-type impurity atoms in the third semiconductor region in contact with the semiconductor layer is higher than a concentration of the p-type impurity atoms or the n-type impurity atoms in the third semiconductor region in contact with the second insulating film.

8. The semiconductor device according to claim 7, wherein A concentration of fluorine atoms in an interface of the third semiconductor region and the second insulating film is substantially uniform throughout the interface.

9. The semiconductor device according to claim 8, wherein The charge accumulation layer is disposed at intersections of the first and second semiconductor regions extending in the first direction and the electrode layers extending in a second direction different from the first direction.

10. The semiconductor device according to claim 8, wherein a plurality of first films are formed apart from each other in a first direction perpendicular to a surface of a substrate, 11. The semiconductor device according to any one of Claims 1 to 4, wherein a first insulating film, a charge accumulation layer, a second insulating film, a first semiconductor region containing silicon, and a second semiconductor region containing silicon and carbon are sequentially formed on side surfaces of the first films; 12. A method of manufacturing a semiconductor device, comprising the steps of: the method of manufacturing the semiconductor device further includes a step of forming a second film containing carbon and fluorine on side surfaces of the first semiconductor region before the second semiconductor region is formed, and the first semiconductor region and the second insulating film are formed in such a manner that an interface of the first semiconductor region and the second insulating film contains fluorine.

13. The method of manufacturing the semiconductor device according to claim 12, further comprising steps of: the second semiconductor region is formed between the first semiconductor region and the second film by heating the second film, and fluorine is supplied to an interface of the first semiconductor region and the second insulating film. a liquid or gaseous substance containing carbon and fluorine is attached to side surfaces of the first semiconductor region before the second semiconductor region is formed, the second semiconductor region is formed on side surfaces of the first semiconductor region by heating the substance, and fluorine is supplied to an interface of the first semiconductor region and the second insulating film.

14. The method for manufacturing a semiconductor device according to claim 13, wherein The second film is formed using C x H y F z gas, wherein C represents carbon, H represents hydrogen, F represents fluorine, x represents an integer of 1 or more, y represents an integer of 0 or more, and z represents an integer of 1 or more.

15. The method of manufacturing a semiconductor device according to Claim 12, further comprising the step of: The substance contains a silanizing agent. a third film containing silicon and nitrogen is formed on side surfaces of the first semiconductor region after the substance is attached and before the second semiconductor region is formed.

16. The method of manufacturing a semiconductor device according to claim 15, wherein ​ 17. The method of manufacturing a semiconductor device according to claim 15, further comprising the step of: ​ 18. The method of fabricating a semiconductor device according to any one of claims 12 to 17, wherein, forming an electrode layer as the first film, or forming an insulating film as the first film and replacing the insulating film with an electrode layer.

Images