Current sharing circuit and current sharing system based on COT buck converter

Abstract

This invention discloses a current-sharing circuit and system based on a COT buck converter. The current-sharing circuit includes a current sampling unit for acquiring a current sampling signal representing the magnitude of the inductor current in the COT buck converter; and a current balancing control unit for converting the current sampling signal into a reference voltage signal that gradually decreases as the inductor current in the COT buck converter increases, thereby achieving current-sharing control. This invention can achieve current-sharing control when multiple phases are connected in parallel within a COT architecture.

Description

Technical Field

[0001] The present invention belongs to the technical field of COT buck converters, and in particular relates to a current sharing circuit and a current sharing system based on a COT buck converter. Background Art

[0002] Ginseng Figure 1 The circuit diagram of the buck converter in the prior art is shown. The buck converter includes a circuit configured to receive an input voltage V IN A pair of power switches M1 and M2 are alternately turned on and off to generate a switching output voltage V at the switch node (SW). SW . Switch output voltage V SW is directly coupled to the output inductor L and output capacitor C OUT The LC filter circuit generates a regulated output voltage V with a substantially constant value at the output terminal. OUT . Then it is possible to use the output voltage V OUT To drive the load, the buck converter provides the load current to make the output voltage V OUT Keep it at a constant level.

[0003] The buck converter includes a feedback control circuit to regulate the energy transfer to the LC filter circuit to maintain a constant output voltage within the desired load limits of the circuit. More specifically, the feedback control circuit causes the power switches M1 and M2 to turn on and off to adjust the output voltage V OUT Adjust to equal the reference voltage V REF Or with reference voltage V REF In this embodiment, the output voltage V is divided by the voltage divider resistors R1 and R2. OUT , which is then used as the feedback voltage V on the feedback node FB Feedback to the buck converter. The comparator converts the feedback voltage V FB With reference voltage V REF The comparator output is coupled to a controller and a gate drive circuit to generate a control voltage for the power switches based on a buck converter control scheme, which is used to generate drive signals for the power switches M1 and M2.

[0004] Buck converters based on constant on-time (COT) are widely used in industry due to certain important advantages, such as fast load transient response and easy control of relatively large off-time and very small constant on-time to regulate high input voltage to low output voltage. A constant on-time regulator is a type of voltage regulator that uses ripple mode control in which the output voltage is regulated based on the ripple component in the output signal. Due to the switching action at the power switch, all switch-mode regulators generate output ripple current by switching the output inductor. This current ripple itself is mainly due to the output capacitor C placed in parallel with the load. OUT The equivalent series resistance in the circuit is reflected as output voltage ripple.

[0005] However, in existing systems with multiple power management chips (multiple power stages) connected in parallel, the load current on each chip varies, affecting the overall efficiency of the system. Furthermore, when the load current exceeds the capacity of a single chip, the system may not function properly and enter overload protection mode.

[0006] Therefore, in order to solve the above technical problems, it is necessary to provide a current sharing circuit and current sharing system based on a COT buck converter. Summary of the Invention

[0007] In view of this, an object of the present invention is to provide a current sharing circuit and a current sharing system based on a COT buck converter.

[0008] In order to achieve the above-mentioned purpose, the technical solution provided by one embodiment of the present invention is as follows:

[0009] A current balancing circuit based on a COT buck converter, the current balancing circuit comprising:

[0010] A current sampling unit, used to obtain a current sampling signal representing the magnitude of the inductor current in the COT buck converter;

[0011] The current balancing control unit is used to convert the current sampling signal into a reference voltage signal that gradually decreases as the inductor current in the COT buck converter increases, thereby achieving current balancing control.

[0012] In one embodiment, the COT buck converter includes a comparator, a controller and a gate drive circuit, a first switch tube, a second switch tube, a first voltage divider resistor, a second voltage divider resistor, an output inductor, and an output capacitor, wherein:

[0013] The first switch tube and the second switch tube are connected in series to the input voltage V IN A node between the first switch tube and the second switch tube is a switching node;

[0014] The first voltage dividing resistor and the second voltage dividing resistor are connected in series to the output voltage VOUT The voltage between the first voltage-dividing resistor and the second voltage-dividing resistor is a voltage-dividing signal;

[0015] The output inductor is connected to the switch node and the output voltage V OUT Between, the output capacitor is connected to the output voltage V OUT Between the reference potential;

[0016] The comparator is used to receive the voltage division signal and the reference voltage signal, and output a comparison signal;

[0017] The controller and the gate drive circuit are used to generate a gate control signal according to the comparison signal to control the first switch tube and the second switch tube to be alternately turned on and off to generate a switch output voltage at the switch node.

[0018] In one embodiment, the first switch transistor is a PMOS transistor, and the second switch transistor is an NMOS transistor, wherein:

[0019] The source of the first switch tube is connected to the input voltage V IN connected, the drain is connected to the switch node, and the gate is connected to the controller and the gate drive circuit;

[0020] The source of the second switch tube is connected to the reference potential, the drain is connected to the switch node, and the gate is connected to the controller and the gate drive circuit.

[0021] In one embodiment, the current sampling signal is a current signal or a voltage signal.

[0022] In one embodiment, the current sampling unit includes a plurality of sampling transistors, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor and a second NMOS transistor, a first current source, a second current source, a third resistor, and a filtering unit, wherein:

[0023] The sampling tube is connected in series to the input voltage V IN Between the first node and the source of the sampling tube and the input voltage V IN or the drain of the previous sampling tube is connected, the drain of the sampling tube is connected to the first node or the source of the next sampling tube, the gates of all sampling tubes are connected to the reference potential, and the voltage of the first node is equal to the voltage of the switch node;

[0024] The source of the first PMOS transistor is connected to the first node, the drain is connected to the first current source and then to the reference potential, and the gate and the drain are short-circuited;

[0025] The source of the second PMOS transistor is connected to the switch node, the drain is connected to the second current source and then to the reference potential, and the gate is connected to the gate of the first PMOS transistor;

[0026] The gate of the third PMOS transistor is connected to the drain of the second PMOS transistor, the source is connected to the first node, the drain is connected to the drain of the first NMOS transistor, the gate and drain of the first NMOS transistor are short-circuited, and the source is connected to the reference potential;

[0027] The gate of the second NMOS tube is connected to the gate of the first NMOS tube, the source is connected to the reference potential, the drain is connected to the drain of the fourth PMOS tube, the gate and drain of the fourth PMOS tube are short-circuited, and the source is connected to the input voltage V IN connected;

[0028] The source of the fifth PMOS tube is connected to the input voltage V IN The gate is connected to the gate of the fourth PMOS tube, and the drain is connected to the third resistor and then to the reference potential;

[0029] The filtering unit is used to filter the voltage across the third resistor to obtain a DC voltage signal, namely the current sampling signal V SENSE .

[0030] In one embodiment, the filtering unit includes a first switch, a fourth resistor, and a first capacitor, wherein:

[0031] The first end of the first switch is connected to the first end of the third resistor, the second end is connected to the first end of the fourth resistor, the second end of the fourth resistor is connected to the first plate of the first capacitor, the second plate of the first capacitor is connected to the second end of the third resistor, and the second end of the fourth resistor outputs the current sampling signal V SENSE ;

[0032] The first switch is closed when the first switch tube is turned on, and is opened when the first switch tube is turned off.

[0033] In one embodiment, the current balancing control unit includes a third NMOS transistor, a fourth NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a fifth resistor, a sixth resistor, a first error amplifier, and a second error amplifier, wherein:

[0034] The source of the sixth PMOS tube is connected to the input voltage V IN The gate and the drain are short-circuited, the drain is connected to the drain of the fifth NMOS transistor, the source of the fifth NMOS transistor is connected to the third node, and the fifth resistor is connected between the third node and the reference potential;

[0035] The source of the seventh PMOS tube is connected to the input voltage V IN The gate is connected to the gate of the sixth PMOS tube, the drain is connected to the drain of the third NMOS tube, the gate and drain of the third NMOS tube are short-circuited, and the source is connected to the reference potential;

[0036] The source of the eighth PMOS tube is connected to the input voltage V IN The gate of the fourth NMOS transistor is connected to the gate of the third NMOS transistor, the source is connected to the reference potential, and the sixth resistor is connected between the drain of the eighth PMOS transistor and the drain of the fourth NMOS transistor;

[0037] The first input terminal of the first error amplifier is connected to the current sampling signal V SENSE The second input terminal is connected to the third node, and the output terminal is connected to the gate of the fifth NMOS transistor;

[0038] The first input terminal of the second error amplifier is connected to the reference voltage V REF The second input terminal and the output terminal are both connected to the second node;

[0039] The drain of the fourth NMOS tube outputs a reference voltage signal V REF_LOOP .

[0040] In one embodiment, the voltage of the second node is equal to the reference voltage V REF , reference voltage signal V REF_LOOP is equal to the difference between the voltage of the second node and the voltage drop of the sixth resistor.

[0041] In one embodiment, the reference voltage signal V REF_LOOP for:

[0042]

[0043] Where K is the current sampling coefficient, I OUT is the output current.

[0044] Another embodiment of the present invention provides a technical solution as follows:

[0045] A current sharing system based on a COT buck converter includes a plurality of power management chips, each of which includes the above-mentioned current sharing circuit to make the inductor currents of the plurality of power management chips equal.

[0046] The present invention has the following beneficial effects:

[0047] The present invention obtains a current sampling signal representing the magnitude of the inductor current through a current sampling unit, and converts the current sampling signal into a reference voltage signal that gradually decreases as the inductor current increases through a current balancing control unit, thereby realizing current sharing control when multiple phases are used in parallel under a COT architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0049] Figure 1 A circuit diagram of a buck converter in the prior art;

[0050] Figure 2 1 is a circuit diagram of a current sharing circuit based on a COT buck converter according to the present invention;

[0051] Figure 3 is a circuit diagram of a current sampling unit in a specific embodiment of the present invention;

[0052] Figure 4 is a circuit diagram of a current balancing control unit in a specific embodiment of the present invention;

[0053] Figure 5 This is an application circuit diagram of two chips used in parallel in a specific embodiment of the present invention;

[0054] Figure 6 This is a simulation waveform diagram of current sharing when two chips are used in parallel in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0056] Ginseng Figure 2 As shown, the present invention discloses a current sharing circuit based on a COT buck converter (COT BUCK), the current sharing circuit comprising:

[0057] The current sampling unit (Current Sense) is used to obtain a current sampling signal representing the magnitude of the inductor current in the COT buck converter;

[0058] The current sharing control unit is used to convert the current sampling signal into a reference voltage signal that gradually decreases as the inductor current in the COT buck converter increases, thereby achieving current sharing control.

[0059] The COT buck converter (COT BUCK) includes a comparator (Comparator), a controller and gate drive circuit (Control Logic & Driver), a first switch tube M1, a second switch tube M2, a first voltage divider resistor R1, a second voltage divider resistor R2, an output inductor L and an output capacitor C OUT ,in:

[0060] The first switch tube M1 and the second switch tube M2 are connected in series to the input voltage V IN The node between the first switch tube M1 and the second switch tube M2 is the switch node SW;

[0061] The first voltage dividing resistor R1 and the second voltage dividing resistor R2 are connected in series with the output voltage V OUT The voltage between the first voltage divider resistor R1 and the second voltage divider resistor R2 is the voltage divider signal V FB ;

[0062] The output inductor L is connected between the switch node SW and the output voltage V OUT Between, the output capacitor C OUT Connect to the output voltage V OUT Between the reference potential;

[0063] The comparator is used to receive the voltage divided signal V FB and the reference voltage signal V REF_LOOP , and output comparison signal;

[0064] The controller and gate drive circuit are used to generate a gate control signal according to the comparison signal to control the first switch tube M1 and the second switch tube M2 to turn on and off alternately, so as to generate a switch output voltage V at the switch node SW. SW .

[0065] Specifically, the first switch tube M1 is a PMOS tube, and the second switch tube M2 is an NMOS tube, wherein:

[0066] The source of the first switch tube M1 is connected to the input voltage V IN connected, the drain is connected to the switch node SW, and the gate is connected to the controller and the gate drive circuit;

[0067] The source of the second switch tube M2 is connected to the reference potential, the drain is connected to the switch node SW, and the gate is connected to the controller and the gate drive circuit.

[0068] Preferably, the reference potential in this embodiment is described by taking the ground potential (GND) as an example, and may be other reference potentials in other embodiments.

[0069] The current sampling signal in the present invention is a current signal or a voltage signal. The current sampling unit can sample the current of the first switch tube M1, the current of the second switch tube M2, or any other signal in the sampling circuit that represents the magnitude of the inductor current.

[0070] Ginseng Figure 3 As shown, in a specific embodiment of the present invention, the current sampling unit is described by taking sampling the current of the first switch tube M1 as an example.

[0071] Specifically, the current sampling unit in this embodiment includes several sampling transistors sense FET, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a first NMOS transistor MN1 and a second NMOS transistor MN2, a first current source I1, a second current source I2, a third resistor R3, and a filter unit, wherein:

[0072] The sampling tube sense fet is connected in series with the input voltage V IN Between the first node A and the source of the sampling tube sense fet and the input voltage V IN Or the drain of the previous sampling tube sense FET is connected, the drain of the sampling tube sense FET is connected to the first node A or the source of the next sampling tube sense FET, the gates of all sampling tube sense FETs are connected to the reference potential, and the voltage of the first node A is equal to the voltage of the switch node SW;

[0073] The source of the first PMOS transistor MP1 is connected to the first node A, the drain is connected to the first current source I1 and then to the reference potential, and the gate and the drain are short-circuited;

[0074] The source of the second PMOS transistor MP2 is connected to the switch node SW, the drain is connected to the second current source I2 and then to the reference potential, and the gate is connected to the gate of the first PMOS transistor MP1;

[0075] The gate of the third PMOS transistor MP3 is connected to the drain of the second PMOS transistor MP2, the source is connected to the first node A, the drain is connected to the drain of the first NMOS transistor MN1, the gate and drain of the first NMOS transistor MN1 are short-circuited, and the source is connected to the reference potential;

[0076] The gate of the second NMOS transistor MN2 is connected to the gate of the first NMOS transistor MN1, the source is connected to the reference potential, the drain is connected to the drain of the fourth PMOS transistor MP4, the gate and drain of the fourth PMOS transistor MP4 are short-circuited, and the source is connected to the input voltage V IN connected;

[0077] The source of the fifth PMOS tube MP5 is connected to the input voltage VIN The gate is connected to the gate of the fourth PMOS transistor MP4, and the drain is connected to the third resistor R3 and then to the reference potential;

[0078] The filtering unit is used to filter the voltage across the third resistor R3 to obtain a DC voltage signal, namely the current sampling signal V SENSE .

[0079] Preferably, the filtering unit in this embodiment includes a first switch switch1, a fourth resistor R4 and a first capacitor C1, wherein:

[0080] The first end of the first switch switch1 is connected to the first end of the third resistor R3, the second end is connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is connected to the first plate of the first capacitor C1, the second plate of the first capacitor C1 is connected to the second end of the third resistor R3, and the second end of the fourth resistor R4 outputs the current sampling signal V SENSE ;

[0081] The first switch switch1 is closed when the first switch tube M1 is turned on, and is opened when the first switch tube M1 is turned off.

[0082] In this embodiment, the current sampling unit samples the current of the first switch tube M1. When the first switch tube M1 is turned on, V IN SW is connected to the source and drain of the first switching transistor M1, respectively. After the sampled current flows through the sampling transistor, the voltage generated at node A is exactly equal to the voltage at node SW. At this point, the source, drain, and gate voltages of the sampling transistor are equal to those of M1. The sampled current is related to the ratio of the W / L of the sampling transistor to that of M1.

[0083] The sampling current is mirrored by the two pairs of current mirrors MN1 / MN2 and MP4 / MP5, and then converted into a voltage signal by the resistor R3. The first switch switch1 is closed when the first switch tube M1 is turned on, and is opened when the first switch tube M1 is turned off. The voltage on R3 is filtered by switch1, R4, and C1 to become a DC voltage signal V SENSE , and the voltage signal is proportional to the average value of the inductor current.

[0084] Of course, in other embodiments, the current sampling unit may also sample the current of the second switch tube M2, or be a sampling circuit for sampling any other signal representing the magnitude of the inductor current. The circuit structure is similar and will not be described one by one here.

[0085] Ginseng Figure 4As shown, the current balancing control unit in a specific embodiment of the present invention includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a fifth resistor R5, a sixth resistor R6, a first error amplifier EA1, and a second error amplifier EA2, wherein:

[0086] The source of the sixth PMOS transistor MP6 is connected to the input voltage V IN The gate and the drain are short-circuited, the drain is connected to the drain of the fifth NMOS transistor MN5, the source of the fifth NMOS transistor MN5 is connected to the third node C, and the fifth resistor R5 is connected between the third node C and the reference potential;

[0087] The source of the seventh PMOS tube MP7 is connected to the input voltage V IN The gate is connected to the gate of the sixth PMOS transistor MP6, the drain is connected to the drain of the third NMOS transistor MN3, the gate and drain of the third NMOS transistor MN3 are short-circuited, and the source is connected to the reference potential;

[0088] The source of the eighth PMOS tube MP8 is connected to the input voltage V IN The gate of the fourth NMOS transistor MN4 is connected to the gate of the third NMOS transistor MN3, the source is connected to the reference potential, and the sixth resistor R6 is connected between the drain of the eighth PMOS transistor MP8 and the drain of the fourth NMOS transistor MN4;

[0089] The first input terminal of the first error amplifier EA1 is connected to the current sampling signal V SENSE The second input terminal is connected to the third node C, and the output terminal is connected to the gate of the fifth NMOS transistor MN5;

[0090] The first input terminal of the second error amplifier EA2 is connected to the reference voltage V REF The second input terminal and the output terminal are both connected to the second node B;

[0091] The drain of the fourth NMOS transistor MN4 outputs a reference voltage signal V REF_LOOP .

[0092] The current balancing control unit in this embodiment converts the current sampling signal into a reference voltage signal V that decreases slowly as the inductor current increases. REF_LOOP The larger the inductor current, the larger the current sampling signal V SENSE The larger the resistor R5 is, the larger the current generated in the resistor R5 is, and the larger the current flowing through R6 is.

[0093] Under the action of EA2, the voltage of the second node B is equal to the reference voltage V REF, reference voltage signal V REF_LOOP It is equal to the difference between the voltage of the second node B and the voltage drop of the sixth resistor R6.

[0094] That is, the reference voltage signal V REF_LOOP for:

[0095]

[0096] Where K is the current sampling coefficient, I OUT is the output current.

[0097] The present invention also discloses a current sharing system based on a COT buck converter. The current sharing system includes multiple power management chips, each of which includes the above-mentioned current sharing circuit to make the inductor currents of the multiple power management chips equal.

[0098] Ginseng Figure 5 As shown, the present invention is described in a specific embodiment by taking two power management chips chip1 and chip2 as an example. Chip1 and chip2 respectively include the current sharing circuit (current sampling unit and current balancing control unit) in the above embodiment, and the output inductors corresponding to chip1 and chip2 are L1 and L2 respectively.

[0099] If chip1 and chip2 don't use a current-sharing circuit, it's very easy for one chip to provide the majority of the load current, while the other chip provides only a small portion, affecting the overall system efficiency. If the load exceeds the capacity of a single chip, the system may not function properly and enter overload protection mode.

[0100] In this embodiment, both chip1 and chip2 use a current balancing circuit to avoid the above situation. When the current provided by one chip (assuming chip1) is greater than the current provided by the other chip (assuming chip2), the current sampling unit can collect the inductor currents of the two chips respectively. The current balancing control unit will make the reference voltage V REF_LOOP1 Lower than the reference voltage V of chip2 REF_LOOP2 Lower, so that the off time of each cycle of chip1 is longer than that of chip2, the inductor current of chip1 will gradually decrease, and the inductor current of chip2 will gradually increase until the inductor currents of chip1 and chip2 are equal and reach equilibrium, thus stabilizing in this equilibrium state.

[0101] Ginseng Figure 6 is a simulation waveform diagram in this embodiment. It can be seen that when the load changes dynamically, the inductor currents of L1 and L2 tend to evenly divide the load current and change in unison, indicating that the present invention can achieve a good current sharing effect.

[0102] It can be seen from the above technical solutions that the present invention has the following advantages:

[0103] The present invention obtains a current sampling signal representing the magnitude of the inductor current through a current sampling unit, and converts the current sampling signal into a reference voltage signal that gradually decreases as the inductor current increases through a current balancing control unit, thereby realizing current sharing control when multiple phases are used in parallel under a COT architecture.

[0104] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0105] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A current sharing circuit based on a COT buck converter, characterized in that: The current sharing circuit includes: A current sampling unit, used to obtain a current sampling signal representing the magnitude of the inductor current in the COT buck converter; The current balancing control unit is used to convert the current sampling signal into a reference voltage signal that gradually decreases as the inductor current in the COT buck converter increases, thereby achieving current balancing control; The COT buck converter includes a comparator, a controller, a gate drive circuit, a first switch tube, a second switch tube, a first voltage divider resistor, and a second voltage divider resistor, wherein: The node between the first switching transistor and the second switching transistor is a switching node; The comparator is used to receive the divided voltage signal of the output voltage and the reference voltage signal, and output a comparison signal; The controller and the gate drive circuit are used to generate a gate control signal according to the comparison signal to control the first switch tube and the second switch tube to be alternately turned on and off to generate a switch output voltage at the switch node; The current sampling unit includes a plurality of sampling tubes, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a first NMOS tube and a second NMOS tube, a first current source, a second current source, a third resistor and a filter unit, wherein: The sampling tube is connected in series to the input voltage V IN Between the first node and the source of the sampling tube and the input voltage V IN or the drain of the previous sampling tube is connected, the drain of the sampling tube is connected to the first node or the source of the next sampling tube, the gates of all sampling tubes are connected to the reference potential, and the voltage of the first node is equal to the voltage of the switch node; The source of the first PMOS transistor is connected to the first node, the drain is connected to the first current source and then to the reference potential, and the gate and the drain are short-circuited; The source of the second PMOS transistor is connected to the switch node, the drain is connected to the second current source and then to the reference potential, and the gate is connected to the gate of the first PMOS transistor; The gate of the third PMOS transistor is connected to the drain of the second PMOS transistor, the source is connected to the first node, the drain is connected to the drain of the first NMOS transistor, the gate and drain of the first NMOS transistor are short-circuited, and the source is connected to the reference potential; The gate of the second NMOS tube is connected to the gate of the first NMOS tube, the source is connected to the reference potential, the drain is connected to the drain of the fourth PMOS tube, the gate and drain of the fourth PMOS tube are short-circuited, and the source is connected to the input voltage V IN connected; The source of the fifth PMOS tube is connected to the input voltage V IN The gate is connected to the gate of the fourth PMOS tube, and the drain is connected to the third resistor and then to the reference potential; The filtering unit is used to filter the voltage across the third resistor to obtain a DC voltage signal, namely the current sampling signal V SENSE .

2. The current sharing circuit based on the COT buck converter according to claim 1, characterized in that: The COT buck converter further includes an output inductor and an output capacitor, wherein: The first switch tube and the second switch tube are connected in series to the input voltage V IN Between the reference potential; The first voltage dividing resistor and the second voltage dividing resistor are connected in series to the output voltage V OUT The voltage between the first voltage-dividing resistor and the second voltage-dividing resistor is a voltage-dividing signal; The output inductor is connected to the switch node and the output voltage V OUT Between, the output capacitor is connected to the output voltage V OUT Between the reference potential.

3. The current sharing circuit based on the COT buck converter according to claim 1, characterized in that: The first switch tube is a PMOS tube, and the second switch tube is an NMOS tube, wherein: The source of the first switch tube is connected to the input voltage V IN connected, the drain is connected to the switch node, and the gate is connected to the controller and the gate drive circuit; The source of the second switch tube is connected to the reference potential, the drain is connected to the switch node, and the gate is connected to the controller and the gate drive circuit.

4. The current sharing circuit based on the COT buck converter according to claim 1, characterized in that: The filtering unit includes a first switch, a fourth resistor and a first capacitor, wherein: The first end of the first switch is connected to the first end of the third resistor, the second end is connected to the first end of the fourth resistor, the second end of the fourth resistor is connected to the first plate of the first capacitor, the second plate of the first capacitor is connected to the second end of the third resistor, and the second end of the fourth resistor outputs the current sampling signal V SENSE ; The first switch is closed when the first switch tube is turned on, and is opened when the first switch tube is turned off.

5. The current sharing circuit based on the COT buck converter according to claim 1, characterized in that: The current balancing control unit includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a fifth resistor, a sixth resistor, a first error amplifier, and a second error amplifier, wherein: The source of the sixth PMOS tube is connected to the input voltage V IN The gate and the drain are short-circuited, the drain is connected to the drain of the fifth NMOS transistor, the source of the fifth NMOS transistor is connected to the third node, and the fifth resistor is connected between the third node and the reference potential; The source of the seventh PMOS tube is connected to the input voltage V IN The gate is connected to the gate of the sixth PMOS tube, the drain is connected to the drain of the third NMOS tube, the gate and drain of the third NMOS tube are short-circuited, and the source is connected to the reference potential; The source of the eighth PMOS tube is connected to the input voltage V IN The gate of the fourth NMOS transistor is connected to the gate of the third NMOS transistor, the source is connected to the reference potential, and the sixth resistor is connected between the drain of the eighth PMOS transistor and the drain of the fourth NMOS transistor; The first input terminal of the first error amplifier is connected to the current sampling signal V SENSE The second input terminal is connected to the third node, and the output terminal is connected to the gate of the fifth NMOS transistor; The first input terminal of the second error amplifier is connected to the reference voltage V REF The second input terminal and the output terminal are both connected to the second node; The drain of the fourth NMOS tube outputs a reference voltage signal V REF_LOOP .

6. The current sharing circuit based on the COT buck converter according to claim 5, characterized in that: The voltage of the second node is equal to the reference voltage V REF , reference voltage signal V REF_LOOP is equal to the difference between the voltage of the second node and the voltage drop of the sixth resistor.

7. The current sharing circuit based on the COT buck converter according to claim 6, characterized in that: The reference voltage signal V REF_LOOP for: ； Where K is the current sampling coefficient, I OUT is the output current.

8. A current sharing system based on a COT buck converter, characterized in that: The current sharing system includes multiple power management chips, each of which includes the current sharing circuit according to any one of claims 1 to 7, so as to make the inductor currents of the multiple power management chips equal.

Images