Integrated circuit power-on reset circuit

Abstract

The invention discloses an integrated circuit power-on reset circuit, wherein a first resistor and a second resistor are connected in series between a working power supply and a drain end of a first NMOS tube; a gate end of the first NMOS tube and a gate end of a third NMOS tube are connected to the connection point of the first resistor and the second resistor; the source ends of the first NMOS tube, the second NMOS tube and the third NMOS tube are all grounded; the drain end and the gate end of the first PMOS tube and the gate end of the second PMOS tube are connected to the drain end of the third NMOS tube; the source end of the first PMOS tube and the source end of the second PMOS tube are connected to the working power supply; the drain end of the second NMOS tube is connected to the drain end of the second PMOS tube and serves as a power-on reset voltage output end. The integrated circuit power-on reset circuit of the invention reduces the deviation of the power-on reset voltage with temperature changes, has good temperature compensation effect, small power-on reset voltage deviation and low power consumption.

Description

Technical Field

[0001] The invention relates to semiconductor circuit technology, in particular to an integrated circuit power-on reset circuit. Background Art

[0002] Many integrated circuits contain a power-on reset circuit, which is used to ensure that analog and digital modules are initialized to a known state after power is applied. Basically, the power-on reset (POR) function generates an internal reset pulse to avoid "competition" and keep the device static until the power supply voltage reaches a threshold that ensures normal operation. In ultra-low power power-on reset circuits, the voltage points of power-on and power-off are affected by process corners and temperature changes, which seriously affects the yield of the chip.

[0003] An existing integrated circuit power-on reset circuit is as follows Figure 1 As shown in the figure, the absolute value of the temperature coefficient of the NMOS tube M1 of the integrated circuit will be greatly different under different process angles. The large temperature coefficient difference of the NMOS tube M1 will significantly increase the deviation of the power-on reset voltage V2, causing the internal reset pulse RSTB applied to the internal circuit of the integrated circuit to have a large deviation due to temperature, affecting the normal reset of the integrated circuit. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide an integrated circuit power-on reset circuit, which reduces the deviation of the power-on reset voltage VPOR1 with temperature changes, has good temperature compensation effect, small power-on reset voltage deviation and low power consumption.

[0005] In order to solve the above technical problems, the present invention provides an integrated circuit power-on reset circuit, which includes a first resistor R1, a second resistor R2, a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a first PMOS transistor P1 and a second PMOS transistor P2;

[0006] The first resistor R1 and the second resistor R2 are connected in series between the working power supply VDD and the drain terminal of the first NMOS transistor M1;

[0007] The gate end of the first NMOS transistor M1 and the gate end of the third NMOS transistor M3 are both connected to the series connection point of the first resistor R1 and the second resistor R2;

[0008] The source ends of the first NMOS transistor M1, the second NMOS transistor M2 and the third NMOS transistor M3 are all grounded;

[0009] The drain terminal and gate terminal of the first PMOS tube P1 and the gate terminal of the second PMOS tube P2 are connected to the drain terminal of the third NMOS tube M3;

[0010] The source end of the first PMOS tube P1 and the source end of the second PMOS tube P2 are both connected to the working power supply VDD;

[0011] The drain terminal of the second NMOS tube M2 is connected to the drain terminal of the second PMOS tube P2 and serves as a power-on reset voltage output terminal por1.

[0012] Preferably, the first NMOS transistor M1 is composed of M basic NMOS transistors with the same structure connected in parallel;

[0013] The second NMOS tube M2 is composed of N basic NMOS tubes with the same structure connected in parallel;

[0014] The width-to-length ratio of each basic NMOS tube is the same;

[0015] N is greater than M, and both N and M are positive integers.

[0016] Preferably, N=K*M, where K is an integer greater than 1.

[0017] Preferably, K is 5-10.

[0018] Preferably, the third NMOS transistor M3 is composed of S basic NMOS transistors with the same structure connected in parallel, where S is a positive integer.

[0019] Preferably, S=J*M, where J is an integer greater than 1.

[0020] Preferably, J is 3-15.

[0021] Preferably, the resistance of the first resistor R1 is 0.1MΩ to 100MΩ;

[0022] The resistance of the second resistor R2 is 0.1MΩ to 100MΩ.

[0023] Preferably, the first NMOS transistor M1, the second NMOS transistor M2, and the third NMOS transistor M3 are enhanced NMOS;

[0024] The first PMOS tube P1 and the second PMOS tube P2 are enhancement type PMOS;

[0025] The first PMOS transistor P1 and the second PMOS transistor P2 have the same width-to-length ratio.

[0026] Preferably, the integrated circuit power-on reset circuit further includes a Schmitt trigger and an inverter;

[0027] The Schmitt trigger has an input end connected to the power-on reset voltage output end por1, and an output end connected to the input end of the inverter;

[0028] The output end of the inverter is used to connect to the internal circuit of the integrated circuit.

[0029] The integrated circuit power-on reset circuit of the present invention performs temperature compensation through the same type of NMOS tubes (M2, M1), and the power-on reset voltage VGS1 is the gate-source voltage of the first NMOS tube M1, and VGS2 is the gate-source voltage of the second NMOS tube M2. When the first NMOS tube M1 and the second NMOS tube M2 have the same temperature coefficient, when the temperature changes, the first temperature coefficient related to the resistance is basically offset, and there is only one gate-source voltage temperature coefficient of the first NMOS tube M1, which can avoid the uncertainty of using multiple types of MOSFET temperature compensation in different processes, reduce the deviation of the power-on reset voltage Vpor1 with temperature changes, have good temperature compensation effect, small power-on reset voltage deviation, and low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 The invention discloses an integrated circuit power-on reset circuit;

[0032] Figure 2 It is a circuit diagram of an embodiment of an integrated circuit power-on reset circuit of the present invention. DETAILED DESCRIPTION

[0033] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] Embodiment 1

[0035] like Figure 2 As shown, the integrated circuit power-on reset circuit includes a first resistor R1, a second resistor R2, a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a first PMOS transistor P1 and a second PMOS transistor P2;

[0036] The first resistor R1 and the second resistor R2 are connected in series between the working power supply VDD and the drain terminal of the first NMOS transistor M1;

[0037] The gate end of the first NMOS transistor M1 and the gate end of the third NMOS transistor M3 are both connected to the series connection point of the first resistor R1 and the second resistor R2;

[0038] The source ends of the first NMOS transistor M1, the second NMOS transistor M2 and the third NMOS transistor M3 are all grounded;

[0039] The drain terminal and gate terminal of the first PMOS tube P1 and the gate terminal of the second PMOS tube P2 are connected to the drain terminal of the third NMOS tube M3;

[0040] The source end of the first PMOS tube P1 and the source end of the second PMOS tube P2 are both connected to the working power supply VDD;

[0041] The drain terminal of the second NMOS tube M2 is connected to the drain terminal of the second PMOS tube P2 and serves as a power-on reset voltage output terminal por1.

[0042] The integrated circuit power-on reset circuit of the first embodiment uses the same type of NMOS tubes (M2, M1) for temperature compensation, and the power-on reset voltage VGS1 is the gate-source voltage of the first NMOS tube M1, and VGS2 is the gate-source voltage of the second NMOS tube M2. When the first NMOS tube M1 and the second NMOS tube M2 have the same temperature coefficient, when the temperature changes, the first temperature coefficient related to the resistance is basically offset, and there is only one gate-source voltage temperature coefficient of the first NMOS tube M1, which can avoid the uncertainty of using multiple types of MOSFET temperature compensation in different processes, reduce the deviation of the power-on reset voltage Vpor1 with temperature changes, have good temperature compensation effect, small power-on reset voltage deviation, and low power consumption.

[0043] Embodiment 2

[0044] Based on the integrated circuit power-on reset circuit of implementation 1, the first NMOS transistor M1 is composed of M basic NMOS transistors with the same structure connected in parallel;

[0045] The second NMOS tube M2 is composed of N basic NMOS tubes with the same structure connected in parallel;

[0046] The width-to-length ratio of each basic NMOS tube is the same;

[0047] N is greater than M, and both N and M are positive integers.

[0048] Preferably, N=K*M, where K is an integer greater than 1.

[0049] Preferably, K is 5-10.

[0050] Preferably, the third NMOS transistor M3 is composed of S basic NMOS transistors with the same structure connected in parallel, where S is a positive integer.

[0051] Preferably, S=J*M, where J is an integer greater than 1.

[0052] Preferably, K is 3-15.

[0053] Preferably, the resistance of the first resistor R1 is 0.1MΩ to 100MΩ;

[0054] The resistance of the second resistor R2 is 0.1MΩ to 100MΩ.

[0055] Preferably, the first NMOS transistor M1 , the second NMOS transistor M2 , and the third NMOS transistor M3 are enhancement-type NMOS transistors.

[0056] Preferably, the first PMOS transistor P1 and the second PMOS transistor P2 have the same width-to-length ratio.

[0057] Preferably, the first PMOS transistor P1 and the second PMOS transistor P2 are enhancement type PMOS transistors.

[0058] Embodiment 3

[0059] Based on implementation 1 or 2, the integrated circuit power-on reset circuit further includes a Schmitt trigger and an inverter;

[0060] The Schmitt trigger has an input end connected to the power-on reset voltage output end por1, and an output end connected to the input end of the inverter;

[0061] The output end of the inverter is used to connect to the internal circuit of the integrated circuit.

[0062] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An integrated circuit power-on reset circuit, characterized in that: It includes a first resistor (R1), a second resistor (R2), a first NMOS transistor (M1), a second NMOS transistor (M2), a third NMOS transistor (M3), a first PMOS transistor (P1) and a second PMOS transistor (P2); A first resistor (R1) and a second resistor (R2) are connected in series between a working power supply (VDD) and a drain end of a first NMOS tube (M1); The gate end of the first NMOS tube (M1) and the gate end of the third NMOS tube (M3) are both connected to the series connection point of the first resistor (R1) and the second resistor (R2); The source ends of the first NMOS tube (M1), the second NMOS tube (M2) and the third NMOS tube (M3) are all grounded; The drain terminal and gate terminal of the first PMOS tube (P1) and the gate terminal of the second PMOS tube (P2) are connected to the drain terminal of the third NMOS tube (M3); The source end of the first PMOS tube (P1) and the source end of the second PMOS tube (P2) are both connected to a working power supply (VDD); The drain terminal of the second NMOS tube (M2) is connected to the drain terminal of the second PMOS tube (P2) and serves as a power-on reset voltage output terminal (por1); The gate terminal of the second NMOS transistor (M2) is connected to the drain terminal of the first NMOS transistor (M1).

2. The integrated circuit power-on reset circuit according to claim 1, characterized in that: The first NMOS tube (M1) is composed of M basic NMOS tubes with the same structure connected in parallel; The second NMOS tube (M2) is composed of N basic NMOS tubes with the same structure connected in parallel; The width-to-length ratio of each basic NMOS tube is the same; N is greater than M, and both N and M are positive integers.

3. The integrated circuit power-on reset circuit according to claim 2, characterized in that: N=K*M, K is an integer greater than 1.

4. The integrated circuit power-on reset circuit according to claim 3, characterized in that: K is 5 to 10.

5. The integrated circuit power-on reset circuit according to claim 2, characterized in that: The third NMOS transistor (M3) is composed of S basic NMOS transistors with the same structure connected in parallel, where S is a positive integer.

6. The integrated circuit power-on reset circuit according to claim 5, characterized in that: S=J*M, where J is an integer greater than 1.

7. The integrated circuit power-on reset circuit according to claim 6, characterized in that: J is 3 to 15.

8. The integrated circuit power-on reset circuit according to claim 1, characterized in that: The resistance of the first resistor (R1) is 0.1MΩ to 100MΩ; The resistance of the second resistor (R2) is 0.1MΩ to 100MΩ.

9. The integrated circuit power-on reset circuit according to claim 1, characterized in that: The first NMOS tube (M1), the second NMOS tube (M2), and the third NMOS tube (M3) are enhancement type NMOS; The first PMOS tube (P1) and the second PMOS tube (P2) are enhancement type PMOS; The first PMOS tube (P1) and the second PMOS tube (P2) have the same width-to-length ratio.

10. The integrated circuit power-on reset circuit according to claim 1, characterized in that: The integrated circuit power-on reset circuit also includes a Schmitt trigger and an inverter; The Schmitt trigger has an input end connected to a power-on reset voltage output end (por1), and an output end connected to an input end of an inverter; The output end of the inverter is used to connect to the internal circuit of the integrated circuit.

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