Display with discrete on-board gating circuit

Abstract

Methods, systems, and apparatus for displays with discrete in-panel gating circuits, including computer programs encoded on computer storage media. In some embodiments, a display includes an array of emissive pixels arranged in rows and columns, wherein the array includes a first continuous region having a first pixel density and a second continuous region having a second pixel density less than the first pixel density, and continuous rows of emissive pixels extending between the first continuous region and the second continuous region. The display also includes a gating in-panel (GIP) circuit in the second continuous region, a data line connected to the array of emissive pixels, and a signal line connected to the array of emissive pixels.

Description

Technical Field

[0001] The present description relates to displays having emissive pixels. Background Art

[0002] Traditionally, a display includes an active display area and a bezel containing processing components surrounding the active display area. The larger the bezel, the smaller the active display area and effective size of the display. Accordingly, the bezel limits the user experience while also reducing the aesthetic appeal of the display and / or a device including the display. Summary of the invention

[0003] In some embodiments, a display device includes an active display area having a pixel array. The active display area may have multiple parts, including a first active display area and a second extended active display area. The extended active display area may include multiple embedded pixels and a gate-in-panel (GIP) circuit. Each row of pixels in the pixel array may include two or more GIP circuits within the extended active display area. The GIP circuit may be placed adjacent to one or more pixels in a given pixel row. Unlike the extended active display area, the first active display area does not include any GIP circuits. The first active display area includes multiple embedded pixels of the pixel array.

[0004] In some embodiments, the GIP circuit of a given pixel row in the pixel array provides gate signals to the pixels in the pixel row. These gate signals may include, for example, scan signals and emission control (EM) signals.

[0005] In some implementations, the first active display area has a resolution (eg, pixel density) that is greater than a resolution (eg, pixel density) of the extended active display area.

[0006] In one general aspect, a display panel includes: an array of emissive pixels arranged in a plurality of rows and columns, wherein the array includes a first continuous region having a first pixel density and a second continuous region having a second pixel density less than the first pixel density, and a plurality of continuous rows of emissive pixels extending between the first continuous region and the second continuous region; a plurality of gate-in-panel (GIP) circuits disposed in the second continuous region, wherein each row in the second continuous region includes at least two GIP circuits separated by at least one emissive pixel, and the GIP circuits in each row are configured to provide signals to emissive pixels in corresponding rows in both the first continuous region and the second continuous region of the array; a plurality of data lines connected to the array of emissive pixels, wherein each of the data lines electrically connects a single pixel in each row; and a plurality of signal lines connected to the array of emissive pixels, wherein each of the signal lines electrically connects the emissive pixels in the corresponding row and each of the GIP circuits.

[0007] Implementations may include one or more of the following features. For example, in some implementations, the second contiguous region is located between an edge of the display and the first contiguous region.

[0008] In some embodiments, the pixel density of the second contiguous region is in a range of 25% to 75% of the pixel density of the first contiguous region.

[0009] In some embodiments, a width of the first continuous region in the row direction is greater than a width of the second continuous region in the row direction.

[0010] In some embodiments, the display panel further includes a third continuous region between an edge of the display panel and the second continuous region, the third continuous region having no emitting pixels.

[0011] In some embodiments, a width of the third continuous region in the row direction is smaller than a width of the second continuous region in the row direction.

[0012] In some embodiments, each row in the second continuous region includes alternating emission pixels and GIP circuits.

[0013] In some embodiments, alternating emission pixels and GIP circuits in adjacent rows are arranged in corresponding ones of the columns.

[0014] In some embodiments, alternating emission pixels and GIP circuits in adjacent rows are offset in a checkerboard pattern.

[0015] In some embodiments, alternating emission pixels and GIP circuits in adjacent rows are offset in a diamond pattern.

[0016] In some embodiments, each pixel in a row in the second continuous region is separated by more than one GIP circuit.

[0017] In some embodiments, each GIP circuit in a row in the second contiguous region is separated by more than one emission pixel.

[0018] In some embodiments, each emissive pixel includes a light emitting diode (LED).

[0019] In some embodiments, each LED is an organic LED (OLED).

[0020] In some embodiments, the plurality of signal lines include a plurality of scan lines and a plurality of emission control lines, wherein each scan line and each emission control line is associated with a corresponding row.

[0021] In some embodiments, each emission pixel includes multiple sub-pixels, each row has multiple corresponding emission control lines, one emission control line is used for each sub-pixel in the multiple sub-pixels, and each emission control line electrically connects the corresponding sub-pixel of each emission pixel in the corresponding row.

[0022] In some embodiments, each emissive pixel includes a plurality of sub-pixels, and each sub-pixel is connected to a signal line of the plurality of signal lines.

[0023] In some embodiments, each emission pixel includes at least one thin film transistor (TFT), a data line among a plurality of data lines is connected to the TFT of each emission pixel electrically connected to the data line, and a signal line among a plurality of signal lines is connected to the TFT of each emission pixel electrically connected to the signal line.

[0024] In some embodiments, each of the data lines in the first continuous region electrically connects each of the emission pixels in a corresponding column, and each of the data lines in the second continuous region electrically connects emission pixels in multiple columns.

[0025] In some embodiments, the data lines in the second continuous region are electrically connected to each of the emission pixels in each odd row of the first column and each of the emission pixels in each even row of the second column.

[0026] Advantageous embodiments may include one or more of the following features. For example, by providing the GIP circuit in the active display area rather than in the non-display area (e.g., bezel), the size of the active display area can be increased and the size of the non-display area can be reduced. This expansion of the active display area provides many benefits, including, for example, a smaller bezel, which improves the functionality and aesthetic appeal of the device housing such a display and allows the creation of a smaller device with the same effective display size. Specifically, these techniques can be used to reduce the bezel size of a display device by 50% to more than 75%. Smaller devices with the same effective display size provide their own set of benefits, including, for example, requiring less material, improved ergonomics, improved aesthetic appeal, etc.

[0027] Additionally, by placing an extended display area (e.g., a lower resolution display area) between the first active display area (e.g., a full resolution display area) and a bezel of the display device, the aesthetic appeal of the display device and a device housing such a display is improved when compared to placing the extended display area in a different location because the human eye is less sensitive to non-uniformities at the edges of the display device than to, for example, non-uniformities at the center of the display device.

[0028] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features and advantages of the invention will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is an example schematic block diagram of a display having light-emitting pixels and a GIP circuit.

[0030] Figure 2 is an example diagram showing a display having multiple active display areas.

[0031] Figure 3A-3C is an example diagram of an active display area of ​​a display having a discrete intra-panel strobed active display area.

[0032] The same reference numbers and names in different drawings represent the same elements. DETAILED DESCRIPTION

[0033] The display includes an active display area, an extended active display area, and a thin bezel (e.g., less than or equal to 1 mm). The extended active display area includes a gate-in-panel (GIP) circuit and embedded light-emitting pixels, such as light-emitting diodes (LEDs) (e.g., micro-LEDs) or organic light-emitting diodes (OLEDs) (e.g., micro-LEDs). Providing the GIP circuit in the extended active display area results in the display having a reduced bezel area, an increased total active display area formed by the combination of the active display area and the extended active display area, and a lower resolution in the extended active display area compared to the active display area.

[0034] Figure 1 1 is a schematic block diagram of an example display 100 having light emitting pixels and GIP circuits. The display 100 includes an active display area 110, a controller 102 having a processor 104 and a memory 106, a source or data driver 108, a plurality of GIP circuits 112, and a plurality of light emitting pixels 116. In addition, the display 100 includes a power supply electrically connected to and providing power to the pixels 116. The pixels 116 are arranged in an array having a plurality of rows and a plurality of columns in the active display area 110. In a portion of the active display area 110, the GIP circuits 112 are disposed in the array of pixels 116 such that each row includes at least one of the GIP circuits 112.

[0035] The GIP circuit 112 provides a gate signal to a gate line 114 electrically connected to each of the pixels 116. Through the gate line 114, the pixel 116 receives the gate signal. The gate signal includes a scan signal and an emission control (EM) signal. Accordingly, the GIP circuit 112 acts as a scan driver and an EM driver. Specifically, the GIP circuit of a specific row acts as a scan driver and an EM driver for the pixels in the row. The GIP circuit 112 may include one or more thin film transistors (TFTs).

[0036] Pixel 116 can be a light emitting diode (LED), an organic light emitting diode (OLED), a micro light emitting diode (micro LED), or a micro organic light emitting diode (micro OLED). Each of the pixels 116 can include two or more sub-pixel elements. For example, each of the pixels 116 can include one or more red micro LEDs, one or more green micro LEDs, and one or more blue micro LEDs. Each of the pixels 116 can include one or more TFTs. For example, each of the pixels 116 can include one or more circuit switching TFTs and a driving TFT. Each of the pixels 116 can include other electronic components, such as one or more capacitors, such as storage capacitors.

[0037] like Figure 1As shown in the example of FIG. 1 , the active display area 110 of the display 100 may include hundreds, thousands, or millions of pixels 116. Similarly, the active display area 110 of the display 100 may include hundreds or thousands of GIP circuits 112.

[0038] The controller 102 provides image data to the data driver 108 and can control the operation of the data driver 108. The image data may include timing information such as a clock signal. Alternatively, the controller 102 may provide timing information such as a clock signal to the data driver 108. The controller 102 may include a processor 104 and a memory 106.

[0039] The data driver 108 receives image data from the controller 102. The data driver 108 may provide a clock signal to the GIP circuit 112 via a clock line 118. The data driver 108 may provide image data to the pixels 116 via data lines 120.

[0040] The techniques disclosed in this document can be used to provide a display device having a greater ratio of active display area to bezel or non-display area. By providing a GIP circuit in an extended active display area and embedding the area with light-emitting pixels, the amount of active display area of ​​the display device can be increased and the bezel area of ​​the display can be reduced. Specifically, these techniques can be used to reduce the bezel size of the display device by more than 50% to 75%. Increasing the active display area and / or reducing the size of the bezel area has the additional benefit of improving the user experience and improving the aesthetic appeal of the display and / or a device including the display.

[0041] Increasing the size of the active display area and / or reducing the size of the bezel area also allows for a reduction in device size. For example, a device with a smaller display having a larger ratio of active display area to bezel area (e.g., a device with an extended active display area) can have the same active display area as a larger device with a larger display having a smaller ratio of active display area to bezel area. Thus, a smaller device with an improved display can be selected to replace a larger device. The benefits of a smaller device include, for example, reduced material requirements and costs, reduced weight, better ergonomics, etc.

[0042] like Figure 1As shown, the display 100 can display an image frame by controlling the brightness of pixels 116 in its active display area 110 based at least in part on the received image data. To facilitate displaying the image frame, the controller 102 can provide the image data to the data driver 108, and the timing controller can determine a clock signal based at least in part on the image data and send the clock signal to the GIP gate driver through the clock line 118. As an example, the timing controller can be included in the data driver 108. As another example, the timing controller can be included in the controller 102. In this example, the controller 102 can provide the timing information and the image data to the data driver 108. Alternatively, the timing information can be included as part of the image data.

[0043] The image data received by the data driver 108 from the controller 102 may indicate a desired brightness of one or more display pixels 116 for displaying an image frame. The data driver 108 may analyze the image data to determine a clock signal to provide to the GIP circuit 112. Determining the clock signal may be based at least in part on what display pixel 116 the image data corresponds to. The data driver 108 may send the clock signal to the GIP circuit 112 via a clock line 118. Alternatively, where a timing controller is included as part of the controller 102, the controller 102 may provide the clock signal directly to the GIP circuit 112, rather than through the data driver 108. As will be described below with reference to Figure 3A-3C As described in more detail, the clock line generally extends perpendicularly relative to the gate line 114. Based at least in part on the received clock signal, the GIP circuit 112 can then send a gate activation signal via the gate line 114 to activate a row of pixels within the pixels 116. For example, the GIP circuit 112a can activate the first row of pixels 116a via the gate line 114a. The GIP circuit 112b can activate the second row of pixels 116b via the gate line 114b. The GIP circuit 112c can activate the last row of pixels 116b via the gate line 114c. Each of the gate lines 114 can include a scan line and an EM line. For example, the gate line 114a can include a first scan line and a first EM line, the gate line 114b can include a second scan line and a second EM line, and the gate line 114c can include a last scan line and a last EM line of the display 100.

[0044] When activated, the brightness of one or more pixels 116 can be adjusted by image data received via data line 120. In some embodiments, data driver 108 can generate voltage data by receiving digital image data from controller 102. Data driver 108 can then provide the image data to the activated display pixels 116. Therefore, as shown, each display pixel in pixels 116 can be located at the intersection of a gate line (e.g., a scan line) in gate lines 114 and a data line (e.g., a source line) in data lines 120. Based on the received image data, one or more of display pixels 116 can adjust their brightness using power provided from a power supply.

[0045] Each display pixel in the pixel 116 may include one or more circuit switching thin film transistors (TFTs), a storage capacitor, an LED that may be composed of a plurality of sub-pixel elements, and a driving TFT. Each display pixel may also include additional components, such as one or more additional capacitors, such as a gate-source capacitor between the gate of the driving thin film TFT and the LED. In order to facilitate brightness adjustment, the driving TFT of each of the pixels 116 and the one or more circuit switching TFTs of each of the pixels 116 may each be used as a switching device that is controllably turned on and off by a voltage applied to its corresponding gate. As an example, the gate of the circuit switching TFT of a given pixel in the row of pixels 116a may be electrically coupled to the gate line 114a. The source of the circuit switching TFT of the pixel may be electrically coupled to one of the data lines 120, such as the data line 120a. Accordingly, when the circuit switching TFT of the pixel receives a gate activation signal higher than the threshold voltage from the gate line 114a, the circuit switching TFT may be turned on, thereby activating the pixel and charging its storage capacitor with the image data received at its data line 120a. The gate activation signal may be provided by the GIP circuit 112a.

[0046] Specifically, the gate activation signal may be a scan signal provided by a scan line of the gate line 114a. When the scan signal is provided to the scan line of the gate line 114a, one or more of the pixels in the row of pixels 116a in the display 100 are respectively selected and receive the data signal provided from the data line 120. The pixels in the row of pixels 116a receiving the corresponding data signal generate light with a brightness corresponding to the data signal, thereby displaying an image (e.g., a predetermined image). Here, the emission time of each of the pixels is controlled by the EM signal provided from the EM line of the gate line 114a. The EM signal provided to one or more pixels in the row of pixels 116a may be provided by the GIP circuit 112a. Typically, the EM signal overlaps the scan signal provided to one or two scan lines, and the pixel to which the data signal is provided is set to a non-emission state.

[0047] In some embodiments, the gate of the driving TFT of a given pixel is electrically coupled to a storage capacitor. In this embodiment, the voltage of the storage capacitor can control the operation of the driving TFT. As an example, the driving TFT can operate in the active area to control the amplitude of the power current of the corresponding LED flowing from the power supply through the pixel. When the amplitude of the gate-to-source voltage difference (e.g., the storage capacitor voltage) increases to above its threshold voltage, the driving TFT can increase the amount of the channel that can be used to conduct electrical energy, thereby increasing the power current flowing to the LED. When the amplitude of the gate-to-source voltage difference decreases while still above its threshold voltage, the driving TFT can reduce the amount of the channel that can be used to conduct electrical energy, thereby reducing the power current flowing to the LED. In this way, the display 100 can control the brightness of each of the display pixels 116 to display an image frame.

[0048] As shown, the pixels 116 are arranged in an array having a plurality of rows and a plurality of columns in the active display area 110. Figure 2 In more detail, in a first portion of the active display area 110, GIP circuits 112 are provided in an array of pixels 116 such that each row includes at least one of the GIP circuits 112. The active display area 110 may include a second portion that does not include any GIP circuits. The second portion of the active display area 110 may include only pixels and their corresponding circuits. As described above, the GIP circuits 112 provide gating signals to the pixels 116, including, for example, scan signals and EM signals. The GIP circuits 112 may each include a TFT and may be disposed in a boundary of the active display area 110 between adjacent pixels (e.g., between pixels in the same row of pixels).

[0049] The GIP circuits 112 can receive a clock signal from the data driver 108 via a clock line 118. The GIP circuits 112 can use the clock signal when generating the gating signals that they provide to the pixels 116. In some embodiments, the clock signal may have been provided to the data driver 108 by the controller 102. In some embodiments, the controller 102 can provide the clock signal directly to the GIP circuits 112, rather than through the data driver 108.

[0050] Figure 2 is an example diagram showing a display 200 having multiple active display areas. In some embodiments, the display 200 is Figure 1 A display 100 is shown.

[0051] The display 200 includes a border area 202 as a non-display area and an active display area 210. The border area 202 does not include any emitting pixels. However, the border area 202 can accommodate multiple components of the display 200. For example, power lines or packaging structures can be placed in the border area 202.

[0052] The active display area 210 includes a first active display area 222 and an extended active display area 224. The active display area 210 may include an array of emissive pixels. In some embodiments, the active display area 210 is Figure 1 In some embodiments, the active display area 210 is Figure 3A In some embodiments, the active display area 210 is Figure 3B In some embodiments, the active display area 210 is Figure 3C The active display area 310c is shown.

[0053] In some embodiments, the border region 202 has a width that is less than a width of the active display area. In some embodiments, the border region 202 has a width that is less than 1 mm.

[0054] The active display area 222 corresponds to a portion of the active display area 210 having embedded pixels but no discrete GIP circuits. The extended active display area 224 corresponds to a portion of the active display area 210 having embedded pixels and discrete GIP circuits. The extended active display area 224 is located between the edge of the display 200 and the active display area 222. For example, the extended active display area 224 is located between the border area 202 of the display 200 and the active display area 222. The GIP circuit can be arranged between adjacent pixels in the extended active display area 224. Accordingly, the active display area 222 can have a higher resolution (e.g., pixel density) than the resolution of the extended active display area 224 because they are some of the spaces occupied by the discrete GIP circuits in the extended active display area 224. That is, the active display area 222 can accommodate a higher density of pixels than the extended active display area 224. Specifically, the resolution of the extended active display area 224 can reach 25% to 75% of the maximum possible resolution of the active display area 222. Accordingly, the resolution or pixel density of the extended active display area 224 may be 25%-75% of the resolution or pixel density of the active display area 222. The resolution of the extended active display area 224 may depend on the density of the GIP circuits in the extended active display area 224 and the arrangement of the GIP circuits and pixels in the active display area 224.

[0055] Active display area 222 may have a width greater than the width of extended active display area 224. As shown, active display area 222 does have a width greater than the width of extended active display area 224. The widths of active display areas 222 and 224 may be defined as being in the direction of a row of pixels in the pixel array of active display area 210 (see Figure 3A-3C ). Similarly, the active display area 222 can have an area greater than the area of ​​the extended active display area 224. In addition, the active display area 222 can have a width greater than the width of the border area 202, for example, a width greater than or equal to 1 mm. In addition, the extended active display area 224 can have a width greater than the width of the border area 202, for example, a width greater than or equal to 1 mm.

[0056] Because active display area 222 has a higher pixel density than expanded active display area 224 and / or because active display area 222 occupies a larger area than expanded active display area 224, active display area 222 may include a majority or a majority of the pixels of display 200. A majority of the pixels may be defined as, for example, greater than or equal to 75% of the total pixels, greater than or equal to 80% of the total pixels, greater than or equal to 90% of the total pixels, greater than or equal to 95% of the total pixels, greater than or equal to 97% of the total pixels, greater than or equal to 99% of the total pixels, and so forth.

[0057] Figure 3A-3C is an example diagram of an active display area of ​​a display having a discrete intra-panel strobed active display area.

[0058] Figure 3A An active display area 310a of a display device is shown. The active display area 310a includes an array of pixels 116. The display device may be Figure 1 The display device may be a display 100. Figure 2 2. The display 200 shown in FIG. 2 shows an active display area 310a including an active display area 322a and an extended active display area 324a. The extended active display area 324a includes the embedded pixels in the pixel 316 and all of the discrete GIP circuits 312. The active display area 322a does not include any discrete GIP circuits 312. Instead, the active display area includes only a portion of the pixel 316 and its corresponding circuits.

[0059] Each row in the extended active display area 324a includes at least two GIP circuits of the GIP circuit 312 separated by at least one emission pixel in the pixel 316 (here, each row includes three GIP circuits). The GIP circuits in each row are configured to provide signals to the emission pixels of the corresponding rows in both the extended active display area 324a and the active display area 322a. For example, the GIP circuit 312b corresponding to the pixels in the second row is configured to provide a gating signal to each pixel in the row of pixels 316b through the gating line 314b. Specifically, the GIP circuit 312b can provide a scan signal to each pixel in the row of pixels 316b through the scan line 330b, and provide an EM signal thereto through the EM line 332b.

[0060] like Figure 3A As shown, the extended active display area 324a is arranged in a checkerboard pattern so that the pixels and GIP circuits of a given row are offset by one relative to the pixels and GIP circuits of subsequent rows. As shown, the first row of the active display area 310a includes rows of pixels 316a and GIP circuits 312a. As an example, the extended active display area 324a is arranged relative to the first row so that the first row starts with a pixel, followed by the first GIP circuit, followed by the second pixel, followed by the second GIP circuit, followed by the third pixel, followed by the third GIP circuit, etc. The second row of the active display area 310a includes rows of pixels 316b and GIP circuits 312b. The pixels and GIP circuits of the second row in the extended active display area 324a are offset by one relative to the pixels and GIP circuits of the (multiple) previous rows (e.g., the first row) and (multiple) subsequent rows in the extended active display area 324a, thereby forming a checkerboard pattern that continues in the rest of the extended active display area 324a. For example, the extended active display area 324a is arranged relative to the second row so that the second row starts with one GIP circuit, followed by a pixel, followed by a second GIP circuit, followed by a second pixel, followed by a third GIP circuit, followed by a third pixel, and so on.

[0061] In this checkerboard arrangement, each of the data lines 320 in the active display area 322a (e.g., data lines 320e-320i) electrically connects each of the emission pixels in the corresponding column. For example, data line 320e electrically connects each of the emission pixels in the seventh column of the pixel array of the active display area 310a.

[0062] In this checkerboard arrangement, each of the data lines 320 in the extended active display area 324a (e.g., data lines 320a-320d) electrically connects each of the emission pixels in a plurality of corresponding columns. For example, data line 320a electrically connects each of the emission pixels in the first column and the second column of the pixel array of the active display area 310a.

[0063] Each of the pixels 316 is electrically coupled to one of the data lines 320. Although the data lines 320 are generally vertical, they can be electrically coupled to pixels in multiple columns of the pixel array of the active display area 310a, such as when the extended active display area 324a is arranged in a checkerboard pattern as shown. The pixels 316 are also electrically coupled to the gate lines 314. The gate lines 314 each include a corresponding scan line in the scan lines 330 and a corresponding EM line in the EM lines 332. Accordingly, each of the pixels 316 is electrically coupled to a scan line in the scan lines 330 and an EM line in the EM lines 332. For example, each pixel in the row of pixels 316a is electrically coupled to the scan line 330a and the EM line 332a.

[0064] Each of the GIP circuits 312 is electrically coupled to a clock line in the clock lines 118. The GIP circuits 312 are also electrically coupled to the gate line 314. Accordingly, each of the GIP circuits 312 is electrically coupled to a scan line in the scan lines 330 and an EM line in the EM lines 332, wherein the GIP circuits 312 can provide signals to the pixels 316 via the scan lines in the scan lines 330 and the EM lines in the EM lines 332.

[0065] Figure 3B An active display area 310b of a display device is shown. The active display area 310b includes an array of pixels 116. The display device may be Figure 1 The display device may be a display 100. Figure 2 2. The display 200 shown in FIG. 2 shows an active display area 310b including an active display area 322b and an extended active display area 324b. The extended active display area 324b includes the embedded pixels of the pixel 316 and all of the discrete GIP circuits 312. The active display area 322b does not include any discrete GIP circuits 312. Instead, the active display area includes only a portion of the pixel 316 and its corresponding circuits.

[0066] Each row in the extended active display area 324b includes at least two GIP circuits (here, each row includes three GIP circuits) of the GIP circuit separated by at least one emission pixel in the pixel 316. The GIP circuits in each row are configured to provide signals to the emission pixels of the corresponding rows in both the extended active display area 324b and the active display area 322b. For example, the GIP circuit 312b corresponding to the pixels in the second row is configured to provide a gating signal to each pixel in the row of pixels 316b through the gating line 314b. Specifically, the GIP circuit 312b can provide a scan signal to each pixel in the row of pixels 316b through the scan line 330b, and provide an EM signal thereto through the EM line 332b.

[0067] like Figure 3B As shown, the extended active display area 324b is arranged in a striped pattern so that a given column in the extended active display area 324b contains either pixels or GIP circuits, but does not contain both pixels and GIP circuits. As shown, the first row of the active display area 310a includes rows of pixels 316a and GIP circuits 312a. As an example, the extended active display area 324b is arranged relative to the first row so that the first row starts with a pixel, followed by a first GIP circuit, followed by a second pixel, followed by a second GIP circuit, followed by a third pixel, followed by a third GIP circuit, and so on. The second row of the active display area 310b includes rows of pixels 316b and GIP circuits 312b. The pixels and GIP circuits of the second row in the extended active display area 324b are not offset relative to the pixels and GIP circuits of the (multiple) previous rows (e.g., the first row) and (multiple) subsequent rows in the extended active display area 324b, thereby forming a striped pattern that continues in the rest of the extended active display area 324b. For example, the extended active display area 324b is arranged relative to the second row so that the second row starts with one pixel, followed by one GIP circuit, followed by a second pixel, followed by a second GIP circuit, followed by a third pixel, followed by a third GIP circuit, and so on.

[0068] In this striped arrangement, each of the data lines 320 in the active display area 322b (e.g., data lines 320e-320i) is electrically connected to each of the emission pixels in the corresponding column. For example, data line 320e is electrically connected to each of the emission pixels in the seventh column of the pixel array of the active display area 310b (where each column features a pixel or GIP circuit).

[0069] In this striped arrangement, each data line (e.g., data lines 320a-320d) of data lines 320 in extended active display area 324b is also electrically connected to each emission pixel in the corresponding column. For example, data line 320a is electrically connected to each emission pixel in the first column of the pixel array of active display area 310b.

[0070] Each of the pixels 316 is electrically coupled to one of the data lines 320. In the case where the extended active display area 324b is arranged in a stripe pattern as shown, the data lines 320 are vertical and electrically coupled to the pixels in a single column. The pixels 316 are also electrically coupled to the gate lines 314. The gate lines 314 each include a corresponding scan line in the scan lines 330 and a corresponding EM line in the EM lines 332. Accordingly, each of the pixels 316 is electrically coupled to a scan line in the scan lines 330 and an EM line in the EM lines 332. For example, each pixel in the row of pixels 316a is electrically coupled to the scan line 330a and the EM line 332a.

[0071] Each of the GIP circuits 312 is electrically coupled to a clock line in the clock lines 118. The GIP circuits 312 are also electrically coupled to the gate line 314. Accordingly, each of the GIP circuits 312 is electrically coupled to a scan line in the scan lines 330 and an EM line in the EM lines 332, wherein the GIP circuits 312 can provide signals to the pixels 316 via the scan lines in the scan lines 330 and the EM lines in the EM lines 332.

[0072] Figure 3C An active display area 310c of a display device is shown. The active display area 310c includes an array of pixels 116. The display device may be Figure 1 The display device may be a display 100. Figure 2 2. The display 200 shown in FIG. 2 shows an active display area 310c including an active display area 322c and an extended active display area 324c. The extended active display area 324c includes the embedded pixels in the pixel 316 and all of the discrete GIP circuits 312. The active display area 322c does not include any discrete GIP circuits 312. Instead, the active display area includes only a portion of the pixel 316 and its corresponding circuits.

[0073] Each row in the extended active display area 324c includes at least two GIP circuits in the GIP circuit 312 separated by at least one emission pixel in the pixel 316. The GIP circuit in each row is configured to provide signals to the emission pixels of the corresponding rows in both the extended active display area 324c and the active display area 322c. For example, the GIP circuit 312b corresponding to the pixels in the second row is configured to provide a gating signal to each pixel in the row of pixels 316b through the gating line 314b. Specifically, the GIP circuit 312b can provide a scan signal to each pixel in the row of pixels 316b through the scan line 330b, and provide an EM signal thereto through the EM line 332b.

[0074] like Figure 3CAs shown, the extended active display area 324c is arranged in a diamond pattern so that in the extended active display area 324c, one or more pixels of a given row overlap with one or more pixels of a subsequent row, and one or more GIP circuits of a given row overlap with one or more pixels of a subsequent row. As shown, the first row of the active display area 310a includes rows of pixels 316a and GIP circuits 312a. As an example, the extended active display area 324c is arranged relative to the first row so that the first row starts with a pixel, followed by a first GIP circuit, followed by a second pixel, followed by a third pixel, followed by a second GIP circuit, followed by a fourth pixel, and so on. The second row of the active display area 310c includes rows of pixels 316b and GIP circuits 312b. The pixels and GIP circuits of the second row in the extended active display area 324 c follow the arrangement described above with respect to the pixels and GIP circuits of the previous row(s) (e.g., the first row) and the subsequent row(s) in the extended active display area 324 c, thereby forming a diamond pattern that continues in the remainder of the extended active display area 324 c. For example, the extended active display area 324 c is arranged relative to the second row such that the second row begins with one pixel, followed by a second pixel, followed by one GIP circuit, followed by a third pixel, followed by a fourth pixel, followed by a second GIP circuit, and so on.

[0075] In this diamond arrangement, each of the data lines 320 in the active display area 322c (e.g., data lines 320f-320j) electrically connects each of the emission pixels in the corresponding column. For example, data line 320f electrically connects each of the emission pixels in the seventh column of the pixel array of the active display area 310c.

[0076] In this diamond arrangement, each of the data lines 320 in the extended active display area 324c (e.g., data lines 320a-320e) electrically connects at least some of the emission pixels in a plurality of corresponding columns. For example, data line 320a electrically connects each emission pixel in the first column of the pixel array of the active display area 310c, and electrically connects some of the emission pixels in the second column of the pixel array of the active display area 310c.

[0077] Each of the pixels 316 is electrically coupled to one of the data lines 320. Although the data lines 320 are generally vertical, they can be electrically coupled to pixels in multiple columns of the pixel array of the active display area 310c, such as when the extended active display area 324c is arranged in a diamond pattern as shown. The pixels 316 are also electrically coupled to the gate lines 314. The gate lines 314 each include a corresponding scan line in the scan lines 330 and a corresponding EM line in the EM lines 332. Accordingly, each of the pixels 316 is electrically coupled to a scan line in the scan lines 330 and an EM line in the EM lines 332. For example, each pixel in the row of pixels 316a is electrically coupled to the scan line 330a and the EM line 332a.

[0078] Each of the GIP circuits 312 is electrically coupled to a clock line in the clock lines 118. The GIP circuits 312 are also electrically coupled to the gate line 314. Accordingly, each of the GIP circuits 312 is electrically coupled to a scan line in the scan lines 330 and an EM line in the EM lines 332, and the GIP circuits 312 can provide signals to the pixels 316 through the scan lines in the scan lines 330 and the EM lines in the EM lines 332.

[0079] In some embodiments, Figure 3A-3C Each of the pixels 316 shown in includes a plurality of sub-pixel elements. In these embodiments, each of the gate lines 114 of a given row may include a plurality of EM lines. Each of the plurality of EM lines is capable of sending a respective EM signal to a particular sub-pixel element of each pixel in a row of pixels of the pixel array. For example, the gate line 114a may include three EM lines corresponding to the first row of pixels 116a. The first EM line of the first row may be electrically coupled to and / or capable of transmitting an EM signal to a red sub-pixel element of each pixel in the row of pixels 116a. The second EM line of the first row may be electrically coupled to and / or capable of transmitting an EM signal to a green sub-pixel element of each pixel in the row of pixels 116a. The third EM line of the first row may be electrically coupled to and / or capable of transmitting an EM signal to a blue sub-pixel element of each pixel in the row of pixels 116a.

[0080] Many embodiments have been described. However, it should be understood that various modifications may be made without departing from the spirit and scope of the present disclosure. For example, the various forms of the processes shown above may be used with steps reordered, added, or removed.

[0081] All functional operations described in the embodiments of the present invention and this specification may be implemented in digital electronic circuits, or in computer software, firmware or hardware (including the structures disclosed in this specification and their structural equivalents), or in a combination of one or more of them. Embodiments of the present invention may be implemented as one or more computer program products, for example, one or more modules of computer program instructions encoded on a computer-readable medium, for execution by a data processing device or for controlling the operation of the data processing device. The computer-readable medium may be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition that implements a machine-readable propagation signal, or a combination of one or more of them. The term "data processing device" includes all devices, equipment and machines for processing data, including, for example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, the device may also include code that creates an execution environment for the computer program in question, for example, code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them. A propagation signal is an artificially generated signal (e.g., a machine-generated electrical, optical or electromagnetic signal) that is generated to encode information for transmission to a suitable receiver device.

[0082] A computer program (also referred to as a program, software, software application, script, or code) may be written in any form of programming language, including compiled or interpreted languages, and it may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple collaborative files (e.g., files that store one or more modules, subroutines, or portions of code). A computer program may be deployed to execute on one computer, or on multiple computers located at one site or distributed across multiple sites and interconnected by a communications network.

[0083] The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. These processes and logic flows can also be performed by special purpose logic circuits, and the apparatus can also be implemented as special purpose logic circuits, such as FPGAs (field programmable gate arrays) or ASICs (application specific integrated circuits).

[0084] For example, processors suitable for executing computer programs include general and special purpose microprocessors and any one or more processors of any type of digital computer. Typically, the processor will receive instructions and data from a read-only memory or a random access memory or both. The basic elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, the computer will also include or be operatively coupled to one or more mass storage devices (e.g., magnetic disks, magneto-optical disks, or optical disks) for storing data to receive data from it, or to transfer data to it, or both. However, the computer does not need to have such a device. In addition, the computer can be embedded in another device, such as a tablet computer, a mobile phone, a personal digital assistant (PDA), a mobile audio player, a global positioning system (GPS) receiver, etc. Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example: semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD ROM and DVD-ROM disks. The processor and memory can be supplemented or incorporated in them by dedicated logic circuits.

[0085] To provide interaction with a user, embodiments of the present invention may be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback; and input from the user may be received in any form, including sound, voice, or tactile input.

[0086] Embodiments of the present invention may be implemented in a computing system that includes a back-end component (e.g., as a data server), or includes a middleware component (e.g., an application server), or includes a front-end component (e.g., a client computer having a graphical user interface or a web browser through which a user can interact with an embodiment of the present invention), or any combination of one or more such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include local area networks ("LANs") and wide area networks ("WANs"), such as the Internet.

[0087] A computing system may include clients and servers. Clients and servers are generally remote from each other and typically interact through a communication network. The relationship of client and server arises through computer programs running on the respective computers and having a client-server relationship to each other.

[0088] Although this specification includes many details, these details should not be interpreted as limitations on the scope of the present invention or the content that may be claimed, but rather as descriptions of the features of a specific embodiment of the present invention. Certain features described in the context of separate embodiments in this specification may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, and even initially claimed as such, in some cases, one or more features from the claimed combination may be deleted from the combination, and the claimed combination may point to a variant of a sub-combination or a sub-combination.

[0089] Similarly, although operations are described in a particular order in the accompanying drawings, this should not be understood as requiring that the operations be performed in the particular order shown or in a sequential order, or that all of the operations shown be performed to obtain the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated into a single software product or packaged into multiple software products.

[0090] In each instance where an HTML file is mentioned, other file types or formats may be substituted. For example, an HTML file may be replaced by XML, JSON, plain text, or other types of files. Additionally, when a table or hash table is mentioned, other data structures (such as a spreadsheet, a relational database, or a structured file) may be used.

[0091] Certain embodiments of the present invention have been described. Other embodiments are within the scope of the following claims. For example, the steps recited in the claims can be performed in a different order and still achieve desirable results.

Claims

1. A display panel, comprising: an array of emissive pixels arranged in a plurality of rows and columns, wherein the array comprises a first contiguous region having a first pixel density and a second contiguous region having a second pixel density less than the first pixel density, and a plurality of contiguous rows of emissive pixels extending between the first contiguous region and the second contiguous region; a plurality of intra-plane gated GIP circuits disposed in the second continuous region, wherein each row in the second continuous region includes at least two GIP circuits separated by at least one emission pixel, and the GIP circuits in each row are configured to provide signals to emission pixels in corresponding rows in both the first continuous region and the second continuous region of the array; a plurality of data lines connected to the array of emissive pixels, wherein each of the data lines electrically connects a single pixel in each row; and A plurality of signal lines are connected to the array of emission pixels, wherein each of the signal lines electrically connects the emission pixels in a corresponding row and each of the GIP circuits.

2. The display panel according to claim 1, wherein: The second continuous area is located between an edge of the display and the first continuous area.

3. The display panel according to claim 1, wherein: The pixel density of the second continuous area is in the range of 25% to 75% of the pixel density of the first continuous area.

4. The display panel according to claim 1, wherein: A width of the first continuous region in the direction of the row is greater than a width of the second continuous region in the direction of the row. 5 . The display panel of claim 1 , further comprising a third continuous area between an edge of the display panel and the second continuous area, the third continuous area having no emitting pixels.

6. The display panel according to claim 5, wherein: A width of the third continuous region in the direction of the row is smaller than a width of the second continuous region in the direction of the row.

7. The display panel according to claim 1, wherein: Each row in the second continuous region includes alternating emission pixels and GIP circuits.

8. The display panel according to claim 7, wherein: Alternating emission pixels and GIP circuits in adjacent rows are arranged in corresponding ones of the columns.

9. The display panel according to claim 8, wherein: Alternating emission pixels and GIP circuits in adjacent rows are offset in a checkerboard pattern.

10. The display panel according to claim 8, wherein: Alternating emission pixels and GIP circuits in adjacent rows are offset in a diamond pattern.

11. The display panel according to claim 1, wherein: Each pixel in a row in the second continuous region is separated by more than one GIP circuit.

12. The display panel according to claim 1, wherein: Each GIP circuit in a row in the second continuous region is separated by more than one emission pixel.

13. The display panel according to claim 1, wherein: Each emitting pixel comprises a light emitting diode LED.

14. The display panel according to claim 13, wherein: Each LED is an organic LED OLED.

15. The display panel according to claim 1, wherein: The plurality of signal lines include a plurality of scan lines and a plurality of emission control lines, wherein each scan line and each emission control line is associated with a corresponding row.

16. The display panel according to claim 15, wherein: Each emissive pixel includes multiple sub-pixels. Each row has a plurality of corresponding emission control lines, one emission control line for each of the plurality of sub-pixels, and Each of the emission control lines electrically connects a corresponding sub-pixel of each of the emission pixels in a corresponding row.

17. The display panel according to claim 1, wherein: Each emissive pixel includes a plurality of sub-pixels, and Each of the sub-pixels is connected to a signal line of a plurality of signal lines.

18. The display panel according to claim 1, wherein: Each emission pixel includes at least one thin film transistor TFT, A data line of the plurality of data lines is connected to a TFT of each emission pixel electrically connected to the data line, and A signal line among the plurality of signal lines is connected to a TFT of each emission pixel electrically connected to the signal line.

19. The display panel according to claim 1, wherein: Each of the data lines in the first continuous region is electrically connected to each of the emission pixels in the corresponding column, and Each of the data lines in the second continuous region electrically connects emission pixels in a plurality of columns.

20. The display panel according to claim 1, wherein: The data line in the second continuous area is electrically connected to each of the emission pixels in each odd-numbered row of the first column and each of the emission pixels in each even-numbered row of the second column.

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