Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device manufacturing method, comprising: providing a substrate; forming a first shallow trench isolation structure in a first region and at least two second shallow trench isolation structures in a second region in the substrate; forming a second mask layer; etching the second mask layer and the at least two second shallow trench isolation structures in the second region in sequence to form a semiconductor protrusion between two adjacent second shallow trench isolation structures.

Description

[0001] This application claims priority to international application No. PCT / CN2021 / 093323 filed on May 12, 2021, and priority to international application No. PCT / CN2021 / 103677 filed on June 30, 2021, both of which are named “MEMORY PERIPHERAL CIRCUIT HAVING THREE-DIMENSIONAL TRANSISTORS AND METHODFOR FORMING THE SAME,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0003] The semiconductor devices in existing integrated circuits typically include a high-voltage device region and a low-voltage device region, both of which utilize planar transistors. With the rapid development of CMOS (Complementary Metal Oxide Semiconductor) technology, the demand for integrated circuit integration and performance is increasing. Consequently, the feature size of semiconductor devices needs to be further reduced. When the feature size is scaled down to 22nm, the planar transistor structure will experience severe short-channel effects, severely impacting device performance.

[0004] Technical Solutions

[0005] The present invention provides a method for manufacturing a semiconductor device, comprising:

[0006] A substrate is provided, the substrate comprising a first region and a second region; a first shallow trench isolation structure located in the first region and at least two second shallow trench isolation structures located in the second region are formed in the substrate; a second mask layer is formed on the substrate, the first shallow trench isolation structure and the at least two second shallow trench isolation structures; the second mask layer located in the second region and the at least two second shallow trench isolation structures are sequentially etched to form a semiconductor protrusion between two adjacent second shallow trench isolation structures.

[0007] Preferably, a first mask layer is formed on the substrate; the sequential etching of the second mask layer located in the second area and the at least two second shallow trench isolation structures includes: forming a second photoresist layer on the second mask layer; sequentially etching the second photoresist layer and the second mask layer located in the second area until the first mask layer and the at least two second shallow trench isolation structures located in the second area are exposed; removing the second photoresist layer located in the first area; and etching the at least two second shallow trench isolation structures using the exposed first mask layer and the remaining second mask layer located in the second area as masks.

[0008] Preferably, the forming of the second photoresist layer on the second mask layer includes: forming a protective layer on the second mask layer; and forming the second photoresist layer on the protective layer.

[0009] Preferably, a first device oxide layer located in the first region and a second device oxide layer located in the second region are further formed between the substrate and the first mask layer; after etching at least two second shallow trench isolation structures, the method further includes: removing the first mask layer and the remaining second mask layer;

[0010] A supplementary oxide layer is formed on both sides of the semiconductor protrusion to extend the second device oxide layer.

[0011] Preferably, the second mask layer is silicon nitride or polysilicon; when the second mask layer is polysilicon, the removal of the first mask layer and the remaining second mask layer includes: carbon or germanium doping on both sides of the semiconductor protrusion; and removing the remaining second mask layer and the first mask layer in sequence.

[0012] Preferably, the carbon doping on both sides of the semiconductor protrusion includes: forming a third mask layer on the remaining second mask layer; using the third mask layer and the first mask layer located in the second area as masks, carbon or germanium doping on both sides of the semiconductor protrusion.

[0013] Preferably, a supplementary oxide layer is formed on both sides of the semiconductor protrusion to extend

[0014] The second

[0015] After forming the device oxide layer, the method further includes: forming a first gate layer on the first device oxide layer; and forming a second gate layer on the extended second device oxide layer.

[0016] Preferably, the thickness of the first device oxide layer in the first direction is greater than the thickness of the second device oxide layer in the first direction.

[0017] Preferably, a first shallow trench isolation structure located in the first region and at least two second shallow trench isolation structures located in the second region are formed in the substrate, including: forming an isolation trench in the substrate, the isolation trench including a first sub-isolation trench located in the first region and at least two second sub-isolation trenches located in the second region; filling the isolation trench with isolation material to form the first shallow trench isolation structure and the at least two second shallow trench isolation structures in the first region and the second region, respectively.

[0018] Preferably, filling the isolation trench with the isolation material includes: depositing the isolation material in the isolation trench and on the first mask layer to fill the isolation trench; and planarizing the isolation material to make the isolation material in the isolation trench flush with the first mask layer.

[0019] Preferably, the first mask layer is made of silicon nitride.

[0020] Preferably, the second mask layer is silicon nitride or polysilicon; when the second mask layer is polysilicon, the second mask layer is formed on the substrate, the first shallow trench isolation structure and at least two of the second shallow trench isolation structures, including: forming a buffer layer on the first mask layer, the first shallow trench isolation structure and the second shallow trench isolation structure; forming the second mask layer on the buffer layer.

[0021] Preferably, the thickness of the buffer layer ranges from 8 nm to 9 nm.

[0022] Preferably, the first region is used to form a planar transistor, and the second region is used to form a fin transistor.

[0023] Preferably, the first shallow trench isolation structure is higher than the substrate, and the substrate is higher than the trench isolation structure.

[0024] In a second aspect, the present invention also provides a semiconductor device comprising: a substrate comprising a first region and a second region; a first shallow trench isolation structure and at least two second shallow trench isolation structures respectively located in the first region and the second region, with a semiconductor protrusion between two adjacent second shallow trench isolation structures; a first device oxide layer located in the first region, and a second device oxide layer located in the second region and covering the semiconductor protrusion; a first gate layer located on the first device oxide layer, and a second gate layer located on the second device oxide layer.

[0025] Preferably, the first region is used to form a planar transistor, and the second region is used to form a fin transistor.

[0026] Preferably, the first shallow trench isolation structure is higher than the substrate, and the substrate is higher than the second shallow trench isolation structure.

[0027] Preferably, the thickness of the first device oxide layer in the first direction is greater than the thickness of the second device oxide layer in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0029] Figure 2 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0030] Figure 3 This is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0031] Figure 4A to Figure 4P Schematic diagram of the cross-sectional structure of the semiconductor device at various stages according to an embodiment of the present invention;

[0032] Figure 5A-5B It is a schematic cross-sectional structure diagram of a semiconductor device when forming a buffer layer when the second mask layer is polysilicon, provided by an embodiment of the present invention.

[0033] Figure 6A-6B An embodiment of the present invention provides a schematic diagram of the cross-sectional structure of a semiconductor device in a doping stage when the second mask layer is polysilicon.

[0034] Modes for Carrying Out the Invention

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0036] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0037] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections, or mutual communication; direct connections or indirect connections through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0038] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0039] The disclosure below provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0040] The semiconductor devices of existing integrated circuits usually include a high-voltage device area and a low-voltage device area, both of which use planar transistors. With the rapid development of CMOS (Complementary Metal Oxide Semiconductor) technology, people have increasingly higher requirements for the integration and performance of integrated circuits. Correspondingly, the characteristic size of semiconductor devices is required to be further reduced. When the characteristic size is proportionally reduced to 22nm, the planar transistor structure will have a serious short channel effect, which seriously affects the device performance. In order to solve this problem, the existing low-voltage device area generally uses FinFET (Fin Field-Effect Transistor), while the process of forming FinFET that meets its performance requirements in the high-voltage device area becomes very difficult, so that the high-voltage device area still uses planar transistors.

[0041] In existing semiconductor devices, the shallow trench isolation structures for the high-voltage device region and the low-voltage device region are formed simultaneously, resulting in the same shallow trench isolation structure for both regions. However, when the low-voltage device region uses FinFETs while the high-voltage device region still uses planar transistors, the existing formation methods cannot meet the actual needs because the requirements for the shallow trench isolation structure differ between planar transistors and FinFETs.

[0042] The present invention provides a semiconductor structure and a manufacturing method thereof, which effectively solves the problem that the existing shallow trench isolation structure cannot simultaneously meet the structural requirements of different regions in a semiconductor device.

[0043] See also Figure 1 , Figure 1 1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. The specific process of the manufacturing method may be as follows:

[0044] Step S101: providing a substrate, wherein the substrate includes a first region and a second region.

[0045] The cross-sectional structure diagram after step S101 is completed is as follows: Figure 4A shown.

[0046] Specifically, the material of the substrate 10 can be a semiconductor material such as silicon, germanium or silicon-on-insulator (SOI). In this embodiment, the substrate 10 may include a first region (region A) and a second region (region B), wherein region A includes a high-voltage device region, which can be used to form a planar transistor in the embodiment of the present invention; region B includes a low-voltage device region (the operating voltage of the devices in the low-voltage device region is lower than the operating voltage of the devices in the high-voltage device region), further, the low-voltage device region may also include a first low-voltage region b1 and a second low-voltage region b2, wherein the operating voltages of the devices (such as transistors or CMOS tubes) in the high-voltage device region, the first low-voltage region and the second low-voltage region may be in descending order. In this embodiment, in order to simplify the diagram, Figure 4A In the following figures, area B is used to summarize b1 and b2; specifically, area B can be a low-voltage device area, or it can include both b1 and b2. Figures 4B-4O The following is an example of an area B containing a low-voltage device area. The area B is used to form a fin transistor (FinFET) in an embodiment of the present invention. In the FinFET, the gate can surround the channel from three sides, increasing the control area of ​​the gate on the channel, greatly enhancing the gate control capability, thereby effectively suppressing the short channel effect and reducing the subthreshold leakage current. The performance of different device areas can be adjusted by changing the channel width of one or more transistors inside the device, and the channel width of the FinFET is proportional to the height of the fin structure. Since the high-voltage device area requires a higher driving voltage, the height of the corresponding FinFET "Fin" (fin structure) is also higher. It is difficult to form a gate structure surrounded on three sides on a higher Fin, so area A still uses a planar transistor.

[0047] Among them, such as Figure 4B As shown, a first device oxide layer 11A located in the first region and a second device oxide layer 11B located in the second region are also formed on the substrate 10. The thickness H1 of the first device oxide layer 11A in the first direction (y direction in the figure) is greater than the thickness H2 of the second device oxide layer 11B in the first direction.

[0048] Specifically, in this embodiment, the formation process of the first device oxide layer 11A and the second device oxide layer 11B includes a thermal oxidation process (Thermal Oxidation), a soft plasma oxidation process (Soft Plasma Oxidation) or a UV photo assistant oxidation process (UV Photo Assistant Oxidation). In this embodiment, when the substrate 10 is a silicon or germanium substrate, the second device oxide layer 11B can be formed simultaneously with the formation of the first device oxide layer 11A. In this case, the first device oxide layer 11A and the second device oxide layer 11B are both composed of silicon oxide or germanium oxide. The composition of the first device oxide layer 11A and the second device oxide layer 11B can also differ depending on whether the A region or the B region of the substrate 10 is pre-doped. For example, the second device oxide layer 11B can be silicon oxide without chlorine, while the first device oxide layer 11A is silicon oxide containing chlorine. The first device oxide layer 11A and the second device oxide layer 11B serve as gate oxide layers for the high-voltage device and the low-voltage device, respectively. Due to different breakdown voltage requirements for the low-voltage device and the high-voltage device, to avoid excessive leakage current in the high-voltage device region, the thickness H1 of the first device oxide layer 11A in the first direction (the y-direction in the figure), i.e., in the thickness direction of the substrate 10, is greater than the thickness H2 of the second device oxide layer 11B in the first direction. To achieve a corresponding thickness relationship, the first device oxide layer 11A and the second device oxide layer 11B can be formed in separate steps or simultaneously. When simultaneous formation is adopted, chloride ions can be pre-doped in region A. Since region A is doped with chloride ions, the oxidation rate of the substrate 10 in region A is accelerated. Therefore, in the same amount of time, the first device oxide layer 11A is formed thicker than the second device oxide layer 11B. When step-by-step formation is adopted, the first step is to form a device oxide layer of the same thickness in the first region and the second region under the same time and process conditions; the second step is to selectively etch the device oxide layer in the second region so that the thickness of the second device oxide layer located in the second region is less than the thickness of the first device oxide layer located in the first region.

[0049] Among them, such as Figure 4C As shown, a first mask layer 12 is formed on the substrate 10 and is located on the first device oxide layer 11A and the second device oxide layer 11B.

[0050] Specifically, the first mask layer 12 is a hard mask layer, wherein the function of the hard mask layer is to transfer a specific pattern on the photoresist to the substrate, that is, first transfer the specific pattern from the photoresist to the hard mask layer. Since the hard mask layer has the characteristics of hardness and density, it has good conformal ability. When the pattern is finally etched and transferred to the substrate 10 through the hard mask layer, a relatively complete pattern can be obtained. The specific material of the first mask layer 12 can be silicon nitride or titanium nitride. In addition, it should be noted that the first device oxide layer 11A and the second device oxide layer 11B are conducive to reducing the stress of the silicon nitride layer (that is, the first mask layer 12) on the substrate 10. In this example, the silicon nitride layer can be formed by the LPCVD process.

[0051] Step S102: forming a first shallow trench isolation structure located in the first region and at least two second shallow trench isolation structures located in the second region in the substrate.

[0052] For details, please refer to Figure 2 , Figure 2 FIG. 1 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention. Step S102 may specifically include:

[0053] Step S1021: forming an isolation trench in the substrate, the isolation trench comprising a first sub-isolation trench located in the first region and at least two second sub-isolation trenches located in the second region;

[0054] The cross-sectional structure diagram after step S1021 is completed is as follows: Figure 4D shown.

[0055] The function of the isolation trench 101 is to be filled with dielectric material to prevent electrical coupling between transistor structures. A first photoresist layer (not shown) can be coated on the surface of the first mask layer 12 and subjected to photolithography processes such as exposure and development to form a photoresist pattern with an opening defining the position of the isolation trench 101. Then, the first mask layer 12, the first device oxide layer 11A, and the second device oxide layer 11B are etched through the opening of the first photoresist layer using reactive ion etching or plasma etching to expose the surface of the substrate 10. Then, a fluorine-containing etching gas is used to etch the substrate 10 using the first mask layer 12 as a mask, thereby forming the isolation trench 101 in the substrate 10. The isolation trench 101 includes a plurality of layers. It includes a first sub-isolation trench 101A and at least two second sub-isolation trenches 101B, the first sub-isolation trench 101A is located in area A, and the second sub-isolation trench 101B is located in area B. The first sub-isolation trench 101A and the at least two second sub-isolation trenches 101B can be formed in the same etching process, that is, the two can have the same height in the first direction; the first sub-isolation trench 101A and the second sub-isolation trench 101B can also be formed in different etching processes, that is, the two can have different heights in the first direction, and the corresponding heights can be set according to different degrees of electrical insulation isolation requirements.

[0056] S1022: Filling the isolation trench with an isolation material to form the first shallow trench isolation structure and the at least two second shallow trench isolation structures in the first region and the second region, respectively.

[0057] The step S1022 may specifically include: depositing the isolation material in the isolation trench and on the first mask layer to fill the isolation trench; and planarizing the isolation material to make the isolation material in the isolation trench flush with the first mask layer.

[0058] Specifically, such as Figure 4E The isolation material 13 may be deposited in the isolation trench 101 and on the first mask layer 12 by a high-density plasma chemical vapor deposition process to fill the isolation trench 101. A planarization process, such as a chemical mechanical polishing process, is then used to planarize the isolation material 13 so that the isolation material 13 in the isolation trench 101 is flush with the first mask layer 12. At this point, the first shallow trench isolation structure 13A and the second shallow trench isolation structure 13B are flush. The first mask layer 12 also serves as a stop layer in the planarization process. The cross-sectional structure diagram after step S1022 is completed is shown in FIG. Figure 4FIn this embodiment, the first shallow trench isolation structure 13A and the second shallow trench isolation structure 13B can be formed in the same process step or in different process steps. Since the heights of the first sub-isolation trench 101A and the second sub-isolation trench 101B can be the same or different, the first shallow trench isolation structure 13A and the second shallow trench isolation structure 13B can be of the same height or different heights. The corresponding heights can be set according to different degrees of electrical insulation isolation requirements.

[0059] Step S103: forming a second mask layer on the substrate, the first shallow trench isolation structure and the at least two second shallow trench isolation structures.

[0060] The cross-sectional structure diagram after step S103 is completed is as follows: Figure 4G shown.

[0061] Specifically, the second mask layer 14 is a hard mask layer, and the specific material may also be silicon nitride or polysilicon. When the second mask layer 14 is selected as a silicon nitride layer, the problem of peeling defect of the hard mask layer during etching can be avoided. In this embodiment, the silicon nitride layer can be formed specifically by an LPCVD process. In addition, when the second mask layer 14 is selected as a silicon nitride layer, when the silicon nitride layer is etched with an inert gas, the byproducts of the reaction between the gas and silicon nitride will form pinholes on the silicon nitride layer and damage the first device oxide layer and / or the second device oxide layer. Therefore, in this embodiment, the material of the second mask layer 14 can be selected as polysilicon to avoid this phenomenon. When the material selected for the second mask layer is different, there are also differences in the process of forming the second mask layer 14 and the subsequent process of removing the second mask layer 14. For example, when the material of the second mask layer 14 is polysilicon, please refer to Figure 5A-5B Step S103 may specifically include: forming a buffer layer 17 on the first mask layer, the first shallow trench isolation structure and the at least two second shallow trench isolation structures. After this step is completed, the structure is as follows Figure 5A As shown; the second mask layer 14 is formed on the buffer layer, and the structure after the step is completed is as shown Figure 5B As shown. The buffer layer 17 serves to better bond the second mask layer 14 made of polysilicon to the first mask layer 12. The buffer layer 17 can be made of silicon oxide or other materials that facilitate bonding the second mask layer 14 made of polysilicon to the first mask layer 12. The thickness of the buffer layer 17 is preferably in the range of 8 nm to 9 nm.

[0062] Step S104: sequentially etching the second mask layer located in the second region and the at least two second shallow trench isolation structures to form a semiconductor protrusion between two adjacent second shallow trench isolation structures.

[0063] Referring to Figure 2 , Figure 2 is a flowchart of another method for manufacturing a semiconductor device according to an embodiment of the present application. Step S104 can specifically include the following steps.

[0064] Step S1041: forming a second photoresist layer on the second mask layer.

[0065] After step S1041, the cross-sectional structure is as shown in Figure 4H . In this embodiment, when the material of the second mask layer 14 is selected to be silicon nitride, in order to avoid the "poisoning phenomenon" of the second photoresist layer 15 caused by the silicon nitride material, that is, in order to avoid the silicon nitride material affecting the morphology of the second photoresist layer 15, a protective layer 19 can be formed in advance before forming the second photoresist layer 15, the material of the protective layer 19 is preferably silicon oxide, which is used to avoid the second photoresist layer from being affected by the silicon nitride material; the second photoresist layer 15 is a photoresist, including a positive photoresist or a negative photoresist. Therefore, step S1061 can specifically include: forming a protective layer on the second mask layer; and forming the second photoresist layer on the protective layer.

[0066] Step S1042: etching the second photoresist layer and the second mask layer in the second region in sequence until the first mask layer and the at least two second shallow trench isolation structures in the second region are exposed.

[0067] After step S1042, the cross-sectional structure is as shown in Figure 4J .

[0068] Specifically, as shown in Figure 4I , the second photoresist layer 15 can be etched according to the defined B region pattern to form a second photoresist layer 15A having the defined B region pattern, and the second mask layer 14 can be etched according to the pattern. Specifically, the second mask layer 14 can be etched according to the pattern by using a reactive ion etching or plasma etching process, until the first mask layer 12 and the at least two second shallow trench isolation structures 13B in the B region are exposed, as shown in Figure 4J .

[0069] Step S1043: removing the second photoresist layer in the first region.

[0070] After step S1043, the cross-sectional structure is as shown in Figure 4K . The second photoresist layer 15A in the A region is removed by exposure and development.

[0071] Step S1044: etching the at least two second shallow trench isolation structures with the exposed first mask layer and the remaining second mask layer in the second region as masks.

[0072] The cross-sectional structure diagram after step S1044 is completed is as follows: Figure 4L shown.

[0073] Specifically, in step S1042, after the second mask layer 14 in region B is completely etched, a residual second mask layer 14A still remains in region A. Therefore, the residual second mask layer 14A protects the first shallow trench isolation structure 13A when etching the at least two second shallow trench isolation structures 13B, while the exposed first mask layer 12 prevents other structures in region B except the second shallow trench isolation structure 13B from being etched. In addition, when the first shallow trench isolation structure 13A and the second shallow trench isolation structure 13B are set to the same height, after the second shallow trench isolation structure 13B is etched, the height of the obtained trench isolation structure 13B' is smaller than the height of the first shallow trench isolation structure 13A. Furthermore, in this embodiment, the second shallow trench isolation structure 13B is selected to be etched to be lower than the substrate 10. Therefore, the first shallow trench isolation structure 13A is higher than the substrate 10, and the substrate 10 is higher than the trench isolation structure 13B', so that the part of the substrate 10 protruding from the two adjacent trench isolation structures 13B' serves as the "Fin" of the FinFET in region B, that is, the semiconductor protrusion 10B in region B serves as the fin structure in the FinFET.

[0074] See also Figure 3 , after step S104, further comprising:

[0075] Step S105: removing the first mask layer and the remaining second mask layer.

[0076] The cross-sectional structure diagram after step S105 is completed is as follows: Figure 4M As shown. After step S105 is completed, the top of the semiconductor protrusion 10B is covered with a portion of the second device oxide layer 11B'. In this example, when the first mask layer 12 and the remaining second mask layer 14A are both silicon nitride materials, hot phosphoric acid can be used to remove the remaining second mask layer 14A and the remaining first mask layer 12 by wet etching. It should be noted that in this embodiment, when the second mask layer 14 is polycrystalline silicon material and the first mask layer 12 is silicon nitride material, tetramethylammonium hydroxide (TMAH) solution can be used to remove the second mask layer 14A in the first area first, and then hot phosphoric acid can be used to remove the remaining first mask layer 12. Since TMAH has a strong corrosive effect on both polycrystalline silicon and single crystal silicon, in order to avoid significant damage to the semiconductor protrusion 10B in area B when removing the second mask layer 14A by a wet process, in this embodiment, as Figure 2 As shown, step S105 may specifically include: performing carbon or germanium doping on both sides of the semiconductor protrusion; and removing the remaining second mask layer and the first mask layer in sequence.

[0077] Among them, since the TMAH solution significantly slows down the etching speed of the two sides 1011B of the semiconductor protrusion after carbon doping, the carbon doping step can protect the Fin structure, and the same is true for germanium.

[0078] See also Figures 6A-6B , wherein the step of doping both sides of the semiconductor protrusion with carbon or germanium includes: forming a third mask layer on the remaining second mask layer; using the third mask layer and the first mask layer located in the second area as masks, doping both sides of the semiconductor protrusion with carbon or germanium.

[0079] In this embodiment, the third mask layer 18 is a photoresist material. Through the masking effect of the third mask layer 18, the second mask layer 14A made of polysilicon is prevented from being doped with carbon or germanium. Therefore, when the second mask layer 14A is removed by the TMAH solution, since the second mask layer 14A is not doped with carbon or germanium, the etching speed of the second mask layer 14A is much faster than the etching speed of the two sides 1011B of the semiconductor protrusion. Therefore, the step of carbon or germanium doping can play a corresponding protective role on the corresponding Fin structure at the two sides 1011B of the semiconductor protrusion, and other structures such as the second shallow trench isolation structure 13B' located in the B area will not be affected by the insulation performance after being doped with carbon or germanium.

[0080] Step S106: forming a supplementary oxide layer on both sides of the semiconductor protrusion to extend the second device oxide layer.

[0081] The structural diagram after step 106 is completed is as follows Figure 4N shown.

[0082] Specifically, the semiconductor protrusion 10B can be oxidized by direct thermal oxidation process to form a supplementary oxide layer on both sides of the semiconductor protrusion 10B. The corresponding supplementary oxide layer is similar to the following: Figure 4M The portion of the second device oxide layer 11B' located on the top of the semiconductor protrusion 10B shown in the figure constitutes an extended second device oxide layer 11B surrounding the fin structure on three sides from the top and both sides 1011B of the semiconductor protrusion. The extended second device oxide layer 11B is used as the gate oxide layer of the FinFET structure.

[0083] See also Figure 3 , Figure 3 This is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention, which, after step S106, further includes:

[0084] Step S107: forming a first gate layer on the first device oxide layer.

[0085] Step S108: forming a second gate layer on the extended second device oxide layer.

[0086] The structural diagram after step 108 is completed is as follows Figure 4O As shown, in Figure 4O In the embodiment, the first gate layer 16A is patterned and etched to form the gate of the planar transistor, and the second gate layer 16B is used as the gate of the FinFET. The second gate layer 16B can surround the channel from three sides, thereby increasing the control area of ​​the gate over the channel, greatly enhancing the gate control capability, thereby effectively suppressing the short channel effect and reducing the subthreshold leakage current. When the first gate layer 16A and the second gate layer 16B are both metal, they are formed on different areas by low pressure chemical vapor deposition (LPCVD). In this embodiment, since the low voltage device area also includes a first low voltage area b1 and a second low voltage area b2, in order to better illustrate the device structure formed on the first low voltage area b1 and the second low voltage area b2, please refer to FIG. Figure 4P Independent FinFETs are formed between the first low-voltage region b1 and the second low-voltage region b2. The oxide layer thicknesses of the devices in the first low-voltage region b1 and the second low-voltage region b2 can be the same or different, and can be set based on the breakdown voltage requirements of the different low-voltage regions. The methods for forming devices in the first and second low-voltage regions are similar to those for forming devices in a single low-voltage device region. Devices in the first and second low-voltage regions can be formed simultaneously or separately.

[0087] In the manufacturing method of the semiconductor device provided by the present invention, a first shallow trench isolation structure and a second shallow trench isolation structure are formed in the first region and the second region respectively, and then the two adjacent second shallow trench isolation structures are etched to obtain a semiconductor protrusion, thereby forming a shallow trench isolation structure that meets the structural requirements of different regions on the semiconductor device. It is also beneficial to form a FinFET on the semiconductor device based on the semiconductor protrusion to alleviate the short channel effect.

[0088] See also Figures 4A to 4P The present invention also provides a semiconductor device, which can be formed according to the above-described fabrication method. The semiconductor device can be used in peripheral circuits within a storage device. Furthermore, the storage device can be a NAND chip. The semiconductor device includes a substrate 10, a first shallow trench isolation structure 13A, a trench isolation structure 13B′, a semiconductor protrusion 10B, a first device oxide layer 11A, a second device oxide layer 11B, a first gate layer 16A, and a second gate layer 16B.

[0089] Specifically, as shown in FIGA , the material of the substrate 10 may be a semiconductor material such as silicon, germanium or silicon-on-insulator (SOI). In this embodiment, the substrate 10 may include a first region (region A) and a second region (region B), wherein region A includes a high-voltage device region, which can be used to form a planar transistor in the embodiment of the present invention; region B includes a low-voltage device region (the operating voltage of the devices in the low-voltage device region is lower than the operating voltage of the devices in the high-voltage device region). Furthermore, the low-voltage device region may also include a first low-voltage region b1 and a second low-voltage region b2, wherein the operating voltages of the devices (such as transistors or CMOS tubes) in the high-voltage device region, the first low-voltage region and the second low-voltage region may be in descending order. In this embodiment, in order to simplify the diagram, Figure 4A In the following figures, area B is used to summarize b1 and b2; specifically, area B can be a low-voltage device area, or it can include both b1 and b2. Figures 4B-4O The following is an example of an area B containing a low-voltage device area. The area B is used to form a fin transistor (FinFET) in an embodiment of the present invention. In the FinFET, the gate can surround the channel from three sides, increasing the control area of ​​the gate on the channel, greatly enhancing the gate control capability, thereby effectively suppressing the short channel effect and reducing the subthreshold leakage current. The performance of different device areas can be adjusted by changing the channel width of one or more transistors inside the device, and the channel width of the FinFET is proportional to the height of the fin structure. Since the high-voltage device area requires a higher driving voltage, the height of the corresponding FinFET "Fin" (fin structure) is also higher. It is difficult to form a gate structure surrounded on three sides on a higher Fin, so area A still uses a planar transistor.

[0090] Among them, such as Figure 4B As shown, a first device oxide layer 11A located in the first region and a second device oxide layer 11B located in the second region are also formed on the substrate 10. The thickness H1 of the first device oxide layer 11A in the first direction (y direction in the figure) is greater than the thickness H2 of the second device oxide layer 11B in the first direction.

[0091] Specifically, in this embodiment, the formation process of the first device oxide layer 11A and the second device oxide layer 11B includes a thermal oxidation process (Thermal Oxidation), a soft plasma oxidation process (Soft Plasma Oxidation) or a UV Photo Assistant Oxidation process (UV Photo Assistant Oxidation), and in this example, when the substrate 10 is selected as a silicon substrate, the second device oxide layer 11B can be formed at the same time as the first device oxide layer 11A is formed. At this time, the components of the first device oxide layer 11A and the second device oxide layer 11B are both silicon oxide. The first device oxide layer 11A and the second device oxide layer 11B serve as the gate oxide layers of the high-voltage device and the low-voltage device, respectively. Due to different breakdown voltage requirements for low-voltage and high-voltage devices, to prevent excessive leakage current in the high-voltage device region, the thickness H1 of the first device oxide layer 11A in the first direction (the y-direction in the figure), i.e., the thickness direction of the substrate 10, is greater than the thickness H2 of the second device oxide layer 11B in the first direction. To achieve this thickness relationship, the first device oxide layer 11A and the second device oxide layer 11B can be formed in separate steps or simultaneously. When simultaneous formation is used, chloride ions can be pre-doped in region A. Due to the chloride ion doping in region A, the oxidation rate of the substrate 10 in region A is accelerated. Therefore, in the same amount of time, the first device oxide layer 11A is formed thicker than the second device oxide layer 11B. When step-by-step formation is used, the first step is to form a device oxide layer of equal thickness in the first region and the second region under the same time and process conditions. The second step is to selectively etch the device oxide layer in the second region so that the thickness of the second device oxide layer in the second region is less than the thickness of the first device oxide layer in the first region. In this embodiment, if Figure 4O As shown, the second device oxide layer 11B surrounds the semiconductor protrusion 10B from both sides and the top of the semiconductor protrusion 10B, that is, the second device oxide layer 11B covers the fin structure of the FinFET structure from three sides. The second device oxide layer 11B is used as the gate oxide layer of the FinFET structure.

[0092] The first shallow trench isolation structure 13A and the second shallow trench isolation structure 13B' are located in the first region and the second region, respectively. Since the first shallow trench isolation structure 13A and the second shallow trench isolation structure 13B can be of the same height, after etching the second shallow trench isolation structure 13B, the height of the trench isolation structure 13B' obtained is less than the height of the first shallow trench isolation structure 13A. Furthermore, in this embodiment, the second shallow trench isolation structure 13B is etched to a level lower than the substrate 10. Therefore, the first shallow trench isolation structure 13A is higher than the substrate 10, and the substrate 10 is higher than the second shallow trench isolation structure 13B' after etching, so that the portion of the substrate 10 protruding from the two adjacent second shallow trench isolation structures 13B' serves as the "Fin" of the FinFET in region B, that is, the semiconductor protrusion 10B in region B serves as the fin structure in the FinFET.

[0093] like Figure 4O As shown, the semiconductor device further includes a first gate layer 16A located on the first device oxide layer 11A and a second gate layer 16B located on the second device oxide layer 12A.

[0094] exist Figure 4O In the embodiment, the first gate layer 16A is patterned and etched to form the gate of the planar transistor, and the second gate layer 16B is used as the gate of the FinFET. The second gate layer 16B can surround the channel from three sides, increasing the control area of ​​the gate over the channel, greatly enhancing the gate control capability, thereby effectively suppressing the short channel effect and reducing the subthreshold leakage current. When the first gate layer 16A and the second gate layer 16B are both metal, they are formed on different areas by low pressure chemical vapor deposition (LPCVD). In this embodiment, since the low voltage device area also includes the first low voltage area b1 and the second low voltage area b2, in order to better illustrate the device structure formed on the first low voltage area b1 and the second low voltage area b2, please refer to Figure 4P, independent FinFETs are formed between the first low-voltage region and the second low-voltage region, and the thickness of the device oxide layer in the first low-voltage region b1 and the second low-voltage region b2 can be the same or different, and can be set according to the requirements of the breakdown voltage of different low-voltage regions. The method for forming devices in the first low-voltage region and the second low-voltage region is similar to the method for forming devices in a low-voltage device region. The devices in the first low-voltage region and the devices in the second low-voltage region can be formed at the same time or separately. The beneficial effects of the present invention are: different from the prior art, in the semiconductor device and the manufacturing method thereof provided by the present invention, a first shallow trench isolation structure and a second shallow trench isolation structure are formed in the first region and the second region respectively, and then the two adjacent second shallow trench isolation structures are etched to obtain a semiconductor protrusion, thereby forming a shallow trench isolation structure that meets the structural requirements of different regions on the semiconductor device, and it is also beneficial to form a FinFET on the semiconductor device according to the semiconductor protrusion, thereby alleviating the short channel effect.

[0095] In addition to the above embodiments, the present invention may also have other implementations. Any technical solution formed by equivalent replacement or equivalent replacement falls within the scope of protection required by the present invention.

[0096] In summary, although the preferred embodiments of the present invention have been disclosed above, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a substrate comprising a first region and a second region; forming a first device oxide layer located in the first region and a second device oxide layer located in the second region on the substrate; forming a first mask layer on the first device oxide layer and the second device oxide layer; forming a first shallow trench isolation structure located in the first region and at least two second shallow trench isolation structures located in the second region in the substrate; forming a second mask layer on the substrate, the first shallow trench isolation structure, and the at least two second shallow trench isolation structures; removing the second mask layer located in the second region, and etching the at least two second shallow trench isolation structures until they are lower than the substrate, so as to form a semiconductor protrusion between two adjacent second shallow trench isolation structures; sequentially removing the second mask layer located in the first area, and the first mask layers in the first area and the second area; forming a supplementary oxide layer on both sides of the semiconductor protrusion to extend the second device oxide layer; forming a first gate layer on the first device oxide layer; forming a second gate layer covering the semiconductor protrusion on the extended second device oxide layer; The first device oxide layer, the substrate and the first gate layer form a planar control transistor, and the second device oxide layer, the semiconductor protrusion and the second gate layer form a fin field effect transistor.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The removing of the second mask layer located in the second region and etching the at least two second shallow trench isolation structures until they are lower than the substrate include: forming a second photoresist layer on the second mask layer; Sequentially etching the second photoresist layer and the second mask layer located in the second region until the first mask layer and at least two second shallow trench isolation structures located in the second region are exposed; removing the second photoresist layer located in the first area; The at least two second shallow trench isolation structures are etched using the exposed first mask layer and the second mask layer located in the first region as masks.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The forming of a second photoresist layer on the second mask layer includes: forming a protective layer on the second mask layer; The second photoresist layer is formed on the protective layer.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The second mask layer is silicon nitride or polysilicon; When the second mask layer is polysilicon, before sequentially removing the second mask layer and the first mask layer located in the first region, the manufacturing method includes: Both sides of the semiconductor protrusion are doped with carbon or germanium.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: The step of doping both sides of the semiconductor protrusion with carbon or germanium comprises: forming a third mask layer on the second mask layer located in the first region; The third mask layer and the first mask layer located in the second region are used as masks to perform carbon or germanium doping on both sides of the semiconductor protrusion.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The thickness of the first device oxide layer in a first direction is greater than the thickness of the second device oxide layer in the first direction, and the first direction is the thickness direction of the substrate.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: A first shallow trench isolation structure located in the first region and at least two second shallow trench isolation structures located in the second region are formed in the substrate, comprising: forming an isolation trench in the substrate, the isolation trench comprising a first sub-isolation trench located in a first region and at least two second sub-isolation trenches located in a second region; An isolation material is filled in the isolation trench to form the first shallow trench isolation structure and the at least two second shallow trench isolation structures in the first region and the second region, respectively.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: Filling the isolation groove with an isolation material comprises: depositing the isolation material in the isolation trench and on the first mask layer to fill the isolation trench; The isolation material is planarized so that the isolation material in the isolation trench is flush with the first mask layer.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: The first mask layer is made of silicon nitride.

10. The method for manufacturing a semiconductor device according to claim 1, wherein: The second mask layer is silicon nitride or polysilicon; when the second mask layer is polysilicon, forming the second mask layer on the substrate, the first shallow trench isolation structure, and at least two of the second shallow trench isolation structures includes: forming a buffer layer on the first mask layer, the first shallow trench isolation structure, and the second shallow trench isolation structure; The second mask layer is formed on the buffer layer.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The thickness of the buffer layer ranges from 8 nm to 9 nm.

12. The method for manufacturing a semiconductor device according to claim 1, wherein: The first shallow trench isolation structure is higher than the substrate, and the substrate is higher than the second shallow trench isolation structure.

13. A semiconductor device comprising: a substrate comprising a first region and a second region; A first shallow trench isolation structure and at least two second shallow trench isolation structures are respectively located in the first region and the second region, with a semiconductor protrusion between two adjacent second shallow trench isolation structures; a first device oxide layer located in the first region, and a second device oxide layer located in the second region and covering the semiconductor protrusion; a first gate layer located on the first device oxide layer, and a second gate layer located on the second device oxide layer, wherein the first shallow trench isolation structure penetrates the first gate layer and the first device oxide layer; and a portion of the second gate layer penetrates the second device oxide layer and contacts the second shallow trench isolation structure; The first device oxide layer, the substrate and the first gate layer form a planar control transistor, and the second device oxide layer, the semiconductor protrusion and the second gate layer form a fin field effect transistor.

14. The semiconductor device according to claim 13, wherein The first shallow trench isolation structure is higher than the substrate, and the substrate is higher than the second shallow trench isolation structure.

15. The semiconductor device according to claim 13, wherein The thickness of the first device oxide layer in a first direction is greater than the thickness of the second device oxide layer in the first direction, and the first direction is the thickness direction of the substrate.

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