Capacitor structure and chip antenna

Abstract

The invention relates to a capacitor structure implemented using a semiconductor process. The capacitor structure comprises a plurality of interdigitated positive and negative electrode fingers separated by a dielectric material, and a plurality of patterned metallization layers separated by the dielectric material. Each interdigitated electrode finger comprises a lateral portion formed on one of at least two substantially parallel first metallization layers, and a vertical portion comprising a plurality of stacked plates or bars disposed on a plurality of second metallization layers between the first metallization layers and electrically connected to each other and to the lateral portion through a plurality of conductive vias traversing the dielectric material separating adjacent metallization layers. The vertical distance between at least partially stacked lateral portions of each pair of two adjacent electrode fingers is substantially equal to the lateral distance between two adjacent vertical portions.

Description

Technical Field

[0001] This invention relates to a semiconductor device structure, specifically, to a capacitor structure. More specifically, this invention discloses a chip antenna implemented using semiconductor technology. Background Technology

[0002] Figure 1a A parallel-plate capacitor is shown, with conductor plates of length L and width W, and a distance D between the two plates (100, 102). The gap between the first conductor plate (100) and the second conductor plate (102) is filled with a dielectric (101) of thickness D, and the relative permittivity ∈r and ∈0 is constant with respect to the vacuum permittivity. The capacitance of the parallel-plate capacitor is given by the following equation:

[0003] C=∈0×∈ r ×(WxL) / D (1)

[0004] In the semiconductor industry, when an insulator is used as the dielectric (101), this type of capacitor is usually manufactured by placing the insulating material between two flat metal sheets, and therefore it is usually called a metal-insulator-metal (MIM) capacitor.

[0005] Equation (1) is accurate when the dimensions of the conductor plates (100, 102), particularly their width (W) and length (L), are significantly greater than the distance (D). This is because in this case, it can be assumed that the electric field between these plates is constant and zero everywhere else, and any edge field can be ignored. Since capacitance is proportional to dimensions W and L and inversely proportional to D, from the viewpoint of capacitance tolerance, the most critical dimension is obviously D, assuming that the absolute tolerances of W, L, and D are of the same order of magnitude, but W and L are clearly greater than D. Figure 1b Show Figure 1a The cross-section of the capacitor. The current flux (103) between the conductor plates (100, 102) is mainly located between the conductor plates (100, 102).

[0006] If W or L is not large compared to D, then the edge field around the capacitor edge makes a significant contribution to the total capacitance and should be taken into account. Figure 2a The vertical parallel plate (VPP) capacitor structure shown is an example of this. Figure 1a Compared to the previous structure, this structure is rotated 90 degrees in the direction of the electric flux. In this specific case, the width W of the capacitor plate cannot be considered significantly greater than the distance D. Equation (2) corresponding to (1) can still be used to roughly estimate the capacitance.

[0007] C≈∈0×∈ r ×(W×L) / D (2)

[0008] Figure 2b Show Figure 2a The cross-section of the capacitor. The edge electric field (104) at the edge of the parallel plates (100, 120), which is not completely perpendicular to the plates (100, 102), has a more significant effect on the total capacitance.

[0009] In mobile wireless devices such as mobile phones, tablets, trackers, or IoT devices, internal antennas are generally preferred over external antennas. Antenna size is typically extremely limited, requiring compact antenna solutions. This reduction in antenna size imposes significant design challenges on antenna engineers. The use of suboptimal antenna solutions can degrade the operating range of the wireless device, but can also adversely affect, for example, the device's battery life.

[0010] When a ground plane of finite size exists, the performance of a small antenna can be fundamentally altered depending on the size and shape of the ground plane or the antenna's placement on it. In wireless mobile devices, antenna performance is virtually always largely dependent on the size and shape of the ground plane, regardless of whether a resonant or non-resonant antenna is used. Examples of resonant wireless mobile device antennas include patch antennas, quarter-wavelength monopole antennas, loop antennas, and slot antennas (and variations such as inverted L-shaped antennas (ILA) and inverted F-shaped antennas (IFA)). Patch antennas consist of a flat metal sheet or "patch" mounted on top of a larger sheet forming the ground plane. Monopole antennas consist of a metal "stub" mounted on or adjacent to the ground plane. Resonant antenna assemblies have at least one solid dimension such that the resonant antenna assembly resonates at the operating frequency, such as a half-wavelength (λ / 2) patch antenna or a quarter-wavelength (λ / 4) monopole. Non-resonant antenna assemblies are typically substantially smaller than the resonant size and require impedance matching. In this case, the ground plane forms the main radiating structure, and the "non-resonant antenna structure" operates more or less as a coupling device. It is sometimes also called an "excitation assembly" because the small antenna assembly is used to "excite" the PCB / chassis wave mode. Or in some cases—if the author does not wish to emphasize the contribution of the conductive chassis to the radiation properties—it can simply be called an antenna assembly, radiator electrode, or even a radiator.

[0011] Slot antennas are a common type of antenna used in mobile wireless devices. They are essentially constructed by creating a slot within a conductive sheet. The slot can be completely enclosed by the conductive sheet, in which case its lowest resonant mode is half a wavelength (λ / 2), or the slot can have openings at the edges of the conductive sheet, in which case its lowest resonant mode will be a quarter wavelength (λ / 4). The latter type of slot antenna can also be called a cutout antenna. Impedance matching is typically required to effectively feed a slot antenna. This may require adding a series matching capacitor to the antenna feed for impedance matching.

[0012] Within the scope of this invention, the terms chip antenna, non-resonant chip antenna, and miniature chip antenna all refer to capacitor devices, such as surface-mount chip capacitors (SMD capacitors), which can be implemented as discrete semiconductors for impedance matching of antenna structures. In connection with this invention, the terms miniature chip antenna, chip antenna, and non-resonant chip antenna are used interchangeably. Antenna implementations utilizing chip antennas can be based on various operating principles known in the art, such as monopole, inverted-F antenna (IFA), loop antenna, or slot antenna. In loop-type configurations, the chip antenna serves as part of the loop, where it primarily operates as a capacitive adjustment component. Furthermore, there are various manufacturing methods for producing chip antennas, but in many cases, chip antennas are manufactured on high-dielectric substrates (in other words, substrates with high dielectric constants, such as ceramic) to reduce the physical size of the antenna. By using high-dielectric substrates, non-resonant chip antennas will have higher capacitance density, thus enabling the desired capacitance to be achieved in a smaller size.

[0013] Description of related technologies

[0014] US6690570 discloses a vertical parallel plate capacitor defined by interdigitated vertical plate electrodes, which are formed of conductive layers coupled to each other through conductive vias.

[0015] Compared to ceramic capacitors, metal-oxide-metal (MOM) capacitors achieve smaller size and higher accuracy. Furthermore, MOM capacitors offer better scalability and price because they can be manufactured in large sizes using semiconductor processes.

[0016] Using an interdigitated electrode structure achieves lower manufacturing costs and higher capacitance density compared to traditional plate capacitors. However, due to variations in the manufacturing process of this type of semiconductor device, the capacitance value tolerance is large. In other words, the accuracy of the achieved capacitance values ​​is poor, which causes problems in manufacturing devices used in certain applications requiring accurate capacitance values. Individual selection of capacitors in mass production is not commercially feasible, but there is a need to control the variation in capacitance values ​​across a large number of capacitor devices in a cost-efficient manner. Summary of the Invention

[0017] The objective is to provide a method and apparatus to address the problem of providing improved capacitor devices, particularly suitable for use as chip antennas. This objective is achieved through a semiconductor device according to the disclosed embodiments.

[0018] The present invention is based on the concept of novelly shaping a capacitor plate into a structure having both vertical parallel plates and lateral parallel plates.

[0019] According to a first aspect, a capacitor structure implemented using a semiconductor process is provided. The capacitor structure includes a plurality of interdigitated positive and negative electrode fingers separated by a dielectric material, and a plurality of patterned metallization layers separated by the dielectric material. Each interdigitated electrode finger includes: a lateral portion formed on one of at least two substantially parallel first metallization layers; and a vertical portion including a plurality of stacked plates or rods disposed on a plurality of second metallization layers residing between the first metallization layers. The plates or rods are electrically connected to each other and to the lateral portion via a plurality of conductive vias traversing the dielectric material separating adjacent metallization layers. The vertical distance between each pair of at least partially stacked lateral portions of two adjacent electrode fingers is substantially equal to the lateral distance between two adjacent vertical portions.

[0020] According to the second aspect, portions of two adjacent electrode fingers are disposed on different metallization layers in the first metallization layer.

[0021] According to the third aspect, the more than one stacked plate or rod also includes a plate or rod disposed on the first metallization layer excluding the vertical portion of the same electrode finger.

[0022] According to the fourth aspect, the two interdigitated combs are formed by a plurality of positive electrode fingers electrically coupled to each other at one end of the fingers and a plurality of negative electrode fingers electrically coupled to each other at opposite ends of the fingers.

[0023] According to the fifth aspect, the vertical portion of the two interdigitated electrode fingers coupled to each other and the cross-section of the lateral portion form an L-shape. The lateral portion forms the pillars of the L-shape and the vertical portion forms the trunk of the L. The pillars of two adjacent L-shapes extending in opposite lateral directions are disposed on different first metallization layers of the capacitor structure and the trunks of the adjacent L-shapes point in opposite vertical directions.

[0024] According to the sixth aspect, the lateral distance and the vertical distance are defined between different adjacent electrode fingers.

[0025] According to a seventh aspect, the capacitor structure includes three first metallization layers. The capacitor structure is mirror-image of the first metallization layers relative to the pillars forming positive or negative interdigitated L-shaped electrode fingers, such that each of the positive or negative electrode fingers includes two lateral portions stacked on top of each other and disposed on two opposite faces of the capacitor structure, and a vertical portion coupling the two lateral portions. An adjacent negative or positive electrode finger includes a single lateral portion disposed on the first metallization layer between the two opposite faces of the capacitor structure, and two vertical portions pointing in opposite vertical directions from the single lateral portion. The single lateral portion is at least partially stacked between the two lateral portions.

[0026] According to the eighth aspect, the cross-section of the vertical portion and the lateral portion of the two interdigitated electrode fingers coupled to each other forms a T-shape. The lateral portion forms the arm of the T-shape and the vertical portion forms the trunk of the T-shape. The trunks of adjacent T-shaped points and the arms of adjacent T-shapes in opposite vertical directions are disposed on different metallization layers in the first metallization layer of the capacitor structure.

[0027] According to the ninth aspect, the lateral distance and the vertical distance are defined between the same adjacent electrode fingers.

[0028] According to a tenth aspect, the capacitor structure includes three first metallization layers, and the capacitor structure is mirror-image of the first metallization layers relative to the arms forming positive or negative interdigitated T-shaped electrode fingers, such that there is a pair of positive or negative T-shaped electrode fingers, wherein their lateral portions overlap each other and are disposed on two opposite faces of the capacitor structure, and their vertical portions point in opposite directions. Each adjacent negative or positive electrode finger includes a single lateral portion disposed on a first metallization layer between the two opposite faces of the capacitor structure, and two vertical portions pointing in opposite vertical directions from the single lateral portion. The single lateral portion is at least partially overlapped between the two lateral portions.

[0029] According to the eleventh aspect, the spacing between any portion of two adjacent electrode fingers is at least 5 times, preferably at least 10 times, the minimum manufacturing process linewidth of the manufacturing process used in the manufacture of the capacitor structure.

[0030] According to the twelfth aspect, a chip antenna device is provided that includes at least one, preferably at least two, capacitor structures according to any one of the preceding aspects.

[0031] According to aspect thirteen, the chip antenna device is housed in a wafer-level chip-scale spherical grid array (WLCSPBGA) package.

[0032] According to the fourteenth aspect, the chip antenna device further includes at least one adjustable capacitor configured in parallel and / or series.

[0033] According to aspect fifteen, an antenna structure utilizing radiation from a ground plane is provided. This antenna structure includes a chip antenna according to any one of aspects twelve to fourteen.

[0034] This invention offers the following advantages: the capacitance and reactance tolerances of the capacitor are improved; in other words, the capacitance value is more accurate, losses are reduced, and the maximum rated voltage required for high-power applications is achieved. The capacitor structure of this invention effectively compensates for the effects of manufacturing tolerances on the capacitance value, thus compensating for capacitance variations. Furthermore, the capacitance density achieved through the capacitor structure of this invention enables the manufacture of capacitance values ​​that are particularly useful in chip antennas of mobile wireless devices where the physical dimensions are well-suited to the physical dimensions of other active components of the antenna. This facilitates shorter interconnects, thereby improving antenna performance. Attached Figure Description

[0035] In the following description, the invention will be described in more detail with reference to the accompanying drawings and preferred embodiments, wherein:

[0036] Figure 1a and Figure 1b A lateral parallel plate capacitor is shown.

[0037] Figure 2a and Figure 2b A vertical parallel plate capacitor is shown.

[0038] Figure 3a and Figure 3b This illustrates a communication device antenna implemented using a chip antenna.

[0039] Figure 4 A simplified circuit model equivalent to an antenna is shown.

[0040] Figure 5a A top view of the VPP capacitor is shown.

[0041] Figure 5b A perspective view of the VPP capacitor is shown.

[0042] Figure 6 A schematic cross-sectional view showing a first exemplary embodiment of a capacitive component is shown.

[0043] Figure 7 It is an illustrative perspective view of the cross-section of the actual MOM T-shaped VLPP structure in 3D view.

[0044] Figure 8 This shows a comparison of the estimated capacitance changes between VLPP and existing VPP capacitors.

[0045] Figure 9 A schematic cross-sectional view showing a second exemplary embodiment of the capacitive component is shown.

[0046] Figure 10 It is an illustrative perspective view of the cross-section of the actual MOM L-shaped VLPP structure in 3D view.

[0047] Figure 11 This is a schematic cross-sectional view of the third embodiment of the capacitor structure of the present invention.

[0048] Figure 12 This is a schematic cross-sectional view of the fourth embodiment of the capacitor structure of the present invention.

[0049] Figure 13 An exemplary chip antenna element is shown.

[0050] Figure 14 A bottom view of the metal components of the chip antenna element is shown.

[0051] Figure 15 The diagram illustrates the variation of the S11 parameters of an antenna implemented using existing ceramic chip antenna technology.

[0052] Figure 16 The variation of S11 parameters of an antenna implemented using a chip antenna according to a preferred embodiment is shown.

[0053] Figure 17 A simplified circuit model equivalent to the first adjustable antenna is shown.

[0054] Figure 18 The S11 parameters of the first adjustable antenna are shown.

[0055] Figure 19 A simplified circuit model equivalent to a second adjustable antenna is shown.

[0056] Figure 20 The S11 parameters of the second adjustable antenna are shown. Detailed Implementation

[0057] As is known in the art, semiconductor devices are typically fabricated in layers. In such layered semiconductor devices, both the terms lateral and horizontal are generally used to refer to structures extending along material layers. Lateral structures may extend along the surface of the semiconductor device, or they may be embedded between other lateral layers. Correspondingly, the term vertical is used to refer to structures extending in a direction perpendicular to the lateral layers. Vertical structures traverse multiple material layers or pass between multiple material layers. Lateral and vertical structures thus have a substantially 90-degree transposition.

[0058] Figure 3a and Figure 3bAn exemplary implementation of a communication device antenna is shown. Figure 3a and Figure 3b The antenna shown is of the slot type.

[0059] Electromagnetic wave modes describe electromagnetic field patterns. Figure 3a A rectangular ground plane with a slotted antenna is shown. The ground plane is illustrated by a surface current vector plot of wave modes on the ground plane (300).

[0060] Figure 3b yes Figure 3a An enlarged view of the device shows the components of the antenna structure in more detail. The radio frequency (RF) signal to be transmitted through the antenna is fed to the antenna via an antenna feed port (301), and a chip antenna with two capacitors (311, 312) (a parallel capacitor (312) and a series capacitor (311)) is used for impedance matching. It should be noted that, although not shown in the figure, the capacitors (311, 312) of the chip antenna are preferably formed in a single semiconductor package for easier mounting compared to two separate capacitors. Fabricating the capacitors in a single semiconductor device also improves the relative accuracy of their capacitance. The ground plane (300) includes a recessed portion (320). In the illustrated embodiment, the recessed portion may be characterized as a slot, but it may alternatively be designed as a loop or cutout. The ground plane (300) may be the PCB ground plane or chassis of the mobile wireless device.

[0061] Figure 4 Showing the equivalent of Figure 3a and Figure 3b A simplified circuit model of the antenna functionality of the device.

[0062] The antenna feed port (301) provides a connection to the RF circuit interface of the wireless mobile device. The chip antenna element (310) includes a parallel capacitor C4 (312) and a series capacitor C3 (311). Preferably, the two capacitors (311, 312) are included in a single chip antenna assembly to facilitate physical proximity and short interconnections. Additionally, placing the capacitors in a single assembly also helps improve the relative accuracy between the two capacitors, making the installation process easier and further facilitating simplified production and logistics compared to two separate capacitor assemblies. The chip antenna primarily functions as an adjustment and / or matching component, as becomes apparent from the circuit model.

[0063] The parallel resonant circuit (320) represents the effect of the recessed portion (320) of the ground plane. If the recessed portion (320) in the ground plane (300) is small compared to the wavelength of the transmitted and received radio signals and has a perimeter in the range of λ / 8 or smaller, the contribution of the recessed portion (320) (such as the exemplary slot in Figure 3) to the total radiation is minimal, and almost all the radiation originates from the ground plane (300). The recessed portion (320) merely acts as a coupling component, which is reflected in the circuit model in such a way that the resonant frequency of the resonator formed by the inductor L2 (321) and the capacitor C2 (322) is significantly higher than the operating frequency of the antenna. In addition, the radiating portion of the slot conductance GsR (323) is almost zero, which means that there is almost no radiation originating from the recessed portion (320), and the real part of the admittance of the recessed portion (320) is almost entirely associated with the loss described by the loss portion of the slot conductance GsL (324). The radiating portion of the slot conductance GsR(323) refers to a portion of the conductance generated by the slot associated with radiation, and the slot portion of the slot conductance GsL(324) refers to a portion of the conductance generated by the slot associated with loss.

[0064] The transformer (330) represents the coupling between the ground plane recess (320) and the PCB wave mode (330).

[0065] Finally, the series resonant circuit (340) represents the wave mode of the PCB or chassis ground plane (300). If the length of the ground plane (300) is close to optimal, roughly (2n+1)*λ / 2, where n={0,1,2,..} and where λ is the approximate wavelength of the RF signal, then the ground plane (300) has a resonant wave mode close to the expected operating frequency, with an appropriate radiation resistance RpR (341) and a reasonably low loss resistance RpL (342). Such a reasonably low resistance can be, for example, an order of magnitude smaller than RpR (341), in other words, at least one-tenth the resistance of RpR (341). The radiation resistance RpR (341) refers to the portion of the PCB or chassis wave mode resistance associated with radiation from the PCB or chassis, and the loss resistance RpL (342) corresponds to the portion of the PCB or chassis wave mode resistance associated with losses in the PCB or chassis. When current I travels through the resistor representing the PCB or chassis wave mode, the power loss in the PCB or chassis wave mode attributable to the loss resistance RpL is given by equation I^2*RpL, and the corresponding radiated power attributable to the radiation resistance RpR is given by equation I^2*RpR. Inductance L1 (343) describes the inductance associated with the PCB or chassis wave mode, and capacitance C1 (344) describes the capacitance associated with the PCB or chassis wave mode. In this case, if the variations between the chip antenna components are not too large, the antenna configuration can have good performance even with a chip antenna and a relatively small recessed portion (320).

[0066] On the other hand, if the chip antenna design differs (e.g., different capacitance values) to require a larger recess (320) in the ground plane (300), with its perimeter in the range of λ / 4 or greater, then the recess (320) will contribute more to the total radiation. This also implies better antenna performance, including at least higher efficiency and wider bandwidth, and the antenna performance becomes increasingly independent of the size and shape of the ground plane and therefore less susceptible to changes in the ground plane size or antenna position.

[0067] However, the capacitance tolerance of the chip antenna becomes important for controlling the antenna resonant frequency and matching variations. The accuracy of the series capacitor, in particular, is highly critical. Therefore, capacitors that are not easily affected by tolerance variations during the manufacturing process are required.

[0068] However, currently available commercial semiconductor capacitors have considerable tolerance limitations, which are attributable, for example, to variations in layer thickness during the manufacturing process of semiconductor capacitor devices. Additionally, multilayer ceramic chip antennas typically exhibit large tolerance variations due to variations in the ceramic manufacturing process.

[0069] Figure 5aA top view of the metallization layers of a vertical parallel plate (VPP) capacitor is shown, wherein the positive and negative electrodes comprise a pattern of stacked interdigitated metal fingers and a pattern of through-holes connecting the stacked metallization layers. The dielectric material between the structures is not shown. Figure 5b Show along Figure 5a The figure shows a perspective view of a metal component with the same structure as the cut line AA shown. This figure illustrates the metallization layers (501 to 505) and interconnect vias (510) of the vertical plate electrodes. This structure is, in principle, similar to that previously mentioned in US6690570. The vertical stack of the simulated device comprises two thick metallization layers (501, 502) and three thinner metallization layers (503, 504, 505).

[0070] Figure 5b The vertical structure shown is typically used for back-end metallization of radio frequency integrated circuits (RFICs) with a thick metal option, suitable for, for example, creating low-loss RF coils or transmission lines and multiple thinner layers for less critical fine-pitch wiring and connections in semiconductor devices. Unfortunately, this is not optimal for layer structures used for manufacturing tolerance control, as two thick metallization layers will likely dominate in thickness variations, thus failing to fully utilize the potential for tolerance improvements. Furthermore, when implementing maximum capacitance density, the distance between the fingers decreases, increasing the risk of voltage collapse. Further large manufacturing tolerances result in high capacitance tolerances. All these characteristics make such capacitors unsuitable for antenna interfaces.

[0071] If the layer thickness variations are independent, then the total stacking height variation—in other words, the sum of the thicknesses of all layers—is the sum of the individual layer thickness variations. Therefore, the deviation in the total stacking thickness will be less than the sum of the deviations in the individual layer thicknesses. However, if the layer thickness variations are correlated, this may not be true. This also applies to the layer-by-layer metallization width tolerance, i.e., the lateral shape tolerance of the metallized structure. The lateral shape tolerance defines the lateral shape accuracy.

[0072] Use 3D electromagnetic simulation to simulate Figure 5a and Figure 5bThe VPP capacitor exhibits nominal and worst-case capacitance corners with variations in metallization and / or semiconductor layer thickness, as well as lateral shape variations. In this simulated structure, the width of the finger metallization is 2 μm, the gap between the fingers is 3 μm, the height of the metal stack, in other words, the height of the vertical capacitor plate, is approximately 10 μm, and the total area occupied by the capacitor is 217 μm × 144 μm. These exemplary dimensions are relatively large for semiconductor capacitors, which also implies a relatively low capacitance density, but on the other hand, better relative tolerance and a higher breakdown voltage. The thickness variation alone results in a worst-case capacitance variation of +15% to -13% at 2.45 GHz. Taking into account the lateral shape tolerance that also causes variations in the position of the lateral edges of the metal components, the worst-case capacitance variation increases to +27%...-18%. This amount of capacitance variation causes unacceptable changes in antenna performance.

[0073] One way to improve capacitance tolerance is to increase the distance between the capacitor fingers. A VPP capacitor structure with sparse electrode spacing was also simulated, where the lateral spacing of the vertical capacitor plates was increased from 3 μm to 13 μm. The capacitance variation caused by thickness tolerance was found to decrease to + / -10%, and, considering the lateral tolerance of the metallization layer, the worst-case capacitance variation increased to between -11% and +13%. The contribution of lateral tolerance to the total capacitance variation was thus significantly reduced, from between approximately 28% and 44% to between approximately 9% and 23%. However, the capacitance density was also significantly reduced due to the larger finger electrode spacing. Nevertheless, such a low capacitance density device may be suitable for some applications.

[0074] Figure 6A schematic cross-sectional view is shown of a first exemplary embodiment of a capacitive assembly, for example suitable for use in a chip antenna element, which can be fabricated using a plurality of back-end-of-line (BEOL) metallization layers in a semiconductor manufacturing process. The structure includes a plurality of interdigitated positive (+) and negative (-) electrode fingers. In this example, there are four metallization layers (501, 502, 503, 504) and an array of conductive vias (510) between the metallization layers. In this embodiment, the lateral portions of adjacent positive and negative electrodes are partially stacked. In this example with four metallization layers, a first metal (501) layer forms a lateral (horizontal) portion every other electrode finger, and a fourth metallization layer (504) forms another set of lateral portions of the interdigitated electrode fingers. However, any number of metallization layers can be used as long as the metallization layers enable both lateral and vertical structures. The lateral portions of the electrode fingers are disposed on metallization layers on opposite top and bottom surfaces of the capacitor structure. In this example, the vertical portion of the electrode is formed by two stacked metal plates or rods formed on intermediate metallization layers (502, 503) and a through-hole (510) that couples the two intermediate metallization layers (502, 503) to each other and to one of the lateral portions. The lateral portions extend in the lateral direction such that at least one lateral dimension of the lateral portion is greater than that of the vertical portion.

[0075] although Figure 6 The thickness of the metallization layers (501, 502, 503, 504) is approximately equal, but the actual thickness of the metallization layers can vary. The capacitor structure can be considered as a combination of interdigitated capacitors, where positive and negative electrodes are arranged alternately and adjacent positive and negative electrodes have vertically and laterally separated electrode plates. Since the vertical and lateral plates are parts of the same electrode finger, these plates can be referred to as the vertical portion and the lateral portion. The lateral portions of two adjacent positive and negative electrode fingers have a vertical separation or vertical distance (D) between them. V Furthermore, the vertical portions of two adjacent positive and negative electrode fingers have a lateral separation or lateral distance (D) between them. L This novel capacitor finger structure can be referred to as a vertical-lateral parallel plate (VLPP) capacitor structure, and this particular embodiment can be referred to as a T-shaped VLPP capacitor structure, because at least most of the interdigitated finger electrodes have a T-shaped cross-section, wherein the lateral portions form T-shaped arms and the vertical portions form T-shaped trunks. However, as Figure 6As shown, the electrode fingers on the outer (end) side of the comb, having only a single adjacent electrode finger of opposite polarity, can have, but do not necessarily have to have, an L-shape. The goal is to create a capacitor device structure that can be created such that it has a small total capacitance variation without prior knowledge of the layer-by-layer thickness and / or makes the capacitance insensitive to variations in the stacking of metallization layers and vias in the vertical dimension.

[0076] If the length of the finger is L, then the capacitance of a pair of fingers is C. i Given as the sum of the lateral and vertical capacitance components, it can be roughly approximated by equation (3):

[0077] C i =C iL +C iV ≈∈0×∈ r ×L×D V / D L +∈0×∈ r ×L×D L / D V (3)

[0078] For example, if the vertical distance (D) V As the summation increases, the first summation term increases and the second term decreases, thus compensating for capacitance variations attributable to manufacturing tolerances such as metallization layers and vias. The key point is utilizing the contributions of both lateral and vertical current flux to the capacitance. This implies that the cross-section of the interdigitated electrode fingers should preferably have substantially equal lateral separation D. V Vertical separation D L .

[0079] Figure 7 Show Figure 6 An illustrative perspective view of the cross-section of a 3D view of the actual MOM T-shaped VLPP structure illustrated herein. At least some of the metallization layers (501, 502, 503, 504) may have different thicknesses than each other. 3D electromagnetic simulations have been performed on such a structure. The simulations show that this structure can compensate very well for variations in the metallization layer thickness. However, in this structure, lateral shape inaccuracies of the metallization may not be well compensated for, and therefore can have a significant impact on capacitance tolerance if they are not controlled sufficiently well.

[0080] exist Figure 7In this structure, the bare thickness tolerance can be reasonably well compensated for within a worst-case variation of + / -5% in the total capacitance. However, when the accuracy of the lateral shape, especially the accuracy of the lateral dimensions of the metal parts' edges—in other words, the lateral shape tolerance—is also considered, the variation increases, totaling approximately from -8% to +12%. This is because if the lateral dimensions of the lateral portions are not accurate, the outer edges of the T-shaped capacitor electrodes may extend closer to the vertical portion of the opposing polarity electrode. However, the T-shaped VLPP structure can provide viable alternatives depending on the desired capacitor performance and capacitance density. Furthermore, the accuracy of the achieved capacitance and performance of the VLPP capacitor structure is affected by the accuracy of the manufacturing process, allowing improved manufacturing methods to provide further improvements in achievable capacitance tolerance.

[0081] An exemplary variation of the T-shaped implementation is the asymmetric T-shape, where the trunk of the T is not positioned in the middle of the arms. Finger electrodes with an asymmetric T-shape can have their lateral portions (arms of the T) fully stacked in cross-section, as long as the vertical portions do not extend to form metallization layers of the stacked lateral portions on opposite faces of the capacitor structure. However, controlling the capacitance can be more difficult with a fully stacked asymmetric T-shaped electrode compared to a partially stacked symmetrical T-shaped electrode. Figure 6 and Figure 7 Similarly, finger electrodes with asymmetrical T-shapes can also be partially stacked, as shown by the symmetrical T-shaped electrodes.

[0082] Figure 8 This illustrates an exemplary case where the metal stack height varies by ±20% around the nominal value while other parameters remain constant, comparing the estimated capacitance variation between a VLPP capacitor with the same nominal capacitance and a prior art VPP capacitor. The capacitance estimation is based on equations (2) and (3). It is assumed that the VLPP structure is a vertically spaced (D) V The capacitance (800) of the VPP structure varies with the width W of the capacitor plate, and it is assumed that the VPP structure is a variation of the vertical distance (D). V The capacitors (801) of the VLPP structure are distributed across a defined vertical distance (D). V The metal stack height presented by ) has only a very small capacitance change.

[0083] Because equations (2) and (3) used for estimation do not take into account the edge field, Figure 8 The plot in the diagram is not precise, but it provides good insight into how to compensate for variations in metal stack height through improved capacitor finger design.

[0084] Figure 9A schematic cross-sectional view is shown of a second exemplary embodiment suitable for use in a chip antenna element, the capacitive component being fabricated using a plurality of back-end-of-line (BEOL) metallization layers in a semiconductor manufacturing process. The structure also includes a plurality of interdigitated positive (+) and negative (-) electrode fingers. In this example, four metallization layers (501, 502, 503, 504) are present, and an array of conductive vias (510) exists between the metallization layers. In this example with four metallization layers, a first metal (501) layer forms a lateral (horizontal) portion (600) of every other electrode finger, and a fourth metallization layer (504) forms another set of lateral portions (600) of interdigitated electrode fingers. However, any number of metallization layers can be used as long as the metallization layers enable both lateral and vertical structures to be constructed. The metallization layers forming the opposing top and bottom surfaces of the capacitor structure form the lateral portions (600) of the electrode fingers. In this example, the vertical portion (601) of the electrode is formed by three stacked metal plates or rods and a through-hole (510). These three stacked metal plates or rods are formed on one of the intermediate metallization layers (502, 503) and the top and bottom metallization layers (501, 504) of the lateral portion (600) where no electrode fingers are formed. The through-hole (510) couples the two intermediate metallization layers (502, 503) and the top or bottom metallization layer (504 or 501) to each other and to one of the lateral portions (600). In this embodiment, the lateral portions of adjacent positive and negative electrodes are partially stacked. In an alternative embodiment, the vertical portion includes only an intermediate metallization layer (502, 503) and a through hole (510), but no plate or rod on one of the top or bottom metallization layers (501, 504) opposite the metallization layer of the lateral portion (600) forming the electrode fingers.

[0085] although Figure 9 The thickness of the metallization layers (501, 502, 503, 504) is approximately equal, but the actual thickness of the metallization layers can vary. The structure can be considered as a combination of interdigitated capacitors, where positive and negative electrodes are arranged alternately and adjacent positive and negative electrodes have vertically and laterally separated electrode plates. Since the vertical and lateral plates are parts of the same electrode finger, these plates can be referred to as the vertical portion and the lateral portion. The lateral portions of two adjacent positive and negative electrode fingers have a vertical separation or vertical distance (D) between them. V Furthermore, the vertical portions of two adjacent positive and negative electrode fingers have a lateral separation or lateral distance (D) between them. LThis capacitor finger structure can also be referred to as a vertical-lateral parallel plate (VLPP) capacitor structure, and this particular embodiment can be referred to as an inverted L-shaped VLPP capacitor structure, wherein the interdigitated finger electrodes have an inverted L-shaped cross-section, wherein the lateral portion (600) forms an L-shaped support and the vertical portion (601) forms an L-shaped trunk and the positive and negative L-shaped electrode fingers are in an inverted position relative to each other.

[0086] Figure 10 Show Figure 9 An illustrative perspective view of the cross-section of a 3D view of the actual MOM L-shaped VLPP structure illustrated herein. At least some of the metallization layers (501, 502, 503, 504, 505) may have different thicknesses from each other. 3D electromagnetic simulations have been performed on such a structure, showing that this structure can compensate for variations in metallization layer thickness very well.

[0087] The inverted L-shaped VLPP capacitor structure results in the main vertical and lateral fluxes being formed at different physical locations, and the edges of the L-shaped capacitor electrodes are further apart than in a T-shaped VLPP. These characteristics further improve control over capacitance tolerance, and the increased amount of dielectric material between the positive and negative electrodes also reduces the risk of destructive discharge. In simulations, the capacitance tolerance of the inverted L-shaped VLPP has been found to decrease to ±5%, which is sufficient to provide good performance for chip antennas.

[0088] When building VLPP capacitors on a single semiconductor, in addition to achieving a reduced tolerance for absolute capacitance values, the capacitance matching between capacitors on the same IC is also extremely high.

[0089] In an alternative version of the inverted L-shaped capacitor implementation, the lateral portions of adjacent electrodes can be stacked even completely, as long as the vertical portions of the electrodes do not extend to form a metallization layer of the lateral portions of the stacked electrodes on the opposite surface of the capacitor structure.

[0090] Table 1 below compares the simulated achievable capacitance density and capacitance tolerance for different types of parallel-plate capacitors. VPP refers to a conventional vertical parallel-plate capacitor, and VPP-s refers to a "sparse" vertical parallel-plate capacitor with increased lateral spacing between the vertical plates compared to a conventional VPP, used to improve tolerance but reduce capacitance density. T-VLPP refers to the T-shaped VLPP capacitor structure according to the first embodiment, and L-VLPP refers to the inverted L-shaped VLPP capacitor structure according to the second embodiment. Capacitance tolerance is expressed as the maximum and minimum deviations from the expected capacitance value.

[0091]

[0092] Table 1

[0093] While increasing the distance between the electrode fingers in a VLPP inevitably leads to a decrease in capacitance density, it is advantageous to manufacture a VLPP capacitor according to the disclosed embodiment that, in addition to having an improved (reduced) capacitance variation, also possesses two capacitance values ​​suitable for use in chip antennas in mobile wireless device antennas, and a physical dimension that mechanically matches the size of a mobile wireless device, such as a slot antenna, primarily defined by the wavelength of the RF carrier frequency used. Currently, typical capacitance values ​​achievable with such a structure can range from 100 fF to 5 pF, but the range of achievable capacitance values ​​depends on the manufacturing process and is likely to increase (or change) with advancements in manufacturing technology. The good correspondence between the physical dimensions of the entire capacitor device and the physical dimensions of the antenna components outside the chip antenna also enables short interconnections between the active components of the antenna, further improving performance. The selection of a preferred capacitor design depends on the capacitance density and capacitance tolerance requirements of the specific device design.

[0094] Figure 11 This is a schematic cross-sectional view of a third embodiment of the capacitor structure of the present invention. This structure is based on... Figure 6 The structure has a T-shaped cross-section of electrode fingers, but the entire structure is further mirrored relative to the metallization layer (504) that forms the lateral portion (600b) of a set of electrode fingers (i.e., the T-shaped arm of a set of electrode fingers).

[0095] In this example, there are several pairs of positive electrode fingers, each having its overlapping lateral portion (600a), i.e., T-shaped arms, and its vertical portion (601a), i.e., T-shaped trunks pointing in opposite vertical directions, on two opposite surfaces of the capacitor structure. Between the rows of pairs of positive T-shaped electrode fingers, there are negative electrode fingers having a single lateral portion (600b) and two vertical portions (601b) pointing in opposite directions. The lateral portion (600b) of the negative electrode finger partially overlaps with the lateral portion (600a) of the positive electrode finger.

[0096] This type of structure can be advantageous if a high number of available metallization layers (501, 502, 503, 504, 505, 506, 507) are available, as it can also increase the capacitance density achieved in a given region of the structure. Preferably, the vertical distance (D) between the two sides of the mirror structure... V ) and lateral distance (D L Both are equal. Although the illustration shows a mirror image of the arm relative to the negative electrode finger, the capacitor structure can alternatively be mirror image of the metallization layer (504) relative to the lateral portion forming the positive electrode finger (i.e., the T-shaped arm of the positive electrode finger). In other words, the polarity of the positive and negative electrodes can be set in either way.

[0097] As in the previously shown embodiments, in this embodiment, the metallization layers (501, 502, 503, 504, 505, 506, 507) may also have different nominal thicknesses than each other. Preferably, the thickness of the metallization layers is designed such that the vertical distance and the lateral distance (D) are such that... V D L Keep them equal.

[0098] Figure 12 This is a schematic cross-sectional view of the fourth embodiment of the capacitor structure of the present invention. This structure is based on... Figure 9 The structure has an inverted L-shaped cross-section of electrode fingers, but the entire structure is further mirrored relative to the metallization layer (504) that forms the lateral portion (600b) of a set of electrode fingers (i.e., the L-shaped support of a set of electrode fingers).

[0099] In this example, each positive electrode finger has two overlapping lateral portions (600a), i.e., L-shaped pillars, on two opposite surfaces of the capacitor structure, and a vertical portion (601a) coupling the two lateral portions (600a) together. The negative electrode finger has a single lateral portion (600b) and two vertical portions (601b) pointing in opposite directions. The lateral portion (600b) of the negative electrode finger partially overlaps with the lateral portion (600a) of the adjacent positive electrode finger.

[0100] This type of structure can be advantageous if a high number of available metallization layers (501, 502, 503, 504, 505, 506, 507) are available, as it can further increase the capacitance density achieved in a given region of the structure. Preferably, the vertical distance (D) between the two sides of the mirror structure... V ) and lateral distance (D L Both are equal. Although the illustration shows the arm of the capacitor as a mirror image relative to the negative electrode finger, the capacitor structure may alternatively be mirror image relative to the metallization layer of the lateral portion forming the positive electrode finger (i.e., the L-shaped strut of the positive electrode finger).

[0101] In this embodiment, the metallization layers (501, 502, 503, 504, 505, 506, 507) can have different nominal thicknesses. Preferably, the thickness of the metallization layers is designed such that the vertical distance and lateral distance (D) are relatively equal. V D L Keep them equal.

[0102] Figure 13The diagram shows a perspective view of the PCB contact side implemented from an exemplary chip antenna element (310), which includes a wafer-level chip-scale ball grid array design (WLCSP BGA) known in the art, comprising two capacitive devices according to a preferred embodiment of the invention. The chip antenna element (310) includes a plurality of dielectric layers (1111) and two pairs of solder ball contacts (1112). The capacitor structure according to the preferred embodiment is constructed from metal sheets and vias disposed within and between the dielectric layers. The chip antenna element (310) may also include a back coating. Preferably, the dimensions of the chip antenna element (310) are designed such that the interconnections between the ball contacts and the remainder of the antenna design can be kept short.

[0103] Figure 14 Show Figure 13 The diagram shows a bottom view of the metal components of the element, where all dielectrics are concealed, making the interdigitated electrode fingers (101, 102) of the two capacitive devices (1200, 1201) according to the disclosed embodiment visible. An electrical contact (1203) is disposed between the capacitor electrode and the solder ball contact (1112).

[0104] Figure 15 The diagram illustrates the variation of antenna S11 parameters when using a ceramic chip antenna of current technology. Measurements were performed on antennas using ten different chip antennas, showing significant variations in both indicated frequency and return loss, as indicated by the location and depth of the drop-off in the S11 curve.

[0105] Figure 16 The variation of S11 parameters of the antenna implemented using a chip antenna according to a preferred embodiment is shown. Similarly, ten different chip antennas were used in the measurements, with antenna designs similar in other respects. The measurement results indicate a significant improvement in performance, attributed to... Figure 15 Compared to the significant changes shown, the changes in both frequency and backhaul loss are smaller.

[0106] In another embodiment, the chip antenna element may further include circuit components for conditioning and / or matching purposes, such as adjustable or selectable response components arranged in parallel and / or series in the signal path. More specifically, the chip antenna element may include one or more variable capacitors or capacitor arrays or memory banks with semiconductor switches or adjustable capacitors. Additionally, the chip antenna element may include one or more variable inductors or inductor arrays or memory banks with adjustable inductors.

[0107] Figure 17 An additional embodiment of the invention is shown, wherein the chip antenna is further provided with an adjustment circuit (1700) for adjusting the frequency of the antenna. The adjustment circuit (1700) includes a variable capacitor C. V(1701), and additional reactive elements L3 (1703) and L4 (1704), as shown in the circuit model. The other components of the antenna design remain similar. Figure 3a , Figure 3b and Figure 4 The components shown are illustrated. For simplicity, the conductive elements GsL and GsR in the circuit equivalent model have been replaced with a single conductive element G2 (1720), and the resistive elements RpR and RpL have been replaced with a single resistive element R1 (1741). The S-parameters of the antenna can be adjusted by adjusting the capacitance value of the variable capacitor. Figure 18 This shows the adjustment of the S11 parameter. Figure 18 The S11 parameter curves in the figure illustrate the use of different variable capacitors C in the exemplary design. V (1701) S11 parameter obtained from the capacitance value. Using value C. V =1pF to obtain S11 parameter curve 1601, using C V =3pF to obtain curve 1603, using C V =6pF to obtain curve 1606, and use C V =8pF to obtain curve 1608.

[0108] Figure 19 Another additional embodiment of the invention is shown, wherein the chip antenna element is further provided with an adjustment and matching circuit (1900) for adjusting the frequency of the antenna. This adjustment and matching circuit (1900) includes two variable capacitors shown in the model, and an adjustment capacitor C. V1 (1701) and matching capacitor C V2 (1702), and additional reactive elements L3 (1703), L4 (1704), and L5 (1705). Other components of the antenna design remain similar. Figure 3a , Figure 3b and Figure 4 The components shown. For simplicity, as in Figure 17 In the circuit equivalent model, the reactive elements GsL and GsR have been replaced with a single reactive element G2 (1720), and the resistive elements RpR and RpL have been replaced with a single reactive element R1 (1741). The S-parameters of the antenna can be adjusted by adjusting the capacitance value of the variable capacitor. Figure 20 This shows the adjustment of parameter S11. The variable adjustment capacitor C... V1 The adjustment of (1701) mainly affects the operating frequency of the antenna and the variable matching capacitor C. V2 The adjustment of (1702) primarily affects the antenna's return loss. For example, Figure 20 The S11 parameter curves 1801, 1803, and 1808 have been verified by setting the matching capacitor value C. V2=1pF is obtained, and the adjusting capacitor C is adjusted. V1 The values ​​were changed to 1pF, 3pF, and 8pF respectively. Similarly, the S11 parameter curves 1881, 1883, and 1888 have been modified by setting the matching capacitor value C. V2 =8pF, thus enabling the adjustment capacitor C. V1 The values ​​were changed to 1 pF, 3 pF and 8 pF respectively.

[0109] It will be apparent to those skilled in the art that, with advancements in technology, the basic concept of this invention can be implemented in various ways. Therefore, this invention and its embodiments are not limited to the examples described above, but can vary within the scope of the claims.

Claims

1. A capacitor structure implemented using a semiconductor process, the capacitor structure comprising a plurality of interdigitated positive and negative electrode fingers separated by a dielectric material and a plurality of patterned metallization layers separated by the dielectric material. Its features are, Each interdigitated electrode finger includes: The lateral portion is formed by at least one of two parallel first metallization layers, and The vertical portion includes a plurality of stacked plates or rods formed by a plurality of second metallization layers residing between the first metallization layers, wherein the plates or rods are electrically connected to each other and electrically connected to the lateral portion through a plurality of conductive vias that traverse a dielectric material separating adjacent metallization layers. Wherein, the vertical distance between each pair of at least partially overlapping lateral portions of two adjacent electrode fingers is equal to the lateral distance between two adjacent vertical portions, or the vertical distance between each pair of at least partially overlapping lateral portions of two adjacent electrode fingers is equal to the lateral distance between two adjacent vertical portions where no lateral portion is provided.

2. The capacitor structure according to claim 1, wherein, The lateral portions of the two adjacent electrode fingers are disposed on different metallization layers in the first metallization layer.

3. The capacitor structure according to any one of claims 1 to 2, wherein, The plurality of stacked plates or rods also include plates or rods disposed on the first metallization layer of the vertical portion excluding the same electrode finger.

4. The capacitor structure according to claim 1, wherein, The two interdigitated combs are formed by a plurality of positive electrode fingers of a plurality of interdigitated positive and negative electrode fingers electrically coupled to each other at one end of the fingers and a plurality of negative electrode fingers of a plurality of interdigitated positive and negative electrode fingers electrically coupled to each other at opposite ends of the fingers.

5. The capacitor structure according to claim 1, wherein, The cross-sections of the vertical and lateral portions of the two interdigitated electrode fingers coupled to each other form an L-shape, wherein the lateral portions form the pillars of the L-shape and the vertical portions form the trunk of the L-shape, and wherein the pillars of two adjacent L-shapes extending to opposite lateral directions are disposed on different metallization layers in the first metallization layer of the capacitor structure, and wherein the trunks of adjacent L-shapes point in opposite vertical directions.

6. The capacitor structure according to claim 5, wherein, The lateral distance and the vertical distance are defined between different adjacent electrode fingers.

7. The capacitor structure according to claim 5 or 6, wherein, The capacitor structure includes three first metallization layers, and the capacitor structure is mirror-image of the first metallization layers of the pillars forming positive or negative interdigitated L-shaped electrode fingers, such that each of the positive or negative interdigitated L-shaped electrode fingers includes two lateral portions stacked on each other and disposed on two opposite faces of the capacitor structure, and a vertical portion coupling the two lateral portions, and an adjacent negative or positive interdigitated L-shaped electrode finger of each of the positive or negative interdigitated L-shaped electrode fingers includes a single lateral portion disposed on the first metallization layer disposed between the two opposite faces of the capacitor structure, and two vertical portions pointing in opposite vertical directions from the single lateral portion, wherein the single lateral portion is at least partially stacked between the two lateral portions.

8. The capacitor structure according to claim 1, wherein, The cross-sections of the vertical and lateral portions of the two interdigitated electrode fingers coupled to each other form a T-shape, wherein the lateral portion forms the arm of the T-shape and the vertical portion forms the trunk of the T-shape, and wherein the trunks and arms of adjacent T-shapes pointing in opposite vertical directions are disposed on different first metallization layers of the capacitor structure.

9. The capacitor structure according to claim 8, wherein, The lateral distance and the vertical distance are defined between the same adjacent electrode fingers.

10. The capacitor structure according to claim 8 or 9, wherein, The capacitor structure includes three first metallization layers, and the capacitor structure is mirror-image of the first metallization layers forming the arms of positive or negative interdigitated T-shaped electrode fingers, such that there is a pair of positive or negative T-shaped electrode fingers, wherein the lateral portions of the pair of positive or negative T-shaped electrode fingers are stacked on each other and disposed on two opposite faces of the capacitor structure, and the vertical portions of the pair of positive or negative T-shaped electrode fingers point in opposite directions to each other, and adjacent negative or positive electrode fingers of the pair of positive or negative T-shaped electrode fingers include a single lateral portion disposed on a first metallization layer disposed between the two opposite faces of the capacitor structure, and two vertical portions pointing in opposite vertical directions from the single lateral portion, wherein the single lateral portion is at least partially stacked between the two lateral portions.

11. The capacitor structure according to claim 1, wherein, The spacing between any portion of two adjacent electrode fingers is at least five times the minimum manufacturing process linewidth of the manufacturing process used in the manufacture of the capacitor structure.

12. A chip antenna device comprising at least one capacitor structure according to any one of claims 1 to 11.

13. The chip antenna device according to claim 12, wherein, The chip antenna device is housed in a wafer-level chip-scale spherical grid array (WLCSP) BGA package.

14. The chip antenna device according to any one of claims 12 or 13, wherein, The chip antenna device also includes at least one adjustable capacitor configured in parallel and / or series.

15. An antenna structure that utilizes radiation from a grounded plane, wherein, The antenna structure includes a chip antenna according to any one of claims 12 to 14.

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