An ultra-thin 2.5D packaging structure and its packaging method

Abstract

This invention provides an ultra-thin 2.5D packaging structure and method, which reduces the thickness of the package and shortens the process flow. An ultra-thin 2.5D packaging structure includes: a functional chipset comprising at least two sets of functional chips, each set of functional chips having a first dielectric material layer on its lower surface, and an exposed copper pad at the bottom of the first dielectric material layer; a silicon interposer board comprising a silicon interposer board body, a second dielectric material layer on top, and a third dielectric material layer on the bottom, the second dielectric material layer having an exposed mating copper pad on its surface, metal circuitry within the second dielectric material layer, a TSV copper pillar embedded in the silicon interposer board body, the upper part of the TSV copper pillar being connected to the corresponding metal circuitry, and the lower part of the TSV copper pillar being inserted into the third dielectric material layer; a plurality of bump structures; a substrate including an upper connecting pad and a lower connecting pad; a molding compound; and an adhesive filler layer.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor chip packaging, specifically to an ultra-thin 2.5D packaging structure, and also provides an ultra-thin 2.5D packaging method. Background Technology

[0002] In the current mature 2.5D packaging structure using silicon interposers, the chip and the silicon interposer are interconnected by flip-chip bonding. This structure has some technical challenges: there are solder joints tens of micrometers high between the chip and the silicon interposer, which increases the thickness of the entire package; at the same time, the presence of solder joints requires flux cleaning and underfilling processes after the flip-chip process. However, as the chip area continues to increase, the difficulty of flux cleaning and underfilling also increases.

[0003] Therefore, there is an urgent need to develop an ultra-thin 2.5D packaging structure that eliminates the need for flux cleaning and underfill in subsequent operations, thereby reducing the chip packaging process. Summary of the Invention

[0004] To address the aforementioned issues, this invention provides an ultra-thin 2.5D packaging structure that reduces the thickness of the package and eliminates the need for flux cleaning and underfill processes, thus shortening the process flow.

[0005] An ultra-thin 2.5D packaging structure, characterized in that it comprises: A functional chipset, comprising at least two sets of functional chips, wherein a first dielectric material layer is disposed on the lower surface of each set of functional chips, and an exposed copper pad is disposed at the bottom of the first dielectric material layer. A silicon adapter board includes a silicon adapter board body, a second dielectric material layer on top, and a third dielectric material layer on the bottom. The surface of the second dielectric material layer is provided with exposed copper pads, and the interior of the second dielectric material layer is provided with metal circuits. The silicon adapter board body has built-in TSV copper pillars, the upper part of the TSV copper pillars is connected to the metal circuits at corresponding positions, and the lower part of the TSV copper pillars is inserted into the third dielectric material layer. Several bump structures; The substrate includes an upper connecting pad and a lower connecting pad; Plastic encapsulation; And the glue filler layer; A first dielectric material layer of several groups of functional chips is laid flat and attached to the upper surface of the second dielectric material layer of the silicon interposer. The copper pads and mating copper pads of each group of functional chips are bonded together. All functional chips and the second dielectric material layer are encapsulated to obtain a molded body. The lower part of each TSV copper pillar is connected to a bump structure. The lower part of the bump structure is bonded to the upper connecting pad at the corresponding position of the substrate. An adhesive filling layer is provided on the outer periphery and bottom of the silicon interposer.

[0006] Its further features are: The area occupied by several groups of functional chips is smaller than the area of ​​the silicon adapter board, which allows for the placement of plastic encapsulation between adjacent functional chips and around the periphery of several groups of functional chips. The upper surface of each functional chip is exposed after being ground and thinned to enhance heat dissipation and reduce the overall thickness of the package structure. The functional chipset typically includes a logic chipset and a memory chipset, the number of which is arranged according to the actual situation; The area of ​​the substrate is larger than the surface area of ​​a single silicon adapter board. The adhesive filler layer fills the gap between the silicon adapter board and the substrate. The adhesive filler layer has the effect of blocking water and oxygen and buffering stress. The lower layer connecting pad of the substrate is provided with a solder ball structure.

[0007] A method for fabricating an ultra-thin 2.5D packaging structure is characterized by: using hybrid bonding instead of flip bonding, such that the chip is bonded to a mating copper pad on a silicon interposer, and the mating copper pad is connected to a TSV copper pillar through a metal circuit, and the TSV copper pillar is connected to a bump structure below it, and the bump structure is bonded to the corresponding upper layer of the substrate via a pad bonding.

[0008] Its further feature is that it includes the following steps: S1 uses a hybrid bonding process to bond several groups of functional chips to the upper surface of the silicon interposer. S2 performs wafer-level molding on the chip side of the silicon adapter board, encapsulating all functional chipsets with molding compound; S3 grinds and thins the plastic cover to expose the back of the functional chip; S4 uses a ring-cutting process to remove the molding compound around the silicon interposer. S5 performs grinding and thinning and chemical mechanical polishing on the back of the silicon interposer to expose the TSV copper pillars; S6 performs silicon etching on the back of the silicon adapter board, causing the TSV copper pillars to protrude a certain height relative to the lower plane of the silicon. S7 deposits a third dielectric material layer on the back side of the silicon interposer. S8 performs chemical mechanical polishing on the back of the silicon interposer, exposing the TSV copper pillars after polishing, and the remaining thickness of the third dielectric material layer must meet the insulation requirements; S9 sets a bump structure on the back of the silicon interposer through sputtering a metal seed layer, photolithography, and electroplating processes; S10 cuts the silicon interposer into individual pieces and uses a flip-chip process to solder the individual silicon interposer to the upper surface of the substrate. S11 uses glue to fill the gap between a single silicon adapter board and the substrate, forming a glue filling layer; S12 utilizes a ball-planting process to create a solder ball structure on the back of the substrate, resulting in a single 2.5D package with an ultra-thin thickness that uses hybrid bonding technology.

[0009] Its further features are: In step S1, a copper pad is provided on the lower surface of each functional chip. The copper pad is surrounded by a first dielectric material layer. A TSV copper pillar structure is provided inside the silicon interposer, and a mating copper pad is provided on its surface. Similarly, a second dielectric material layer is provided around the mating copper pad. The second dielectric material layer also contains metal lines connecting the TSV copper pillar and the mating copper pad. The copper pad on the surface of each functional chip is bonded to the mating copper pad at the corresponding position on the surface of the silicon interposer. The first dielectric material layer on the lower surface of the functional chip is bonded to the second dielectric material layer at the corresponding position on the upper surface of the silicon interposer. Due to the extremely high flatness of the functional chip and the silicon interposer surface, there are no gaps between them after bonding. In step S2, the thickness of the molding compound exceeds the thickness of any group of functional chips. The purpose is to prevent the back of the functional chips from being exposed. Since wafer-level molding cannot make the diameter of the molding compound equal to the diameter of the carrier, a full mold process is used. The diameter of the molding compound is slightly larger than the diameter of the silicon interposer. The silicon interposer is surrounded by a molding compound. In step S4, the ring cutting depth exceeds the thickness of the molding compound and extends below the upper surface of the silicon adapter plate. The depth of the ring cutting into the silicon adapter plate exceeds the depth of the through-silicon via but does not penetrate the entire silicon adapter plate. Finally, a ring of molding compound near the back side remains around the silicon adapter plate. The circumferential cutting process in step S4 is either wheel circumferential cutting or laser circumferential cutting.

[0010] With this invention, the first dielectric material layer of several groups of functional chips is laid flat and bonded to the upper surface of the second dielectric material layer of the silicon adapter board. That is, the first dielectric material layer on the lower surface of the functional chip is bonded to the second dielectric material layer at the corresponding position on the upper surface of the silicon adapter board. Due to the extremely high flatness of the functional chip and the silicon adapter board surface, there are no gaps between them after bonding. Furthermore, the copper pads and mating copper pads of each group of functional chips are bonded, thus the bonding between the functional chip and the silicon adapter board is a hybrid bonding. Using hybrid bonding instead of flip bonding eliminates the solder joint structure, reduces the interconnection distance between chips, and reduces signal delay. Moreover, since the solder joint structure is eliminated, it is more conducive to reducing the thickness of the package. Finally, by using hybrid bonding instead of flip bonding, the solder joint structure is eliminated, the gap between the chip and the adapter board disappears, and the flux cleaning process and underfill process are eliminated, shortening the process flow. Attached Figure Description

[0011] Figure 1 This is a cross-sectional view of the 2.5D packaging structure of the present invention, and also a flowchart of step S12 of the 2.5D packaging method; Figure 2 This is a flowchart illustrating step S1 of the 2.5D packaging method of the present invention; Figure 3 This is a flowchart illustrating step S2 of the 2.5D packaging method of the present invention; Figure 4 This is a flowchart illustrating step S3 of the 2.5D packaging method of the present invention; Figure 5 This is a flowchart illustrating step S4 of the 2.5D packaging method of the present invention; Figure 6 This is a flowchart illustrating step S5 of the 2.5D packaging method of the present invention; Figure 7 This is a flowchart illustrating step S6 of the 2.5D packaging method of the present invention; Figure 8 This is a flowchart illustrating step S7 of the 2.5D packaging method of the present invention; Figure 9 This is a flowchart illustrating step S8 of the 2.5D packaging method of the present invention; Figure 10 This is a flowchart illustrating step S9 of the 2.5D packaging method of the present invention; Figure 11 This is a flowchart illustrating step S10 of the 2.5D packaging method of the present invention; Figure 12 This is a flowchart illustrating step S11 of the 2.5D packaging method of the present invention; The names corresponding to the serial numbers in the diagram are as follows: Silicon interposer 1, TSV copper pillar 101, metal circuit 102, second dielectric material layer 103, mating copper pad 104, molding compound 2, molding compound 201, third dielectric material layer 3, bump structure 4, substrate 5, adhesive filling layer 6, solder ball structure 7. First functional chip D1, copper pad D101, first dielectric material layer D102, second functional chip D2, copper pad D201, first dielectric material layer D202. Detailed Implementation

[0012] An ultra-thin 2.5D packaging structure, see Figure 1 It includes a functional chipset, a silicon adapter board 1, several bump structures 4, a substrate 5, a molding compound 2, and an adhesive filler layer 6. The functional chipset includes at least two sets of functional chips. Each set of functional chips has a first dielectric material layer on its lower surface, and an exposed copper pad is provided at the bottom of the first dielectric material layer. The silicon adapter board 1 includes a silicon adapter board body, a second dielectric material layer 103 located on the upper layer, and a third dielectric material layer 3 located on the bottom layer. The surface of the second dielectric material layer 103 is provided with exposed mating copper pads 104, and the interior of the second dielectric material layer 103 is provided with metal circuits 102. The silicon adapter board body has a built-in TSV copper pillar 101. The upper part of the TSV copper pillar 101 is connected to the metal circuits 102 at the corresponding position, and the lower part of the TSV copper pillar 101 is inserted into the third dielectric material layer 3. The substrate 5 includes an upper connecting pad and a lower connecting pad; A first dielectric material layer of several groups of functional chips is laid flat and attached to the upper surface of the second dielectric material layer 103 of the silicon interposer 1. The copper pads and mating copper pads 104 of each group of functional chips are bonded together. All functional chips and the second dielectric material layer 103 are encapsulated to obtain a molded body. The lower part of each TSV copper pillar 101 is connected to a bump structure 4. The lower part of the bump structure 4 is bonded to the upper connecting pad at the corresponding position of the substrate 5. An adhesive filling layer 6 is provided on the outer periphery and bottom of the silicon interposer.

[0013] In a specific embodiment, the functional chipset includes a first functional chip D1 and a second functional chip D2, wherein the first functional chip D1 and the second functional chip D2 are logic chips and memory chips, respectively, and their number is not specifically limited. A copper pad D101 is disposed on the lower surface of the first functional chip D1, and a first dielectric material layer D102 is disposed around the copper pad D101. A copper pad D201 is disposed on the lower surface of the second functional chip D2, and a first dielectric material layer D202 is disposed around the copper pad D201.

[0014] The area occupied by the two sets of functional chips is smaller than the area of ​​the silicon interposer 1, which allows for the placement of a plastic encapsulation 2 between adjacent functional chips and around the two sets of functional chips. The upper surface of each functional chip is exposed after being ground and thinned to enhance heat dissipation and reduce the overall thickness of the package structure. The area of ​​substrate 5 is larger than the surface area of ​​a single silicon adapter plate 1. The adhesive filling layer 6 fills the gap between silicon adapter plate 1 and substrate 5. The adhesive filling layer 6 has the effect of blocking water and oxygen and buffering stress.

[0015] In a specific embodiment, the lower connecting pad of the substrate 5 is configured with a solder ball structure 7 through a ball-planting process.

[0016] A 2.5D packaging method for fabricating an ultra-thin 2.5D packaging structure, see [link to method]. Figures 1-12 First, a hybrid bonding process is used to solder the functional chip to the silicon interposer, ensuring face-to-face bonding without gaps. Next, wafer-level molding is performed, encapsulating the entire silicon interposer with a molding compound slightly larger than the 12-inch silicon interposer. The molded silicon interposer is then circumferentially cut to remove the edge molding compound. Following this, a back-side copper exposure process is performed, involving back-side grinding, a first chemical mechanical polishing (CMP), silicon etching, chemical vapor deposition (CVD), and a second CMP. C4 metal bumps are then added to the back of the silicon interposer using electroplating. The silicon interposer is then cut into individual chips. Each molded silicon interposer is then mounted onto a substrate. An underfill process is used to fill the gaps between the individual silicon interposers and the substrate with adhesive. Finally, solder ball joints are added to the back of the substrate, resulting in a single, ultra-thin 2.5D package.

[0017] In a specific embodiment, the functional chipset includes a first functional chip D1 and a second functional chip D2, wherein the first functional chip D1 and the second functional chip D2 are logic chips and memory chips, respectively, and their number is not specifically limited. A copper pad D101 is disposed on the lower surface of the first functional chip D1, and the copper pad D101 is surrounded by a first dielectric material layer D102. A copper pad D201 is disposed on the lower surface of the second functional chip D2, and the copper pad D201 is surrounded by a first dielectric material layer D202. The process includes the following steps: S1 uses a hybrid bonding process to bond several groups of functional chips to the upper surface of a silicon interposer. The dielectric material layer is silicon oxide. After hybrid bonding, the copper pad structures D101 and D201 on the surface of the functional chips are bonded to the corresponding copper pad structures 104 on the surface of the silicon interposer. The first dielectric material layers D102 and D202 on the surface of the functional chips are bonded to the corresponding second dielectric material layers 103 on the surface of the silicon interposer. Due to the extremely high flatness of the functional chips and the silicon interposer surface, there are no gaps between them after bonding. The first functional chip D1 and the second functional chip D2 are typically logic chips and memory chips, respectively. S2 performs wafer-level molding on the chip side of the silicon adapter board 1, covering all functional chip groups with molding compound. The thickness of the molding compound 2 exceeds the thickness of any functional chip group. The purpose is to prevent the back of the functional chips from being exposed. Since wafer-level molding cannot make the diameter of the molding compound equal to the diameter of the carrier, a full mold process is used. The diameter of the molding compound 2 is slightly larger than the diameter of the silicon adapter board 1. The silicon adapter board 1 is surrounded by a ring of molding compound. S3 grinds and thins the plastic cover to expose the back of the first functional chip D1 and the second functional chip D2, with the aim of enhancing the heat dissipation effect on the back. S4 uses a circumferential cutting process to remove the molding compound around the silicon adapter 1. The circumferential cutting depth exceeds the thickness of the molding compound 2 and extends below the upper surface of the silicon adapter 1. The depth of the circumferential cutting into the silicon adapter 1 exceeds the depth of the through-silicon via but does not penetrate the entire silicon adapter 1. Finally, a ring of molding compound 201 remains around the silicon adapter 1 near the back side. In specific implementation, the circumferential cutting process is either wheel circumferential cutting or laser circumferential cutting. S5 performs grinding and thinning and chemical mechanical polishing on the back side of the silicon adapter board 1 to expose the TSV copper pillars. At this time, the remaining ring of molding compound 201 after circumferential cutting has been cleaned by grinding. S6 performs silicon etching on the back of the silicon adapter board 1, so that the copper pillar TSV copper pillar 101 protrudes a certain height relative to the lower plane of the silicon. S7 deposits a third dielectric material layer 3 on the back side of the silicon interposer 1. The third dielectric material layer 3 is usually silicon oxide or silicon nitride, or a composite film of the two. S8 performs chemical mechanical polishing on the back side of the silicon adapter board 1, exposing the TSV copper pillar 101 after polishing, and the remaining thickness of the third dielectric material layer 3 must meet the insulation effect; S9 sets a bump structure 4 on the back of the silicon interposer 1 through sputtering a metal seed layer, photolithography and electroplating processes. The bump structure 4 is specifically a C4 bump structure, which usually contains several metal elements such as copper, nickel, tin and silver. S10 cuts the silicon interposer 1 into individual pieces and uses a flip-chip process to weld the individual silicon interposers to the upper surface of the substrate 5. S11 uses glue to fill the gap between the single silicon adapter board and the substrate to form glue filling layer 6, which plays the role of blocking water and oxygen and buffering stress. S12 utilizes a ball-planting process to create a solder ball structure on the back of the substrate, resulting in a single 2.5D package with an ultra-thin thickness that uses hybrid bonding technology.

[0018] The principle is as follows: The first dielectric material layer of several groups of functional chips is laid flat and attached to the upper surface of the second dielectric material layer of the silicon adapter board. That is, the first dielectric material layer on the lower surface of the functional chip is bonded to the second dielectric material layer at the corresponding position on the upper surface of the silicon adapter board. Due to the extremely high flatness of the functional chip and the silicon adapter board surface, there are no gaps between them after bonding. Furthermore, the copper pads of each group of functional chips and the mating copper pads are bonded. Thus, the bonding between the functional chip and the silicon adapter board is a hybrid bonding. Hybrid bonding replaces flip bonding, eliminating the solder joint structure, reducing the interconnection distance between chips, and reducing signal delay. Moreover, since the solder joint structure is eliminated, it is more conducive to reducing the thickness of the package. Finally, by using hybrid bonding instead of flip bonding, the gap between the chip and the adapter board disappears, thereby eliminating the flux cleaning process and the underfill process, shortening the process flow.

[0019] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0020] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A 2.5D packaging structure with ultra-thin thickness, characterized in that, It includes: A functional chipset, comprising at least two sets of functional chips, wherein a first dielectric material layer is disposed on the lower surface of each set of functional chips, and an exposed copper pad is disposed at the bottom of the first dielectric material layer. A silicon adapter board includes a silicon adapter board body, a second dielectric material layer on top, and a third dielectric material layer on the bottom. The surface of the second dielectric material layer is provided with exposed copper pads, and the interior of the second dielectric material layer is provided with metal circuits. The silicon adapter board body has built-in TSV copper pillars, the upper part of the TSV copper pillars is connected to the metal circuits at corresponding positions, and the lower part of the TSV copper pillars is inserted into the third dielectric material layer. Several bump structures; The substrate includes an upper connecting pad and a lower connecting pad; Plastic encapsulation; And the glue filler layer; A first dielectric material layer of several groups of functional chips is laid flat and attached to the upper surface of the second dielectric material layer of the silicon interposer. The copper pads and mating copper pads of each group of functional chips are bonded together. All functional chips and the second dielectric material layer are encapsulated to obtain a molded body. The lower part of each TSV copper pillar is connected to a bump structure. The lower part of the bump structure is bonded to the upper connecting pad at the corresponding position of the substrate. An adhesive filling layer is provided on the outer periphery and bottom of the silicon interposer.

2. The ultra-thin 2.5D packaging structure according to claim 1, characterized in that: The area occupied by several groups of functional chips laid out is smaller than the area of ​​the silicon adapter board.

3. The ultra-thin 2.5D packaging structure according to claim 1, characterized in that: The upper surface of each functional chip is exposed after being ground and thinned.

4. The ultra-thin 2.5D packaging structure according to claim 1, characterized in that: The functional chipset typically includes a logic chipset and a memory chipset, the number of which is arranged according to the actual situation.

5. The ultra-thin 2.5D packaging structure according to claim 1, characterized in that: The area of ​​the substrate is larger than the surface area of ​​a single silicon adapter plate, and the adhesive filler layer fills the gap between the silicon adapter plate and the substrate.

6. The ultra-thin 2.5D packaging structure according to claim 1, characterized in that: The lower layer connecting pad of the substrate is provided with a solder ball structure.

7. A method for fabricating an ultrathin 2.5D packaging structure as described in any one of claims 1-6, characterized in that: Hybrid bonding is used instead of flip-chip bonding, so that the chip is bonded to the mating copper pad on the silicon interposer board through copper pads, and the mating copper pads are connected to the TSV copper pillars through metal lines, and the TSV copper pillars are connected to the bump structure below, and the bump structure is connected to the corresponding upper layer of the substrate through pad bonding.

8. The 2.5D packaging method for ultra-thin thickness according to claim 7, characterized in that, It includes the following steps: S1 uses a hybrid bonding process to bond several groups of functional chips to the upper surface of the silicon interposer. S2 performs wafer-level molding on the chip side of the silicon adapter board, encapsulating all functional chipsets with molding compound; S3 grinds and thins the plastic cover to expose the back of the functional chip; S4 uses a ring-cutting process to remove the molding compound around the silicon interposer. S5 performs grinding and thinning and chemical mechanical polishing on the back of the silicon interposer to expose the TSV copper pillars; S6 performs silicon etching on the back of the silicon adapter board, causing the TSV copper pillars to protrude a certain height relative to the lower plane of the silicon. S7 deposits a third dielectric material layer on the back side of the silicon interposer. S8 performs chemical mechanical polishing on the back of the silicon interposer, exposing the TSV copper pillars after polishing, and the remaining thickness of the third dielectric material layer must meet the insulation requirements; S9 sets a bump structure on the back of the silicon interposer through sputtering a metal seed layer, photolithography, and electroplating processes; S10 cuts the silicon interposer into individual pieces and uses a flip-chip process to solder the individual silicon interposer to the upper surface of the substrate. S11 uses glue to fill the gap between a single silicon adapter board and the substrate, forming a glue filling layer; S12 utilizes a ball-planting process to create a solder ball structure on the back of the substrate, resulting in a single 2.5D package with an ultra-thin thickness that uses hybrid bonding technology.

9. The 2.5D packaging method with ultra-thin thickness according to claim 8, characterized in that: In step S1, a copper pad is provided on the lower surface of each functional chip. The copper pad is surrounded by a first dielectric material layer. A TSV copper pillar structure is provided inside the silicon interposer, and a mating copper pad is provided on its surface. Similarly, a second dielectric material layer is provided around the mating copper pad. The second dielectric material layer also contains metal lines connecting the TSV copper pillar and the mating copper pad. The copper pad on the surface of each functional chip is bonded to the mating copper pad at the corresponding position on the surface of the silicon interposer. The first dielectric material layer on the lower surface of the functional chip is bonded to the second dielectric material layer at the corresponding position on the upper surface of the silicon interposer. Due to the extremely high flatness of the functional chip and the silicon interposer surface, there are no gaps between them after bonding.

10. The 2.5D packaging method with an ultra-thin thickness according to claim 8, characterized in that: In step S4, the ring cutting depth exceeds the thickness of the molding compound and extends below the upper surface of the silicon adapter plate. The ring cutting depth extends into the silicon adapter plate to a depth exceeding the depth of the through-silicon via, but does not penetrate the entire silicon adapter plate. Finally, a ring of molding compound remains around the silicon adapter plate near the back side.

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