Merge candidate reordering based on global motion vector

Abstract

A decoder includes circuitry configured to receive a bitstream, construct a motion vector candidate list for a current block including motion vector candidates with motion information describing global motion vectors, reorder the motion vector candidate list such that the motion vector candidates with motion information characterizing the global motion vectors are placed first in the reordered motion vector candidate list, and reconstruct pixel data of the current block and use the reordered motion vector candidate list. Related apparatuses, systems, techniques and articles are also described.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 856,339, filed June 3, 2019, entitled “Merger Candidate Reordering Based on Global Motion Vectors,” which is incorporated herein by reference in its entirety. Technical Field

[0003] This invention generally relates to the field of video compression. In particular, this invention relates to merging candidate reordering based on global motion vectors. Background Technology

[0004] A video codec can include electronic circuitry or software that compresses or decompresses digital video. It can convert uncompressed video into a compressed format and vice versa. In the case of video compression, the device that compresses the video (and / or performs some of the functions of that device) is generally called an encoder, while the device that decompresses the video (and / or performs some of the functions of that device) is called a decoder.

[0005] The format of compressed data can conform to standard video compression specifications. Compression may be lossy because compressed video lacks some information present in the original video. Such results may include decompressed video having lower quality than the original uncompressed video because there is not enough information to accurately reconstruct the original video.

[0006] There can be complex relationships between video quality, the amount of data used to represent the video (e.g., determined by bit rate), the complexity of encoding and decoding algorithms, sensitivity to data loss and errors, ease of editing, random access, end-to-end latency (e.g., waiting time), and so on.

[0007] Motion compensation can include a method that predicts a video frame or a portion of a given reference frame (e.g., previous and / or future frames) by taking into account the motion of objects in the camera and / or video. It can be used in the encoding and decoding of video data for video compression, such as encoding and decoding using the Moving Picture Experts Group (MPEG)-2 (also known as High-Level Video Coding (AVC) and H.264) standards. Motion compensation can describe an image based on the transformation from a reference image to the current image. The reference image may be temporally previous when compared to the current image, and may be from the future when compared to the current image. Compression efficiency can be improved when images can be accurately synthesized from previously transmitted and / or stored images. Summary of the Invention

[0008] In one aspect, a decoder includes circuitry configured to receive a bitstream; build a motion vector candidate list for a current block, the motion vector candidate list containing a motion vector candidate having motion information characterizing a global motion vector; reorder the motion vector candidate list such that the motion vector candidate having the motion information characterizing the global motion vector is first in the reordered motion vector candidate list; and reconstruct pixel data of the current block using the reordered motion vector candidate list.

[0009] In another aspect, a method includes receiving, by a decoder, a bitstream; building a motion vector candidate list for a current block, the motion vector candidate list containing a motion vector candidate having motion information characterizing a global motion vector; reordering the motion vector candidate list such that the motion vector candidate having the motion information characterizing the global motion vector is first in the reordered motion vector candidate list; and reconstructing pixel data of the current block using the reordered motion vector candidate list.

[0010] The details of one or more variations of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features and advantages of the subject matter described herein will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0011] To illustrate the present application, the accompanying drawings show various aspects of one or more embodiments of the present application. It will be appreciated, however, that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, wherein:

[0012] Figure 5 is a process flow diagram in accordance with some example implementations of the current subject matter;

[0013] Figure 6 is a system block diagram of an example decoder in accordance with some example implementations of the current subject matter;

[0014] Figure 7 is a process flow diagram in accordance with some example implementations of the current subject matter;

[0015] Figure 8 is a system block diagram of an example encoder in accordance with some example implementations of the current subject matter;

[0016] Figure 1 is a diagram illustrating motion vectors of example frames having global and local motion;

[0017] Figure 4 three example motion models that can be used for global motion are illustrated, including index values (0, 1, or 2) for the three example motion models;

[0018] Figure 2 is a block diagram illustrating spatial candidates considered in the method of merge mode;

[0019] Figure 3 is a block diagram illustrating global motion vectors considered in the method of merge mode and associated spatial candidates; and

[0020] Figure 9 is a block diagram of a computing system that can be used to implement any one or more of the methods disclosed herein and any one or more portions thereof.

[0021] The drawings are not necessarily to scale and, in certain instances, certain details can have been omitted for the sake of clarity. In the various drawings, like reference numerals designate like elements. DETAILED DESCRIPTION

[0022] Global motion in a video refers to motion that occurs throughout a frame. Global motion can be caused by camera motion, for example, camera panning and zooming, which creates motion that can typically affect the entire frame. Motion that exists in some portions of a video can be referred to as local motion. Local motion can be caused by moving objects in a scene. For example, an object moving from left to right in a scene. A video can contain a combination of local and global motion. Some implementations of the current subject matter can provide for constructing a merge candidate list based on global motion vectors, which can improve compression by reducing the bits necessary to signal candidates and encode motion vector differences.

[0023] Figure 1 is a diagram illustrating motion vectors of an example frame 100 having global and local motion. Frame 100 can include a plurality of blocks of pixels shown as squares, and motion vectors associated with them shown as arrows. Squares with arrows pointing upwards and to the left (e.g., pixel blocks) indicate blocks with motion that can be considered global motion, and squares with arrows pointing in other directions (indicated by 104) indicate blocks with local motion. In the example shown in Figure 1 In the example shown in

[0024] As an example, and continuing to refer to Figure 1 a motion vector (MV) having two components MV x , MV y may be used to describe simple translational motion, the MV x , MV yDisplacements of blocks and / or pixels in the current frame are described. More complex motions such as rotations, scaling, and warping can be described using affine motion vectors, where an "affine motion vector" as used in this disclosure is a vector that describes a uniform displacement of a set of pixels or points represented in a video image and / or picture, e.g., describing a set of pixels that illustrate movement of an object across views in a video without changing appearance shape during the motion. Some methods of video encoding and / or decoding can use a four-parameter or six-parameter affine model for motion compensation in inter-image coding.

[0025] For example, a six-parameter affine motion model can be described as:

[0026] x' = ax + by + c

[0027] y' = dx + ey + f

[0028] A four-parameter affine motion can be described as:

[0029] x' = ax + by + c

[0030] y' = -bx + ay + f

[0031] where (x, y) and (x', y') are the pixel positions in the current and reference images, respectively; a, b, c, d, e, and f are the parameters of the affine motion model.

[0032] With continued reference to Figure 1 Block- and / or sub-block-based affine transform motion compensation prediction can alternatively or additionally be applied. The affine motion region of a block and / or sub-block can be described by motion information of two control points (four-parameter) or three control point motion vectors (six-parameter). In the four-parameter affine motion model, the motion vector at a sample position (x, y) in the block can be derived as:

[0033]

[0034] For the six-parameter affine motion model, the motion vector at a sample position (x, y) in the block can be derived as:

[0035]

[0036] where (mv 0x , mv 0y ) is the motion vector of the top-left control point, (mv 1x , mv 1y ) is the motion vector of the top-right control point, and (mv 2x , mv 2y ) is the motion vector of the bottom-left control point.

[0037] To simplify motion-compensated prediction, block-based affine transform prediction can be applied. As an illustrative example, to derive the motion vector for each 4x4 luma sub-block, the motion vector of the center sample of each sub-block can be calculated according to the above equation and rounded to 1 / 16 fraction accuracy. A motion-compensated interpolation filter can then be applied to generate the prediction for each sub-block using the derived motion vector. Continuing with this example, the sub-block size for the chroma components can also be set to 4x4. The motion vector for a 4x4 chroma sub-block can be calculated as the average of the MVs of the four corresponding 4x4 luma sub-blocks.

[0038] As with translational inter-prediction, there are also two affine inter-prediction modes: affine merge mode and affine AMVP mode. Referring still to Figure 1 The parameters used to describe the affine motion can be signaled to the decoder to apply affine motion compensation at the decoder. In some approaches, the motion parameters can be signaled explicitly or by signaling translational control point motion vectors (CPMVs) and deriving the affine motion parameters from the translational motion vectors. Two control point motion vectors (CPMVs) can be utilized to derive the affine motion parameters of a four-parameter affine motion model and three control point translational motion vectors (CPMVs) to obtain the parameters of a six-parameter motion model. Signaling the affine motion parameters using control point motion vectors can allow the affine motion parameters to be signaled using efficient motion vector coding methods.

[0039] Continuing with the Figure 1 Some blocks can share the same motion vector information. For example, two blocks corresponding to an object moving across the screen can share the same motion vector because they both relate to the same object. In such cases, some approaches to motion compensation can utilize a merge mode in which a neighboring block can share a motion vector that allows the motion information of a first block to be coded in the bitstream and a second block can inherit the motion information from the first block (e.g., merge with the first block). During encoding, a merge list can be constructed containing available merge candidates. A merge candidate can be selected from the constructed merge list and an index to the merge list can be signaled in the bitstream. During decoding, the merge list can again be constructed from available merge candidates and the index signaled in the bitstream can be used to indicate from which block the current block will inherit the motion information (e.g., merge with which block).

[0040] Figure 2For an exemplary embodiment showing spatial candidates considered in typical methods such as merge mode implemented for HEVC, a block diagram 200 is shown. A current block 204 can include a coding unit or a prediction unit. Spatial merge candidates can include A0, Al, B0, Bl, and B2. A0, Al, B0, and B2 can include neighboring prediction and / or coding units. When creating a merge candidate list, the list can be constructed by considering up to four spatial merge candidates derived from five spatial neighboring blocks, as shown in Figure 2 In this example, a threshold of five spatial candidates can be applied. In addition to considering spatial candidates as explained in Figure 2 In addition to the spatial candidates explained in

[0041] Still referring to Figure 2 , spatial merge candidates can be added to the merge list in response to determining that they are available. In a quad-tree plus binary decision tree (QTBT) partitioning, some of the neighboring blocks can be asymmetric blocks and thus the neighboring blocks can not be considered as spatial merge candidates because they can be asymmetric partitions as the partitions (e.g., prediction units) do not share similar motion information.

[0042] As described above, and with continued reference to Figure 2 In some methods of video coding, a merge candidate list can be constructed based on: up to four spatial merge candidates derived from five spatial neighboring blocks; one temporal merge candidate derived from two temporally co-located blocks; an additional merge candidate including a combined bi-predictive candidate; and a zero motion vector candidate.

[0043] Still referring to Figure 2 To derive the list of spatial candidates, (a) a neighboring block can be checked for availability and whether it contains motion information, and (b) a redundancy check to avoid candidates in the list having redundant motion data.

[0044] With continued reference to Figure 2 When N is the number of spatial merge candidates, a full redundancy check can consist of Nx(N-1) / 2 motion data comparisons. In the case of five potential merge candidates, ten motion data comparisons can be used, such that all candidates in the merge list have different motion data. This can result in an increased complexity of the decoder.

[0045] In some methods of video coding, and still referring to Figure 2To improve coding efficiency, after constructing the merge candidate list (the processing order of spatial candidate positions is Al, Bl, B0, A0, B2), the ranking of each merge candidate is adjusted according to template matching cost. The template matching cost can be measured by the sum of absolute difference (SAD) between neighboring samples of the current coding unit (CU) and their corresponding reference samples. For example, without limitation, the merge candidates can be ranked in increasing order of the SAD calculated for the merge candidates. The number of merge candidates selected using the template matching cost can be limited. For example, a set of four lowest cost candidates out of the five originally generated and / or provided candidates can be selected.

[0046] Still referring to Figure 2 Some implementations of the current subject matter can further improve coding efficiency by reordering the merge candidates using global motion vectors. As used in this disclosure, global motion in a video refers to motion that occurs in the entire frame. Global motion can typically be caused by camera motion that affects the entire frame such as camera pan and zoom.

[0047] Still referring to Figure 3 Some implementations of the current subject matter can create a merge candidate list based on motion vectors signaled to the decoder. If global motion is signaled, this global motion can be expected to be shared by many blocks in the frame. For example, as illustrated for exemplary purposes in Updated (reordered) merge candidate list Table 1, three out of the five spatial merge candidates (Bl, B2, and Al) can be signaled based on the global motion. Based on the signaling, at the decoder, the decoder can create the following merge candidate list. They are ordered such that the global motion candidate is the first candidate in the list, as shown in Table 1.

[0048] B1-GMV1 B2-GMV2 A1-GMV3 Figure 2 B0 A0

[0049] Still referring to Figure 2 Since a block can have motion similar to the global motion, modifying the list such that the global motion vector is the first candidate in the list can reduce the bits necessary to signal the prediction candidate and encode the motion vector difference. In this way, motion vector coding can be improved and the bit rate can be reduced, which will improve compression efficiency.

[0050] In some implementations, and continuing to refer to Figure 4 The global motion signaling can be included in a header such as PPS or SPS. The global motion can vary from image to image. The motion vector signaled in the image header can describe the motion relative to a previously decoded frame. In some implementations, the global motion can be translational or affine. The motion mode used, such as the number of parameters, whether the model is affine, translational, or similar, can also be signaled in the picture header. Figure 4Three exemplary embodiments of the motion model 600 are shown, which can be used for global motion, including their index values (0, 1, or 2).

[0051] Still referring to Figure 4 The translation CPMV can be signaled in the PPS. The control points can be predefined. For example, the control point MV0 can be related to the top-left corner of the picture, MV1 can be related to the top-right corner of the picture, and MV3 can be related to the bottom-left corner of the picture.

[0052] Continuing to refer to Figure 5 The global motion can be related to a previously encoded frame. When there is only one set of global motion parameters, the motion can be relative to the frame immediately preceding the current frame.

[0053] Figure 5 is a process flow diagram showing an exemplary embodiment of a process 500 for reordering of merge candidates based on global motion vectors.

[0054] At step 505, and still referring to Figure 5 , a decoder receives a bitstream including a current block. The current block can be included in a bitstream received by the decoder. The bitstream can include data found in a bitstream input to the decoder, for example, when using data compression. The bitstream can include information necessary to decode a video. Receiving can include extracting and / or parsing the block and associated signaling information from the bitstream. In some implementations, the current block can include a coding tree unit (CTU), a coding unit (CU), or a prediction unit (PU).

[0055] At step 510, and further referring to Figure 5 A motion vector candidate list including motion information characterizing global motion vectors can be constructed for the current block. The global motion vectors can be characterized by a header of the bitstream, the header including a picture parameter set (PPS) and / or a sequence parameter set (SPS).

[0056] At step 515, and continuing to refer to Figure 5 , the motion vector candidate list is reordered such that the motion vector candidate having motion information characterizing global motion vectors is listed first in the reordered motion vector candidate list. The reordering can include inserting a first global motion vector candidate into the merge candidate list. In some implementations, the construction of the motion vector candidate list can include the reordering.

[0057] At step 520, and further referring to Figure 5 The reordered motion vector candidate list can be used to reconstruct pixel data of the current block.

[0058] Still referring to Figure 6In some implementations, the decoder can be configured to determine that global motion is indicated for a current frame that contains the current block. The global motion vector can include a control point motion vector. The control point motion vector can include a translation motion vector. The control point motion vector can include a vector of a four-parameter affine motion model or a six-parameter affine motion model.

[0059] Figure 6 is a system block diagram illustrating an example decoder 600 that can decode a bitstream based on reordering of merge candidates of global motion vectors. The decoder 600 can include an entropy decoder processor 604, an inverse quantization and inverse transform processor 608, a deblocking filter 612, a frame buffer 616, a motion compensation processor 620, and / or an intra prediction processor 624.

[0060] In operation, and still referring to Figure 7 The bitstream 628 can be received by the decoder 600 and input to the entropy decoder processor 604, which entropy decodes portions of the bitstream into quantized coefficients. The quantized coefficients can be provided to the inverse quantization and inverse transform processor 608, which can perform inverse quantization and inverse transform to create a residual signal that can be added to an output of the motion compensation processor 620 or the intra prediction processor 624 depending on the processing mode. The output of the motion compensation processor 620 and the intra prediction processor 624 can include block predictions based on previously decoded blocks. The sum of the predictions and the residual can be processed by the deblocking filter 612 and stored in the frame buffer 616.

[0061] Figure 8 is a process flow diagram illustrating an example embodiment of a process 700 that encodes a video based on reordering of merge candidates of global motion vectors in accordance with some aspects of the current subject matter that can reduce encoding complexity while improving compression efficiency. At step 705, a video frame can be initially block partitioned, e.g., using a macroblock partitioning scheme that can include partitioning an image frame into CTUs and CUs using a tree structure.

[0062] At step 710, a candidate list can be determined. The candidate list can be based on global motion for a current block. The candidate list can include motion vector candidates having motion information that characterizes a global motion vector. The list of motion vector candidates can be reordered such that the motion vector candidate having motion information that characterizes the global motion vector is listed first in the reordered list of motion vector candidates. The reordering can include inserting a first global motion vector candidate into the merge candidate list. In some implementations, the construction of the list of motion vector candidates can include the reordering.

[0063] At step 715, the block can be encoded and included in the bitstream. As a non-limiting example, the encoding can include utilizing inter-prediction modes and intra-prediction modes. More specifically, the reordered index of the candidate list can be included and / or encoded into the bitstream for use by a decoder.

[0064] Figure 8 To illustrate a system block diagram of an example video encoder 800 that is capable of encoding video based on reordered merging candidates of global motion vectors. The example video encoder 800 can receive an input video 804, which can be initially partitioned or divided according to a tree-structured macroblock partitioning scheme (e.g., quad-tree plus binary tree). Examples of tree-structured macroblock partitioning schemes can include dividing an image frame into large block elements called coding tree units (CTUs). In some implementations, each CTU can be further divided into one or more sub-blocks called coding units (CUs). The end result of this division can include a group of sub-blocks called prediction units (PUs). Transform units (TUs) can also be used.

[0065] Still referring to Figure 8 , the example video encoder 800 can include an intra-prediction processor 808, a motion estimation / compensation processor 812, which can also be referred to as an inter-prediction processor, capable of constructing a motion vector candidate list, including adding global motion vector candidates to the motion vector candidate list, a transform / quantization processor 816, an inverse quantization / inverse transform processor 820, an in-loop filter 824, a decoded picture buffer 828, and / or an entropy encoding processor 832. Bitstream parameters can be input to the entropy encoding processor 832 for inclusion in an output bitstream 836.

[0066] In operation, and continuing to refer to Figure 8 , for each block of a frame of the input video 804, a determination can be made as to whether the block is to be processed by intra-prediction or using motion estimation / compensation. The block can be provided to the intra-prediction processor 808 or the motion estimation / compensation processor 812. If the block is to be processed by intra-prediction, the intra-prediction processor 808 can perform processing to output a prediction value. If the block is to be processed by motion estimation / compensation, the motion estimation / compensation processor 812 can perform processing including constructing a motion vector candidate list, including adding global motion vector candidates to the motion vector candidate list, if applicable.

[0067] Further referring to Figure 8Residuals can be formed by subtracting the predictor from the input video. The residuals can be received by transform / quantization processor 816, which can perform a transform process (e.g., a discrete cosine transform (DCT)) to produce coefficients that can be quantized. The quantized coefficients and any associated signaling information can be provided to entropy encoding processor 832 for entropy encoding and inclusion in output bitstream 836. Entropy encoding processor 832 can support encoding of signaling information related to encoding the current block. In addition, the quantized coefficients can be provided to inverse quantization / inverse transform processor 820, which can reproduce pixels that can be combined with the predictor and processed by in-loop filter 824, which outputs can be stored in decoded picture buffer 828 for use by motion estimation / compensation processor 812, which can be capable of constructing a motion vector candidate list, including adding a global motion vector candidate to the motion vector candidate list.

[0068] With continued reference to Figure 8 While some variations have been described in detail above, other modifications or additions are possible. For example, in some implementations, the current block can include any symmetric block (8x8, 16x16, 32x32, 64x64, 128x128, etc.) as well as any asymmetric block (8x4, 16x8, etc.).

[0069] In some implementations, and still referring to Figure 8 A quad-tree plus binary decision tree (QTBT) can be implemented. In the QTBT, at the coding tree unit layer, the partition parameters of the QTBT are derived dynamically to adapt to local characteristics without transmitting any overhead. Subsequently, at the coding unit layer, a joint classifier decision tree structure can eliminate unnecessary iterations and control the risk of error prediction. In some implementations, the LTR frame block update mode can be used as an additional option available at each leaf node of the QTBT.

[0070] In some implementations, and still referring to Figure 9 Additional syntax elements can be signaled at different levels of the bitstream. For example, a flag can be enabled for an entire sequence by an enabling flag encoded in a sequence parameter set (SPS). In addition, a CTU flag can be encoded at the coding tree unit (CTU) layer.

[0071] It should be noted that as would be apparent to one of ordinary skill in the computer arts, any of the aspects and embodiments described herein can be conveniently implemented using digital electronic circuitry, integrated circuitry, specially designed application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), computer hardware, firmware, software, and / or combinations thereof programmed according to the teachings of the present specification and implemented within one or more machines, such as one or more computing devices used as user computing devices for electronic documents, one or more server devices such as document servers, and the like, that are programmed with the teachings of the present specification. These various aspects or features can include implementation in one or more computer programs and / or software that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device. Those of ordinary skill in the software art will appreciate that the skilled programmer can easily develop an appropriate software coding based on the teachings of the present disclosure. The aspects and implementations discussed above employing software and / or software modules can also include appropriate hardware for assisting in the implementation of the machine executable instructions of the software and / or software modules.

[0072] Such software can be in the form of a computer program product which can employ a machine-readable storage medium. The machine-readable storage medium can be any medium that can store and / or encode a sequence of instructions for execution by a machine (e.g., a computing device) and that causes the machine to perform any one of the methodologies and / or embodiments described herein. Examples of machine-readable storage media include, but are not limited to, magnetic disks, optical disks (e.g., CD, CD-R, DVD, DVD-R, etc.), magneto-optical disks, read-only memory (ROM) devices, random access memory (RAM) devices, magnetic cards, optical cards, solid-state memory devices, EPROM, EEPROM, programmable logic devices (PLDs), and / or any combination thereof. Machine-readable media as used herein does not include transitory forms of signal transmission. As used herein, a "computer-readable medium" can include one or more memory devices and / or storage devices configured to store the program means during the execution by a computer, a machine and / or a processor. As used herein, a "computer-readable medium" can include one or more memories (e.g., volatile memory, non-volatile memory, etc.) and / or storage devices (e.g., removable storage devices, non-removable storage devices, etc.). As used herein, a "computer-readable medium" does not include propagating signals per se.

[0073] Such software can also include information (e.g., data) carried by a data signal, such as a carrier wave. For example, machine-executable information can include a data carrying signal that encodes a sequence of instructions or a portion thereof for execution by a machine (e.g., a computing device), as well as any related information (e.g., data structures and data) that causes the machine to perform any of the methods and / or embodiments described herein.

[0074] Examples of computing devices include, without limitation, e-book readers, computer workstations, terminal computers, server computers, handheld devices (e.g., tablet computers, smart phones, etc.), network devices, network routers, network switches, network bridges, any machine capable of executing a sequence of instructions

[0075] ​ An illustration of one embodiment is shown, which is a computing device in the exemplary form of a computer system 900 within which instructions for causing a control system to perform any one or more of the aspects and / or methods of the present disclosure can be executed. It is also contemplated that a plurality of computing devices can be utilized to implement a specially configured instruction set for causing one or more of the devices to perform any one or more of the aspects and / or methods of the present invention. The computer system 900 includes a processor 904 and a memory 908 that are in communication with each other via a bus 912. The bus 912 can include any of several types of bus structures including, but not limited to, memory buses, memory controller, a peripheral bus, a local bus, and any combinations thereof, using any of a variety of bus architectures, including, but not limited to, Industrial Standard Architecture (ISA), Micro Channel Architecture (MCA), Enhanced ISA (EISA), Video Electronics Standards Association (VESA), and Accelerated Graphics Port (AGP) bus.

[0076] The memory 908 can include various components (e.g., machine-readable media), including, but not limited to, a random access memory component, a read only component, and any combinations thereof. In one example, a basic input / output system 916 (BIOS), including, for example, a basic routine that helps to transfer information between elements within the computer system 900 during startup, can be stored in the memory 908. The memory 908 can also include (e.g., stored on one or more machine-readable media) instructions (e.g., software) 920 embodying any one or more of the aspects and / or methods of the present disclosure. In another example, the memory 908 can also include any number of program modules including, but not limited to, an operating system, one or more application programs, other program modules, program data, and any combinations thereof.

[0077] The computer system 900 can also include a storage device 924. Examples of storage devices (e.g., the storage device 924) include, but are not limited to, a hard disk drive, a magnetic disk drive, an optical disk drive in combination with an optical medium, a solid-state memory device, and any combinations thereof. The storage device 924 can be connected to the bus 912 by an appropriate interface (not shown). Exemplary interfaces include, but are not limited to, SCSI, Advanced Technology Attachment (ATA), Serial ATA, Universal Serial Bus (USB), IEEE 1394 (FIREWIRE), and any combinations thereof. In one example, the storage device 924 (or one or more components of the storage device 924) can be removably interfaced with the computer system 900 (e.g., via an external port connector (not shown)). In particular, the storage device 924 and an associated machine-readable medium 928 can provide non-volatile and / or volatile storage of machine-readable instructions, data structures, program modules, and / or other data for the computer system 900. In one example, the software 920 can reside entirely within the machine-readable medium 928. In another example, the software 920 can reside, completely or at least partially, within the processor 904.

[0078] The computer system 900 can also include an input device 932. In one example, a user of the computer system 900 can enter commands and / or other information into the computer system 900 via the input device 932. Examples of input devices 932 include, but are not limited to, alphanumeric input devices (e.g., a keyboard), pointing devices, joysticks, gamepads, audio input devices (e.g., microphones, voice response systems, etc.), cursor control devices (e.g., a mouse), touchpads, optical scanners, video capture devices (e.g., still cameras, video cameras), touch screens, and any combinations thereof. The input device 932 can be interfaced to the bus 912 via any of a variety of interfaces (not shown), including but not limited to a serial interface, a parallel interface, a game port, a USB interface, a FIREWIRE interface, a direct interface to the bus 912, and any combinations thereof. The input device 932 can include a touch screen interface, which can be part of the display 936 or separate from the display 936, as will be discussed further below. The input device 932 can be used as a user selection device for selecting one or more graphical representations in a graphical interface as described above.

[0079] A user can also enter commands and / or other information to the computer system 900 via storage devices 924 (e.g., a removable disk drive, a flash drive, etc.) and / or a network interface device 940. A network interface device, such as the network interface device 940, can be used to connect the computer system 900 to one or more of a variety of networks, such as the network 944, and one or more remote devices 948 connected thereto. Examples of network interface devices include, but are not limited to, a network interface card (e.g., a mobile network interface card, a LAN card), a modem, and any combination thereof. Examples of networks include, but are not limited to, wide area networks (e.g., the Internet, an enterprise network), local area networks (e.g., a network associated with an office, a building, a campus, or other relatively small geographic space), telephone networks, data networks associated with a telephone / voice provider (e.g., a mobile communication provider data and / or voice network), a direct connection between two computing devices, and any combination thereof. A network, such as the network 944, can employ a wired and / or a wireless mode of communication. In general, any network topology can be used. Information (e.g., data, the software 920, etc.) can be communicated to and / or from the computer system 900 via the network interface device 940.

[0080] The computer system 900 can also include a video display adapter 952 for transmitting a displayable image to a display device, such as the display device 936. Examples of display devices include, but are not limited to, liquid crystal displays (LCDs), cathode ray tubes (CRTs), plasma displays, light emitting diode (LED) displays, and any combination thereof. The display adapter 952 and the display device 936 can be used in combination with the processor 904 to provide a graphical representation of aspects of the present disclosure. In addition to a display device, the computer system 900 can include one or more other peripheral output devices including, but not limited to, audio speakers, a printer, and any combination thereof. Such peripheral output devices can be connected to the bus 912 via a peripheral interface 956. Examples of peripheral interfaces include, but are not limited to, a serial port, a USB connection, a FIREWIRE connection, a parallel connection, and any combination thereof.

[0081] The foregoing is a detailed description of illustrative embodiments of the application. Various modifications and additions can be made without departing from the spirit and scope of the application. Each of the aforementioned embodiments can stand on its own, or can be combined in various permutations and combinations. Further, although the above description has been described with reference to particular divisions of the embodiments, the disclosure is not limited to such divisions. Additionally, although a particular method can be shown and / or described as being performed in a particular order, this order is highly variable within the scope of the embodiments disclosed herein. Accordingly, this description is meant to be taken only by way of example and not to otherwise limit the scope of this application.

[0082] In the descriptions above and in the claims, phrases such as“at least one” or“one or more” can occur followed by a conjunctive list of elements or features. The term“and / or” can also occur in a list of two or more elements or features. Unless otherwise implicitly or explicitly contradicted by the context in which it used, such a phrase is intended to mean any of the listed elements or features individually or any of the recited elements or features in combination with any of the other recited elements or features. For example, the phrases“at least one of A and B;”“one or more of A and B;” and“A and / or B” each mean“A alone, B alone, or A and B together.” Similar

[0083] The subject matter described herein can be embodied in systems, devices, methods, and / or articles depending on the desired configuration. The implementations set forth in the foregoing description do not represent all implementations consistent with the subject matter described herein. Instead, they are merely some examples consistent with aspects related to the described subject matter. Although a few variations have been described in detail above, other modifications or additions are possible. In particular, further features and / or variations can be provided in addition to those set forth herein. For example, the implementations described above can be directed to various combinations and sub-combinations of the disclosed features and / or combinations and sub-combinations of several of the disclosed features. In addition, the logic flows depicted in the accompanying figures and / or described herein do not necessarily require the particular order shown, or sequential order, to achieve desirable results. Other implementations can be within the scope of the following claims.

Claims

1. A decoder comprising circuitry configured to: receive a bitstream comprising an encoded image, the encoded image comprising a first region having a plurality of first coding units and a second region having a plurality of second coding units; constructing a motion vector candidate list for each coding unit in the first region, each of the motion vector candidate lists having a common motion vector, wherein the motion vector candidate list is ordered such that the common motion vector is ranked first; decode the plurality of first coding units using the common motion vector from the motion vector candidate list, thereby reconstructing in the first region an image region having common motion; determine from the bitstream an independently determined motion vector for each coding unit of the second region, wherein neighboring coding units in the second region have different independently determined motion vectors, each independently determined motion vector being one of a translational motion vector or a control point motion vector for a four-parameter or six-parameter affine motion; and decode the plurality of second coding units using the independently determined motion vectors, thereby reconstructing in the second region local motion.

2. The decoder of claim 1, configured to determine that global motion is indicated for the encoded image. the common motion vector comprises a control point motion vector.

3. The decoder of claim 1, wherein, the control point motion vector is a translational motion vector.

4. The decoder of claim 3, wherein, the control point motion vector is a vector of a four-parameter affine motion model.

5. The decoder of claim 3, wherein, the control point motion vector is a vector of a six-parameter affine motion model.

6. The decoder of claim 3, wherein, 7. The decoder of claim 1, further comprising: an entropy decoder processor configured to receive the bitstream and decode the bitstream into quantized coefficients; an inverse quantization and inverse transform processor configured to process quantized coefficients, including performing inverse discrete cosine; a deblocking filter; a frame buffer; and an intra prediction processor. at least one coding unit of the plurality of first coding units forms part of a quadtree plus binary decision tree.

8. The decoder of claim 1, wherein, at least one coding unit of the plurality of first coding units is a coding tree unit.

9. The decoder of claim 1, wherein, at least one coding unit of the plurality of first coding units is a coding unit.

10. The decoder of claim 1, wherein, ​

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