System on chip and method for regulating voltage and frequency

Abstract

Provided are a system on chip and a method for adjusting voltage and frequency. The system on chip includes: a processing unit, which is used to periodically send a first frequency and voltage modulation instruction at a predetermined time interval; a hardware monitoring unit, which is used to obtain a real-time performance detection signal within a predetermined time interval, and send a second frequency and voltage modulation instruction according to the performance detection signal; a frequency and voltage modulation controller, which is used to adjust the clock frequency and supply voltage according to the first frequency and voltage modulation instruction and the second frequency and voltage modulation instruction; an on-chip bus, which is used to couple the processing unit, the hardware monitoring unit and the frequency and voltage modulation controller. According to an embodiment of the present disclosure, between two first frequency and voltage modulation instructions sent by a software program, the hardware monitoring unit decides whether to send the second frequency and voltage modulation instruction, which helps to solve the problem of inaccurate software prediction and can respond to the frequency and voltage modulation needs of the system more quickly.

Description

Technical Field

[0001] The present disclosure relates to the field of chips, and in particular to a system on chip and a method for adjusting voltage and frequency. Background Art

[0002] The trend of miniaturization of integrated circuits has made processor manufacturers enthusiastic about how to reduce power consumption. There are two main ways to reduce power consumption of processors: Dynamic Voltage and Frequency Scaling (DVFS) and Adaptive Voltage and Frequency Scaling (AVFS). DVFS dynamically adjusts the system's clock frequency and supply voltage according to the different computing power requirements of the applications running on the processor, thereby achieving the purpose of energy saving. AVFS determines the supply voltage by measuring the detection data in real time through sensors.

[0003] For DVFS system or AVFS system, the operating system will adjust the clock frequency at fixed intervals. The general practice is to define an independent timer to initiate an interrupt at a certain period of time (for example, 20ms). In the interrupt service program, the processing unit will predict the load conditions of the next frequency modulation cycle (20ms) and initiate frequency and voltage regulation requests based on the load conditions.

[0004] The disadvantage of this solution is that frequency and voltage regulation requests are initiated at intervals. If the time interval is set too long, it may not meet the frequency regulation requirements. If it is set too short, it may cause additional system overhead due to frequent interruptions, which is not worth the cost in improving system performance. Summary of the invention

[0005] In view of this, an object of the present disclosure is to provide a system on chip and a method for adjusting voltage and frequency to solve the problems in the prior art.

[0006] In a first aspect, an embodiment of the present disclosure provides a system on chip, including:

[0007] A processing unit, configured to periodically send a first frequency and voltage modulation instruction at a predetermined time interval;

[0008] A hardware monitoring unit, configured to obtain a real-time performance detection signal within the predetermined time interval, and send a second frequency and voltage modulation instruction according to the performance detection signal;

[0009] A frequency modulation and voltage regulation controller, used for adjusting the clock frequency and the supply voltage according to the first frequency modulation and voltage regulation instruction and / or the second frequency modulation and voltage regulation instruction;

[0010] The on-chip bus is used to couple the processing unit, the hardware monitoring unit and the frequency and voltage regulation controller.

[0011] Optionally, the processing unit is further used to send the first frequency and voltage modulation instruction to the hardware monitoring unit, and the hardware monitoring unit is further used to delay for a set time period to obtain a real-time performance detection signal after receiving the first frequency and voltage modulation instruction.

[0012] Optionally, the hardware monitoring unit is also used to: determine the target frequency of the processing unit according to the performance detection signal; if the target frequency is the same as the target frequency in the first frequency and voltage modulation instruction, then the second frequency and voltage modulation instruction is not sent; otherwise, the second frequency and voltage modulation instruction is sent.

[0013] Optionally, the frequency modulation and voltage regulation controller includes:

[0014] an arbitrator, configured to, when receiving the first frequency modulation and voltage regulation instruction and the second frequency modulation and voltage regulation instruction at the same time, arbitrate and send only one of the first frequency modulation and voltage regulation instruction and the second frequency modulation and voltage regulation instruction to the frequency modulation and voltage regulation processing unit;

[0015] A frequency modulation and voltage regulation processing unit is used for adjusting the clock frequency and the supply voltage according to the first frequency modulation and voltage regulation instruction or the second frequency modulation and voltage regulation instruction.

[0016] Optionally, the first frequency and voltage modulation instruction or the second frequency and voltage modulation instruction includes indication information, and the arbitrator performs arbitration according to the indication information.

[0017] Optionally, when the first frequency and voltage modulation instruction includes first indication information, the arbitrator stores the first indication information in a register, and arbitrates to send only the first frequency and voltage modulation instruction to the frequency and voltage modulation processing unit currently and thereafter until the first frequency and voltage modulation instruction includes second indication information.

[0018] Optionally, when the second frequency and voltage modulation instruction includes third indication information, the arbitrator stores the third indication information in a register, and arbitrates to send only the second frequency and voltage modulation instruction to the frequency and voltage modulation processing unit currently and thereafter until the second frequency and voltage modulation instruction includes fourth indication information.

[0019] Optionally, the hardware monitoring unit adds indication information to the second frequency and voltage regulation instruction according to the real-time performance detection signal.

[0020] Optionally, the frequency modulation and voltage regulation processing unit includes:

[0021] A plurality of register groups for storing at least one frequency-voltage pair;

[0022] A frequency conversion register, used for storing the target frequency;

[0023] a comparator, configured to compare the target frequency with the at least one frequency-voltage pair, respectively, and output a result signal;

[0024] A frequency conversion generating unit, used for generating the frequency modulation signal according to the result signal;

[0025] A voltage generating unit is used to generate the voltage regulating signal according to the result signal.

[0026] Optionally, the hardware monitoring unit is further used to count the sending frequency of the second frequency and voltage modulation instructions in the previous predetermined time interval and adjust the sending frequency of the second frequency and voltage modulation instructions in the subsequent predetermined time interval accordingly.

[0027] Optionally, the processing unit sends the first frequency and voltage regulation instruction when executing the executable code of the software program.

[0028] In a second aspect, an embodiment of the present disclosure provides a method for adjusting voltage and frequency, including:

[0029] The software program periodically predicts the load condition in the next cycle according to a predetermined time interval, and determines whether to send a first frequency and voltage regulation instruction according to the prediction result and executes it accordingly;

[0030] The hardware monitoring unit obtains a real-time performance detection signal within the predetermined time interval, and determines whether to send a second frequency and voltage regulation instruction and executes it according to the performance detection signal;

[0031] The frequency modulation and voltage regulation controller adjusts the clock frequency and the supply voltage according to the first frequency modulation and voltage regulation instruction or the second frequency modulation and voltage regulation instruction.

[0032] Optionally, the software program is further used to send the first frequency and voltage modulation instruction to the hardware monitoring unit, and the hardware monitoring unit is further used to delay for a set time period to obtain a real-time performance detection signal after receiving the first frequency and voltage modulation instruction.

[0033] Optionally, the hardware monitoring unit is also used to determine the target frequency to which the processing unit is to be adjusted based on the performance detection signal; if the target frequency is the same as the target frequency in the first frequency and voltage regulation instruction, the second frequency and voltage regulation instruction is not sent; otherwise, the second frequency and voltage regulation instruction is sent.

[0034] In a third aspect, an embodiment of the present disclosure provides a computing device, including:

[0035] The system on chip as described in any one of the above items;

[0036] Off-chip bus;

[0037] a storage device coupled to the system on chip via the off-chip bus;

[0038] A power management circuit is coupled to the frequency and voltage regulation controller in the system on chip.

[0039] The system on chip provided by the embodiment of the present disclosure determines whether to send a second frequency and voltage modulation instruction through a hardware monitoring unit between two first frequency and voltage modulation instructions sent by a software program. Since the software program determines whether frequency modulation is required by predicting the load condition in the next cycle, inaccurate predictions may occur. The hardware monitoring unit determines whether to send the second frequency and voltage modulation instruction by monitoring system performance. Therefore, it determines whether to send the second frequency and voltage modulation signal between the two first frequency and voltage modulation instructions based on performance monitoring conditions, thereby helping to solve the problem of inaccurate load condition predictions by the software program and responding to the system's frequency and voltage modulation needs more quickly. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and other objects, features and advantages of the present disclosure will become more apparent through the description of the embodiments of the present disclosure with reference to the following drawings, in which:

[0041] Figure 1 is a schematic diagram of the structure of a system on a chip provided by an embodiment of the present disclosure;

[0042] Figure 2 It is a timing diagram for illustrating the timing relationship between sending a first frequency modulation and voltage modulation instruction and a second frequency modulation and voltage modulation instruction;

[0043] Figure 3 is a schematic diagram of the structure of a system on a chip provided by another embodiment of the present disclosure;

[0044] Figure 4 and 5 They are Figure 1 or Figure 3 A schematic diagram of the structure of two different embodiments of the frequency and voltage modulation processing unit;

[0045] Figure 6 is an exemplary structural diagram of a hardware monitoring unit;

[0046] Figure 7 is a flow chart of a method for adjusting voltage and frequency provided by an embodiment of the present disclosure;

[0047] Figure 8 is a schematic diagram of the structure of a general computer system used in the embodiments of the present disclosure;

[0048] Fig. 9 It is a schematic diagram of the structure of the embedded system used in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] The present disclosure is described below based on embodiments, but the present disclosure is not limited to these embodiments. In the detailed description of the present disclosure below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present disclosure without the description of these details. In order to avoid confusing the essence of the present disclosure, well-known methods, processes, and procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0050] The system on chip of the present disclosure

[0051] Figure 1 Schematic diagram of the structure of the system on chip 100 used in the embodiment of the present disclosure.

[0052] As shown in the reference figure, the processing unit 101 and the high-speed memory 103 are coupled to the on-chip bus 102. The on-chip bus 102 is, for example, an AXI bus. The AXI bus is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0 and above protocols proposed by ARM. It is an on-chip bus oriented to high performance, high bandwidth, and low latency. The AIX bus separates the address / control and data phases, supports unaligned data transmission, and supports burst transmission and out-of-order transmission, thus meeting the requirements of ultra-high performance and complex on-chip system design.

[0053] As shown in the figure, the FM / V controller 103 and the hardware monitoring unit 104 are coupled to the on-chip bus 102. The FM / V controller 103 is coupled to the clock management unit 105 and the power management circuit 211 located outside the chip. The hardware monitoring unit 104 is also coupled to the FM / V controller 103.

[0054] The on-chip bus 102 is also coupled to an interface circuit not shown, and is coupled to an external device outside the chip through the interface circuit. The external device may be, for example, an input / output device for text, audio, and video and various memories. The processing unit 101 may access the external device outside the chip through the interface circuit. Different from the high-speed memory 103 provided in the system on chip, the memory outside the chip may have a larger capacity but a slower speed and a lower cost. In some implementations, the high-speed memory 103 may be a static random access memory (SRAM), while the memory outside the chip may be a DRAM (dynamic random access memory) and a flash memory.

[0055] As shown in the figure, the system on chip 100 is also embedded with basic software (such as embedded control system 121) and application programs (such as application program AN). Other application programs can be stored in a memory outside the system on chip 100, and these application programs can be copied to the high-speed memory 104 in the system on chip 100 through the interface circuit, or access resources on the system on chip 100 through the interface circuit.

[0056] The processing unit 101 is responsible for reading various instructions, decoding and executing the instructions, for example, decoding and executing executable codes from the embedded control system 121, the application AN or other applications. In this embodiment, when executing the executable code, the processing unit 101 periodically sends the first frequency modulation and voltage regulation instruction to the frequency modulation and voltage regulation controller 103 via the on-chip bus 102 at a predetermined time interval.

[0057] The hardware monitoring unit 104 is used to obtain the real-time performance detection signal by hardware, and send the second frequency modulation and voltage regulation instruction to the frequency modulation and voltage regulation controller 103 within a predetermined time interval according to the real-time performance detection signal. For example, within the predetermined time interval, if the real-time performance detection signal reflects that the current system load is very high and the clock frequency needs to be increased to speed up the processing, then the second frequency modulation and voltage regulation instruction for increasing the clock frequency is sent. The first and second here are used to distinguish frequency modulation and voltage regulation instructions from different sources, and there is no difference in priority or importance.

[0058] The frequency modulation and voltage regulation controller 103 completes the frequency modulation and voltage regulation operation according to the first frequency modulation and voltage regulation instruction or the second frequency modulation and voltage regulation instruction at a specific moment. Specifically, at a specific moment, the frequency modulation and voltage regulation controller 103 receives the first frequency modulation and voltage regulation instruction or the second frequency modulation and voltage regulation instruction, and then generates a frequency modulation signal REGF and a voltage regulation signal REGV, sends the frequency modulation signal REGF to the clock circuit management unit 105, and sends the voltage regulation signal REGV to the power management circuit 211, and the clock management unit 105 adjusts the clock frequency FCPU of the system 100, and the power management circuit 211 adjusts the power supply voltage VCPU provided to the system 100. It should be understood that since the hardware monitoring unit 104 sends the second frequency modulation and voltage regulation instruction within a predetermined time interval, the frequency modulation and voltage regulation controller 103 usually receives the first frequency modulation and voltage regulation instruction and the second frequency modulation and voltage regulation instruction in time division. Of course, if there is a delay, the frequency modulation and voltage regulation controller 103 may also receive the first frequency modulation and voltage regulation instruction and the second frequency modulation and voltage regulation instruction at the same time. If the frequency modulation and voltage regulation controller 103 receives the first frequency modulation and voltage regulation instruction and the second frequency modulation and voltage regulation instruction at the same time, it is necessary to determine which one of the first frequency modulation and voltage regulation instruction to execute according to the arbitration logic.

[0059] In some embodiments, an executable code in the embedded control system 121 or the application AN includes the following process: regularly collecting signals related to the system load, calculating the current system load; then predicting the load of the system in the next cycle based on the current system load; then converting the load of the next cycle into the required frequency, and then modifying the clock frequency of the processor to the required frequency and modifying the power supply voltage of the processor at the same time. Based on this, when the processing unit 101 executes the above executable code, it generates a first frequency and voltage regulation instruction and sends it to the frequency and voltage regulation controller 103 to adjust the clock frequency of the system to the required frequency and adjust the power supply voltage at the same time.

[0060] In some embodiments, as shown in the figure, the FM / V controller 103 includes an arbitrator 1031 and an FM / V processing unit 1032. The arbitrator 1031 is used to send one of the first FM / V instruction and the second FM / V instruction to the FM / V processing unit 1032 through arbitration logic when receiving the first FM / V instruction and the second FM / V instruction at the same time.

[0061] The arbitration logic may be a fixed arbitration logic. For example, since the first frequency modulation and voltage regulation instruction is based on the predicted load conditions to adjust the frequency and voltage, and the second frequency modulation and voltage regulation instruction is based on the monitored performance indicators to adjust the frequency and voltage, if the first frequency modulation and voltage regulation instruction and the second frequency modulation and voltage regulation instruction are received at the same time, the first frequency modulation and voltage regulation instruction may be discarded and the second frequency modulation and voltage regulation instruction may be executed. For another example, a comparator is used to compare the target frequencies contained in the first frequency modulation and voltage regulation instruction and the second frequency modulation and voltage regulation instruction, and the frequency modulation and voltage regulation instruction containing the larger target frequency in the first and second frequency modulation and voltage regulation instructions is sent to the frequency modulation and voltage regulation processing unit 1032.

[0062] The frequency modulation and voltage regulation controller 103 can also adjust the arbitration logic in real time. In one implementation, the first frequency modulation and voltage regulation instruction or the second frequency modulation and voltage regulation instruction includes indication information, and the arbitrator 1031 arbitrates the first frequency modulation and voltage regulation instruction and the second frequency modulation and voltage regulation instruction received simultaneously according to the indication information.

[0063] The following is an example. When the arbitrator 1031 determines that the first frequency modulation and voltage regulation instruction contains the first indication information, the arbitrator 1031 stores the first indication information in the register, and arbitrates only the first frequency modulation and voltage regulation instruction from the processing unit 101 to the frequency modulation and voltage regulation processing unit 1032 at present and in the future, until the arbitrator 1031 receives the first frequency modulation and voltage regulation instruction containing the second indication information, it will continue to use the original arbitration logic to arbitrate the first frequency modulation and voltage regulation instruction and the second frequency modulation and voltage regulation instruction. When the second frequency modulation and voltage regulation instruction contains the third indication information, the arbitrator 1031 stores the third indication information in the register, and arbitrates only the second frequency modulation and voltage regulation instruction to the frequency modulation and voltage regulation processing unit 1032 at present and in the future, until the arbitrator 1031 receives the second frequency modulation and voltage regulation instruction containing the fourth indication information, it will continue to use the original arbitration logic to arbitrate the first frequency modulation and voltage regulation instruction and the second frequency modulation and voltage regulation instruction.

[0064] Optionally, the frequency modulation and voltage regulation controller 103 adds indication information to the second frequency modulation and voltage regulation instruction according to the real-time performance detection signal. For example, the hardware monitoring unit 104 obtains the real-time cache hit rate, and adds third indication information to the second frequency modulation and voltage regulation instruction under the condition that the cache hit rate is greater than the first threshold, and adds second indication information to the second frequency modulation and voltage regulation instruction under the condition that the cache hit rate drops to less than the second threshold. Similarly, the processing unit 101 also adds first indication information and second indication information to the first frequency modulation and voltage regulation instruction based on similar reasons. It should be pointed out that in this embodiment, other indicators can also be used to replace the cache hit rate.

[0065] The frequency modulation and voltage regulation processing unit 1032 may use AVFS or DVFS technology. Based on the AVFS technology, the system supply voltage is determined according to the detection data measured in real time and the target frequency in the frequency modulation and voltage regulation instruction. Based on the DVFS technology, a frequency voltage pair is selected from a plurality of verified frequency voltage pairs that enable any processor to work normally to set the system clock frequency and supply voltage.

[0066] Figure 2It is a timing diagram for illustrating the timing relationship between sending the first frequency modulation and voltage regulation instruction and the second frequency modulation and voltage regulation instruction. As shown in the figure, the processing unit 101 periodically sends the first frequency modulation and voltage regulation instruction at intervals of time length T, wherein at time S0, the first frequency modulation and voltage regulation instruction indicates that the clock frequency of the system is to be adjusted to Fs0, at time S1, the first frequency modulation and voltage regulation instruction indicates that the clock frequency of the system is to be adjusted to Fs1, and at time S2, the first frequency modulation and voltage regulation instruction indicates that the clock frequency of the system is to be adjusted to Fs2. The hardware monitoring unit 104 sends the second frequency modulation and voltage regulation instruction at times H0-H3 respectively, at time H0, the second frequency modulation and voltage regulation instruction indicates that the clock frequency of the system is to be adjusted to Hs0, at time H1, the second frequency modulation and voltage regulation instruction indicates that the clock frequency of the system is to be adjusted to Hs1, at time H2, the second frequency modulation and voltage regulation instruction indicates that the clock frequency of the system is to be adjusted to Hs2, and at time H3, the second frequency modulation and voltage regulation instruction indicates that the clock frequency of the system is to be adjusted to Hs3.

[0067] Combination Figure 1 As shown, as an optional implementation, the processing unit 101 simultaneously sends the first frequency modulation and voltage regulation instruction to the hardware monitoring unit 104 and the frequency modulation and voltage regulation controller 103. After receiving the first frequency modulation and voltage regulation instruction, the hardware monitoring unit 104 delays the setting time to obtain the real-time performance detection signal, and then determines whether to send the second frequency modulation and voltage regulation instruction at present according to the real-time performance detection signal and the frequency included in the first frequency modulation and voltage regulation instruction. Specifically, refer to Figure 2 As shown, assuming that the hardware monitoring unit 104 receives the first frequency modulation and voltage regulation instruction at time S0, delays the time period (H0-S0) to obtain the real-time performance detection signal, and then decides whether to send the second frequency modulation and voltage regulation instruction at time H0 based on the performance detection signal. The advantage of this is that since the processing unit 101 and the hardware monitoring unit 104 send the first frequency modulation and voltage regulation instruction and the second frequency modulation and voltage regulation instruction in a time-sharing manner, if the delay is not considered, the frequency modulation and voltage regulation controller 103 will not receive the first frequency modulation and voltage regulation instruction and the second frequency modulation and voltage regulation instruction at the same time, so the frequency modulation and voltage regulation controller 103 does not need to arbitrate the instructions. Further, still referring to Figure 2 , the delay time (H0-S0) may be equal to the product of T and the set ratio. For example, if the set ratio is 1 / 3 and 2 / 3, the real-time performance detection signal is obtained by delaying T / 3 and 2T / 3. And determining whether to send the second frequency modulation and voltage regulation instruction at present according to the real-time performance detection signal and the target frequency included in the first frequency modulation and voltage regulation instruction includes: determining the target frequency to which the processing unit 101 is to be adjusted according to the real-time performance detection signal, if the target frequency is the same as the target frequency included in the first frequency modulation and voltage regulation instruction, then the second frequency modulation and voltage regulation instruction is not sent, otherwise the second frequency modulation and voltage regulation instruction is sent.

[0068] Combination Figure 1 and2 As shown, as an optional implementation, the hardware monitoring unit 104 also counts the sending frequency of the second frequency and voltage modulation instructions in the previous time interval T, and determines the sending frequency of the second frequency and voltage modulation instructions in the subsequent time interval T according to the previous sending frequency. Figure 2 As shown, the hardware monitoring unit 104 can be pre-configured with several enumeration values. In multiple time intervals T, the hardware monitoring unit 104 uses the corresponding enumeration values ​​in ascending order as the sending frequency of the second frequency modulation and voltage regulation instruction. For example, 3 enumeration values ​​are set (1 time / T, 2 times / T, 3 times / T). For every 3 time intervals T, the hardware monitoring unit 104 decides whether to send the second frequency modulation and voltage regulation instruction at the moment T / 2 of the first time interval T according to the performance detection signal, decides whether to send the second frequency modulation and voltage regulation instruction at the moments T / 3 and 2T / 3 of the second time interval T according to the performance detection signal respectively, and decides whether to send the second frequency modulation and voltage regulation instruction at the moments T / 4, T / 2 and 3T / 4 of the third time interval T according to the performance detection signal respectively.

[0069] Figure 3 FIG. 1 is a schematic diagram of a system on chip 300 provided in another embodiment of the present disclosure. Figure 1 The difference is that in Figure 3 In the embodiment, the power management circuit 211 is arranged inside the system on chip 300 .

[0070] Figure 4 and 5 They are Figure 1 or Figure 3 A schematic structural diagram of two different embodiments of the frequency and voltage modulation processing unit in FIG.

[0071] Figure 4A frequency modulation and voltage regulation processing unit 400 of DVFS is shown. As shown in the figure, register F is used to store the target frequency in the first frequency modulation and voltage regulation instruction or the second frequency modulation and voltage regulation instruction. Register group FV is used to store multiple frequency voltage pairs. Multiple comparators 403 are used to compare the target frequency in register F with the frequency voltage in register group FV. If they match, the voltage generation unit 402 generates a voltage regulation signal REGV, and the frequency conversion generation unit 401 generates a frequency modulation signal FCPU. If the error detection unit 404 detects that the target frequency does not match the frequency in any frequency voltage pair, the interrupt generation unit 405, the reset generation unit 406 or the bus response unit 407 generates an interrupt signal SINT, a reset signal RESET or a bus error signal SBUS. The interrupt signal SINT is processed by an interrupt controller (not shown in the figure). The interrupt controller can be set inside the processing unit 101. The interrupt controller defines various processing routines for various interrupt signals. When the corresponding interrupt signal occurs, the corresponding processing routine is started to perform the corresponding processing. The reset signal RESET will be sent to a reset circuit (not shown), and the reset circuit will reset the system on chip and then restart. The bus error signal SBUS will be sent to the bus 402 for processing.

[0072] Figure 5 The figure shows a frequency modulation and voltage regulation processing unit 450 of an AVFS. As shown in the figure, the frequency modulation and voltage regulation processing unit 450 includes a register group for storing a frequency point table 451, a voltage calculation unit 452, a temperature sensor controller 453, a process sensor controller 454 and a voltage sensor controller 455. The frequency point table 451 includes a plurality of frequencies, which are generated by the AVFS controller 450 according to the frequency configuration instruction.

[0073] The temperature sensor 456, the process sensor 457 and the voltage sensor 458 are located inside the system on chip 100 but outside the controller 450. The temperature sensor 456, the process sensor 457 and the voltage sensor 458 respectively collect analog signals of the real-time temperature, process deviation and real-time voltage of the system on chip, and convert the analog signals into digital signals. The temperature sensor controller 453, the process sensor controller 454 and the voltage sensor controller 455 are respectively used to control the temperature sensor 456, the process sensor 457 and the voltage sensor 458, for example, to control the start and stop of the sensor to collect detection data. Among them, the process deviation will have an impact on the calculation of the power supply voltage.

[0074] The voltage calculation unit 452 calculates the supply voltage based on the target frequency and the real-time temperature of the system and the process deviation according to the predefined voltage calculation rules, or first calculates the supply voltage based on the target frequency and the real-time temperature of the system according to the predefined voltage calculation rules, and then biases the supply voltage according to the process deviation. Afterwards, the voltage calculation unit 452 provides a voltage regulation signal to the power management circuit 211 according to the supply voltage, and the supply voltage can also be compared with the real-time voltage obtained by the voltage sensor 458 to determine whether the voltage regulation operation is successful. If it is unsuccessful, for example, the voltage value difference between the real-time voltage and the supply voltage is too large, the voltage calculation rules can be adjusted accordingly in the subsequent voltage calculation.

[0075] Figure 6 It is an exemplary structural diagram of the hardware monitoring unit. As shown in the figure, the hardware monitoring unit 104 includes a bus hardware monitoring unit 1041, a processor hardware monitoring unit 1042, an emergency monitoring unit 1043 and a performance monitoring event arbitrator 1044. The bus hardware monitoring unit 1041 is used to obtain a real-time bus performance detection signal. The processor hardware monitoring unit 1042 is used to obtain a real-time processor performance detection signal. The emergency monitoring unit 1043 is used to obtain real-time emergency events. The performance monitoring event arbitrator 1044 determines whether to send a second frequency and voltage modulation instruction based on the bus performance detection signal, the processor performance detection signal and the emergency event.

[0076] In summary, the on-chip system provided by the embodiments of the present disclosure determines whether to send a second frequency and voltage modulation instruction through a hardware monitoring unit between two first frequency and voltage modulation instructions sent by a software program. Since the software determines whether frequency modulation is needed by predicting the load condition in the next cycle, inaccurate predictions may occur. The hardware monitoring unit determines whether to send the second frequency and voltage modulation instruction by monitoring system performance, and determines whether to send the second frequency and voltage modulation signal between the two first frequency and voltage modulation instructions based on performance monitoring conditions, thereby helping to solve the problem of inaccurate predictions of load conditions by the software program and respond to the system's frequency and voltage modulation needs more quickly.

[0077] Method for adjusting voltage and frequency according to the embodiment of the present disclosure

[0078] Figure 7 1 is a flow chart of a method for adjusting voltage and frequency provided by an embodiment of the present disclosure. The method is executed by the above-mentioned system on chip. As shown in the figure, the method includes the following steps.

[0079] In step S701, the software program periodically predicts the load status in the next cycle at a predetermined time interval, and determines whether to send a first frequency and voltage regulation instruction according to the prediction result and executes it accordingly.

[0080] In step S702, the hardware monitoring unit obtains a real-time performance detection signal within a predetermined time interval, and determines whether to send a second frequency and voltage regulation instruction according to the performance detection signal and executes it accordingly.

[0081] In step S703, the frequency and voltage regulation controller adjusts the clock frequency and operating voltage of the system according to the first frequency and voltage regulation instruction and the second frequency and voltage regulation instruction at a specific moment.

[0082] In this embodiment, the software program predicts and performs the following operations periodically at predetermined time intervals: predict the load condition of the next cycle, determine whether to send a first frequency and voltage regulation instruction and execute the sending operation based on the load condition. For example, if it is predicted that the load of the next cycle is high, a first frequency and voltage regulation instruction for increasing the clock frequency can be sent; if it is predicted that the load of the next cycle is low, a first frequency and voltage regulation instruction for reducing the clock frequency can be sent; if it is predicted that the load of the next cycle does not change much, the frequency and voltage regulation instruction may not be sent.

[0083] In this embodiment, the hardware monitoring unit obtains a real-time performance detection signal within a predetermined time interval, and sends a second frequency and voltage modulation instruction based on the performance detection signal. For example, if the performance detection signal reflects that the current system load is too high, the system clock frequency can be increased. If the performance detection signal reflects that the current system load is too low, the system clock frequency can be reduced, and a second frequency and voltage modulation instruction for increasing or reducing the system clock frequency is sent.

[0084] In this embodiment, the frequency modulation and voltage regulation controller receives the first frequency modulation and voltage regulation instruction and the second frequency modulation and voltage regulation instruction, and completes the frequency modulation and voltage regulation operation according to the first frequency modulation and voltage regulation instruction and the second frequency modulation and voltage regulation instruction. Since the first frequency modulation and voltage regulation instruction and the second frequency modulation and voltage regulation instruction are issued at different times, the frequency modulation and voltage regulation controller usually receives the first frequency modulation and voltage regulation instruction and the second frequency modulation and voltage regulation instruction in time-sharing and completes the frequency modulation and voltage regulation operation in time-sharing. However, due to system delay, the frequency modulation and voltage regulation controller may also receive the first frequency modulation and voltage regulation instruction and the second frequency modulation and voltage regulation instruction at the same time. In this case, the frequency modulation and voltage regulation controller arbitrates and uses only one of them to complete the frequency modulation and voltage regulation operation.

[0085] In the method for adjusting voltage and frequency provided in this embodiment, the hardware monitoring unit sends a second frequency and voltage regulation instruction between two first frequency and voltage regulation instructions sent by the software program. Since the software program predicts the load condition of the next cycle to send the first frequency and voltage regulation instruction, inaccurate predictions may occur. The hardware monitoring unit decides whether to send the second frequency and voltage regulation instruction by monitoring the system performance, which can help solve the problem of inaccurate prediction of the load condition by the software program and respond to the system's frequency and voltage regulation needs more quickly.

[0086] In an optional embodiment, the software program is further used to send the first frequency modulation and voltage regulation instruction to the hardware monitoring unit, and the hardware monitoring unit is further used to delay the set time length to obtain the real-time performance detection signal after receiving the first frequency modulation and voltage regulation instruction. The set time length is equal to the product of the predetermined time interval and the set ratio. For example, if the predetermined time interval is 20ms and the set ratio is 1 / 10, the real-time performance detection signal is obtained through the hardware monitoring unit after a delay of 2ms after receiving the first frequency modulation and voltage regulation instruction.

[0087] In an optional embodiment, the hardware monitoring unit is also used to: determine the target frequency to which the processing unit is to be adjusted based on the performance detection signal; if the target frequency is the same as the target frequency in the first frequency and voltage regulation instruction, then the second frequency and voltage regulation instruction is not sent; otherwise, the second frequency and voltage regulation instruction is sent.

[0088] Specific Applications of System-on-Chip

[0089] Figure 8 8 is a schematic diagram of the structure of a general computer system used in the embodiments of the present disclosure. As shown in the figure, the computer system 800 may include one or more processors 12 and a memory 14. The system on chip provided in the above embodiments may be used as the processor 12.

[0090] The memory 14 in the computer system 800 may be a main memory (hereinafter referred to as main memory or internal memory), which is used to store instruction information and / or data information represented by data signals, such as storing data (such as calculation results) provided by the processor 12, and may also be used to implement data exchange between the processor 12 and an external storage device 16 (also referred to as auxiliary memory or external memory).

[0091] In some cases, the processor 12 may need to access the memory 14 to obtain data in the memory 14 or modify the data in the memory 14. Since the access speed of the memory 14 is slow, in order to alleviate the speed gap between the processor 12 and the memory 14, the computer system 800 also includes a cache memory 18 coupled to the bus 11, and the cache memory 18 is used to cache some program data or message data in the memory 14 that may be repeatedly called. The cache memory 18 is implemented by a storage device of the type of static random access memory (SRAM) for example. The cache memory 18 can be a multi-level structure, such as a three-level cache structure with a first-level cache (L1Cache), a second-level cache (L2Cache) and a third-level cache (L3Cache), or a cache structure of more than three levels or other types of cache structures. In some embodiments, a portion of the cache memory 18 (such as a first-level cache, or a first-level cache and a second-level cache) can be integrated inside the processor 12 or integrated with the processor 12 in the same system on a chip.

[0092] Based on this, the processor 12 may include an instruction execution unit 121, a memory management unit 122, and other parts. The instruction execution unit 121 initiates a write access request when executing some instructions that need to modify the memory. The write access request specifies the write data and the corresponding physical address that need to be written into the memory; the memory management unit 122 is used to translate the virtual addresses specified by these instructions into the physical addresses mapped by the virtual addresses. The physical address specified by the write access request may be consistent with the physical address specified by the corresponding instruction.

[0093] The information exchange between the memory 14 and the cache memory 18 is usually organized in blocks. In some embodiments, the cache memory 18 and the memory 14 can be divided into data blocks according to the same spatial size, and the data block can be used as the minimum unit of data exchange between the cache memory 18 and the memory 14 (including one or more data of a preset length). For the sake of simplicity and clarity, the data blocks in the cache memory 18 are referred to as cache blocks (which can be called cache lines or cache lines), and different cache blocks have different cache block addresses; the data blocks in the memory 14 are referred to as memory blocks, and different memory blocks have different memory block addresses. The cache block address includes, for example, a physical address tag for locating the data block.

[0094] Due to space and resource limitations, the cache memory 18 cannot cache all the contents in the memory 14, that is, the storage capacity of the cache memory 18 is usually smaller than that of the memory 14, and the cache block addresses provided by the cache memory 18 cannot correspond to all the memory block addresses provided by the memory 14. When the processor 12 needs to access the memory, it first accesses the cache memory 18 via the bus 11 to determine whether the content to be accessed has been stored in the cache memory 18. If so, the cache memory 18 hits, and the processor 12 directly calls the content to be accessed from the cache memory 18; if the content that the processor 12 needs to access is not in the cache memory 18, the cache memory 18, the processor 12 needs to access the memory 14 via the bus 11 to find the corresponding information in the memory 14. Because the access rate of the cache memory 18 is very fast, when the cache memory 18 hits, the efficiency of the processor 12 can be significantly improved, thereby improving the performance and efficiency of the entire computer system 800.

[0095] In addition, the computer system 800 may also include input / output devices such as a storage device 16, a display device 13, an audio device 19, and a mouse / keyboard 15. The storage device 16 is, for example, a hard disk, an optical disk, a flash memory, and other devices for information access coupled to the bus 11 through a corresponding interface. The display device 13 is, for example, coupled to the bus 11 through a corresponding graphics card, and is used to display according to a display signal provided by the bus 11.

[0096] The computer system 800 also typically includes a communication device 17, so that it can communicate with a network or other devices in various ways. The communication device 17 may include, for example, one or more communication modules. As an example, the communication device 17 may include a wireless communication module suitable for a specific wireless communication protocol. For example, the communication device 17 may include a WLAN module for implementing Wi-FiTM communication that complies with the 802.11 standard established by the Institute of Electrical and Electronics Engineers (IEEE); the communication device 17 may also include a WWAN module for implementing wireless wide area communication that complies with cellular or other wireless wide area protocols; the communication device 17 may also include a communication module that uses other protocols, such as a Bluetooth module, or other custom types of communication modules; the communication device 17 may also be a port for serial transmission of data.

[0097] Of course, the structure of different computer systems may vary according to the motherboard, operating system and instruction set architecture. For example, many computer systems are currently provided with an input / output control center connected between the bus 11 and various input / output devices, and the input / output control center can be integrated into the processor 12 or independent of the processor 12.

[0098] Fig. 9 901 is a structural diagram of an embedded system used in the embodiments of the present disclosure. The system on chip provided in the above embodiments can be used as a processor 901.

[0099] Although embedded systems are highly similar to computer systems in hardware structure, the characteristics of embedded system applications make them quite different from general computer systems in hardware composition and implementation.

[0100] First, in order to meet the requirements of the embedded system 900 in terms of speed, volume and power consumption, the operating system, application software, special data and other data that need to be stored for a long time usually do not use storage media such as disks with large capacity and slow speed, but mostly use random access memory 902 or flash memory (Flash Memory) 903.

[0101] In addition, in the embedded system 900, an A / D (analog / digital conversion) interface 905 and a serial interface 906 are required for measurement and control, which are rarely used in general-purpose computers. The A / D interface 905 mainly completes the conversion of analog signals to digital signals and the conversion of digital signals to analog signals required in the test. The embedded system 900 often needs to be tested when applied to industrial production. Since the single-chip microcomputer generates digital signals, it needs to be converted into analog signals for testing during testing. Therefore, unlike general-purpose computers, an A / D (analog / digital conversion) interface 905 is required to complete the relevant conversion. In addition, multiple embedded systems are often required to be connected in series in industry to complete relevant functions, so a serial interface 906 is required for connecting multiple embedded systems in series, which is mostly not required in general-purpose computers.

[0102] In addition, as a basic processing unit, the embedded system 900 often needs to connect multiple embedded systems 900 into a network in industrial design, so it is necessary to connect the embedded system 900 to the network interface 907. This is also not needed in general-purpose computers. In addition, according to the actual application and scale, some embedded systems 900 need to use external buses 904. With the rapid expansion of the application field of embedded systems 900, embedded systems 900 are becoming more and more personalized, and the types of buses used according to their own characteristics are also increasing. In addition, in order to test the internal circuits of the embedded processor 901, the processor chip generally adopts boundary scan test technology. In order to adapt to this test, a debug interface 908 is adopted.

[0103] With the rapid development of very large scale integration (VLSI) and semiconductor technology, part or all of the above embedded systems can be implemented on a silicon chip, namely an embedded system on chip (SoC).

[0104] The commercial value of the disclosed embodiments

[0105] The system on chip provided by the embodiment of the present disclosure sends frequency modulation and voltage regulation instructions through a combination of software programs and hardware detection units to better respond to the system's frequency modulation and voltage regulation requirements and achieve the purpose of further reducing power consumption. Such a system on chip can be used to form a computing device used in a variety of scenarios, such as a large number of cloud servers in a data center. In this scenario, the power consumption of each cloud server is reduced by reducing the power consumption of the processor, thereby reducing the operating cost of each cloud server and the entire data center; for example, electronic devices used in daily life, including terminal devices such as notebooks and mobile phones, and certain consumer electronic products, can improve the system battery life of electronic devices by reducing power consumption, thereby improving user experience. It can be seen that the system on chip of the embodiment of the present disclosure and the computing device constructed by the system on chip have commercial value and economic value on the basis of practical value.

[0106] Those skilled in the art will appreciate that the present disclosure may be implemented as a system, method, and computer program product. Therefore, the present disclosure may be specifically implemented in the following forms, namely, complete hardware, complete software (including firmware, resident software, microcode), and may also be implemented in the form of a combination of software and hardware. In addition, in some embodiments, the present disclosure may also be implemented in the form of a computer program product in one or more computer-readable media, wherein the computer-readable medium contains a computer-readable program code.

[0107] Any combination of one or more computer-readable media may be used. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example but not limited to, an electrical, magnetic, optical, electromagnetic, infrared or semiconductor system, device or device, or any combination thereof. More specific examples of computer-readable storage media include: an electrical connection of one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this article, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by a processing unit, device or device, or used in combination with it.

[0108] Computer readable signal media may include data signals propagated in baseband or as part of a chopped wave, which carry computer readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any other suitable combination. Computer readable signal media may also be any computer readable medium other than a computer readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction system, apparatus, or device.

[0109] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., and any suitable combination of the foregoing.

[0110] The computer program code for executing the disclosed embodiments may be written in one or more programming languages ​​or in combination. The programming languages ​​include object-oriented programming languages, such as JAVA, C++, and may also include conventional procedural programming languages, such as C. The program code may be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0111] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A system on chip, comprising: A processing unit, configured to periodically send a first frequency and voltage modulation instruction at a predetermined time interval; A hardware monitoring unit, configured to obtain a real-time performance detection signal within the predetermined time interval, and send a second frequency and voltage modulation instruction according to the performance detection signal; A frequency modulation and voltage regulation controller, used for adjusting the clock frequency and the supply voltage according to the first frequency modulation and voltage regulation instruction and / or the second frequency modulation and voltage regulation instruction; An on-chip bus, used to couple the processing unit, the hardware monitoring unit and the frequency and voltage regulation controller; The processing unit is further used to send the first frequency and voltage modulation instruction to the hardware monitoring unit, and the hardware monitoring unit is further used to delay for a set period of time to obtain a real-time performance detection signal after receiving the first frequency and voltage modulation instruction.

2. The system on chip according to claim 1, wherein: The hardware monitoring unit is also used to determine the target frequency of the processing unit according to the performance detection signal, and if the target frequency is the same as the target frequency in the first frequency and voltage modulation instruction, the second frequency and voltage modulation instruction is not sent, otherwise the second frequency and voltage modulation instruction is sent.

3. The system on chip according to claim 2, wherein: The frequency modulation and voltage regulation controller comprises: an arbitrator, configured to, when receiving the first frequency modulation and voltage regulation instruction and the second frequency modulation and voltage regulation instruction at the same time, arbitrate and send only one of the first frequency modulation and voltage regulation instruction and the second frequency modulation and voltage regulation instruction to the frequency modulation and voltage regulation processing unit; A frequency modulation and voltage regulation processing unit is used for adjusting the clock frequency and the supply voltage according to the first frequency modulation and voltage regulation instruction or the second frequency modulation and voltage regulation instruction.

4. The system on chip according to claim 3, wherein: The first frequency and voltage modulation instruction or the second frequency and voltage modulation instruction includes indication information, and the arbitrator performs arbitration according to the indication information.

5. The system on chip according to claim 4, wherein: When the first frequency and voltage modulation instruction includes first indication information, the arbitrator stores the first indication information in a register, and arbitrates to send only the first frequency and voltage modulation instruction to the frequency and voltage modulation processing unit currently and thereafter until the first frequency and voltage modulation instruction includes second indication information.

6. The system on chip according to claim 4, wherein: When the second frequency and voltage modulation instruction includes third indication information, the arbitrator stores the third indication information in a register, and arbitrates to send only the second frequency and voltage modulation instruction to the frequency and voltage modulation processing unit currently and thereafter until the second frequency and voltage modulation instruction includes fourth indication information.

7. The system on chip according to claim 4, wherein: The hardware monitoring unit adds indication information to the second frequency and voltage modulation instruction according to the real-time performance detection signal.

8. The system on chip according to claim 3, wherein: The frequency modulation and voltage regulation processing unit comprises: A plurality of register groups for storing at least one frequency-voltage pair; A frequency conversion register, used for storing a target frequency of the processing unit; a comparator, for comparing the target frequency of the processing unit with the at least one frequency-voltage pair, respectively, and outputting a result signal; A frequency conversion generating unit, used for generating a frequency modulation signal according to the result signal; A voltage generating unit is used to generate a voltage regulating signal according to the result signal.

9. The system on chip according to claim 1, wherein: The hardware monitoring unit is further used to count the sending frequency of the second frequency and voltage modulation instructions in the previous predetermined time interval and determine the sending frequency of the second frequency and voltage modulation instructions in the subsequent predetermined time interval accordingly.

10. The system on chip according to claim 1, wherein: The processing unit sends the first frequency and voltage modulation instruction when executing the executable code of the software program.

11. A method for regulating voltage and frequency, comprising: The software program periodically predicts the load condition in the next cycle according to a predetermined time interval, and determines whether to send a first frequency and voltage regulation instruction according to the prediction result and executes it accordingly; The hardware monitoring unit obtains a real-time performance detection signal within the predetermined time interval, and determines whether to send a second frequency and voltage regulation instruction and executes it according to the performance detection signal; The frequency modulation and voltage regulation controller adjusts the clock frequency and the supply voltage according to the first frequency modulation and voltage regulation instruction or the second frequency modulation and voltage regulation instruction; The software program is further used to send the first frequency and voltage modulation instruction to the hardware monitoring unit, and the hardware monitoring unit is further used to delay for a set period of time to obtain a real-time performance detection signal after receiving the first frequency and voltage modulation instruction.

12. The method according to claim 11, wherein: The hardware monitoring unit is also used to determine the target frequency to which the processing unit is to be adjusted based on the performance detection signal; if the target frequency is the same as the target frequency in the first frequency and voltage modulation instruction, the second frequency and voltage modulation instruction is not sent; otherwise, the second frequency and voltage modulation instruction is sent.

13. A computing device comprising: The system on chip according to any one of claims 1 to 10; Off-chip bus; a storage device coupled to the system on chip via the off-chip bus; A power management circuit is coupled to the frequency and voltage regulation controller in the system on chip.

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