Method for manufacturing semiconductor device and semiconductor manufacturing apparatus

Abstract

Provided are a method for manufacturing a semiconductor device and a semiconductor manufacturing apparatus. According to one embodiment, a method for manufacturing a semiconductor device is provided. The manufacturing method includes attaching a substrate to a sheet. The manufacturing method includes singulating the substrate into a plurality of chips by dividing. The manufacturing method includes expanding the sheet to increase the interval between the plurality of chips. The manufacturing method includes covering and sealing the main surface and side surface of each of the plurality of chips with resin to form a sealed body. The manufacturing method includes forming a laminate in which a plurality of sealed bodies are stacked. The plurality of sealed bodies include a first sealed body and a second sealed body. Forming the laminate includes stacking the second sealed body on the first sealed body in a state in which the position of the chip in the second sealed body is offset in the planar direction with respect to the position of the chip in the first sealed body.

Description

[0001] Citation of relevant applications

[0002] This application is based on and claims the benefit of priority derived from Japanese Patent Application No. 2020-154079, filed on September 14, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This embodiment relates to a method for manufacturing a semiconductor device and a semiconductor manufacturing apparatus. Background Technology

[0004] In the process of manufacturing a semiconductor device by bonding a substrate to a sheet, dividing the substrate into multiple chips, and sealing the chips, it is desirable to increase productivity. Summary of the Invention

[0005] One embodiment aims to provide a method for manufacturing a semiconductor device and a semiconductor manufacturing apparatus that can improve productivity.

[0006] According to one embodiment, a method for manufacturing a semiconductor device is provided. The manufacturing method includes bonding a substrate to a sheet. The manufacturing method includes dividing the substrate to monolithize it into multiple chips. The manufacturing method includes expanding the sheet to increase the spacing between the multiple chips. The manufacturing method includes covering and sealing the main surface and side surfaces of each of the multiple chips with resin to form a sealing body. The manufacturing method includes forming a laminate consisting of multiple sealing bodies. The multiple sealing bodies include a first sealing body and a second sealing body. Forming the laminate includes stacking the second sealing body on top of the first sealing body while the position of a chip in the second sealing body is offset in a planar direction relative to the position of a chip in the first sealing body.

[0007] Based on the above structure, a method for manufacturing a semiconductor device and a semiconductor manufacturing apparatus that can improve productivity can be provided. Attached Figure Description

[0008] Figure 1 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0009] Figure 2 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0010] Figure 3 This is a top view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0011] Figure 4 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0012] Figure 5 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0013] Figure 6 This is a top view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0014] Figure 7 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0015] Figure 8 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0016] Figure 9 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0017] Figure 10 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0018] Figure 11 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0019] Figure 12 This is a cross-sectional view showing the structure of the semiconductor manufacturing apparatus in the first variation of the embodiment.

[0020] Figure 13 This is a top view showing the structure of the semiconductor manufacturing apparatus in the first variation of the embodiment.

[0021] Figure 14 This is a top view showing the operation of a semiconductor manufacturing apparatus according to a first variation of the embodiment.

[0022] Figure 15 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a second variation of the embodiment.

[0023] Figure 16 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a second variation of the embodiment.

[0024] Figure 17 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third variation of the embodiment.

[0025] Figure 18 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third variation of the embodiment.

[0026] Figure 19 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third variation of the embodiment.

[0027] Figure 20This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third variation of the embodiment.

[0028] Figure 21 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third variation of the embodiment. Detailed Implementation

[0029] Hereinafter, a method for manufacturing a semiconductor device according to an embodiment will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to this embodiment.

[0030] (Implementation Method)

[0031] A method for manufacturing the semiconductor device according to the embodiments will be described.

[0032] Semiconductor devices can be like Figures 1 to 10 Manufactured as shown. Figure 1 (a)~ Figure 2 (c) Figure 4 (a)~ Figure 5 (c) Figure 7 (a)~ Figure 11 (c) is a cross-sectional view showing a method of manufacturing a semiconductor device. Figure 3 (a)~ Figure 3 (c) Figure 6 This is a top view illustrating a method for manufacturing a semiconductor device. Hereinafter, the direction perpendicular to the surface of the semiconductor substrate is designated as the Z-direction, and the two mutually orthogonal directions within the plane perpendicular to the Z-direction are designated as the X-direction and the Y-direction.

[0033] exist Figure 1 In step (a), a semiconductor substrate 10' is prepared. The semiconductor substrate 10' has a surface 10a on the +Z side and a back surface 10b' on the -Z side. On the surface 10a' of the semiconductor substrate 10', multiple chip regions are patterned using a prescribed process to form a device layer 2. The pattern of each chip region is a rectangular pattern, including multiple external connection terminals arranged along one side of the rectangle (see reference). Figure 6 Then, the surface 10a of the semiconductor substrate 10' to which the device layer 2 is formed is adhered to the sheet 3. At this time, the semiconductor substrate 10 is adhered to the sheet 3 with its back side 10b' exposed (face-down state). The sheet 3 is a back-grind tape or the like, and an adhesive is formed on its surface 3a. The sheet 3 is, for example, formed of a transparent resin that is translucent.

[0034] exist Figure 1In step (b), the back surface 10b of the semiconductor substrate 10' is polished, and the semiconductor substrate 10 is thinned. The polishing surface of the polishing machine 4 contacts the back surface 10b' of the semiconductor substrate 10', and the polishing machine 4 rotates, thereby polishing the back surface 10b of the semiconductor substrate 10'. As a result, the semiconductor substrate 10 is thinned to a thickness corresponding to the requirements of miniaturization of the package size. The back surface 10b of the semiconductor substrate 10 is polished to become flat.

[0035] exist Figure 1 In process (c), the semiconductor substrate 10 is transferred from sheet 3 to sheet 5. Sheet 5 is a diced tape or the like, and an adhesive is formed on its surface 5a. Sheet 5 is attached to the inside of holding member 101 and held by holding member 101. Sheet 5 is, for example, formed of a transparent resin that is light-transmitting. The back side 10b of semiconductor substrate 10 is attached to sheet 5. At this time, semiconductor substrate 10 is attached to sheet 5 with its surface 10a exposed (face up).

[0036] exist Figure 2 In process (a), the semiconductor substrate 10 is divided into k chips 16-1 to 16-k. k is any integer greater than 3. For example, the semiconductor substrate 10 is cut along a dicing line. The cutting process can be performed by cutting along the dicing line using a cutting blade. Alternatively, the cutting process can be performed by laser processing by irradiating the dicing line with a laser. Each chip 16-1 to 16-k is a semiconductor chip. On the sheet 5, the k chips 16-1 to 16-k are arranged in a matrix in the XY direction.

[0037] exist Figure 2 In step (b), the sheet 5 is expanded, and the spacing between the plurality of chips 16-1 to 16-k on the sheet 5 is increased. For example, the position of each chip 16-1 to 16-k in the sheet 5 is measured while it is held by the holding member 101. Based on the measurement results, while holding the plurality of chips 16-1 to 16-k with them attached, the sheet 5 is expanded outward via the holding member 101. On the sheet 5, the k chips 16-1 to 16-k are arranged in a matrix while being separated in the XY direction.

[0038] exist Figure 2 In step (c), the surfaces 16a and sidewalls 16c of each of the multiple chips 16-1 to 16-k are covered by an insulating film 17 to form a sealed body 18. The insulating film 17 is a thermosetting or photocurable organic resin in an uncured or semi-cured state. The insulating film 17, for example, has insulating and light-transmitting properties. The insulating film 17 has a thickness sufficient to cover the surfaces and sidewalls of each chip 16-1 to 16-k, for example, a thickness approximately twice the thickness of each chip 16-1 to 16-k.

[0039] For example, such as Figure 3 As shown in (a), the insulating film 17 covers a plurality of chips 16-1 to 16-k from its surface 17a side (refer to...). Figure 2 Configured in way (b). In this state, as Figure 3 As shown in (b), the insulating film 17 is pressurized in the -Z direction with a specified stress. Thus, as Figure 2 As shown in (c), the insulating film 17 is adhered in such a way that it covers the surface 16a and side 16c of each of the plurality of chips 16-1 to 16-k. Then, as... Figure 3 As shown in (c), the insulating film 17 is cut into a shape corresponding to the semiconductor substrate 10. This forms a sealing body 18 in which the surfaces 16a and sidewalls 16c of each chip 16-1 to 16-k are covered by the insulating film 17. The sealing body 18 is, for example, a flat, disk-shaped component in the XY direction. Within the sealing body 18, the k chips 16-1 to 16-k are arranged in a matrix while being separated in the XY direction.

[0040] exist Figure 4 In step (a), the support 6 is attached to the back surface 17b of the seal 18. The support 6 is attached to the seal 18 by an adhesive formed on its surface 6a, or by the adhesiveness of the uncured insulating film 17. The support 6 only needs to be able to support the seal 18 and is not required to be rigid, so it can be formed of any translucent material. The support 6 has a shape corresponding to the seal 18, for example, a flat disc shape in the XY direction.

[0041] exist Figure 4 In step (b), the seal 18 is transferred from the sheet 5 to the support 6. While maintaining the back surface 17b supported by the support 6, the seal 18 is peeled from the sheet 5 to expose the surface 17a. Thus, a first-stage seal 18 is obtained with the back surface 17b supported by the support 6 and the surface 17a exposed.

[0042] exist Figure 4 In step (c), the second-stage seal 28 is prepared. The second-stage seal 28 and... Figure 1 (a)~ Figure 3 (c) is prepared in the same manner. The second-stage seal 28 is attached to the sheet 5. The first-stage seal 18 is positioned on the +Z side of the second-stage seal 28 by holding and moving the support 6, etc. Alternatively, the second-stage seal 28 is positioned on the -Z side of the first-stage seal 18 by moving the sheet 5 using the retaining member 101, etc.

[0043] exist Figure 5In process (a), the Y-positions of each chip 16-1 to 16-k in the first-stage sealing body 18 are offset by an offset amount D relative to the Y-positions of each chip 26-1 to 26-k in the second-stage sealing body 28. Since the support body 6 and the insulating films 17 and 27 are transparent, the positions of each chip 16-1 to 16-k and 26-1 to 26-k can be confirmed from the +Z side of the support body 6. Figure 6 As shown, the offset D is smaller than the Y-direction spacing of the chips 26 in the seal 28 and larger than the Y-direction dimension of the pads in the chips 26. Furthermore, the X-positions of each chip 16-1 to 16-k and the X-positions of each chip 26-1 to 26-k are mutually equal, but they can also be offset like the Y-positions.

[0044] exist Figure 5 In step (b), the first-stage sealing body 18 is stacked on top of the second-stage sealing body 28. Thus, a stacked body 7' is formed where the chip positions of the multiple sealing bodies 18 and 28 are offset relative to each other in the planar direction.

[0045] In the stack 7', multiple chips 16-1 to 16-k in the sealing body 18 correspond to multiple chips 26-1 to 26-k in the sealing body 28. In the stack 7', each chip 16-1 to 16-k is separated from its corresponding chip 26 and positioned towards the +Z side, and is electrically insulated from the corresponding chip 26. The Y position of each chip 16-1 to 16-k is offset by an offset D in the +Y direction relative to the Y position of its corresponding chip 26. The X position of each chip 16-1 to 16-k is equal to the X position of its corresponding chip 26.

[0046] exist Figure 5 In step (c), the laminate 7' is transferred from the sheet 5 to the support 6. While maintaining the surface 7a' supported by the support 6, the laminate 7' is peeled off from the back side 7b', exposing the back side 7b'. Thus, a laminate 7' is obtained where the surface 7a' is supported by the support 6 and the back side 7b' is exposed.

[0047] exist Figure 7 In step (a), the third-stage seal 38 is prepared. The third-stage seal 38 and... Figure 1 (a)~ Figure 3 (c) is prepared in the same manner. The third-level seal 38 is attached to the sheet 5. The laminate 7' is positioned on the +Z side of the third-level seal 38 by holding and moving the support 6, etc. Alternatively, the third-level seal 38 is positioned on the -Z side of the laminate 7' by moving the sheet 5 using the retaining member 101, etc.

[0048] exist Figure 7In process (b), the Y-positions of each chip 26-1 to 26-k in the second-stage sealing body 28 are offset by an offset D relative to the Y-positions of each chip 36-1 to 36-k in the third-stage sealing body 38. Since the support body 6 and insulating films 17, 27, and 37 are transparent, the positions of each chip 26-1 to 26-k and 36-1 to 36-k can be confirmed from the +Z side of the support body 6. The offset D is smaller than the Y-direction spacing of the chips 36 in the sealing body 38 and larger than the Y-direction dimension of the pads of the chips 36 (see reference). Figure 5 Furthermore, the X positions of chips 26-1 to 26-k can also be equal to those of chips 36-1 to 36-k. Figure 7 The offset D of (b) can also be related to Figure 5 of (a), Figure 6 The offsets D are equal.

[0049] exist Figure 8 In step (a), the laminate 7' is stacked on the +Z side of the third-level seal 38. Thus, a laminate 7 is formed in which the chip positions of multiple seals 18, 28, and 38 are offset relative to each other in the XY plane direction.

[0050] In the stack 7, multiple chips 16-1 to 16-k in the sealing body 18, multiple chips 26-1 to 26-k in the sealing body 28, and multiple chips 36-1 to 36-k in the sealing body 38 correspond to each other. In the stack 7, each chip 16-1 to 16-k is separated from its corresponding chip 26 and positioned towards the +Z side, and is electrically insulated from its corresponding chip 26. Each chip 26-1 to 26-k is separated from its corresponding chip 36 and positioned towards the +Z side, and is electrically insulated from its corresponding chip 36. The Y position of each chip 16-1 to 16-k is offset by an offset D in the +Y direction relative to the Y position of its corresponding chip 26. The Y position of each chip 26-1 to 26-k is offset by an offset D in the +Y direction relative to the Y position of its corresponding chip 36. The X position of each chip 16-1 to 16-k is equal to the X position of its corresponding chip 26 and equal to the X position of its corresponding chip 36. Viewed from the Z direction, the chip group consisting of chips 16, 26, and 36 arranged in the Z direction is arranged in a matrix while being separated from each other in the X and Y directions (see reference). Figure 6 ).

[0051] exist Figure 8 In step (b), the laminate 7 is transferred from the sheet 5 to the support 6. While maintaining the surface 7a supported by the support 6, the laminate 7 peels off the sheet 5 from the back side 7b, exposing the back side 7b. Thus, a laminate 7 is obtained in which the surface 7a is supported by the support 6 and the back side 7b is exposed.

[0052] exist Figure 8 In step (c), the support 8 is attached to the back side 7b of the laminate 7. An adhesive is formed on the surface 8a of the support 8. The support 8 can be made of a material (such as glass or silicon) that is more rigid than the support 6 and has both light transmission and rigidity. The support 8 has a shape corresponding to the laminate 7, for example, a flat disk shape in the XY direction.

[0053] exist Figure 9 In step (a), the laminate 7 is transferred from the support 6 to the support 8. While maintaining the back surface 7b supported by the support 8, the laminate 7 peels off the support 6 from the surface 7a, exposing the surface 7a. Thus, a laminate 7 is obtained in which the back surface 7b is supported by the support 8 and the surface 7a is exposed.

[0054] exist Figure 9 In step (b), through-holes 41, 42, and 43 are formed on the laminate 7 by laser processing or the like. The depths of through-holes 41, 42, and 43 are different, with the depth increasing sequentially. Through-holes 41-1 to 41-k reach the pads of chips 16-1 to 16-k on the seal 18 from the surface 7a of the laminate 7, respectively, exposing the pads. Through-holes 42-1 to 42-k reach the pads of chips 26-1 to 26-k on the seal 28 from the surface 7a of the laminate 7, respectively, exposing the pads. Through-holes 43-1 to 43-k reach the pads of chips 36-1 to 36-k on the seal 38 from the surface 7a of the laminate 7, respectively, exposing the pads.

[0055] At this time, because the positions of the chips 16, 26, and 36 of each sealing body 18, 28, and 38 in the laminate 7 are offset from each other, through holes 41, 42, and 43 can be formed simultaneously on the laminate 7. In addition, because the laminate 7 is supported by the rigid support body 6, through holes 41, 42, and 43 can be stably formed on the laminate 7.

[0056] exist Figure 9 In step (c), wiring structures such as through-hole plugs 44, 45, and 46 and electrode pads 47 are formed through sputtering and plating processes. Specifically, conductive material is embedded in through-holes 41, 42, and 43 to form through-hole plugs 44, 45, and 46. Then, conductive films are deposited and patterned to form electrode pads 47 electrically connected to the through-hole plugs 44, 45, and 46. For example, electrode pad 47-1 is electrically connected to the pads of chips 16-1, 26-1, and 36-1 via through-hole plugs 44-1, 45-1, and 46-1. Electrode pad 47-2 is electrically connected to the pads of chips 16-2, 26-2, and 36-2 via through-hole plugs 44-2, 45-2, and 46-2. Electrode pad 47-k is electrically connected to the pads of chips 16-k, 26-k, and 36-k via through-hole plugs 44-k, 45-k, and 46-k.

[0057] In addition, Figure 9 In (c), for the sake of simplicity, one electrode pad 47 is shown for each chip 16, 26, 36, but the electrode pad 47 can also be set for each through-hole plug 44, 45, 46.

[0058] exist Figure 10 In step (a), as shown by the dashed line, the target position for the cutting process is determined. The target position for the cutting process is selected so that it does not overlap with the chip group consisting of chips 16, 26, and 36 arranged along the Z direction, but is accessible to the support 8. The target position for the cutting process can be set as a grid-like line that separates the matrix arrangement of multiple chip groups consisting of chips 16, 26, and 36 arranged along the Z direction (see reference). Figure 6 ).

[0059] exist Figure 10 In step (b), cutting is performed along the target position until the support 8' is reached. As a result, the laminate 7 is divided into chip groups consisting of chips 16, 26, and 36 arranged along the Z direction, resulting in multiple mounting bodies 51-1, 51-2, ..., 51-k.

[0060] After that, it can be like Figure 11 As shown in (a), each mounting body 51 has a wiring layer 48 and contact electrodes 49 formed on the electrode pads 47, and is mounted in an LGA package. Thus, the semiconductor device 1 is configured in an LGA package. The contact electrodes 49 are electrically connected to the electrode pads 47, and the semiconductor device 1 can access the chips 16, 26, and 36 via the electrode pads 47 and through-hole plugs 44, 45, and 46.

[0061] Or, it can be like Figure 11 As shown in (b), each mounting body 51 has a wiring layer 52 and a ball electrode 53 formed on the electrode pad 47, and is mounted in a BGA package manner. Thus, the semiconductor device 1 is configured in a BGA package manner. The ball electrode 53 is electrically connected to the electrode pad 47, and the semiconductor device 1 can perform electrical processing on the chips 16, 26, and 36 via the electrode pad 47 and through-hole plugs 44, 45, and 46.

[0062] Or, it can be like Figure 11As shown in (c), each mounting body 51 is mounted on the surface of an organic substrate 54 on which ball electrodes 59 are disposed on the back side. A wiring layer 55 and an electrode 56 are formed on the electrode pad 47. The electrode 56 is bonded to the organic substrate 54 via wires 57 and sealed with resin 58, thus being mounted in a wire bonding package manner. Therefore, the semiconductor device 1 is configured in a wire bonding package manner. The ball electrodes 59 are electrically connected to the electrode pad 47 via wires 57 and electrodes 56, and the semiconductor device 1 can perform electrical processing on chips 16, 26, and 36 via the electrode pads 47 and through-hole plugs 44, 45, and 46.

[0063] Alternatively, although not shown, each mounting element 51 can also be installed as a commercial device such as a USB memory or SD card. Thus, the semiconductor device 1 is configured as a commercial device.

[0064] As described above, in this embodiment, during the manufacture of semiconductor device 1, the spacing between multiple chips is increased on a sheet, and an insulating film is used to laminate the multiple chips to form a sealing body. Multiple such sealing bodies are stacked while being offset. Therefore, even when each chip is thin, individual chip operations are not performed, and mounting is achieved at low cost and stably. That is, while compactly mounting multiple chips, the productivity of manufacturing semiconductor device 1 is improved.

[0065] in addition, Figure 2 The extended process shown in (b) can also be used Figure 12 and Figure 13 The semiconductor manufacturing apparatus 100 shown is used for this purpose. Figure 12 This is a cross-sectional view showing the structure of the semiconductor manufacturing apparatus 100 in the first variation of the embodiment. Figure 13 This is a top view showing the structure of the semiconductor manufacturing apparatus 100 in the first variation of the embodiment.

[0066] The semiconductor manufacturing apparatus 100 includes a stage 102, a measuring mechanism 103, an expansion mechanism 104, an operating mechanism 106, and a controller 107. The measuring mechanism 103 includes an image sensor 103a and an image sensor 103b. The expansion mechanism 104 includes multiple holding members 101-1 to 101-2k and multiple driving elements 105-1 to 105-k. k is any integer greater than 2.

[0067] The worktable 102, on its main surface on the +Z side, is supported by a processing mechanism 106. The sheet 5 is a diced strip or similar material, and an adhesive is formed on its surface 5a. The sheet 5 is, for example, formed of a transparent resin with light transmittance. A semiconductor substrate 10 (see reference) is adhered to the surface 5a of the sheet 5. Figure 1(c) The semiconductor substrate 10 is monolithically divided into k chips 16-1 to 16-k by cutting and other processes. On the sheet 5, the k chips 16-1 to 16-k are arranged in a matrix in the XY direction.

[0068] The measuring mechanism 103 measures the position of each chip 16 in the sheet 5. The measuring mechanism 103 supplies the measurement results to the controller 107.

[0069] The expansion mechanism 104 expands the sheet 5 based on the measurement results of the measuring mechanism 103. The controller 107 controls the amount of expansion performed by the expansion mechanism 104 based on the deviation between the position of the chip 16 measured by the measuring mechanism 103 and the target position. The controller 107 determines the amount of expansion of the sheet 5 in a manner that eliminates this deviation and supplies the determined amount of expansion to the expansion mechanism 104. The expansion mechanism 104 expands the sheet 5 outward according to the amount of expansion received from the controller 107. Thus, the positions of each chip 16 in the sheet 5 can be brought close to the target position, enabling high-precision expansion of the sheet 5.

[0070] The worktable 102 includes a worktable base 102a and an adsorption mechanism 102b. The adsorption mechanism 102b has multiple adsorption holes 102b1-1 to 102b1-n, multiple on / off valves 102b2-1 to 102b2-n, an exhaust pipe 102b3, and a vacuum device 102b4. The worktable base 102a is a flat plate with a sheet 5 mounted on its upper surface. n is any integer greater than 2. The open ends of the multiple adsorption holes 102b1-1 to 102b1-n are arranged two-dimensionally on the upper surface of the worktable base 102a. Each adsorption hole 102b1-1 to 102b1-n extends through the worktable base 102a in a direction substantially perpendicular to the upper surface of the worktable base 102a, and can communicate with the exhaust pipe 102b3. The exhaust pipe 102b3 communicates with the exhaust chamber of the vacuum device 102b4. Each adsorption pore 102b1-1~102b1-n can be vacuumed through the exhaust pipe 102b3 and the vacuum device 102b4.

[0071] Multiple on / off valves 102b2-1 to 102b2-n correspond to multiple adsorption holes 102b1-1 to 102b1-n. Each on / off valve 102b2-1 to 102b2-n opens and closes its corresponding adsorption hole 102b1-1 to 102b1-n according to control from the controller 107. Each adsorption hole 102b1-1 to 102b1-n locally adsorbs the sheet 5 when the vacuum is exhausted. The controller 107, by opening and closing the corresponding on / off valves 102b2 to each adsorption hole 102b1-1 to 102b1-n in the adsorption mechanism 102b, can perform two-dimensional control of the adsorption state of the sheet 5.

[0072] The operating mechanism 106 has arms 106a and 106b, which are used to operate the sheet 5. Arms 106a and 106b adsorb the surface 5a of the sheet 5 and place it on the worktable base 102a. The sheet 5 is adsorbed by the adsorption mechanism 102b onto at least a portion of the adsorption holes 102b1 of the plurality of adsorption holes 102b1-1 to 102b1-n on the worktable base 102a. In this state, the arms 106a and 106b cut the sheet 5 into a generally circular shape.

[0073] The extension mechanism 104 has multiple retaining members 101-1 to 101-2k and multiple driving elements 105-1 to 105-k. The extension mechanism 104 uses the multiple retaining members 101-1 to 101-2k to retain k portions of the sheet 5. These multiple portions are mutually different locations on the outer periphery of the sheet 5. The multiple retaining members 101-1 to 101-2k comprise groups of k sets of two retaining members 101 that hold the sheet 5 vertically. Figure 13 As shown, retaining members 101-1 and 101-2 hold the sheet 5 vertically at a first position on the outer periphery of the generally circular sheet 5. Retaining members 101-3 and 101-4 hold the sheet 5 vertically at a second position on the outer periphery of the generally circular sheet 5. Retaining members 101-(2k-1) and 101-k hold the sheet 5 vertically at a k-th position on the outer periphery of the generally circular sheet 5. The first position to the k-th position correspond to k groups of retaining members 101. The k groups of retaining members 101 correspond to k driving elements 105. The expansion mechanism 104 drives each group of retaining members 101 at the first position to the k-th position using the corresponding driving elements 105, enabling the sheet 5 to expand two-dimensionally.

[0074] For example, such as Figure 14 As shown in (a), the semiconductor substrate 10 is monolithically divided into k chips 16-1 to 16-k through cutting or other processes. On the sheet 5, the k chips 16-1 to 16-k are arranged in a matrix in the XY direction. In this state, the measuring mechanism 103 measures the position of each chip 16-1 to 16-k and supplies the measurement results to the controller 107. The controller 107 calculates the two-dimensional expansion amount of the sheet 5 to be expanded based on the deviation between the position of each chip 16 measured by the measuring mechanism 103 and the target position. The controller 107 decomposes the calculated expansion amount into the driving amounts of multiple driving elements 105-1 to 105-k. Based on the decomposed driving amounts of the multiple driving elements 105-1 to 105-k, the controller 107 controls the multiple driving elements 105-1 to 105-k to independently drive multiple holding members 101-1 to 101-2k.

[0075] Therefore, as Figure 14As shown in (b), the sheet 5 extends outward in the XY direction, increasing the spacing between the chips 16-1 to 16-k. In this state, the measuring mechanism 103 measures the position of each chip 16-1 to 16-k and supplies the measurement results to the controller 107. The controller 107 calculates the deviation between the position of each chip 16 measured by the measuring mechanism 103 and the target position, and determines whether the deviation is within the allowable range. If the deviation is not within the allowable range, the controller 107 calculates the two-dimensional expansion amount of the sheet 5 to be expanded. The controller 107 decomposes the calculated expansion amount into the driving amount of multiple driving elements 105-1 to 105-k. Based on the decomposed driving amounts of the multiple driving elements 105-1 to 105-k, the controller 107 controls the multiple driving elements 105-1 to 105-k to independently drive the multiple holding members 101-1 to 101-2k.

[0076] Therefore, as Figure 14 As shown in (c), the sheet 5 extends outward in the XY direction, further increasing the spacing between the chips 16-1 to 16-k. In this state, the measuring mechanism 103 measures the position of each chip 16-1 to 16-k and supplies the measurement results to the controller 107. The controller 107 calculates the deviation between the position of each chip 16 measured by the measuring mechanism 103 and the target position, and determines whether the deviation is within the allowable range. If the deviation is within the allowable range, the controller 107 terminates the expansion of the sheet 5. Thus, the expansion mechanism 104 can perform two-dimensional expansion of the sheet 5 while making the expansion amount two-dimensionally variable.

[0077] Thus, in the semiconductor manufacturing apparatus 100, the controller 107 controls the expansion mechanism 104 to expand the wafer 5 based on the measurement results of the measuring mechanism 103. The controller 107 controls the amount of expansion performed by the expansion mechanism 104 based on the deviation between the position of the chip 16 measured by the measuring mechanism 103 and the target position. Therefore, the position of each chip 16 in the wafer 5 can be made close to the target position, enabling high-precision expansion of the wafer 5.

[0078] Next, a second variation of the implementation method will be described.

[0079] For example, it can also be in Figure 8 After process (b) Figure 15 (a)~ Figure 16 The process shown in (b). Figure 15 (a)~ Figure 16 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to a second variation of the embodiment.

[0080] exist Figure 15In step (a), an adhesive sheet 9 is adhered to the back side 7b of the laminate 7, and a support 8 is adhered to the back side 9b of the adhesive sheet 9. An adhesive is formed on the surface 9a of the adhesive sheet 9. The adhesive sheet 9 can be formed of a translucent material (e.g., resin). Both the adhesive sheet 9 and the support 8 have shapes corresponding to the laminate 7, such as a flat, disc-shaped form in the XY direction. The rigidity of the adhesive sheet 9 can also be less than that of the support 8.

[0081] exist Figure 15 In step (b), the laminate 7 is transferred from the support 6 to the adhesive sheet 9 and the support 8. While maintaining the back surface 7b supported by the support 8 via the adhesive sheet 9, the laminate 7 peels off the support 6 from the surface 7a, exposing the surface 7a. Thus, a laminate 7 is obtained in which the back surface 7b is supported by the adhesive sheet 9 and the support 8 and the surface 7a is exposed.

[0082] exist Figure 15 In step (c), through holes 41, 42, and 43 are formed on the laminate 7 by laser processing or the like. At this time, because the positions of the chips 16, 26, and 36 of each sealing body 18, 28, and 38 in the laminate 7 are offset from each other, through holes 41, 42, and 43 can be formed simultaneously on the laminate 7. Furthermore, since the laminate 7 is supported by the rigid support body 6 via the adhesive sheet 9, through holes 41, 42, and 43 can be stably formed on the laminate 7. If the rigidity of the support body 6 is high, the laminate 7 can be stably supported even if the rigidity of the adhesive sheet 9 is low.

[0083] exist Figure 16 In process (a), wiring structures such as through-hole plugs 44, 45, 46 and electrode pads 47 are formed through sputtering and plating processes.

[0084] exist Figure 16 In step (b), as shown by the dashed line, the target position for cutting is determined.

[0085] exist Figure 16 In step (c), the cutting process is carried out along the target position until the bonding sheet 9' is reached. As a result, the laminate 7 is divided into chip groups consisting of chips 16, 26, and 36 arranged along the Z direction, resulting in multiple mounting bodies 51-1, 51-2, ..., 51-k.

[0086] At this point, the grooves formed by the cutting process do not reach the support body 8. Therefore, the support body 8 can be reused when manufacturing the next semiconductor device.

[0087] Next, a third variation of the implementation method will be described.

[0088] For example, it can also be in Figure 1 After process (b) Figure 17(a)~ Figure 21 The process shown in (b). Figure 17 (a)~ Figure 21 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third variation of the embodiment.

[0089] exist Figure 17 In process (a), the semiconductor substrate 30 is transferred from sheet 3 to sheet 5. The surface 30a of the semiconductor substrate 30 is adhered to the sheet 5. At this time, the semiconductor substrate 30 is adhered to the sheet 5 with its back side 30b exposed (inverted state).

[0090] exist Figure 17 In process (b), the semiconductor substrate 30 is divided into k chips 36-1 to 36-k. Each chip 36-1 to 36-k is attached to the sheet 5 with its back side 36b exposed (in a flip-chip state).

[0091] exist Figure 17 In process (c), the sheet 5 is expanded, and the spacing between the multiple chips 36-1 to 36-k on the sheet 5 is increased. Each chip 36-1 to 36-k is attached to the sheet 5 with its back surface 36b exposed and its surface 36a exposed.

[0092] exist Figure 18 In process (a), the back surface 36b and side surface 36c of each of the multiple chips 36-1 to 36-k (refer to) Figure 17 (c) is covered by insulating film 37, forming a third-level seal 38.

[0093] exist Figure 18 In process (b), on the back surface 37b of the sealing body 38, a replacement support 6 (see reference) is placed. Figure 4 (a)) and the support body 8 is attached thereon. The support body 8 can also be attached to the support body 8 in the embodiment. Figure 8 The support 8 is the same as that pasted on the back side 7b of the laminate 7 in process (c).

[0094] exist Figure 18 In step (c), the seal 38 is transferred from the sheet 5 to the support 8. Thus, a third-stage seal 38 is obtained, with its back surface 37b supported by the support 8 and its surface 37a exposed.

[0095] exist Figure 19 In process (a), the second-stage sealing body 28 is prepared. The second-stage sealing body 28 and... Figure 17 (a)~ Figure 18(c) is prepared in the same manner. The third-stage seal 38 is positioned on the +Z side of the second-stage seal 28 by holding the support 6 and moving it, etc. Alternatively, the second-stage seal 28 is positioned on the -Z side of the third-stage seal 38 by moving the sheet 5 using the retaining member 101, etc.

[0096] exist Figure 19 In process (b), the Y position of each chip 36-1 to 36-k in the third-stage sealing body 38 is offset by an offset amount D relative to the Y position of each chip 26-1 to 26-k in the second-stage sealing body 28.

[0097] exist Figure 19 In process (c), the third-level sealing body 38 is stacked on top of the second-level sealing body 28. Thus, a stacked body 7 is formed where the chip positions of multiple sealing bodies 38 and 28 are offset relative to each other in the planar direction.

[0098] exist Figure 20 In process (a), the laminate 7” is transferred from the sheet 5 to the support 8. Thus, a laminate 7” is obtained with the back side 7b” supported by the support 6 and the surface 7a” exposed.

[0099] exist Figure 20 In process (b), the first-stage sealing body 18 is prepared. The first-stage sealing body 18 and... Figure 17 (a)~ Figure 18 (c) is prepared in the same way. The laminate 7” is positioned on the +Z side of the first-stage seal 18 by holding the support 6 and moving it, etc. Alternatively, the first-stage seal 18 is positioned on the -Z side of the laminate 7” by moving the sheet 5 using the retaining member 101, etc.

[0100] exist Figure 20 In process (c), the Y position of each chip 16-1 to 16-k in the first-stage sealing body 18 is offset by an offset amount D relative to the Y position of each chip 26-1 to 26-k in the second-stage sealing body 28.

[0101] exist Figure 21 In step (a), the laminate 7” is stacked on the +Z side of the first-stage seal 18. Thus, a laminate 7 is formed in which the chip positions of multiple seals 18, 28, 38 are offset relative to each other in the XY plane direction.

[0102] exist Figure 21 In step (b), the laminate 7 is transferred from the sheet 5 to the support 8. As a result, a laminate 7 is obtained in which the back side 7b is supported by the support 8 and the surface 7a is exposed.

[0103] After that, proceed with... Figure 9(b) The same process afterward.

[0104] Thus, since the sealing body is formed by flipping the chips, the semiconductor device 1 can be manufactured without intermediately using the support 6 (see reference). Figure 11 Therefore, the manufacturing process of semiconductor device 1 is simplified, and the manufacturing cost of semiconductor device 1 can be reduced.

[0105] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: Attach the substrate to the sheet; The substrate is segmented and monolithically divided into multiple chips; Expand the sheet to increase the spacing between the plurality of chips; A sealed body is formed by covering the main surface and side surfaces of each of the plurality of chips with an insulating film; and A laminated body is formed by stacking multiple of the aforementioned sealing bodies. The plurality of sealing bodies includes a first sealing body and a second sealing body. The process of forming the laminate includes the following steps: with the position of the chip in the second sealing body offset in the planar direction relative to the position of the chip in the first sealing body, the second sealing body is laminated on top of the first sealing body.

2. The method for manufacturing a semiconductor device according to claim 1, wherein, The amount of offset is smaller than the chip spacing in the first seal and larger than the size of the pads in the chip.

3. The method for manufacturing a semiconductor device according to claim 1, wherein, The process of increasing the spacing between the plurality of chips includes the following steps: The position of the chip in the sheet is measured, and the sheet is expanded according to the measurement result to increase the spacing between the multiple chips towards the target spacing.

4. The method for manufacturing a semiconductor device according to claim 1, wherein, It also includes the step of transferring the sealant from the sheet to the first support. The process of forming the laminate includes the process of laminating the second sealant, which is transferred to the first support, onto the first sealant. The method for manufacturing the semiconductor device further includes the following steps: The laminate is transferred from the first support to a second support that is more rigid than the first support; and A wiring structure is formed, which is electrically connected to the chips in the plurality of seals while the laminate is supported by the second support.

5. The method for manufacturing a semiconductor device according to claim 1, wherein, The process of forming the seal includes sealing the back and sides of each of the plurality of chips by covering them with resin. The method for manufacturing the semiconductor device further includes a step of transferring the seal from the sheet onto a first support. The lamination process includes forming the laminate while the transferred seal is supported by the first support. The method for manufacturing the semiconductor device further includes the following steps: The process of forming a wiring structure, wherein the wiring structure is electrically connected to the chips in the plurality of seals while the laminate is supported by the first support.

6. A method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein, In the stacked structure, the chip in the first sealing body and the chip in the second sealing body are electrically insulated from each other.

7. A semiconductor device manufactured using the semiconductor device manufacturing method according to any one of claims 1 to 6, comprising: The first sealing body has a plurality of first chips arranged at intervals; The second sealing body is disposed on the upper side of the first sealing body and has a plurality of second chips arranged at intervals. The first via extends upward from the first device layer of the first chip; The second via extends upward from the second device layer of the second chip; as well as A wiring layer is disposed on the upper side of the second sealing body and is electrically connected to the first through hole and the second through hole.

8. The semiconductor device according to claim 7, wherein, The lower surface of the first chip is exposed from the first seal.

9. The semiconductor device according to claim 7 or 8, wherein, The first sealing body covers the side of the first through hole. The second sealing body covers the side of the second through hole.

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