Packaged semiconductor device with improved reliability and inspectability and method of manufacturing the same

Abstract

Embodiments of the present disclosure relate to packaged semiconductor devices having improved reliability and inspectability and methods of manufacturing the same. A packaged device has a carrier base, a receiving cavity in the carrier base, a semiconductor die in the receiving cavity, the semiconductor die having a die pad, a protective layer covering the semiconductor die and the carrier base, a first via in the protective layer at the die pad, and a connection terminal of conductive material. The connection terminal has a first connection portion in the first via and in electrical contact with the die pad, and a second connection portion extending on the protective layer along a side of the packaged device.

Description

Technical Field

[0001] This disclosure relates to a packaged semiconductor device with improved reliability and inspectability, and a method for manufacturing the same. Background Technology

[0002] Semiconductor devices comprising a single die or multiple intercoupled dies are known to be packaged in a housing or package of an insulating material (typically resin or composite material). These packages can have different configurations depending on the intended mounting type. Furthermore, if the device is designed to operate at high voltage and / or high current, these packages typically include structures capable of dissipating heat on one or more surfaces. Summary of the Invention

[0003] This disclosure provides a packaging that overcomes the shortcomings of the prior art.

[0004] According to this disclosure, a packaged electronic device and a method for manufacturing the same are provided.

[0005] In at least one embodiment, an electronic device includes a package device, a support, and an adhesive region. The package device includes: a front side, a back side opposite to the front side, and a side extending between the front and back sides; a carrier base; a receiving cavity in the carrier base; a semiconductor die in the receiving cavity, the semiconductor die having die pads; a protective layer covering the semiconductor die and the carrier base; a first via at the die pads and in the protective layer; and a connection terminal of conductive material, the connection terminal having a first connection portion and a second connection portion, the first connection portion being in the first via and electrically contacting the die pads, and the second connection portion extending along the side of the package device on the protective layer. The support has a conductive contact area facing the first connection portion of the connection terminal. The adhesive region is between the conductive contact area and the front side of the device and electrically contacts the connection terminal, the adhesive region further extending along the side of the package device and contacting the second connection portion of the connection terminal. Attached Figure Description

[0006] To better understand this disclosure, embodiments thereof are now described by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0007] Figures 1 to 10 The cross-sections of the example device are compared during successive packaging steps;

[0008] Figure 11 yes Figure 10 Side view of the comparative example device;

[0009] Figure 12 yes Figure 10 A portion of the comparative example device is similar to Figures 1 to 10 A magnified cross-sectional view;

[0010] Figures 13 to 21 This is a cross-section of the device during the successive steps of this packaging method according to an embodiment;

[0011] Figure 22 yes Figure 14 A top view of the intermediate structure;

[0012] Figure 23 and Figure 24 Two different embodiments are shown. Figure 20 A top view of the middle structure section;

[0013] Figure 25 This is a side view of the packaged device after it has been soldered onto the board;

[0014] Figure 26 It is along Figure 25 The section line XXVI-XXVI intercepted Figure 25 A magnified cross-sectional view of a portion of the device; and

[0015] Figure 27 It shows Figure 26 Changes in cross-section. Detailed Implementation

[0016] In the following text, reference will be made to a surface mount package with double-sided cooling and input / output (I / O) pads arranged on the bottom surface of the device.

[0017] For example, US2017 / 0148746 (US10,083,888) describes different surface mount package structures designed to reduce the risk of die / chip damage during the lamination of housing materials. In these known package structures, a conductive base, typically made of metal, has a cavity to accommodate the die and a protective layer through which conductive vias pass.

[0018] For example, the encapsulation structure of the type described in the aforementioned patent can be used Figures 1 to 10 The process shown and described below is used to form it.

[0019] Figure 1 A conductive base 1 of a metal (such as copper or other metals or metal alloys) is shown, the conductive base 1 having a top surface 1A and a bottom surface 1B.

[0020] The top surface 1A is shaped and has multiple receiving cavities 2, which are surrounded by separation cavities 3. The receiving cavities 2 may have a generally parallelepiped shape, wherein the bottom surface 2A is connected to the sidewall 2B. The sidewall 2B is defined by protrusions 4 of the conductive base 1.

[0021] The conductive base 1 can be formed, for example, by a metal strip, which is processed to remove metal from cavities 2 and 3.

[0022] refer to Figure 2 The bare die 7 is bonded to the receiving cavity 2 via conductive adhesive regions 8, such as conductive gel or epoxy resin layers.

[0023] The die 7 may integrate a single power component or integrated circuit, which includes a power component, a processing component, and electrical connections, schematically shown in the figure and connected to the outside via pads 9 arranged on the front side of the die 7.

[0024] The bare sheet 7 is attached to the bottom surface 2A of the corresponding receiving cavity 2 on its back side.

[0025] Subsequently, Figure 3 For example, a protective layer 10 is deposited on the conductive substrate 1 and the bare die 7 using a lamination technique. The protective layer 10 is made of polyamide (so-called prepreg), for example. The protective layer 10 is deposited in a fluid state to penetrate into the receiving cavity 2, between the sidewall 2B and the bare die 7, and within the separation cavity 3, and completely covers the bare die 7 with a portion 10A extending above the receiving cavity 2.

[0026] exist Figure 4 In this process, after the protective layer 10 is covered by a thin anti-reflective layer (not shown) of, for example, copper, a via 13 may be formed in the protective layer 10, for example, by laser drilling. The via 13 extends over the entire thickness of portion 10A of the protective layer 10 to the pad 9, thus exposing the pad 9. In addition, the via 13 is also formed on the protrusion 4.

[0027] exist Figure 5 In this process, a conductive layer 14 is formed on the protective layer 10 and fills the via 13. The conductive layer 14 may be made of copper or its alloy.

[0028] exist Figure 6 In this process, the conductive layer 14 is patterned, for example by etching, to form connection regions 15, each connection region 15 being in electrical contact with a corresponding pad 9 or a corresponding protrusion 4 of the conductive base 1.

[0029] exist Figure 7 In this configuration, a first insulating layer 16 (e.g., an insulating alloy or solder) is formed and shaped above and between the connection regions 15. The first insulating layer 16 has a first opening 17 at the connection regions 15.

[0030] Furthermore, a second insulating layer 20 is formed and shaped on the bottom surface 1B of the conductive base 1. The second insulating layer 20 has a second opening 21, for example, one second opening 21 for each die 7, and the second opening 21 is located below the corresponding die 7.

[0031] exist Figure 8In the conductive base 1, a top outer pad 22 is formed in a first opening 17 in the first insulating layer 16, and a bottom outer pad 23 is formed in a second opening 21 on the bottom surface 1B of the conductive base 1. The outer pads 22 and 23 are made of conductive material and are formed, for example, by an electroless nickel immersion gold (ENIG) process (i.e., by electroplating growth of nickel and formation of a thin gold layer obtained by immersion) to improve solderability and non-oxidation.

[0032] The connection area 15 and the top external pad 22 form the top terminal of the device; the bottom external pad 23 forms the bottom terminal and the heat dissipation surface of the device (not yet separated).

[0033] Connection elements (not shown), such as solder balls, can be formed on the outer pads 22 and 23 in a manner not shown.

[0034] In the following text, Figure 9 In this process, the conductive base 1 is cut along a scribe line passing through the protective layer 10 arranged in the separation cavity 3 to form a single packaged device 25 (one is shown). For example, in Figure 9 In the package 25, the package device 25 includes a single die 7 arranged in its own receiving cavity 2.

[0035] exist Figure 10 In this process, the packaged device 25 is flipped and bonded to, for example, a printed circuit board 26 via soldering areas 27 of conductive material applied to the top outer pads 22 and soldered to contacts 28 formed on the board 26 (see also...). Figure 11 Side view and Figure 12 (Enlarged cross-section).

[0036] return Figure 10 The bottom outer pad 23 remains exposed here and can be used for electrical connection of the conductive base 1 in a manner not shown.

[0037] Figure 11 and Figure 12 The package shown provides good protection and high dissipation, but can be improved.

[0038] In fact, it does not allow for simple inspection of the soldering areas 27 that electrically connect the front external pads 23 to the board 26, because they are arranged to be hidden beneath the packaged device 25, as can be seen from... Figure 11 and Figure 12 As seen in [the image / image]. Therefore, their integrity may not be guaranteed, thus reducing board-level reliability (BLR).

[0039] On the other hand, an increasing number of applications (such as automobiles) have high reliability and quality requirements that cannot be achieved using the packaging described.

[0040] Figure 13 A support base 30 is shown, which is typically made of metal (such as copper or other metals or alloys) and has a top surface 30A and a bottom surface 30B.

[0041] The top surface 30A is shaped and has multiple receiving cavities 32, which are surrounded by separation cavities 33.

[0042] The separation cavity 33 has, for example, a grid shape and extends along a first line passing through the drawing plane (a first axis Y parallel to the Cartesian reference system XYZ) and a second line along a second axis X parallel to the Cartesian reference system XYZ.

[0043] The receiving cavity 32 may have a substantially parallelepiped, cubic, generally polyhedral, or even cylindrical shape, and is provided with a bottom surface 32A connected to the sidewall 32B. The sidewall 32B is formed by the boundary wall 34 of the supporting base 30.

[0044] The support base 30 may be formed, for example, from a metal strip that is processed to remove metal from cavities 32 and 33.

[0045] refer to Figure 14 The bare die 37 is bonded to the receiving cavity 32 via conductive adhesive regions 38, such as conductive gel or epoxy resin layers.

[0046] Die 37 may integrate a single power component or integrated circuit, which includes power components, processing components and electrical connections, schematically shown in the figure and connected to the outside via die pads 39 arranged on the front side of die 37.

[0047] The bare die 37 is attached to the bottom surface 32A of the corresponding receiving cavity 32 on its back side.

[0048] Subsequently, Figure 15 For example, a protective layer 40 is deposited on the support base 30 and the die 37 using a lamination technique. The protective layer 40 is made of polyamide (so-called prepreg), for example. The protective layer 40 is deposited in a fluid state to penetrate into the receiving cavity 32, between the sidewall 2B and the die 37, and within the separation cavity 33 (where it forms a fill portion 35 with a grid shape having the separation cavity 33). The protective layer 40 also completely covers the die 37 with a cover portion 40A, which extends over the receiving cavity 32 and the fill portion 35.

[0049] The covering portion 40A of the protective layer 40 may have a thickness between 100 and 150 μm.

[0050] exist Figure 16In this process, after the protective layer 40 is covered by a thin anti-reflective layer (not shown) of, for example, copper, a first via 43A and a second via 43B may be formed, for example, by laser drilling through the covered portion 40A of the protective layer 40. The first via 43A extends along the entire thickness of the covered portion 40A of the protective layer 10 to the die pad 39, thus exposing the die pad 39; the second via 43B extends on the boundary wall 34 of the carrier base 30.

[0051] Furthermore, a groove 41 is formed in the filling portion 35 of the separation cavity 33. The depth of the groove 41 can be equal to that of the through holes 43A and 43B (e.g., Figure 16 (As shown) or different depths, typically larger, up to half the thickness of the carrier base 30 or even more (if desired). For example, depending on the package type, the depth of the recess 41 can be at least 100 μm, typically 150 to 200 μm, but in the case of a 700 μm thick package, the recess 41 can reach 350 μm. However, in the case of a standard MLP / QFN package, the recess 41 can also have a smaller thickness, such as 75 to 95 μm.

[0052] The groove 41 also has a minimum width of 100 μm, or in any case, such that the groove 41 can be coated in a subsequent electroplating step, as referenced below. Figure 17 As stated, it does not need to be filled.

[0053] The groove 41 can be formed at a predetermined location, at vias 43A and 43B (hereinafter collectively referred to as vias 43 if no distinction is necessary), or along the line of the separation cavity 33 by laser ablation, cutting through the blade / saw surface, shallow cutting, or even etching. Figure 22 As shown (actually forming a single grid-like groove).

[0054] When the groove 41 is formed by laser ablation or etching, the groove 41 can be formed simultaneously with the via 43.

[0055] The groove 41 may have vertical walls, especially when formed by cutting with a blade / saw, or if formed by laser ablation, it may have slightly inclined walls (2 to 3°).

[0056] If the groove 41 is formed by cutting with a blade / saw, the groove 41 has imperfectly smooth walls, which can help with adhesion in subsequent electroplating steps (see below for reference). Figure 17 The above).

[0057] exist Figure 17In this process, a conductive layer 44 is formed on the protective layer 40 and fills the via 43. The conductive layer 44 also covers the bottom and sidewalls of the groove 41. The conductive layer 44 may be made of copper or its alloy and has a thickness of 35 to 70 μm, which also conforms to the width of the groove 41, and may be electroplated (copper plated).

[0058] exist Figure 18 In this process, the conductive layer 44 is defined or patterned, for example by etching, to form a connection region 45 for electrical connection between the die pad 39 and the carrier base 30.

[0059] Each connection area 45 has a connection portion 45A extending in the corresponding through hole 43; a surface portion 46A extending above the protective layer 40; and a vertical portion 46B extending on the side flank of the adjacent groove 41.

[0060] exist Figure 19 In, for example, an alloy or insulating solder first insulating layer 47 is formed in Figure 18 Above the middle structure. Then, the first insulating layer 47 is patterned to have a first opening 48 at the connection region 45.

[0061] Furthermore, a second insulating layer 50 is formed and patterned on the bottom surface 30B of the support base 30. The second insulating layer 50 has a second opening 51, for example, one second opening 51 for each die 37, the second opening 51 being located below the respective die 37.

[0062] Typically, the first insulating layer 47 and the second insulating layer 50 have the same material and can be deposited and patterned in two different steps.

[0063] exist Figure 20 In the first insulating layer 47, a front external connection is formed in the connection area 45; and a rear external connection 53 is formed in the second opening 51 on the bottom surface 30B of the support base 30. The rear external connection 53 also forms a heat dissipation surface.

[0064] In particular, Figure 20 In the middle, the front external connection 52 has a top portion 54 extending directly on the front side of the bare sheet 37 on the surface portion 46A of the connection area 45; a side portion 55 extending on the vertical portion 46B of the connection area 45; and a bottom portion 56 extending on the bottom 46C of the connection area 45.

[0065] The external connections 52 and 53 are made of highly conductive materials and are formed, for example, by an electroless nickel immersion gold (ENIG) process (i.e., by electroplating growth of nickel and the formation of a thin gold layer obtained by immersion).

[0066] In this step, the vertical portions 46B and side portions 55 of the two different bare sheets 37 facing each other can still pass through the bottom portion 46C and bottom portion 56 at the bottom of the groove 41 (e.g., as shown). Figure 23 (As shown) are connected to each other and then separated in a cutting step, as described below.

[0067] Alternatively, such as Figure 24 As shown, the vertical portions 46B and side portions 55 of the different bare sheets 37 facing each other can be separated from each other, while the smaller bottom portion 46C and bottom portion 56 are not connected in pairs.

[0068] In the following text, Figure 21 middle, Figure 20 The intermediate structure is cut along a scribe line passing through the fill portion 35 of the protective layer 40 to form a single packaged device 57 (one is shown). For example, in Figure 21 In the package 57, the package device 57 includes a single die 37 arranged in its own receiving cavity 32.

[0069] In fact, the scribe line passes through the bottom portion 56 of the front external connection 52 to almost completely remove them, and the side portion 55 of the front external connection 52 is exposed along the side of the package device 57.

[0070] After cutting, each packaged device 57 has a front side 57A, a back side 57B opposite to the front side, and a side side 57C extending between the front side and the back side.

[0071] In this way, after cutting, the connection area 45 and the front external connection 52 form the I / O terminal 49 of the package device 57. Specifically, the I / O terminal 49 is formed by a first connection portion, a second connection portion, and a third connection portion. The first connection portion is in the via 43 and makes electrical contact with the die pad 39 (formed by the connection portion 45A of the connection area 45). The second connection portion includes a vertical portion 46B of the connection area 45 and a side portion 55 of the front external connection 52 extending along the side surface 57C of the package device 57 above the protective layer 40. The third connection portion includes a surface portion 46A of the connection area 45 and a top portion 54 of the front external connection 52 extending along the front surface 57A of the package device 57 above the protective layer 40.

[0072] It is worth noting that the surface portion 46A of the connection area 45 and the top portion 54 of the front external connection 52 are shaped to electrically connect the die pad 39 and the boundary wall 34 in a manner clearly understood by those skilled in the art, according to a desired configuration. For example, Figure 27 An embodiment is shown in which the front external connection 52 does not extend above the first via 43A.

[0073] Then, in Figure 25 In this configuration, the packaged device 57 is flipped and bonded to a board 58, such as a printed circuit board. For this purpose, the board 58 has contacts 60 arranged at I / O terminals 49 and precisely positioned at the top portion 54 of the front external connection 52; solder regions 59 of conductive material (e.g., solder) have been pre-applied to the contacts 60 or I / O terminals 49 on the board 58. According to techniques known to those skilled in the art, the solder regions 59 can be applied by screen printing and heat treatment.

[0074] In particular, such as Figure 26 As can be seen in the cross-section, in the package device 57, the solder area 59 can adhere to both the top portion 54 and the side portion 55 of the front external connection 52.

[0075] Therefore, packaged device 57 has a wettable wing package, as desired in some applications where high board-level reliability (BLR) is required, such as in the automotive field.

[0076] In fact, in this way, the solder area is significantly increased; in addition, the side portion 55 of the front external connection 52 can be optically inspected in a simple manner by both manual operation and automatic means, thereby allowing easy verification of solder integrity (reliable and inspectable meniscus).

[0077] These advantages become more pronounced as the groove 41 becomes deeper and thus the height of the side portion 55 of the front external connection 52 (and the corresponding lower vertical portion 46B of the connection area 45) increases (as described above, it can reach half the thickness of the support base 30) (as a first approximation, equal to the thickness of the package device 57).

[0078] Furthermore, the packaged device 57 thus obtained has a comparable, and only slightly higher, manufacturing cost compared to known devices, because it includes only one additional operational step for forming the recess 41.

[0079] Finally, it is obvious that modifications and variations may be made to the packaging devices and manufacturing methods described and illustrated herein without departing from the scope of this disclosure as defined in the appended claims.

[0080] For example, each receiving cavity 32 may contain more than one bare die 37.

[0081] A package device (57) having a front side (57A), a back side (57B) opposite to the front side, and a side surface (57C) extending between the front side and the back side can be summarized as including: a carrier base (30); a receiving cavity (32) in the carrier base; a die (37) in the receiving cavity (32), the semiconductor die having a die pad (39); a protective layer (40) covering the semiconductor die and the carrier base; a first via (43A) in the protective layer at the die pad (39); and a connection terminal (49) of conductive material having a first connection portion (45A) and a second connection portion (46B, 55), the first connection portion (45A) being in the first via (43A) and in electrical contact with the die pad (39), and the second connection portion (46B, 55) extending along the side surface (57C) of the package device on the protective layer (40).

[0082] The carrier base (30) may be made of a conductive material and may have a boundary wall (34) for receiving cavity (32). The device includes a second via (43B) and a base connection terminal (49). The second via (43B) extends in the protective layer (40) at the boundary wall (34) of the carrier base (30). The base connection terminal (49) has a first base connection portion (45A) and a second base connection portion (46A, 46B, 54, 55). The first base connection portion (45A) extends in the second via and is in electrical contact with the carrier base. The second base connection portions (46A, 46B, 54, 55) are above the protective layer (40) and extend along the side (57C) of the package device (57).

[0083] The front (57A) and back (57B) of the packaged device (57) can be arranged at a certain distance along the height direction of the device, and the length of the second connection portion (54, 55) of the connection terminal (49) in the height direction can be less than the distance between the front (57A) and back (57B) of the packaged device.

[0084] The carrier base (30) has a height in the device height direction, and the length of the second connecting portion (54, 55) of the connecting terminal (49) in the device height direction is equal to half the height of the carrier base (30). The connecting terminal (49) may include a third connecting portion (46A, 54) that extends between the first connecting portion and the second connecting portion over the protective layer (40) along the front side (57A) of the packaged device (57).

[0085] The first connection portion (45A) of the connection terminal (49) may be made of a first material; the second connection portion (46B, 55) of the connection terminal may include a vertical portion (46B) and a side portion (55), the vertical portion (46B) being made of the first material and extending adjacent to the side (57C) of the package device (57), and the side portion (55) being made of a second material and extending above the vertical portion (46B) along the side of the package device; and the third connection portion (46A, 54) of the connection terminal may include a surface portion (46A) and a top portion (54), the surface portion (46A) being made of the first material and extending above the protective layer (40) between the first connection portion (45A) and the vertical portion (46B), and the top portion (54) being made of a second material and extending above the surface portion (46A).

[0086] A first insulating layer (47) may extend between and partially over the surface portions (46A), and the first insulating layer may have a first opening (48) in which the top portion (54) of the connecting terminal (49) extends.

[0087] An electronic device may be summarized as including: a package device (57); a plate (58) having a contact (60) facing a first connection portion (45A) of a connection terminal; a solder region (59) between the contact (60) and the front side (57A) of the device and in electrical contact with the connection terminal (49), the solder region (59) further extending along the side side (57C) of the package device and in contact with a second connection portion (46B), (55) of the connection terminal.

[0088] A method for manufacturing a packaged device can be summarized as including the following steps: forming a carrier base (30) having a plurality of receiving cavities (32) surrounded by boundary walls accommodating a separation cavity (33); bonding a plurality of dies (37) to the receiving cavities (32), the semiconductor dies having die pads (39); forming a protective layer (40) over the semiconductor dies and the carrier base, the protective layer extending around the semiconductor dies in the receiving cavities (32) and in the separation cavity (33); forming a first via (43A) in the protective layer (40) at the die pads (39); and forming a via (43A) in the separation cavity (33). Above 33), a groove (41) is formed in the protective layer (40); a connection terminal with conductive material is formed, the connection terminal having a first connection portion (45A) and a second connection portion (46B, 55), the first connection portion (45A) being in the first via (43A) and in electrical contact with the die (37), the second connection portion (46B, 55) being in the groove; and a carrier base and the protective layer (40) are cut at the groove (41) to separate a plurality of packaged devices (57), each packaged device having a side (57C), and the second connection portion (46B, 55) being exposed along the side of each packaged device.

[0089] Forming the connection terminal (49) may include: depositing a conductive layer (44) of a first conductive material on a protective layer to form a first connection portion (45A) in a first via, a vertical portion (46B) in a groove, a surface portion (46A) between the first connection portion (45A) and the vertical portion (46B), and a bottom portion (46C) on the bottom surface of the groove (41); forming a first insulating layer (47) between and partially above the surface portions (46A), the first insulating layer (47) having a first opening (48); and forming an external connection region of a second conductive material in the first opening (48), the external connection region including a top portion (54) on the surface portion (46A), a side portion (55) on the vertical portion (46B), and a bottom portion (56) on the bottom portion (46C).

[0090] Cutting the support base (30) and the protective layer (40) may include removing the bottom (46C) and bottom portion (56) of the conductive layer (44).

[0091] The support base (30) can have a height and the maximum depth of the groove (41) can be equal to half the height of the support base.

[0092] The carrier base (30) may be made of a conductive material, and the method may further include: forming a second via in the protective layer (40) at the boundary wall (34) of the carrier base; and forming a base connection terminal (49) of conductive material above the protective layer (40), within the second via (43B) and in the groove (41), wherein cutting the carrier base (30) and the protective layer (40) may include exposing the base connection terminal along the side (57C) of each package device (57).

[0093] Forming the groove (41) may include laser ablation, or blade / saw cutting or etching.

[0094] A method for manufacturing an electronic device may include bonding a packaged device (57) to a plate (58) having contacts (60), wherein bonding may include applying solder areas (59) between the contacts (60) and a first connection portion (45A) and on the side of the packaged device (57) in contact with a second connection portion (46B), (55) of a connection terminal (49).

[0095] The various embodiments described above can be combined to provide other embodiments. If it is necessary to employ concepts from various patents, applications, and publications to provide other embodiments, aspects of the embodiments can be modified.

[0096] [Note: Essential content cannot be merged by referencing foreign patents, foreign patent applications, or non-patent publications; however, the USPTO should allow the explicit addition of inappropriately merged subject matter to the specification through revisions without affecting the application date. The ability to merge by referencing ADSs has not been tested. We strongly recommend that you explicitly list the references you wish to merge in the appropriate place within the sentence.]

[0097] Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed as including all possible embodiments to which such claims are entitled, and the full scope of their equivalents. Therefore, the claims are not limited by this disclosure.

Claims

1. A packaged device, comprising: a front side, a back side opposite the front side, and a side extending between the front side and the back side; a carrier base; a containment cavity in the carrier base, wherein the containment cavity is surrounded by a delimiting wall of a separation cavity when the carrier base is formed; a semiconductor die in the containment cavity, the semiconductor die having a die pad; a protection layer covering the semiconductor die and the carrier base, wherein the protection layer extends in the containment cavity around the semiconductor die and in the separation cavity when the protection layer is formed; a first via in the protection layer at the die pad; and a connection terminal of conductive material, the connection terminal having a first connection portion in the first via and in electrical contact with the die pad, and a second connection portion extending on the protection layer along the side of the packaged device, wherein the second connection portion is in a recess in the protection layer above the separation cavity when the connection terminal of conductive material is formed.

2. The packaged device of claim 1, further comprising a second via extending in the protection layer at a delimiting wall of the carrier base, and a base connection terminal having a first base connection portion extending in the second via and in electrical contact with the carrier base, and a second base connection portion extending above the protection layer and along the side of the packaged device, and wherein the carrier base is made of conductive material and has the delimiting wall of the containment cavity.

3. The packaged device of claim 1, wherein the front side and the back side are arranged at a distance along a first direction, and a length of the second connection portion of the connection terminal in the first direction is less than the distance between the front side and the back side.

4. The packaged device of claim 3, wherein the carrier base has a height in the first direction, and the length of the second connection portion of the connection terminal in the first direction is equal to half of the height of the carrier base.

5. The packaged device of claim 1, wherein the connection terminal comprises a third connection portion extending above the protection layer along the front side between the first connection portion and the second connection portion.

6. The packaged device of claim 5, wherein: the first connection portion of the connection terminal is made of a first material; the second connection portion of the connection terminal comprises a vertical portion made of the first material, extending adjacent to the side, and a side portion made of a second material, extending above the vertical portion along the side; and and The third connection portion of the connection terminal comprises a surface portion and a top portion, the surface portion is made of the first material, extends between the first connection portion and the vertical portion over the protection layer, and the top portion is made of the second material, extends over the surface portion.

7. The packaged device of claim 6, wherein a first insulating layer extends between and partially over the surface portions, and the first insulating layer has an opening in which the top portion of the connection terminal extends.

8. An electronic device, comprising: a packaged device, comprising: a front side, a back side opposite the front side, and a side surface extending between the front side and the back side; a carrier base; a containment cavity in the carrier base, wherein the containment cavity is surrounded by a delimiting wall of a separation cavity when the carrier base is formed; a semiconductor die in the containment cavity, the semiconductor die having a die pad; a protection layer covering the semiconductor die and the carrier base, wherein the protection layer extends in the containment cavity around the semiconductor die and in the separation cavity when the protection layer is formed; a first via in the protection layer at the die pad; and a connection terminal of an electrically conductive material, the connection terminal having a first connection portion in the first via and in electrical contact with the die pad, and a second connection portion extending over the protection layer along the side surface of the packaged device, wherein the second connection portion is in a recess in the protection layer over the separation cavity when the connection terminal of the electrically conductive material is formed; a support having an electrically conductive contact area facing the first connection portion of the connection terminal; and an adhesive area between the electrically conductive contact area and the front side of the device and in electrical contact with the connection terminal, the adhesive area further extending along the side surface of the packaged device and in contact with the second connection portion of the connection terminal.

9. The electronic device of claim 8, further comprising a second via extending in the protection layer at a delimiting wall of the carrier base, and a base connection terminal having a first base connection portion extending in the second via and in electrical contact with the carrier base, and a second base connection portion extending over the protection layer and along the side surface of the packaged device, and wherein the carrier base is made of an electrically conductive material and has a delimiting wall of the containment cavity.

10. The electronic device of claim 8, wherein the front side and the back side are arranged at a distance along a first direction, and a length of the second connection portion of the connection terminal in the first direction is less than the distance between the front side and the back side.

11. The electronic device of claim 10, wherein the carrier base has a height in the first direction, and a length of the second connection portion of the connection terminal in the first direction is equal to half of the height of the carrier base.

12. The electronic device of claim 8, wherein the connection terminal includes a third connection portion that extends over the protective layer along the front face between the first connection portion and the second connection portion.

13. The electronic device of claim 12, wherein: the first connection portion of the connection terminal is made of a first material; the second connection portion of the connection terminal includes a vertical portion made of the first material, adjacent to the side face, and a side portion made of a second material, extending over the vertical portion along the side face; and the third connection portion of the connection terminal includes a surface portion made of the first material, extending over the protective layer between the first connection portion and the vertical portion, and a top portion made of the second material, extending over the surface portion.

14. A method for manufacturing packaged devices, comprising: forming a carrier base having a plurality of containment cavities surrounded by a delimiting wall of a separation cavity; bonding a plurality of semiconductor dies into the containment cavities, the semiconductor dies having die pads; forming a protective layer over the semiconductor dies and the carrier base, the protective layer extending in the containment cavities around the semiconductor dies and in the separation cavity; forming first vias in the protective layer at the die pads; forming a recess in the protective layer over the separation cavity; forming a connection terminal having a conductive material, the connection terminal having a first connection portion in the first vias and in electrical contact with the die pads, and a second connection portion in the recess; and cutting the carrier base and the protective layer at the recess, thereby separating a plurality of packaged devices, each packaged device having a side face and exposing the second connection portion along the side face of each packaged device.

15. The method of claim 14, wherein forming a connection terminal comprises: depositing a conductive layer of a first conductive material on the protective layer, thereby forming the first connection portion in the first vias, a vertical portion in the recess, a surface portion between the first connection portion and the vertical portion, and a bottom on a bottom surface of the recess; forming an insulating region between and partially over the surface portions, the insulating region having openings; and forming an outer connection region of a second conductive material in the openings, the outer connection region including a top portion on the surface portions, a side portion on the vertical portion, and a bottom portion on the bottom.

16. The method of claim 15, wherein cutting the carrier base and the protective layer comprises: removing the bottom of the conductive layer and the bottom portion.

17. The method of claim 15, wherein the carrier base has a height, and a maximum depth of the recess is equal to half of the height of the carrier base.

18. The method of claim 14, wherein the carrier base is made of an electrically conductive material, the method further comprising: forming a second via in the protective layer at the delimiting wall of the carrier base; and forming a base connection terminal of electrically conductive material over the protective layer, within the second via and in the recess, wherein cutting the carrier base and the protective layer comprises exposing the base connection terminal along the side face of each packaged device.

19. The method of claim 18, wherein forming the recess comprises: laser ablation, or blade / saw cutting or etching.

20. The method of claim 14, further comprising: bonding at least one of the packaged devices to a support having electrically conductive contact areas, wherein bonding comprises applying an adhesive area between the electrically conductive contact areas and the first connection portion and on a side face of the at least one of the packaged devices in contact with the second connection portion of the connection terminal.

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