Three-dimensional memory device

Abstract

A three-dimensional memory device includes a first substrate; a plurality of semiconductor devices formed at a first side of the first substrate; a plurality of shallow trench isolation (STI) structures in the first substrate, wherein at least one STI structure is formed between adjacent semiconductor devices of the plurality of semiconductor devices; a plurality of deep isolation structures formed on a second side of the first substrate opposite the first side, wherein at least one deep isolation structure of the plurality of deep isolation structures is in physical contact with the at least one STI structure and in physical contact with a portion of a well in which the plurality of semiconductor devices are embedded.

Description

[0001] This disclosure is a divisional application of patent application filed on October 17, 2019, with application number 201980002592.1 and invention title "Three-dimensional storage device with back isolation structure". Background Technology

[0002] Planar memory cells can be scaled down to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. Thus, the storage density of planar memory cells approaches its upper limit. Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. Summary of the Invention

[0003] Embodiments of three-dimensional (3D) storage devices and methods of forming thereof are described in this disclosure.

[0004] In some embodiments, a method includes forming a plurality of semiconductor devices, including at least first and second semiconductor devices, on a first side of a first substrate. The method includes forming a shallow trench isolation (STI) structure between the first and second semiconductor devices and forming a first interconnect layer on the plurality of semiconductor devices. The method also includes forming a memory array including a plurality of memory cells and a second interconnect layer on a second substrate. The method includes connecting the first and second interconnect layers; and forming an isolation trench through the first substrate to expose a portion of the STI structure. The isolation trench is formed through a second side of the first substrate opposite to the first side. The method includes disposing an isolation material in the isolation trench to form an isolation structure; and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.

[0005] In some embodiments, the first semiconductor device and the second semiconductor device respectively include a high-voltage n-type device and a high-voltage p-type device.

[0006] In some embodiments, after connecting the first interconnect layer and the second interconnect layer, the first substrate is thinned through the second side.

[0007] In some embodiments, thinning the first substrate includes exposing a deep well on a second side of the first substrate.

[0008] In some embodiments, the liner is placed in the isolation trench before the isolation material is applied.

[0009] In some embodiments, a dielectric layer is disposed on a second side of the first substrate.

[0010] In some embodiments, connecting the first interconnect layer and the second interconnect layer includes bonding the first interconnect layer and the second interconnect layer by direct bonding.

[0011] In some embodiments, an additional STI structure is formed adjacent to the first semiconductor device or the second semiconductor device, and another deep isolation trench is formed through the first substrate to expose the additional STI structure.

[0012] In some embodiments, the insulating material is placed in another deep insulating trench.

[0013] In some embodiments, trenches are formed in a first substrate and expose the contacts. Conductive material is disposed in the trenches and on the contacts to form through-silicon contacts (TSCs), wherein the TSCs are electrically coupled to the contacts.

[0014] In some embodiments, at least one contact pad is formed on the TSC and electrically coupled to the TSC.

[0015] In some embodiments, the insulating material includes deposited silicon oxide material.

[0016] In some embodiments, bonding the first interconnect layer and the second interconnect layer includes dielectric-to-dielectric bonding and metal-to-metal bonding at the bonding interface.

[0017] In some embodiments, a method for forming a three-dimensional memory device includes: forming peripheral circuitry including a plurality of semiconductor devices and a first interconnect layer on a first side of a first substrate. The method further includes forming a plurality of shallow trench isolation (STI) structures in the first substrate, wherein each of the plurality of STI structures is formed between adjacent semiconductor devices among the plurality of semiconductor devices. The method further includes forming a memory array including a plurality of memory cells and a second interconnect layer on a second substrate. The method further includes connecting the first interconnect layer and the second interconnect layer such that at least one semiconductor device among the plurality of semiconductors is electrically coupled to at least one memory cell among the plurality of memory cells. The method further includes thinning a first pad through a second side of the first substrate, wherein the second side is opposite to the first side. The method further includes forming a plurality of isolation trenches through the first substrate and exposing a portion of one of the plurality of STI structures, wherein the plurality of isolation trenches are formed through the second side of the first substrate. The method further includes disposing an isolation material in the plurality of isolation trenches and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.

[0018] In some embodiments, connecting the first interconnect layer and the second interconnect layer includes bonding the first interconnect layer and the second interconnect layer by direct bonding.

[0019] In some embodiments, a dielectric layer is disposed on a second side of a first substrate, wherein a plurality of isolation trenches extend through the dielectric layer.

[0020] In some embodiments, the liner is placed in the isolation trench before the isolation material is applied.

[0021] In some embodiments, providing an insulating material includes providing a silicon oxide material.

[0022] In some embodiments, the plurality of semiconductor devices include high-voltage n-type and p-type devices.

[0023] In some embodiments, trenches are formed in a first substrate and contacts are exposed. Conductive material is disposed in the trenches and on the contacts to form through-silicon contacts (TSCs), wherein the TSCs are electrically coupled to the contacts.

[0024] In some embodiments, the three-dimensional memory device includes a peripheral circuit wafer comprising a first substrate and a plurality of semiconductor devices and a first interconnect layer formed on a first side of the first substrate. The peripheral circuit wafer also includes a plurality of shallow trench isolation (STI) structures in the first substrate, wherein at least one STI structure is formed between adjacent semiconductor devices among the plurality of semiconductor devices. The peripheral circuit wafer also includes a plurality of deep isolation structures formed on a second side of the first substrate opposite to the first side, wherein at least one of the deep isolation structures is in physical contact with at least one STI structure. The three-dimensional memory device also includes a memory array wafer comprising a plurality of memory cells, wherein at least one of the plurality of semiconductor devices is electrically coupled to at least one of the plurality of memory cells. The memory array wafer also includes a second interconnect layer in physical contact with the first interconnect layer.

[0025] In some embodiments, at least one deep isolation structure includes a liner and an isolation material, wherein the liner is located between the isolation material and a first substrate.

[0026] In some embodiments, physical contact includes chemical bonds formed between the first and second interconnect layers.

[0027] In some embodiments, at least one deep isolation structure comprises silicon oxide.

[0028] In some embodiments, the plurality of semiconductor devices include high-voltage devices.

[0029] In some embodiments, the plurality of semiconductor devices include high-voltage n-type and p-type devices.

[0030] In some embodiments, the first substrate includes contacts electrically coupled to through-silicon contacts (TSCs).

[0031] In some embodiments, the three-dimensional storage device further includes contact pads that are in contact with and electrically coupled to the TSC. Attached Figure Description

[0032] Embodiments of this disclosure are illustrated in conjunction with the accompanying drawings, which are incorporated herein and form part of this specification, and together with the specification serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0033] Figure 1A A schematic top view of an exemplary three-dimensional (3D) memory die according to some embodiments of the present disclosure is shown.

[0034] Figure 1B A schematic top view of a region of a 3D memory die according to some embodiments of the present disclosure is shown.

[0035] Figure 2 A perspective view of a portion of an exemplary 3D storage array structure according to some embodiments of the present disclosure is shown.

[0036] Figure 3 A flowchart illustrating the formation of a 3D memory array with a deep isolation structure according to some embodiments of the present disclosure is shown.

[0037] Figure 4 A cross-sectional view of a peripheral circuit having high-voltage n-type and p-type devices according to some embodiments of the present disclosure is shown.

[0038] Figure 5 A cross-sectional view of a storage array according to some embodiments of the present disclosure is shown.

[0039] Figure 6 A cross-sectional view of a 3D memory device after bonding peripheral circuitry and a memory array, according to some embodiments of the present disclosure, is shown.

[0040] Figure 7-9 Cross-sectional views of 3D storage devices at various processing stages according to some embodiments of the present disclosure are shown.

[0041] Figures 10A-10B A top view of a 3D storage device according to some embodiments of the present disclosure is shown.

[0042] The features and advantages of the invention will become more apparent from the specific embodiments described below in conjunction with the accompanying drawings, in which similar reference numerals consistently identify corresponding elements. In the drawings, similar reference numerals generally denote identical, functionally similar, and / or structurally similar elements. The first appearance of an element in a figure is indicated by the leftmost numeral in the corresponding reference numeral.

[0043] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0044] Although specific configurations and settings have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and settings can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0045] It should be noted that the use of terms such as "an embodiment," "an embodiment," "an exemplary embodiment," and "some embodiments" in the specification indicates that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments (whether explicitly described or not) should be within the knowledge of those skilled in the art.

[0046] Generally, terms can be understood at least partially from their use in context. For example, depending at least partially on the context, the term "one or more" as used herein can be used to describe a feature, structure, or characteristic in a singular sense, or a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partially on the context, terms such as "a" or "described" can be understood to convey either a singular or a plural use. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but can, at least partially on the context, allow for the presence of other factors that do not necessarily have to be explicitly described.

[0047] It should be readily understood that the meanings of “on,” “above,” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only “directly on” something, but also includes something with an intervening feature or layer. Furthermore, “above” or “above” means not only “on” or “above” something, but also includes something “above” or “above” without an intervening feature or layer (i.e., directly on something).

[0048] Furthermore, spatially related terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for convenience to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the accompanying drawings. Spatially related terms are intended to cover different orientations in the use or handling of the device besides those depicted in the drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptive terms used herein may be interpreted similarly accordingly.

[0049] As used herein, the term "substrate" refers to the material on which subsequent material is added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite the top surface, and therefore the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0050] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, while the top side is relatively far from the substrate. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along an inclined surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnect lines, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0051] In this disclosure, for ease of description, the term "level" is used to refer to elements having substantially the same height along the vertical direction. For example, a word line and the underlying gate dielectric layer may be referred to as a "level", a word line and the underlying insulating layer may be referred to together as a "level", word lines having substantially the same height may be referred to as a "level of word lines" or similar, and so on.

[0052] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter for a component or processing step, set during the design phase of production or process, and the range of values ​​higher and / or lower than the expected value. The range of values ​​may be due to slight variations in the manufacturing process or tolerances. As used herein, the term "about" indicates a value of a given quantity that can vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" can indicate a value of a given quantity that varies, for example, within 10%–30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0053] In this disclosure, the terms “horizontal / horizontally / laterally” refer to a lateral surface that is nominally parallel to the substrate, and the terms “vertical” or “perpendicularly” refer to a lateral surface that is nominally perpendicular to the substrate.

[0054] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in a vertical direction relative to the substrate.

[0055] High-voltage devices, such as high-voltage n-type or p-type devices, are implemented in 3D memory cells to facilitate cell operation. In 3D memory circuits, high-voltage n-type and p-type devices can be placed adjacent to each other and connected to high voltages (e.g., approximately 15V-25V) during operation. Therefore, sufficient isolation is required between the high-voltage n-type and p-type devices to prevent crosstalk between adjacent high-voltage devices. The development of 3D memories (e.g., 3D NAND flash memory) is moving towards high-density and high-capacity memory cells, with an increasing number of devices and metal wiring. As the spacing between devices continues to shrink, high-quality isolation structures become increasingly important for preventing crosstalk between adjacent devices.

[0056] Various embodiments of this disclosure provide structures and methods for fabricating isolation structures that improve isolation between high-voltage devices in 3D memory structures. A peripheral device wafer containing CMOS devices can be bonded to an array wafer containing a 3D memory array. Isolation structures can be implemented in the bonded peripheral / memory array wafers to prevent crosstalk between adjacent structures, such as between wells of different doping types used for high-voltage devices (e.g., high-voltage n-type devices and high-voltage p-type devices). The isolation structures can be formed by thinning the dielectric layer of the peripheral wafer and forming a through-silicon isolation (TSI) structure to effectively separate different functional regions. By using isolation structures, rather than relying on larger spacing between devices or increasing the doping level of those functional regions, the overall storage density and manufacturing cost of 3D NAND flash memory can be improved.

[0057] Figure 1A A top view of an exemplary three-dimensional (3D) storage device 100 according to some embodiments of the present disclosure is shown. The 3D storage device 100 may be any portion of a memory chip (package), memory die, or memory die, and may include one or more storage planes 101, each storage plane including a plurality of storage blocks 103. The same and simultaneous operations may occur on each storage plane 101. Storage blocks 103, which may be megabytes (MB) in size, may be the minimum size for performing an erase operation. Figure 1AAs shown, an exemplary 3D storage device 100 includes four storage planes 101, and each storage plane 101 includes six storage blocks 103. Each storage block 103 may include multiple storage cells, wherein each storage cell can be addressed via interconnects such as bit lines and word lines. The bit lines and word lines may be arranged vertically (e.g., in rows and columns, respectively) to form an array of metal lines. Figure 1A In this disclosure, the directions of the bit lines and word lines are marked as "BL" and "WL". The memory block 103 is also referred to as a "memory array" or "array". A memory array is the core area in a storage device that performs storage functions.

[0058] The 3D memory device 100 also includes a peripheral region 105, which surrounds the memory plane 101. The peripheral region 105 may contain a variety of digital, analog, and / or mixed-signal circuitry to support the functionality of the memory array, such as page buffers, row and column decoders, and sense amplifiers. The peripheral circuitry uses active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as will be apparent to those skilled in the art.

[0059] Figure 1A The arrangement of storage planes 101 in the 3D storage device 100 shown and the arrangement of storage blocks 103 in each storage plane 101 are provided as examples only and do not limit the scope of this disclosure.

[0060] Reference Figure 1B Some embodiments according to this disclosure are shown. Figure 1A An enlarged top view of region 108 in the 3D storage device 100. Region 108 may include a stepped region 210 and a channel structure region 211. Channel structure region 211 may include an array of memory strings 212, each memory string including a plurality of stacked memory cells. Stepped region 210 may include a stepped structure and an array of contact structures 214 formed on the stepped structure. In some embodiments, a plurality of slot structures 216 extending across channel structure region 211 and stepped region 210 in the WL direction may divide the memory block into a plurality of finger memory regions 218. At least some of the slot structures 216 may serve as common source contacts for the array of memory strings 212 in channel structure region 211. Top select gate cutout 220 may be provided in the middle of each finger memory region 218 to divide the top select gate (TSG) of finger memory region 218 into two parts, thereby dividing the finger memory region into two programmable (read / write) pages. While erase operations on 3D NAND memory can be performed at the block level, read and write operations can be performed at the page level. The page size can be kilobytes (KB). In some embodiments, region 108 also includes virtual memory strings for controlling process variations during manufacturing and / or for additional mechanical support.

[0061] Figure 2 A perspective view of a portion of an exemplary three-dimensional (3D) memory array structure 200 according to some embodiments of the present disclosure is shown. The memory array structure 200 includes a substrate 330, an insulating film 331 over the substrate 330, a lower select gate (LSG) 332 over the insulating film 331, and a multilayer control gate 333 (also referred to as a “word line (WL)”), and a film stack layer 335 stacked on top of the LSG 332 to form alternating conductive and dielectric layers. For clarity, in Figure 2 The dielectric layer adjacent to the control gate layer is not shown.

[0062] Each layer of the control gate is separated by slot structures 216-1 and 216-2 passing through the film stack 335. The memory array structure 200 also includes a top select gate (TSG) 334 above the stack of control gates 333. The stack of TSG 334, control gate 333, and LSG 332 is also referred to as the “gate electrode”. The memory array structure 300 also includes memory strings 212 and doped source line regions 344 in portions of the substrate 330 between adjacent LSGs 332. Each memory string 212 includes a channel via 336 extending through an insulating film 331 and alternating conductive and dielectric layers and the film stack 335. The memory string 212 may also include a memory film 337 on the sidewall of the channel via 336, a channel layer 338 above the memory film 337, and a core-filling film 339 surrounded by the channel layer 338. Memory cells 340 may be formed at the intersection of the control gate 333 and the memory string 212. The memory array structure 300 also includes multiple bit lines (BLs) 341 connected to the memory string 212 above the TSG 334. The memory array structure 300 also includes multiple metal interconnects 343 connected to the gate electrode via multiple contact structures 214. The edges of the film stack 335 are configured in a stepped shape to allow electrical connection to each layer of the gate electrode.

[0063] exist Figure 2 For illustrative purposes, three layers of control gates 333-1, 333-2, and 333-3, along with one layer of TSG 334 and one layer of LSG 332, are shown together. In this example, each memory string 212 may include three memory cells 340-1, 340-2, and 340-3, which correspond to control gates 333-1, 333-2, and 333-3, respectively. In some embodiments, the number of control gates and the number of memory cells may be greater than three to increase storage capacity. The memory array structure 200 may also include other structures, such as TSG cutouts, common-source contacts, and virtual channel structures. For simplicity, these structures are not shown. Figure 2 As shown in the image.

[0064] To achieve higher storage density, the number of vertically stacked WL layers or the number of memory cells per memory string in 3D memories has been significantly increased, for example, from 24 stacked WL layers (i.e., 24L) to 128 layers or more. To further reduce the size of 3D memories, the memory array can be stacked on top of the peripheral circuitry, and vice versa. For example, the peripheral circuitry can be fabricated on a first substrate, and the memory array can be fabricated on a second substrate. The memory array and the peripheral circuitry can then be electrically coupled (e.g., electrically connected or physically contacted) through various interconnects that bond the first and second substrates together. This not only increases the 3D storage density but also enables higher bandwidth and lower power consumption in communication between the peripheral circuitry and the memory array, as interconnect lengths can be shortened through substrate (wafer) bonding.

[0065] As the density and performance of 3D memory devices increase, improvements in peripheral circuitry are also needed to provide functional support for the memory array, such as reading, writing, and erasing data from memory cells. Isolation structures can be implemented within the bonded peripheral / memory array wafer to prevent crosstalk between adjacent structures, such as wells with different doping types. These isolation structures can be formed by thinning the dielectric layer of the peripheral wafer and forming a through-silicon isolation (TSI) structure to effectively separate different functional regions.

[0066] Figure 3 This is a flowchart of an exemplary method 300 for forming an isolation structure in a 3D memory device according to some embodiments of the present disclosure. The 3D memory device can be formed by connecting a peripheral circuitry wafer to a memory array wafer via wafer bonding and forming a deep isolation structure in the peripheral circuitry wafer to prevent crosstalk. The operation of method 300 may be performed in a different order and / or changed, and method 300 may include further operations not described for simplicity. Figure 3-9 This is a cross-sectional view of an exemplary semiconductor structure 300 incorporated into an isolation structure. Provided Figure 3-9 As an exemplary cross-sectional view, this is provided to illustrate method 300. Although the manufacturing process for forming an isolation structure in a dielectric layer is described herein as an example, this manufacturing process can be applied to a variety of other layers, such as interlayer dielectrics, insulating layers, conductive layers, and any other suitable layers. The manufacturing process provided herein is exemplary, and alternative processes not shown in these figures according to this disclosure can be performed.

[0067] In operation 302, according to some embodiments of this disclosure, a peripheral circuit wafer for a 3D memory device is formed. (See also...) Figure 4The peripheral circuitry 400 may include various components of the 3D memory device, such as a first substrate 430, multiple peripheral devices such as high-voltage devices 450A and 450B, a shallow trench isolation (STI) 452, a first well 451, a second well 454, a third well 457, a gate stack layer 456, a gate spacer 458, and a peripheral interconnect layer 462. In some embodiments, the high-voltage devices 450A and 450B may be high-voltage p-type and n-type devices, respectively. In some embodiments, the first well 451 and the second well 454 may be n-type wells doped with n-type dopant. In some embodiments, the third well 457 may be a p-type well doped with p-type dopant.

[0068] The first substrate 430 may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride, silicon carbide, glass, III-V compounds, any other suitable material, or any combination thereof. In some embodiments, the first substrate 430 may be double-sided polished prior to the fabrication of peripheral devices. In this example, the first substrate 430 includes surfaces on a top side and a bottom side (also referred to as first side 430-1 and second side 430-2, or front side and back side, respectively), both of which are polished and processed to provide smooth surfaces for use in high-quality semiconductor devices. The first side and the second side are opposite sides of the first substrate 430.

[0069] The peripheral circuit 400 may include one or more peripheral devices 450A and 450B on the first substrate 430. Peripheral devices 450A and 450B are adjacent to each other and may be formed on the first substrate 430, wherein all or part of peripheral devices 450A and 450B are formed in the first substrate 430 (e.g., below the top surface of the first substrate 430) and / or directly on the first substrate 430. Peripheral devices 450A and 450B may include any suitable semiconductor device; for example, peripheral device 450A may be a high-voltage p-type device such as a high-voltage PFET. Peripheral device 450B may be a high-voltage n-type device such as a high-voltage NFET. Peripheral devices 450A and 450B may also be metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), diodes, resistors, capacitors, inductors, etc. Among semiconductor devices, p-type and / or n-type MOSFETs (i.e., CMOS) are widely implemented in logic circuit designs and are used as examples of peripheral devices 450A and 450B in this disclosure. Therefore, the peripheral circuit 400 can also be referred to as CMOS wafer 400. Peripheral devices 450A and 450B can be p-channel MOSFETs or n-channel MOSFETs, and can include, but are not limited to, an active device region surrounded by a shallow trench isolation (STI) 452 and a gate stack layer 456 including a gate dielectric, gate conductor, and / or gate hard mask. The first, second, and third wells 451, 454, and 457 can be any suitable wells for peripheral devices 450A and 450B. Peripheral devices 450A and 450B may also include source / drain extensions and / or halo regions. Figure 4 (Not shown in the diagram) Gate spacer 458 and source / drain 460 are located on each side of the gate stack layer. Peripheral devices 450A and 450B may further include silicide contact regions (not shown) on top of the source / drain. Other suitable devices may also be formed on the first substrate 430.

[0070] The STI 452 can be formed by patterning a substrate using photolithography and etching, filling it with an insulating material, and polishing the insulating material to form a coplanar surface on the first substrate 430. The insulating material used for the STI may include silicon oxide, silicon oxynitride, TEOS, low-temperature oxide (LTO), high-temperature oxide (HTO), silicon nitride, etc. The insulating material used for the STI 452 can be set using techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), low-pressure chemical vapor deposition (LPCVD), high-density plasma (HDP) chemical vapor deposition, rapid thermal chemical vapor deposition (RTCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), sputtering, thermal oxidation or nitriding, or combinations thereof. The formation of the STI 452 may also include a high-temperature annealing step to densify the set insulating material to improve electrical isolation.

[0071] The first, second, and third wells 451, 454, and 457 of peripheral devices 450A and 450B may include p-type doping for an n-channel MOSFET or n-type doping for a p-channel MOSFET. For example, peripheral device 450A may be a high-voltage p-type device such as an HVPFET, and the first well 451 may be a high-voltage n-type well. In some embodiments, peripheral device 450B may be a high-voltage n-type device such as an HVNFET, and the second and third wells may be doped with n-type and p-type dopants, respectively. The dopant distribution and concentration of the first, second, and third wells 451, 454, and 470 may affect the device characteristics of peripheral devices 450A or 450B. For MOSFET devices with a low threshold voltage (Vt), one or more suitable wells may be doped at a lower concentration, and a low-voltage p-well or a low-voltage n-well may be formed. For MOSFETs with a high Vt, one or more suitable wells may be doped at a higher concentration, and a high-voltage p-well or a high-voltage n-well may be formed. In some embodiments, to provide electrical isolation from the p-type substrate, a deep n-well can be formed beneath the high-voltage p-well of the n-channel MOSFET having a high Vt. Peripheral devices 450A and 450B can be devices that operate under any suitable conditions. For example, peripheral device 450A can be a low-voltage device, while peripheral device 450B can be a high-voltage device, and a suitable well can be an n-type well embedded in a substrate 430, which can be a p-type substrate. In some embodiments, other wells and structures may be included.

[0072] The formation of n-wells can include any suitable n-type dopant, such as phosphorus, arsenic, antimony, etc., and / or any combination thereof. The formation of p-wells can include any suitable p-type dopant, such as boron. Dopant incorporation can be achieved by ion implantation followed by activation annealing, or by in-situ doping of the active device region during epitaxy.

[0073] The gate stack 456 of peripheral devices 450A and 450B can be formed using a "gate-first" approach, in which the gate stack 456 is set and patterned before the source / drain is formed. Alternatively, the gate stack 456 of peripheral devices 450A and 450B can be formed using a "replacement" approach, in which a sacrificial gate stack can be formed first, and then replaced with a high-k dielectric layer and gate conductor after the source / drain is formed.

[0074] In some embodiments, the gate dielectric may be made of silicon oxide, silicon nitride, silicon oxynitride, and / or a high-k dielectric film, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, magnesium oxide, or lanthanum oxide, and / or combinations thereof. The gate dielectric can be formed by any suitable method, such as CVD, PVD, PECVD, LPCVD, RTCVD, sputtering, MOCVD, ALD, thermal oxidation, or nitriding, or combinations thereof.

[0075] In some embodiments, the gate conductor may be made of a metal or metal alloy, such as tungsten, cobalt, nickel, copper, or aluminum and / or combinations thereof. In some embodiments, the gate conductor may also comprise a conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), etc. The gate conductor may be formed by any suitable deposition method, such as sputtering, thermal evaporation, electron beam evaporation, ALD, PVD, and / or combinations thereof.

[0076] In some embodiments, the gate conductor may further comprise a polycrystalline semiconductor, such as polycrystalline silicon, polycrystalline germanium, polycrystalline germanium-silicon, and any other suitable material, and / or combinations thereof. In some embodiments, the polycrystalline material may be combined with any suitable type of dopant (such as boron, phosphorus, or arsenic). In some embodiments, the gate conductor may also be an amorphous semiconductor having the aforementioned materials.

[0077] In some embodiments, the gate conductor may be made of a metal silicide, including WSix, CoSix, NiSix, or AlSix. The formation of the metal silicide material may include forming a metal layer and a polycrystalline semiconductor using techniques similar to those described above. The formation of the metal silicide may further include applying a thermal annealing process to the deposited metal layer and polycrystalline semiconductor layer, followed by removal of unreacted metal.

[0078] The gate spacer 458 can be formed by setting an insulating material and then performing anisotropic etching. The insulating material of the gate spacer 458 can be any insulator, including silicon oxide, silicon nitride, silicon oxynitride, TEOS, LTO, HTO, etc. Techniques such as CVD, PVD, PECVD, LPCVD, RTCVD, MOCVD, ALD, sputtering, or combinations thereof can be used to set the gate spacer 458. Anisotropic etching of the gate spacer 458 includes dry etching, such as reactive ion etching (RIE).

[0079] The length of the gate stack 456 between the source / drain 460 is a crucial characteristic of the MOSFET. The gate length L determines the magnitude of the MOSFET's drive current and thus significantly reduces the required current for logic circuitry. The gate length can be less than about 100 nm. In some embodiments, the gate length can range from about 5 nm to about 30 nm. Patterning a gate stack with such a small size is highly challenging and can be achieved using techniques including optical proximity correction, double exposure and / or double etching, self-aligned double patterning, etc.

[0080] In some embodiments, the source / drain 460 of peripheral devices 450A and 450B is bonded with a high concentration of dopant. For n-type MOSFETs, the dopant used for the source / drain 460 can include any suitable n-type dopant, such as phosphorus, arsenic, antimony, etc., and / or any combination thereof. For p-type MOSFETs, the dopant used for the source / drain 460 can include any suitable p-type dopant, such as boron. Dopant incorporation can be achieved by ion implantation followed by dopant activation annealing. The source / drain 460 can be made of the same material as the first substrate 430, such as silicon. In some embodiments, the source / drain 460 of peripheral devices 450A and 450B can be made of a different material than the first substrate 430 to achieve high performance. For example, on a silicon substrate, the source / drain 460 for a p-type MOSFET can include SiGe, and the source / drain 460 for an n-type MOSFET can be bonded with carbon. Forming the source / drain 460 with different materials may include etching back the substrate material in the source / drain regions and using techniques such as epitaxy to set new source / drain materials. Doping of the source / drain 460 may also be achieved through in-situ doping between epitaxial layers.

[0081] Peripheral devices 450A and 450B may also have optional source / drain extensions and / or halo regions along each side of the gate stack 456. Figure 2(Not shown in the diagram). The source / drain extension and / or halo region is located within the active device region below the gate stack and is primarily implemented for improved short-channel control of peripheral devices 450A and 450B with channel lengths less than about 0.5 μm. The formation of the source / drain extension and / or halo region can be similar to the formation of the source / drain 460, but different implantation conditions (e.g., dose, angle, energy, type, etc.) can be used to obtain optimized doping profile, depth, or concentration.

[0082] Peripheral devices 450A and 450B can be formed in a region with planar active devices (e.g., Figure 4 The MOSFET channel and current flow direction are parallel to the surface of the first substrate 430 (as shown). In some embodiments, peripheral devices 450A and 450B may also be formed on the first substrate 430 having a 3D active device region, for example in the form of a so-called "FINFET" (not shown) in the shape of a "fin", wherein the gate stack of the MOSFET surrounds the fin, and the MOSFET channel runs along three sides of the fin (the top and two sidewalls below the gate).

[0083] In some embodiments, the peripheral circuitry 400 may include a peripheral interconnect layer 462 (or a first interconnect layer) over the peripheral devices 450A and 450B to provide electrical connections between the various peripheral devices 450A and 450B and external devices (e.g., power supplies, another chip, I / O devices, etc.). The peripheral interconnect layer 462 may include one or more interconnect structures, such as one or more vertical contact structures 464 and one or more lateral conductors 466. The contact structures 464 and conductors 466 may broadly include any suitable type of interconnect, such as midline (MOL) interconnects and back-end line (BEOL) interconnects. The contact structures 464 and conductors 466 in the peripheral circuitry 400 may include any suitable conductive material, such as tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel, silicides (WSix, CoSix, NiSix, AlSix, etc.), metal alloys, or any combination thereof. Conductive materials can be deposited using one or more thin film deposition processes, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering, evaporation, or any combination thereof.

[0084] The peripheral interconnect layer 462 may further include an insulating layer 468. The insulating layer 468 in the peripheral interconnect layer 462 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide (such as F-, C-, N-, or H-doped oxides), tetraethoxysilane (TEOS), polyimide, spin-coated glass (SOG), low-k dielectric material (e.g., porous SiCOH), silsesquioxane (SSQ), or any combination thereof. The insulating material may be deposited using one or more thin-film deposition processes, such as CVD, PVD, PECVD, ALD, high-density plasma CVD (HDP-CVD), sputtering, spin coating, or any combination thereof.

[0085] exist Figure 4 The example uses two conductive layers 470-1 and 470-2 (also referred to as "metal layers"), each of which may include a contact structure 464 and a wire 466, wherein the wires 466 of the same metal layer are located at the same distance from the first substrate 430. The number of metal layers 470 used for the peripheral circuitry 400 is not limited and can be any number optimized for the performance of the 3D memory.

[0086] The peripheral interconnect layer 462 can be formed by stacking metal layers 470 from bottom to top of the peripheral circuit 400. Figure 4 In the example of the peripheral circuit 400, a bottom metal layer 470-1 can be formed first, and then an upper metal layer 470-2 can be formed on top of the bottom metal layer 470-1. The manufacturing process of each metal layer 470 may include, but is not limited to, setting a portion of the insulating layer 468 to the required thickness of the metal layer, patterning a portion of the insulating layer 468 using photolithography and dry / wet etching to form contact holes for contact structures 464 and wires 466, setting conductive material to fill the contact holes for contact structures 464 and wires 466, and removing excess conductive material outside the contact holes by using a planarization process such as chemical mechanical polishing (CMP) or reactive ion etching (RIE).

[0087] In some embodiments, the peripheral circuitry 400 further includes one or more substrate contacts 472, wherein the substrate contacts 472 provide electrical connections to the first substrate 430. The substrate contacts 472 may include one or more conductive layers 470 having multilayer vertical contact structures 464 and lateral conductors 466. Figure 4As an example, a substrate contact 472 with a single contact structure and wires is shown, wherein the vertical contact structure of the substrate contact 472 extends through the insulating layer 468 and makes electrical contact with the first substrate 430. In some embodiments, the peripheral circuit 400 may further include a contact 471 to provide electrical connection to a suitable device embedded in the insulating layer 468. The contact 471 may be electrically coupled to a lateral wire 466.

[0088] In some embodiments, the topmost wire 466 (e.g., Figure 4 466-2 in the circuit can be exposed as the top surface of the peripheral circuit 400, wherein the topmost wire 466-2 can be directly connected to wires on another chip or external device.

[0089] In some embodiments, the topmost wire 466-2 may be embedded within the insulating layer 468 (e.g., Figure 4 As shown), the insulating material on top of conductor 466 provides scratch protection during transport or handling. An electrical connection to the topmost conductor 466 can later be established by forming a metal through-hole or simply by etching back the insulating layer 468 using a dry / wet etching process.

[0090] However, peripheral devices 450A and 450B are not limited to MOSFETs. The structures of other devices, such as diodes, resistors, capacitors, inductors, BJTs, etc., can be formed simultaneously during MOSFET fabrication using different mask designs and layouts. To form devices other than MOSFETs, process steps can be added or modified in the MOSFET process flow, for example, processes to obtain different dopant distributions, film thicknesses, or material stacking layers. In some embodiments, peripheral devices 450A and 450B, other than MOSFETs, can also be fabricated using additional designs and / or photolithographic mask levels to achieve specific circuit requirements.

[0091] In some embodiments, the plurality of peripheral devices 450A and 450B can be used to form any digital, analog, and / or mixed-signal circuitry for the operation of peripheral circuitry 400. Peripheral circuitry 400 can perform, for example, row / column decoding of a memory array, timing and control, reading, writing, and erasing data.

[0092] In some embodiments, a deep well 455 may be formed in the first substrate 430 simultaneously with the formation of a well for a MOSFET. The deep well 455 may be p-type doped or n-type doped. The n-type dopant may be phosphorus, arsenic, antimony, etc. The p-type dopant may be, for example, boron. Dopant bonding can be achieved by ion implantation of the first substrate 430 followed by activation annealing. In some embodiments, the deep well 455 may be formed on the first substrate 430 by epitaxy and in-situ doping. The implantation of the deep well 455 may be performed immediately before or after the implantation of other suitable wells. The dopant activation annealing of the deep well 455 may be performed simultaneously with other suitable wells. In some embodiments, a deep well contact 473 may be formed to provide electrical connection to the deep well 455. In some embodiments, the deep well contact 473 forms an ohmic contact with the deep well 455. The deep well contact 473 may form an electrical connection with a corresponding circuit of the peripheral circuitry 400 via contact structures 464 and wires 466 in the peripheral interconnect layer 462. For example, the deep well contact 473 can be connected to ground, the substrate contact 472 of the first substrate 430, the source or drain 460 of the peripheral devices 450A and 450B, or the gate stack layer 456.

[0093] In operation 304, according to some embodiments of this disclosure, a 3D storage array is formed. (Refer to...) Figure 5 The 3D memory array 500 may be a 3D NAND memory array and may include a second substrate 530, memory cells 540, and an array interconnect layer 562 (or a second interconnect layer). The second substrate 530 may be similar to the first substrate 430. The memory cells 540 may be similar to those described above. Figure 2 The described memory cells are 340-1, 340-2, or 340-3. The array interconnect layer 562 can be similar to the peripheral interconnect layer 462 and can be formed using similar materials and processes. For example, the interconnect structures (e.g., contact structures 564 and wires 566) and insulating layer 568 of the array interconnect layer 562 are similar to the interconnect structures (e.g., contact structures 464, wires 466) and insulating layer 468 of the peripheral interconnect layer 462, respectively.

[0094] In some embodiments, the 3D storage array 500 may be a storage array for 3D NAND flash memory, wherein storage cells 540 may be stacked vertically as storage strings 212. Storage strings 212 extend through multiple pairs of conductor layers 574 and dielectric layers 576. The multiple conductor / dielectric layer pairs are also referred to herein as “alternating conductor / dielectric stacks” 578. The conductor layers 574 and dielectric layers 576 in the alternating conductor / dielectric stacks 578 alternate in the vertical direction. In other words, except for those at the top or bottom of the alternating conductor / dielectric stacks 578, each conductor layer 574 may be sandwiched between two dielectric layers 576 on both sides, and each dielectric layer 576 may be sandwiched between two conductor layers 574 on both sides. Each conductor layer 574 may have the same thickness or different thicknesses. Similarly, each dielectric layer 576 may have the same thickness or different thicknesses. In some embodiments, the alternating conductor / dielectric stack 578 includes more conductor layers or more dielectric layers with different materials and / or thicknesses than the conductor / dielectric layer pairs. Conductor layer 574 may include conductor materials such as tungsten, cobalt, copper, aluminum, titanium, tantalum, titanium nitride, tantalum nitride, nickel, doped silicon, silicides (e.g., NiSix, WSix, CoSix, TiSix), or any combination thereof. Dielectric layer 576 may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0095] like Figure 5 As shown, each memory string 212 may include a channel layer 338 and a memory film 337. In some embodiments, the channel layer 338 includes silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In some embodiments, the memory film 337 is a composite layer including a tunneling layer, a memory layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. Each memory string 212 may have a cylindrical shape (e.g., a column). According to some embodiments, the channel layer 338, the tunneling layer, the memory layer, and the barrier layer are arranged sequentially along a direction from the center of the column toward the outer surface. The tunneling layer may include silicon oxide, silicon nitride, or any combination thereof. The barrier layer may include silicon oxide, silicon nitride, a high dielectric constant (high k) dielectric, or any combination thereof. The memory layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the memory film 337 includes an ONO dielectric (e.g., a tunneling layer including silicon oxide, a memory layer including silicon nitride, and a barrier layer including silicon oxide).

[0096] In some embodiments, each conductor layer 574 in the alternating conductor / dielectric stack 578 can be used as a control gate for each memory cell of the storage string 212 (e.g., Figure 3 (Control gate 333 in the middle). For example Figure 5As shown, memory string 212 may include a lower select gate 332 (e.g., a source select gate) at the lower end of memory string 212. Memory string 212 may also include a top select gate 334 (e.g., a drain select gate) at the upper end of memory string 212. As used herein, the “upper end” of a component (e.g., memory string 212) is the end that is away from the second substrate 530 in the z-direction, and the “lower end” of a component (e.g., memory string 212) is the end that is closer to the second substrate 530 in the z-direction. Figure 5 As shown, for each memory string 212, the drain select gate 334 may be located above the source select gate 332. In some embodiments, the select gates 332 / 334 comprise a conductor material, such as tungsten, cobalt, copper, aluminum, doped silicon, silicide, or any combination thereof.

[0097] In some embodiments, the 3D memory array 500 includes an epitaxial layer 580 on the lower end of the channel layer 338 of the memory string 212. The epitaxial layer 580 may include a semiconductor material such as silicon. The epitaxial layer 580 may be epitaxially grown from a semiconductor layer 582 on a second substrate 530. The semiconductor layer 582 may be undoped, partially doped (in the thickness and / or width direction), or fully doped with p-type or n-type dopants. For each memory string 212, the epitaxial layer 580 is referred to herein as an “epitaph”. The epitaxial plug 580 at the lower end of each memory string 212 may contact the channel layer 338 of the semiconductor layer 582 and the doped region. The epitaxial plug 580 may serve as a channel for the lower select gate 332 at the lower end of the memory string 212.

[0098] In some embodiments, the array device further includes a plurality of contact structures 214 (also referred to as word line contacts) for word lines in the stepped region 210. Each word line contact structure 214 may form an electrical contact with a corresponding conductor layer 574 in alternating conductor / dielectric stacks 578 to control memory cells 340 respectively. The word line contact structures 214 may be formed by dry / wet etching contact holes and then filling them with conductors (e.g., tungsten, titanium, titanium nitride, copper, tantalum nitride, aluminum, cobalt, nickel, or any combination thereof).

[0099] like Figure 5 As shown, the 3D memory array 500 also includes bit line contacts 584 formed on top of the memory string 212 to provide individual access to the channel layer 338 of the memory string 212. Wires connected to the word line contact structure 214 and the bit line contacts 584 form the word lines and bit lines of the 3D memory array 500, respectively. Typically, the word lines and bit lines are placed perpendicular to each other (e.g., in rows and columns, respectively), thus forming an "array" of memory.

[0100] In some embodiments, the 3D memory array 500 further includes substrate contacts 572 of a second substrate 530. The substrate contacts 572 can be formed using similar materials and processes to those used for the substrate contacts 472 of the first substrate 430. The substrate contacts 572 can provide electrical connections to the second substrate 530 of the 3D memory array 500.

[0101] In operation 306, according to some embodiments of this disclosure, the peripheral circuit wafer and the 3D memory array wafer are connected. (Refer to...) Figure 6 A 3D memory device 600 is formed by wafer bonding of peripheral circuitry 400 fabricated on a first substrate 430 and a 3D memory array 500 fabricated on a second substrate 530. For example... Figure 6 As shown, the peripheral circuitry 400 is flipped upside down and bonded to the 3D memory array 500 via a suitable wafer bonding process (e.g., direct bonding or hybrid bonding). In some embodiments, other methods for connecting the peripheral circuitry wafer and the 3D memory array wafer may be used. At the bonding interface 688, the peripheral circuitry 400 and the 3D memory array 500 are electrically connected via multiple interconnect VIAs 486 / 586.

[0102] In some embodiments, the bonding interface 688 of the 3D memory device 600 is located between the insulating layer 468 of the peripheral interconnect layer 462 and the insulating layer 568 of the array interconnect layer 562. Interconnects 486 and 586 may be joined at the bonding interface 688 to electrically connect any wires 466 or contact structures 464 of the peripheral interconnect layer 462 and any wires 566 or contact structures 564 of the array interconnect layer 562. In this way, the peripheral circuitry 400 and the 3D memory array 500 can be electrically connected.

[0103] In some embodiments, the bonding interface 688 of the 3D storage device 600 is located inside the bonding layer 690. In this example, interconnects VIAs 486 and 586 extend through the bonding layer 690 and also form electrical connections between any wires 466 or contact structures 464 of the peripheral interconnect layer 462 and the wires 566 or contact structures 564 of the array interconnect layer 562. Thus, the peripheral circuitry 400 and the 3D storage array 500 can also be electrically connected.

[0104] In some embodiments, the bonding layer 690 may be disposed on the peripheral circuit 400 prior to the bonding process. Figure 4 (in) and / or 3D storage array 500 (in Figure 5The bonding layer 690 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The bonding layer 690 may also include an adhesive material, such as epoxy resin, polyimide, dry film, photopolymer, etc. The bonding layer 690 may be formed by one or more thin film deposition processes, such as CVD, PVD, PECVD, ALD, high-density plasma CVD (HDP-CVD), sputtering, spin coating, or any combination thereof.

[0105] In some embodiments, after forming the bonding layer 690, interconnects VIAs 486 and 586 can be formed for the peripheral circuitry 400 and the 3D memory array 500, respectively. The interconnects VIAs 486 / 586 can comprise metals or metal alloys, such as copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), and any combination thereof. The metal or metal alloy of the interconnects VIAs 486 / 586 can be deposited using one or more thin-film deposition processes, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering, evaporation, or any combination thereof. The fabrication process of the interconnects VIAs 486 / 586 can further include, but is not limited to, photolithography, wet / dry etching, planarization (e.g., CMP or RIE etch-back), etc.

[0106] In some embodiments, depending on the product design and manufacturing strategy, the peripheral circuitry 400 and the 3D memory array 500 can be connected together at the die level (e.g., die-to-die, or chip-to-chip) or at the wafer level (e.g., wafer-to-wafer). Wafer interconnection (e.g., wafer-level bonding) can provide high throughput, where all dies / chips on a first substrate 430 having the peripheral circuitry 400 can be simultaneously bonded to a second substrate 530 having the 3D memory array 500. The individual 3D memory devices 600 can be diced after wafer bonding. Alternatively, die-level bonding can be performed after dicing and die testing, where functional dies of the peripheral circuitry 400 and the 3D memory array 500 can be selected first and then bonded to form the 3D memory device 600, thereby achieving higher throughput for the 3D memory device 600.

[0107] In some embodiments, during the bonding process, when the interconnect VIA 486 of the peripheral circuitry 400 is aligned with the corresponding interconnect VIA 586 of the 3D memory array 500, the peripheral interconnect layer 462 can be aligned with the array interconnect layer 562. Therefore, the corresponding interconnect VIAs 486 / 586 can be connected to the bonding interface 688, and the 3D memory array 500 can be electrically connected to the peripheral circuitry 400.

[0108] In some embodiments, the peripheral circuitry 400 and the 3D memory array 500 can be joined by hybrid bonding. Hybrid bonding (particularly metal / dielectric hybrid bonding) can be a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer, such as solder or adhesive), which simultaneously achieves metal-to-metal bonding and dielectric-to-dielectric bonding. During the bonding process, chemical bonds can be formed on both the metal-to-metal bonding surfaces and the dielectric-to-dielectric surfaces.

[0109] In some embodiments, the peripheral circuitry 400 and the 3D memory array 500 can be bonded using a bonding layer 690. At the bonding interface 688, in addition to metal-to-metal bonding, bonding can also occur between silicon nitride and silicon nitride, silicon oxide and silicon oxide, or silicon nitride and silicon oxide. In some embodiments, the bonding layer may further include an adhesive material to enhance bond strength, such as epoxy resin, polyimide, dry film, etc.

[0110] In some embodiments, a processing technique may be used to enhance the bonding strength at the bonding interface 688. This processing technique may prepare the surfaces of the array interconnect layer 562 and the peripheral interconnect layer 462 such that chemical bonds are formed on the surfaces of the insulating layers 562 / 462. This processing technique may include, for example, plasma treatment (e.g., using plasma containing F, Cl, or H) or chemical processes (e.g., formic acid). In some embodiments, the processing technique may include a heat treatment that can be performed in a vacuum or inert environment (e.g., using nitrogen or argon) at a temperature of about 250°C to about 600°C. The heat treatment may cause interdiffusion of the metals between interconnects VIAs 486 and 586. As a result, the metal materials in the corresponding pairs of interconnects VIAs may mix or form alloys after the bonding process.

[0111] After bonding the peripheral and array interconnect layers together, at least one peripheral device of the peripheral circuit 400 fabricated on the first substrate 430 can be electrically connected to at least one memory cell of the 3D memory array 500 fabricated on the second substrate 530. Although Figure 6 The diagram shows that the peripheral circuitry 400 is bonded to the top of the 3D memory array 500; however, the 3D memory array 500 can also be bonded to the top of the peripheral circuitry 400.

[0112] Through wafer interconnection methods such as bonding, the 3D memory device 600 can function similarly to peripheral circuitry and the memory array being fabricated on the same substrate (e.g., Figure 1AThe function of the 3D memory (shown) is as follows. By stacking the 3D memory array 500 and the peripheral circuitry 400 on top of each other, the density of the 3D memory device 600 can be increased. Simultaneously, since the interconnect distance between the peripheral circuitry 400 and the 3D memory array 500 can be reduced by using a stacking design, the bandwidth of the 3D memory device 600 can be increased. After the bonding process, the peripheral circuitry 400 has an exposed back surface 430-2, ready for subsequent processing.

[0113] In operation 308, according to some embodiments of this disclosure, the peripheral circuit wafer is thinned and a dielectric layer is provided. (See also...) Figure 7 The 3D storage device 700 shown is similar to Figure 6 The 3D memory device 600 includes peripheral circuitry 400 and a 3D memory array 500. The peripheral circuitry 400 is bonded to the 3D memory array 500 at a bonding interface 688. After the 3D memory device 600 is formed by bonding, the 3D memory device 700 can be formed by thinning the first substrate 430 of the peripheral circuitry 400.

[0114] In some embodiments, the first substrate 430 of the peripheral circuitry 400 may be thinned from the back side 430-2. In some embodiments, the substrate thinning process may include one or more of grinding, dry etching, wet etching, and chemical mechanical polishing (CMP). After thinning, the thickness T of the first substrate 430 may be in the range of approximately 1 μm to approximately 5 μm. For example, the thickness T may be between approximately 2 μm and approximately 4 μm. In some embodiments, the thinning process may continue until the deep well 455 is exposed.

[0115] After thinning the first substrate 430, a dielectric layer 792 can be formed on the back side 430-1 (or the second side) of the first substrate 430. The dielectric layer 792 can be any suitable semiconductor material, such as silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide (e.g., F-, C-, N-, or H-doped oxides), tetraethoxysilane (TEOS), polyimide, spin-coated glass (SOG), low-k dielectric material (e.g., porous SiCOH), silsesquioxane (SSQ), or any combination thereof. The insulating material can be deposited using one or more thin-film deposition processes (e.g., CVD, PVD, PECVD, ALD, high-density plasma CVD (HDP-CVD), sputtering, spin coating, or any combination thereof). After deposition, the dielectric layer 792 covers the entire surface of the first substrate 430. In some embodiments, the thickness t of the dielectric layer 792 can be between approximately 100 nm and approximately 1 μm. In some embodiments, the thickness t can be between approximately 300 nm and approximately 600 nm. For example, the thickness t can be approximately 500 nm.

[0116] In operation 310, deep isolation trenches are formed in the peripheral circuit wafer and between adjacent devices. (See reference...) Figure 8 The 3D memory device 800 includes a plurality of deep isolation trenches 894 formed on the back side 430-2 of the first substrate 430. The isolation trenches penetrate the dielectric layer 792 and portions of the first substrate 430 until the STI 452 is exposed at the bottom of the isolation trench 894. In some embodiments, the deep isolation trenches 894 also expose portions of the well and other structures of the peripheral devices 450A and 450B.

[0117] The cross-sectional shape and number of deep isolation trenches can be determined by various factors, such as the number of devices requiring isolation and the type of devices. For example, a single deep isolation structure can be formed on an STI 452. In some embodiments, two or more deep isolation structures can be formed on an STI 452. In some embodiments, any suitable number of deep isolation trenches can be used. Deep isolation trenches can also have any suitable cross-sectional shape. For example, Figure 8 The cross-sectional shape of the deep isolation trench 894 shown can be trapezoidal, having a top width W1 measured at the top of the deep isolation trench 894 and a bottom width W2 measured at the bottom of the deep isolation trench 894. For example... Figure 8 As shown, the width of the deep isolation trench 894 at the top can be greater than its width at the bottom of the structure, and this configuration can prevent voids in the subsequently applied isolation material. In some embodiments, the width W1 can be in the range of about 0.1 μm to about 5 μm. In some embodiments, the width W2 can be in the range of about 0.05 μm to about 0.25 μm. In some embodiments, the widths W1 and W2 can be substantially the same. For example, the widths W1 and W2 can be about 0.2 μm. In some embodiments, the top-to-bottom ratio R1 of W1 and W2 can be between about 1.5 and about 2.5. For example, R1 can be about 2. In some embodiments, since the deep isolation trench 894 can penetrate a portion of the dielectric layer 792 and the first substrate 430, the depth D of the deep isolation trench 894 can be in the range of about 1 μm to about 6 μm. In some embodiments, the depth of STI 452 can be between about 300 nm and about 450 nm. In some embodiments, the ratio of depth D to the combined thickness (thicknesses T and t) of the thinned first substrate 430 and dielectric layer 792 can be in the range of about 60% to about 95%. In some embodiments, the aspect ratio of the deep isolation structure can be between about 10 and about 20. In some embodiments, the aspect ratio can be greater than about 20. In some embodiments, the angle α between the bottom surface and the sidewall surface of the deep isolation trench 894 can be in the range of about 90° to about 45°. In some embodiments, the deep isolation trench 894 may have sidewalls substantially perpendicular to its bottom surface.

[0118] In some embodiments, trench 896 can be formed simultaneously with deep isolation trench 894. Trench 896 can be formed through dielectric layer 792 and first substrate 430. Trench 896 can be aligned with underlying contact 471, and the etching process for forming trench 896 can continue until the surface of underlying contact 471 is exposed, such as... Figure 8 As shown. In some embodiments, different processes for forming deep isolation trenches 894 can be used to form trenches 896.

[0119] In operation 312, according to some embodiments of this disclosure, insulating material is placed in a deep insulating trench, and a planarization process is performed. (See also...) Figure 9 A deep isolation structure 994 is formed in a deep isolation trench 894 of the 3D memory device 900 by depositing an isolation material and performing a planarization process. The deep isolation structure 994 can be used to prevent crosstalk occurring between adjacent devices, such as peripheral devices 450A and 450B, through the first substrate 430. The deep isolation structure 994 can also prevent peripheral devices 450A and 450B from affecting any other surrounding devices. For example, the deep isolation structure 994 can prevent electrical short circuits between adjacent wells of different types, such as between an n-type well and a p-type well. In some embodiments, the deep isolation structure can prevent electrical short circuits between wells coupled to different bias voltages. For example, it can prevent short circuits between a first well coupled to a high voltage (e.g., approximately 20V) and a second well coupled to a ground voltage reference level (e.g., approximately 0V). In some embodiments, the deep isolation structure 994 can prevent electrical short circuits between terminals of different devices embedded in the same well. For example, the deep isolation structure 994 can prevent electrical short circuits between the source / drain terminals of the first device and the source / drain terminals of the second device, where both devices are formed in the same well (e.g., an n-type well or a p-type well). The deep isolation structure 994 can be in physical contact with the STI structure 452. The isolation material can be any suitable material that prevents crosstalk between adjacent devices. For example, the isolation material can be a low-k material (e.g., having a dielectric constant less than about 3.9). In some embodiments, the isolation material can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, fluoride-doped silicate glass (FSG), any suitable dielectric material, and / or combinations thereof. In some embodiments, a liner can be disposed in the deep isolation trench 894 prior to depositing the isolation material. For example, the liner ( Figure 9 (Not shown) may be a catalytic layer that promotes the adhesion of subsequently deposited isolation material or a barrier layer that prevents potential contamination of the first substrate due to subsequent deposition of the isolation material. For example, the liner may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, titanium nitride, tantalum nitride, any suitable material and / or combinations thereof. In some embodiments, the liner is located between the isolation material and the first substrate 430.

[0120] In some embodiments, the isolation material can be deposited using a uniform thickness deposition process until the deep isolation trench 894 is completely filled with the isolation material, followed by a planarization process that removes any excess isolation material disposed on the top surface of the dielectric layer 792. The planarization process can be chemical mechanical polishing (CMP), reactive ion etching (RIE), wet etching, suitable processes, and / or combinations thereof. The planarization process can be performed until the top surface of the deep isolation structure 994 and the dielectric layer 792 is substantially coplanar (e.g., horizontal). In some embodiments, the deep isolation structure 994 can be formed in any suitable location of the 3D memory device 900 where device isolation is required.

[0121] Conductive material can be deposited into trench 896 to form through-silicon contact (TSC) 996. TSC 996 can be electrically coupled (e.g., electrically connected) to contact 471 to conduct power and / or electrical signals. In some embodiments, trench 896 can be filled with tungsten, copper, silver, aluminum, other suitable conductive materials, and / or combinations thereof. CVD, PVD, sputtering, electroplating, electroless plating, any suitable deposition method, and / or combinations thereof can be used to form the conductive material. CMP processes can be performed on dielectric layer 792 and the conductive material disposed in trench 896 such that the top surfaces of TSC 996, dielectric layer 792, and deep isolation structure 994 are substantially coplanar (e.g., horizontal).

[0122] Dielectric layer 997 may be disposed on the top surface of TSC 996, dielectric layer 792, and deep isolation structure 994. In some embodiments, dielectric layer 997 may be formed using any suitable dielectric material (e.g., a low-k dielectric material, such as a dielectric material with a dielectric constant below about 3.9). In some embodiments, dielectric layer 997 may be formed using silicon oxide, silicon nitride, any suitable dielectric material, and / or combinations thereof.

[0123] One or more contact pads 998 may be formed in the dielectric layer 997 and electrically coupled to the underlying TSC 996. The contact pads 998 may be formed using tungsten, aluminum, copper, silver, any suitable conductive material, and / or combinations thereof. One or more contact pads 998 may provide access points for external control to electrically access and control the 3D memory device 900. In some embodiments, the contact pads 998 may be formed by patterning and etching processes (e.g., damascene processes).

[0124] Figures 10A to 10BThis diagram shows a top view of a portion of an exemplary three-dimensional (3D) memory device 1000 according to some embodiments of the present disclosure. The 3D memory device 1000 includes a dielectric layer 1097 and peripheral devices 1010A and 1010B formed beneath the dielectric layer 1097. The peripheral devices 1010A and 1010B may be high-voltage devices such as high-voltage p-type devices and n-type devices. The dielectric layer 1097, peripheral devices 1010A and 1010B may be respectively similar to... Figure 9 The dielectric layer 997 and peripheral devices 450A and 450B are shown, and for simplicity, they will not be described in detail here. See reference... Figure 9 Peripheral devices 450A and 450B are formed below dielectric layer 997 and are therefore not visible in a direct top-down view. For illustrative purposes, peripheral devices 1010A and 1010B are... Figures 10A-10B The outline is visible in the middle and is delineated with dashed lines for clarity.

[0125] like Figures 10A-10B As shown, peripheral device 1010B can be surrounded by a deep isolation structure 1094, which provides isolation and prevents crosstalk between adjacent devices, such as crosstalk between peripheral devices 1010B and 1010A and / or between adjacent peripheral devices 1010B. The deep isolation structure 1094 can be similar to... Figure 9 The deep isolation structure 994 is shown. For example, the deep isolation structure 1094 can prevent electrical short circuits between adjacent wells of different types (e.g., between an n-type well and a p-type well). In some embodiments, the deep isolation structure can prevent electrical short circuits between wells coupled to different bias voltages. For example, it can prevent short circuits between a first well coupled to a high voltage (e.g., about 20V) and a second well coupled to a ground voltage reference level (e.g., about 0V). In some embodiments, the deep isolation structure 1094 can prevent electrical short circuits between the terminals of different devices embedded in the same well. For example, the deep isolation structure 1094 can prevent electrical short circuits between the source / drain terminals of a first device and the source / drain terminals of a second device, where both devices are formed in the same well (e.g., an n-type well or a p-type well). In some embodiments, both peripheral devices 1010A and 1010B can be surrounded by the deep isolation structure 1094. In some embodiments, peripheral device 1010A can be surrounded by the deep isolation structure 1094. Peripheral devices 1010A and 1010B can include the above-mentioned... Figure 4 The gate stack 456 described herein is similar to the gate stack 1056. In some embodiments, the gate stack 456 may extend in the x-direction and / or in the y-direction.

[0126] Various embodiments of this disclosure provide structures and methods for fabricating isolation structures that improve isolation between structures in 3D memory structures. A peripheral device wafer containing CMOS devices can be bonded to an array wafer containing a 3D memory array. Isolation structures can be implemented in the bonded peripheral / memory array wafers to prevent crosstalk between adjacent structures (e.g., between wells of different doping types). Isolation structures can be formed by thinning the dielectric layer of the peripheral wafer and forming a through-silicon isolation (TSI) structure to effectively separate different functional regions.

[0127] The above description of specific embodiments will therefore fully reveal the general nature of this disclosure, enabling others to readily modify and / or adapt such specific embodiments for various applications using knowledge within the scope of the art, without excessive experimentation and without departing from the general concept of this disclosure. Therefore, based on the disclosure and guidance presented herein, such modifications and adaptations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology used herein is for illustrative purposes and not for limitation, and thus the terminology or terminology of this specification will be interpreted by those skilled in the art in accordance with the disclosure and guidance presented.

[0128] The embodiments of this disclosure have been described above using functional building blocks, which exemplify implementations of specified functions and their relationships. The boundaries of these functional building blocks are arbitrarily defined herein for ease of description. Alternative boundaries may be defined, provided that the specified functions and their relationships are appropriately performed.

[0129] The summary and abstract may set forth one or more exemplary embodiments of the present disclosure as conceived by the inventors, but not necessarily all exemplary embodiments, and therefore are not intended to limit the present disclosure and the appended claims in any way.

[0130] The scope and extent of this disclosure should not be limited by any of the exemplary embodiments described above, and should be defined solely by the appended claims and their equivalents.

Claims

1. A three-dimensional memory device, comprising: a first substrate; a plurality of semiconductor devices formed on a first side of the first substrate; a plurality of shallow trench isolation (STI) structures in the first substrate, wherein at least one STI structure is formed between adjacent semiconductor devices of the plurality of semiconductor devices; a plurality of deep isolation structures formed on a second side of the first substrate opposite the first side, wherein at least one deep isolation structure of the plurality of deep isolation structures is in physical contact with the at least one STI structure and in physical contact with a portion of a well in which the plurality of semiconductor devices are embedded; the plurality of semiconductor devices are embedded in a same well; each deep isolation structure of the plurality of deep isolation structures is between the plurality of semiconductor devices embedded in the same well; and the plurality of semiconductor devices include high voltage devices.

2. The three-dimensional memory device of claim 1, wherein, the at least one deep isolation structure includes a liner and an isolation material, wherein the liner is between the isolation material and the first substrate.

3. The three-dimensional memory device of claim 2, wherein, the isolation material filling the deep isolation structure includes at least one of: silicon oxide; silicon nitride; silicon oxynitride; silicon carbide; or fluoride-doped silicate glass.

4. The three-dimensional memory device of claim 1, wherein, each of the STI structures includes a monolithic STI structure or a plurality of stacked sub-STI structures.

5. The three-dimensional memory device of claim 1, wherein, a first end of the deep isolation structure in physical contact with the STI structure has a dimension that is less than or equal to a second end of the deep isolation structure away from the STI structure.

6. The three-dimensional memory device of claim 1, wherein, an aspect ratio of the at least one deep isolation structure is greater than 10.

7. The three-dimensional memory device of claim 1, wherein, the three-dimensional memory device further includes a second substrate and a plurality of memory cells on the second substrate, wherein at least one peripheral device of the plurality of semiconductor devices is electrically coupled to at least one memory cell of the plurality of memory cells.

8. The three-dimensional memory device of claim 7, wherein, the three-dimensional memory device further includes: a first interconnect layer formed on the first side of the first substrate; and a second interconnect layer formed on the second substrate and in physical contact with the first interconnect layer.

9. The three-dimensional memory device of claim 8, wherein, the physical contact includes a chemical bond formed between the first interconnect layer and the second interconnect layer.

10. The three-dimensional memory device of claim 1, wherein, the plurality of semiconductor devices include high voltage n-type devices and high voltage p-type devices.

11. The three-dimensional memory device of claim 1, wherein, the first substrate includes a contact electrically coupled to a through-silicon contact (TSC).

12. The three-dimensional memory device of claim 11, further comprising a contact pad in contact with and electrically coupled to the through-silicon contact.

13. The three-dimensional memory device of claim 1, wherein, the three-dimensional memory device includes a three-dimensional NAND-type memory device.

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