Display panel and display device

Abstract

The display panel comprises a substrate, a driving functional layer located on one side of the substrate, the driving functional layer comprising a gate line, a data line and a pixel driving circuit, the data line extending along a second direction, the pixel driving circuit comprising a data writing transistor, the driving functional layer comprising a first conductive layer, a planarization layer located on a side of the driving functional layer away from the substrate, a second conductive layer located on a side of the planarization layer away from the driving functional layer, wherein a normal projection of any one of conductive patterns extending along the second direction in the first conductive layer and located within a region defined by at least one pixel driving circuit on the substrate does not overlap with a normal projection of an active region pattern of the data writing transistor on the substrate, and / or a normal projection of any one of conductive patterns extending along the second direction in the second conductive layer and located within the region defined by at least one pixel driving circuit on the substrate does not overlap with the normal projection of the active region pattern of the data writing transistor on the substrate.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the acceleration of the update iteration of display products, the emergence of flexible display panel provides a new product form for display products - folding screen, accompanied by higher quality requirements for flexible display panel: the screen remains intact after 200,000 times of folding. However, it is found that with the increase of the number of bending, abnormal bright spots are easily generated in the display panel during the bending reliability test of the flexible display panel or in the actual use process.

[0003] The flexible display panel is usually stacked by a flexible substrate and a plurality of functional film layers on the flexible substrate; it is found that with the increase of the number of bending, abnormal bright spots are easily generated in the display panel during the bending reliability test of the flexible display panel or in the actual use process. SUMMARY

[0004] The present application aims to at least solve one of the technical problems existing in the prior art, and proposes a display panel and a display device.

[0005] In a first aspect, the embodiments of the present application provide a display panel, comprising:

[0006] a substrate;

[0007] a driving functional layer located on one side of the substrate, comprising a plurality of gate lines, a plurality of data lines and a plurality of pixel driving circuits, the gate lines extending along a first direction, the data lines extending along a second direction, the first direction intersecting the second direction, the pixel driving circuit comprising: a data writing transistor, a control electrode of the data writing transistor being electrically connected with a corresponding gate line, a first electrode of the data writing transistor being electrically connected with a corresponding data line, the data writing transistor being electrically connected with a preset node in the pixel driving circuit, the driving functional layer comprising a first conductive layer, the first conductive layer comprising a plurality of conductive patterns, the data lines being located on the first conductive layer;

[0008] a planarization layer located on a side of the driving functional layer away from the substrate;

[0009] a second conductive layer located on a side of the planarization layer away from the driving functional layer, the second conductive layer comprising a plurality of conductive patterns;

[0010] wherein the orthogonal projection of any one of the conductive patterns extending along the second direction in the first conductive layer and located in the area defined by at least one pixel driving circuit on the substrate does not overlap with the orthogonal projection of the active area pattern of the data writing transistor on the substrate.

[0011] and / or any one of the electrically conductive patterns in the second electrically conductive layer and within the region defined by the at least one pixel driving circuit extends in the second direction has a non-overlapping orthogonal projection on the base with the orthogonal projection on the base of the active region pattern of the data writing transistor.

[0012] In some embodiments, any one of the electrically conductive patterns in the first electrically conductive layer and within the region defined by the at least one pixel driving circuit has a non-overlapping orthogonal projection on the base with the orthogonal projection on the base of the active region pattern of the data writing transistor.

[0013] and / or any one of the electrically conductive patterns in the second electrically conductive layer and within the region defined by the at least one pixel driving circuit extends in the second direction has a non-overlapping orthogonal projection on the base with the orthogonal projection on the base of the active region pattern of the data writing transistor.

[0014] In some embodiments, the pixel driving circuit further comprises a driving transistor and a threshold compensation transistor.

[0015] a control electrode of the driving transistor is electrically connected with a first electrode of the threshold compensation transistor, a first electrode of the driving transistor is electrically connected with the preset node, a second electrode of the driving transistor is electrically connected with a second electrode of the threshold compensation transistor, and a control electrode of the threshold compensation transistor is electrically connected with the corresponding gate line.

[0016] any one of the electrically conductive patterns in the first electrically conductive layer and within the region defined by the at least one pixel driving circuit extends in the second direction has a non-overlapping orthogonal projection on the base with the orthogonal projection on the base of the active region pattern of the threshold compensation transistor.

[0017] and / or any one of the electrically conductive patterns in the second electrically conductive layer and within the region defined by the at least one pixel driving circuit extends in the second direction has a non-overlapping orthogonal projection on the base with the orthogonal projection on the base of the active region pattern of the threshold compensation transistor.

[0018] In some embodiments, any one of the electrically conductive patterns in the first electrically conductive layer and within the region defined by the at least one pixel driving circuit has a non-overlapping orthogonal projection on the base with the orthogonal projection on the base of the active region pattern of the threshold compensation transistor.

[0019] and / or any one of the electrically conductive patterns in the second electrically conductive layer and within the region defined by the at least one pixel driving circuit has a non-overlapping orthogonal projection on the base with the orthogonal projection on the base of the active region pattern of the threshold compensation transistor.

[0020] In some embodiments, the pixel driving circuit further comprises: a first light emitting control transistor;

[0021] The control electrode of the first light emitting control transistor is electrically connected with a corresponding light emitting control signal line, the first electrode of the first light emitting control transistor is electrically connected with a working voltage transmission line, and the second electrode of the first light emitting control transistor is electrically connected with the preset node.

[0022] In some embodiments, the working voltage transmission line is located in the second conductive layer, and the working voltage transmission line extends along the second direction.

[0023] In some embodiments, the orthogonal projection of the data line on the substrate is located on a third side of the orthogonal projection of the active region pattern of the corresponding data write transistor on the substrate;

[0024] The orthogonal projection of the working voltage transmission line on the substrate is located on a fourth side of the orthogonal projection of the active region pattern of the corresponding data write transistor on the substrate;

[0025] The third side and the fourth side are opposite sides in the first direction.

[0026] In some embodiments, the working voltage transmission line is located in the first conductive layer, and the working voltage transmission line extends along the second direction.

[0027] In some embodiments, the orthogonal projection of the data line on the substrate is located on a third side of the orthogonal projection of the active region pattern of the corresponding data write transistor on the substrate;

[0028] The orthogonal projection of the working voltage transmission line on the substrate is located on a fourth side of the orthogonal projection of the active region pattern of the corresponding data write transistor on the substrate;

[0029] The third side and the fourth side are opposite sides in the first direction.

[0030] In some embodiments, the plurality of conductive patterns in the second conductive layer comprises: a plurality of first working voltage connection lines and a plurality of second working voltage connection lines, the first working voltage connection lines extend along the second direction, the second working voltage connection lines extend along a third direction, and the third direction intersects with the second direction;

[0031] Each of the second working voltage connection lines is electrically connected with at least two of the first working voltage transmission lines, and any one of the first working voltage connection lines is electrically connected with other first working voltage connection lines.

[0032] The working voltage transmission line is electrically connected with the first working voltage connection line.

[0033] In some embodiments, the first working voltage connection line corresponds to the working voltage transmission line one by one.

[0034] The normal projection of the data line on the substrate is located at a third side of the normal projection of the active region pattern of the corresponding data write transistor on the substrate;

[0035] The normal projection of the working voltage transmission line on the substrate is located at a fourth side of the normal projection of the active region pattern of the corresponding data write transistor on the substrate;

[0036] The normal projection of the first working voltage connection line on the substrate is located at the fourth side of the normal projection of the active region pattern of the corresponding data write transistor on the substrate;

[0037] The third side and the fourth side are opposite sides in the first direction.

[0038] In some embodiments, the display panel further comprises a light emitting element, the light emitting element comprising: a first electrode, a light emitting layer and a second electrode arranged in sequence away from the substrate;

[0039] The pixel driving circuit further comprises a first reset transistor, a second reset transistor, a second light emitting control transistor and a storage capacitor.

[0040] The control electrode of the first reset transistor is electrically connected with a corresponding reset control signal line, the first electrode of the first reset transistor is electrically connected with a reset voltage transmission line, and the second electrode of the first reset transistor is electrically connected with the control electrode of the driving transistor.

[0041] The control electrode of the second reset transistor is electrically connected with a corresponding reset control signal line, the first electrode of the second reset transistor is electrically connected with a reset voltage transmission line, and the second electrode of the second reset transistor is electrically connected with the first electrode.

[0042] The control electrode of the second light emitting control transistor is electrically connected with the light emitting control signal line, the first electrode of the second light emitting control transistor is electrically connected with the second electrode of the driving transistor, and the second electrode of the second light emitting control transistor is electrically connected with the first electrode.

[0043] The first end plate of the storage capacitor is connected with the working voltage transmission line, and the second end plate of the storage capacitor is electrically connected with the control electrode of the driving transistor.

[0044] In some embodiments, the driving function layer further comprises: an active semiconductor layer, a first insulating layer, a third conductive layer, a second insulating layer, a fourth conductive layer and a third insulating layer arranged in sequence along the direction away from the substrate, and the first conductive layer is located on the side of the third insulating layer away from the substrate.

[0045] The active semiconductor layer comprises: an active region pattern and a source-drain doped region of each transistor in the pixel driving circuit.

[0046] The third conductive layer comprises: a control electrode of each transistor in the pixel driving circuit, the reset control signal line, the gate line, a second end plate of the storage capacitor and the light-emitting control signal line.

[0047] The fourth conductive layer comprises: the reset voltage transmission line and a first end plate of the storage capacitor.

[0048] In some embodiments, the control electrode of the data writing transistor, the control electrode of the threshold value compensation transistor, the control electrode of the first reset transistor and the control electrode of the second reset transistor are all located on the first side of the control electrode of the driving transistor, the control electrode of the first light-emitting control transistor and the control electrode of the second light-emitting control transistor are all located on the second side of the control electrode of the driving transistor, and the first side and the second side are opposite sides in the second direction.

[0049] The control electrode of the data writing transistor and the control electrode of the first light-emitting control transistor are all located on the third side of the control electrode of the driving transistor, the first control electrode of the threshold value compensation transistor, the control electrode of the second light-emitting control transistor and the control electrode of the second reset transistor are all located on the fourth side of the control electrode of the driving transistor, and the third side and the fourth side are opposite sides in the first direction.

[0050] In a second aspect, the embodiments of the present disclosure further provide a display device, comprising: the display panel provided in the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0051] Figure 1 A top view of a display panel provided in the embodiments of the present disclosure;

[0052] Figure 2A A circuit structure diagram of a pixel driving circuit in the embodiments of the present disclosure;

[0053] Figure 2B A working timing diagram of the pixel driving circuit shown in Figure 2A

[0054] Figure 3 A layout of the pixel driving circuit shown in the embodiments of the present disclosure Figure 2A ​​

[0055] Figure 4 FIG. 1 is a schematic cross-sectional view of a display panel in a direction of A-A' according to an embodiment of the present disclosure; Figure 3 FIG. 2 is a schematic cross-sectional view of a display panel in a direction of B-B' according to an embodiment of the present disclosure;

[0056] Figure 5 FIG. 3 is a schematic cross-sectional view of a display panel in a direction of C-C' according to an embodiment of the present disclosure;

[0057] Figure 6 FIG. 4 is a schematic cross-sectional view of a display panel in a direction of D-D' according to an embodiment of the present disclosure; Figure 3 FIG. 5 is a schematic layout of an active semiconductor layer in a display panel according to an embodiment of the present disclosure;

[0058] Figure 7 FIG. 6 is a schematic layout of a third conductive layer in a display panel according to an embodiment of the present disclosure; Figure 3

[0059] Figure 8 FIG. 7 is a schematic layout of a fourth conductive layer in a display panel according to an embodiment of the present disclosure; Figure 3

[0060] Figure 9 FIG. 8 is a schematic layout of a first conductive layer in a display panel according to an embodiment of the present disclosure; Figure 3

[0061] Figure 10 FIG. 9 is a schematic layout of a second conductive layer in a display panel according to an embodiment of the present disclosure; Figure 3

[0062] FIG. 10 is another schematic layout of a pixel driving circuit in a display panel according to an embodiment of the present disclosure; Figure 11 Figure 2A

[0063] Figure 12 FIG. 11 is a schematic cross-sectional view of a display panel in a direction of E-E' according to an embodiment of the present disclosure; Figure 11

[0064] Figure 13 FIG. 12 is a schematic layout of a first conductive layer in a display panel according to an embodiment of the present disclosure; Figure 11

[0065] Figure 14 FIG. 13 is a schematic layout of a second conductive layer in a display panel according to an embodiment of the present disclosure. Figure 11 DETAILED DESCRIPTION

[0066] In order to make the technical solution of the present application better understood by those skilled in the art, a display panel and a display device provided by the present application are described in detail below with reference to the drawings.

[0067] It is found that, with an increase in the number of bending, abnormal pixel points (for example, abnormal bright spots) are easily generated in a display panel in the related art during a bending reliability test and in actual use.

[0068] ​​​​​​​​It is found through research that one of the main reasons for the abnormal bright spots in the related art is that after the display panel is bent multiple times (generally, bending is performed along the extension direction of the data line), micro-cracks are generated at the bending position due to stress concentration of part of the functional film layer, and the micro-cracks are particularly prone to occur at the region where the active area pattern of the data writing transistor in the pixel driving circuit is located. The micro-cracks at the region where the active area pattern of the data writing transistor is located can cause abnormal performance of the data writing transistor, so that in the process of writing the data voltage loaded in the data line to the inside of the pixel driving circuit by the data writing transistor, the case of abnormal data voltage Vdata writing (for example, insufficient data voltage Vdata writing) occurs, and then abnormal light emission of the light emitting element (for example, the light emission brightness of the light emitting element is too bright in the case of insufficient data voltage writing) occurs, that is, abnormal pixel points are formed.

[0069] To effectively solve the above technical problems existing in the related art, the display panel provided in the embodiments of the present disclosure is described in detail below in combination with specific embodiments.

[0070] It should be noted that the transistor used in the embodiments of the present disclosure can be a thin film transistor or a field effect transistor or other devices with the same or similar characteristics. Since the source and drain of the transistor used are symmetrical, the source and drain are not distinguished. In the embodiments of the present disclosure, one of the poles is referred to as the first pole and the other pole is referred to as the second pole to distinguish the source and drain of the transistor. In addition, the transistor can be divided into N-type and P-type according to the characteristics of the transistor. When a P-type transistor is used, the first pole is the drain of the P-type transistor, and the second pole is the source of the P-type transistor. The N-type is opposite. The N-type transistor is turned on when a high-level signal is applied to the control pole and is turned off when a low-level signal is applied to the control pole. The P-type transistor is turned on when a low-level signal is applied to the control pole and is turned off when a high-level signal is applied to the control pole.

[0071] The light emitting element in the embodiments of the present disclosure is specifically an electroluminescent element, such as a light emitting diode (LED), an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), and the like. In the embodiments of the present disclosure, the light emitting element is an organic light emitting diode

[0072] Figure 1 A top view of a display panel provided in the embodiments of the present disclosure, Figure 2AThis is a schematic diagram of a pixel driving circuit in an embodiment of the present disclosure. Figure 2B for Figure 2A The diagram shows a timing diagram of one type of pixel driving circuit. Figure 3 As described in this embodiment of the disclosure Figure 2A The diagram shows a layout of a pixel driving circuit. Figure 4 for Figure 3 A schematic diagram of a cross-section along line A-A'. Figure 5 This is a cross-sectional schematic diagram of the second light-emitting control transistor and the connected light-emitting device in an embodiment of this disclosure. Figure 6 for Figure 3 A layout with an active semiconductor layer. Figure 7 for Figure 3 A layout of the third conductive layer. Figure 8 for Figure 3 One layout of the fourth conductive layer. Figure 9 for Figure 3 One layout of the first conductive layer in the middle. Figure 10 for Figure 3 A layout of the second conductive layer. For example... Figures 1 to 10 As shown, the display panel includes a substrate 10 and a driving function layer 2, a planarization layer 17, and a second conductive layer 9 arranged sequentially along a direction away from the substrate 10.

[0073] The substrate 10 is a flexible substrate 10, and the material of the substrate 10 includes polyimide (PI) or cycloolefin copolymer (COP).

[0074] The driving functional layer 2 is located on one side of the substrate 10. The driving functional layer 2 includes multiple gate lines (Gates), multiple data lines (Data), and multiple pixel driving circuits 1. The gate lines extend along a first direction X, and the data lines extend along a second direction Y, with the first direction X intersecting the second direction Y. The pixel driving circuits 1 are used to drive corresponding light-emitting elements E to emit light. Each pixel driving circuit 1 includes a data writing transistor T2. The control electrode of the data writing transistor T2 is electrically connected to the corresponding gate line (Gate). The first electrode of the data writing transistor T2 is electrically connected to the corresponding data line (Data). The data writing transistor T2 is electrically connected to a preset node W within the pixel driving circuit 1. The data writing transistor T2 is configured to write the data voltage provided by the data line (Data) to the preset node W within the pixel driving circuit 1 in response to the gate scan signal provided by the gate line (Gate). The driving functional layer 2 includes a first conductive layer 8, which includes multiple conductive patterns. The data lines (Data) are located in the first conductive layer 8; that is, the data lines (Data) are conductive patterns in the first conductive layer 8.

[0075] The planarization layer 17 is located on the side of the driving functional layer 2 away from the substrate 10, and the surface of the planarization layer 17 away from the driving functional layer 2 is a planarization surface, so as to facilitate the preparation of subsequent film layer structures.

[0076] The second conductive layer 9 is located on the side of the planarization layer 17 away from the driving functional layer 2, and the second conductive layer 9 comprises a plurality of conductive patterns.

[0077] In the embodiments of the present disclosure, the orthogonal projection of any one conductive pattern extending along the second direction Y in the first conductive layer 8 and located in the region defined by the at least one pixel driving circuit 1 on the substrate 10 does not overlap with the orthogonal projection of the active region pattern T2a of the data writing transistor T2 on the substrate 10; and / or, the orthogonal projection of any one conductive pattern extending along the second direction Y in the second conductive layer 9 and located in the region defined by the at least one pixel driving circuit 1 on the substrate 10 does not overlap with the orthogonal projection of the active region pattern T2a of the data writing transistor T2 on the substrate 10.

[0078] In the embodiments of the present disclosure, in the region defined by at least part of the pixel driving circuits (for the convenience of description, the region is referred to as a "bending stress reduction region"; the specific position of the "bending stress reduction region" can be pre-set according to actual needs; for example, the "bending stress reduction region" can be the region where a certain row or multiple rows of pixel driving circuits are located, or the region where part of the pixel driving circuits in the display panel are frequently bent, or the region where all the pixel driving circuits are located; here, no example is given for description), the orthogonal projection of any one conductive pattern extending along the second direction Y in the first conductive layer 8 and located in the "bending stress reduction region" on the substrate 10 does not overlap with the orthogonal projection of the active region pattern T2a of the data writing transistor T2 on the substrate 10, that is, there is no conductive pattern extending in the second direction Y and passing through the active region pattern T2a of the data writing transistor T2 in the first conductive layer 8 in the "bending stress reduction region", so when the display panel is bent along the second direction Y (i.e., the extension direction of the data line Data) and the bending position is located in the "bending stress reduction region", the first conductive layer 8 does not generate bending stress in the region where the active region pattern T2a of the data writing transistor T2 is located, so as to reduce the bending stress in the region where the active region pattern T2a of the data writing transistor T2 is located in the "bending stress reduction region" to a certain extent, thereby effectively avoiding the generation of micro-cracks in the functional film layers in the region where the active region pattern T2a of the data writing transistor T2 is located, and being beneficial to ensuring the normal performance of the data writing transistor T2, so that the pixel driving circuit 1 can output corresponding driving current, and then the light emitting element E can emit light normally.

[0079] Based on the above, by designing the first conductive layer 8 as described above, the bending stress in the region where the active region pattern T2a of the data writing transistor T2 is located within the "bending stress reduction region" can be reduced to some extent, which is conducive to improving the problem of abnormal light emission of the light emitting element E caused by bending stress.

[0080] Similarly, the orthogonal projection of any conductive pattern extending in the second direction Y in the second conductive layer 9 and within the "bending stress reduction region" on the substrate 10 does not overlap with the orthogonal projection of the active region pattern T2a of the data writing transistor T2 on the substrate 10, that is, there is no conductive pattern extending in the second direction Y in the second conductive layer 9 and within the "bending stress reduction region" that passes through the active region pattern T2a of the data writing transistor T2, so when the display panel is bent along the second direction Y (i.e., the extension direction of the data line Data) and the bending position is located in the "bending stress reduction region", the second conductive layer 9 will not generate bending stress in the region where the active region pattern T2a of the data writing transistor T2 is located, so the bending stress in the region where the active region pattern T2a of the data writing transistor T2 is located within the "bending stress reduction region" can be reduced to some extent, thereby effectively avoiding the generation of micro-cracks in each functional film layer in the region where the active region pattern T2a of the data writing transistor T2 is located, which is conducive to ensuring the normal performance of the data writing transistor T2, and the pixel driving circuit 1 can output corresponding driving current, thereby enabling the light emitting element E to emit light normally.

[0081] Based on the above, by designing the second conductive layer 9 as described above, the bending stress in the region where the active region pattern T2a of the data writing transistor T2 is located within the "bending stress reduction region" can be reduced to some extent, which is conducive to improving the problem of abnormal light emission of the light emitting element E caused by bending stress.

[0082] It should be noted that the drawings in the above Figure 3 and Figure 4 only exemplarily show the case where the orthogonal projection of any conductive pattern extending in the second direction Y in the first conductive layer 8 and within the region defined by one pixel driving circuit on the substrate 10 does not overlap with the orthogonal projection of the active region pattern T2a of the data writing transistor T2 on the substrate 10, and the orthogonal projection of any conductive pattern extending in the second direction Y in the second conductive layer 9 and within the region defined by one pixel driving circuit on the substrate 10 does not overlap with the orthogonal projection of the active region pattern T2a of the data writing transistor T2 on the substrate 10, which only serves as an example.

[0083] The skilled in the art should know that, only the first conductive layer 8 is designed as aforementioned (i.e. any one of the conductive patterns extending along the second direction Y in the first conductive layer 8 and located within the area defined by one pixel driving circuit has no intersection with the active area pattern T2a of the data writing transistor T2 on the substrate 10, while in the second conductive layer 9 and within the area defined by the same pixel driving circuit, there is a conductive pattern extending along the second direction Y and having an intersection with the active area pattern T2a of the data writing transistor T2 on the substrate 10; this case is not given corresponding drawings), or only the second conductive layer 9 is designed as aforementioned (i.e. any one of the conductive patterns extending along the second direction Y in the second conductive layer 9 and located within the area defined by the same pixel driving circuit has no intersection with the active area pattern T2a of the data writing transistor T2 on the substrate 10, while in the first conductive layer 8 and within the area defined by the same pixel driving circuit, there is a conductive pattern extending along the second direction Y and having an intersection with the active area pattern T2a of the data writing transistor T2 on the substrate 10; this case is not given corresponding drawings), both of the two cases can reduce the bending stress of the area where the active area pattern T2a of the data writing transistor T2 is located to some extent, which is beneficial to improve the problem of abnormal light emission of the light emitting element E caused by the bending stress.

[0084] In some embodiments, the projection of any one of the conductive patterns in the first conductive layer 8 and located within the area defined by at least one pixel driving circuit 1 (i.e. the aforementioned "bending stress reduction area") on the substrate 10 has no intersection with the projection of the active area pattern T2a of the data writing transistor T2 on the substrate 10; and / or, the projection of any one of the conductive patterns in the second conductive layer 9 and located within the area defined by at least one pixel driving circuit (i.e. the aforementioned "bending stress reduction area") on the substrate 10 has no intersection with the projection of the active area pattern T2a of the data writing transistor T2 on the substrate 10.

[0085] Since the orthogonal projection of any one conductive pattern in the first conductive layer 8 and located in the area defined by the at least one pixel driving circuit on the substrate 10 does not overlap with the orthogonal projection of the active area pattern T2a of the data writing transistor T2 on the substrate 10 (the first conductive layer 8 forms an avoidance in the area where the active area pattern T2a of the data writing transistor T2 is located in the "bending stress reduction area"), when the flexible substrate is bent in any direction and the bending position is located in the "bending stress reduction area", the area where the active area pattern T2a of the data writing transistor T2 is located in the "bending stress reduction area" of the first conductive layer 8 will not generate bending stress, so as to reduce the bending stress at the area where the active area pattern T2a of the data writing transistor T2 is located to a certain extent, thereby effectively avoiding the micro-cracks of the functional film layers at the area where the active area pattern T2a of the data writing transistor T2 is located.

[0086] Similarly, since the orthogonal projection of any one conductive pattern in the second conductive layer 9 and located in the area defined by the at least one pixel driving circuit on the substrate 10 does not overlap with the orthogonal projection of the active area pattern T2a of the data writing transistor T2 on the substrate 10 (the first conductive layer 8 forms an avoidance in the area where the active area pattern T2a of the data writing transistor T2 is located in the "bending stress reduction area"), when the flexible substrate is bent in any direction, the area where the active area pattern T2a of the data writing transistor T2 is located in the "bending stress reduction area" of the second conductive layer 9 will not generate bending stress, so as to reduce the bending stress at the area where the active area pattern T2a of the data writing transistor T2 is located to a certain extent, thereby effectively avoiding the micro-cracks of the functional film layers at the area where the active area pattern T2a of the data writing transistor T2 is located.

[0087] In some embodiments, the pixel driving circuit 1 further comprises a driving transistor T1 and a threshold compensation transistor T3; the control electrode of the driving transistor T1 is electrically connected with the first electrode of the threshold compensation transistor T3, the first electrode of the driving transistor T1 is electrically connected with a preset node W, the second electrode of the driving transistor T1 is electrically connected with the second electrode of the threshold compensation transistor T3, and the control electrode of the threshold compensation transistor T3 is electrically connected with a corresponding gate line Gate.

[0088] In the embodiments of the present disclosure, after the data voltage is written into the preset node W in the pixel driving circuit 1 through the data writing transistor T2, the data voltage after threshold compensation needs to be written into the control electrode of the driving transistor T1 through the threshold compensation transistor T3, and the performance of the threshold compensation transistor T3 also determines whether the data voltage after threshold compensation can be normally written into the control electrode of the driving transistor T1.

[0089] In order to avoid the problem that the functional film layers produce micro-cracks at the region where the active region pattern T3a of the threshold compensation transistor T3 is located, causing abnormal performance of the threshold compensation transistor T3; in the embodiment of the present disclosure, the orthographic projection of any conductive pattern extending along the second direction Y in the first conductive layer 8 and located in the region defined by the at least one pixel driving circuit (i.e., the aforementioned “bending stress reduction region”) on the substrate 10 does not overlap with the orthographic projection of the active region pattern T3a of the threshold compensation transistor T3 on the substrate 10; and / or, the orthographic projection of any conductive pattern extending along the second direction Y in the second conductive layer 9 and located in the region defined by the at least one pixel driving circuit (i.e., the aforementioned “bending stress reduction region”) on the substrate 10 does not overlap with the orthographic projection of the active region pattern T3a of the threshold compensation transistor T3 on the substrate 10.

[0090] In the embodiment of the present disclosure, since the orthographic projection of any conductive pattern extending along the second direction Y in the first conductive layer 8 and located in the “bending stress reduction region” on the substrate 10 does not overlap with the orthographic projection of the active region pattern T3a of the threshold compensation transistor T3 on the substrate 10, that is, there is no conductive pattern extending along the second direction Y and passing through the active region pattern T3a of the threshold compensation transistor T3 in the first conductive layer 8 and located in the aforementioned “bending stress reduction region”, therefore, when the display panel is bent along the second direction Y (i.e., the extension direction of the data line Data) and the bending position is located in the “bending stress reduction region”, the first conductive layer 8 does not produce bending stress at the region where the active region pattern T3a of the threshold compensation transistor T3 is located, so that the bending stress at the region where the active region pattern T3a of the threshold compensation transistor T3 is located in the “bending stress reduction region” can be reduced to a certain extent, thereby effectively avoiding the problem that the functional film layers produce micro-cracks at the region where the active region pattern T3a of the threshold compensation transistor T3 is located, and facilitating to ensure the normal performance of the threshold compensation transistor T3, so that the pixel driving circuit 1 can output corresponding driving current, and then the light emitting element E can emit light normally.

[0091] Based on the above, by designing the first conductive layer 8 as described above, the bending stress at the region where the active region pattern T3a of the threshold compensation transistor T3 is located in the “bending stress reduction region” can be reduced to a certain extent, which is conducive to improving the problem that the light emitting element E emits light abnormally due to bending stress.

[0092] Similarly, since any one of the conductive patterns in the second conductive layer 9 and located in the "bending stress reduction area" extending in the second direction Y has no intersection with the normal projection of the active area pattern T3a of the threshold compensation transistor T3 on the substrate 10, that is, there is no conductive pattern in the second conductive layer 9 and located in the "bending stress reduction area" extending in the second direction Y and passing through the active area pattern T3a of the threshold compensation transistor T3, when the display panel is bent along the second direction Y (i.e., the extension direction of the data line Data), the second conductive layer 9 will not generate bending stress in the region where the active area pattern T3a of the threshold compensation transistor T3 is located, so as to reduce the bending stress in the region where the active area pattern T3a of the threshold compensation transistor T3 is located in the "bending stress reduction area" to a certain extent, thereby effectively avoiding the functional film layers from generating micro-cracks in the region where the active area pattern T3a of the threshold compensation transistor T3 is located, and facilitating to ensure the performance of the threshold compensation transistor T3 normal, so that the pixel driving circuit 1 can output corresponding driving current, and then the light emitting element E can emit light normally.

[0093] Based on the above, it can be seen that by designing the second conductive layer 9 as described above, the bending stress in the region where the active area pattern T3a of the threshold compensation transistor T3 is located in the "bending stress reduction area" can be reduced to a certain extent, which is conducive to improving the problem of abnormal light emission of the light emitting element E caused by bending stress.

[0094] It should be noted that, the above-mentioned Figure 3 and the above-mentioned Figure 4In the case that the orthogonal projection of any one of the conductive patterns extending along the second direction Y in the first conductive layer 8 and located within the region defined by one pixel driving circuit on the substrate 10 does not overlap with the orthogonal projection of the active region pattern T3a of the threshold compensation transistor T3 on the substrate 10, and the orthogonal projection of any one of the conductive patterns extending along the second direction Y in the second conductive layer 9 and located within the region defined by one pixel driving circuit on the substrate 10 does not overlap with the orthogonal projection of the active region pattern T3a of the threshold compensation transistor T3 on the substrate 10, this case only serves as an example. Those skilled in the art should know that only the first conductive layer 8 is designed as described above (i.e., the orthogonal projection of any one of the conductive patterns extending along the second direction Y in the first conductive layer 8 and located within the region defined by one pixel driving circuit on the substrate 10 does not overlap with the orthogonal projection of the active region pattern T3a of the threshold compensation transistor T3 on the substrate 10, while the second conductive layer 9 has a conductive pattern extending along the second direction Y and overlapping with the orthogonal projection of the active region pattern T3a of the threshold compensation transistor T3 on the substrate 10; this case does not have a corresponding figure), or only the second conductive layer 9 is designed as described above (i.e., the orthogonal projection of any one of the conductive patterns extending along the second direction Y in the second conductive layer 9 and located within the region defined by one pixel driving circuit on the substrate 10 does not overlap with the orthogonal projection of the active region pattern T3a of the threshold compensation transistor T3 on the substrate 10, while the first conductive layer 8 has a conductive pattern extending along the second direction Y and overlapping with the orthogonal projection of the active region pattern T3a of the threshold compensation transistor T3 on the substrate 10; this case does not have a corresponding figure), both of which can reduce the bending stress of the region where the active region pattern T3a of the threshold compensation transistor T3 is located to some extent, which is beneficial to improve the problem of abnormal light emission of the light emitting element E caused by the bending stress.

[0095] In some embodiments, the orthogonal projection of any one of the conductive patterns in the first conductive layer 8 and located within the region defined by at least one pixel driving circuit 1 (i.e., the aforementioned "bending stress reduction region") on the substrate 10 does not overlap with the orthogonal projection of the active region pattern T3a of the threshold compensation transistor T3 on the substrate 10; and / or, the orthogonal projection of any one of the conductive patterns in the second conductive layer 9 on the substrate 10 does not overlap with the orthogonal projection of the active region pattern T3a of the threshold compensation transistor T3 on the substrate 10.

[0096] Since the orthogonal projection of any one conductive pattern in the first conductive layer 8 and located in the area defined by the at least one pixel driving circuit on the base 10 does not overlap with the orthogonal projection of the active area pattern T3a of the threshold compensation transistor T3 on the base 10 (the first conductive layer 8 forms an avoidance in the area where the active area pattern T3a of the threshold compensation transistor T3 is located in the "bending stress reduction area"), when the flexible substrate is bent in any direction and the bending position is located in the "bending stress reduction area", the area where the active area pattern T3a of the threshold compensation transistor T3 is located in the "bending stress reduction area" in the first conductive layer 8 will not generate bending stress, so as to reduce the bending stress in the area where the active area pattern T3a of the threshold compensation transistor T3 is located to a certain extent, thereby effectively avoiding the functional film layers to generate micro-cracks in the area where the active area pattern T3a of the threshold compensation transistor T3 is located.

[0097] Similarly, since the orthogonal projection of any one conductive pattern in the second conductive layer 9 and located in the area defined by the at least one pixel driving circuit on the base 10 does not overlap with the orthogonal projection of the active area pattern T3a of the threshold compensation transistor T3 on the base 10 (the first conductive layer 8 forms an avoidance in the area where the active area pattern T3a of the threshold compensation transistor T3 is located in the "bending stress reduction area"), when the flexible substrate is bent in any direction, the area where the active area pattern T3a of the threshold compensation transistor T3 is located in the "bending stress reduction area" in the second conductive layer 9 will not generate bending stress, so as to reduce the bending stress in the area where the active area pattern T3a of the threshold compensation transistor T3 is located to a certain extent, thereby effectively avoiding the functional film layers to generate micro-cracks in the area where the active area pattern T3a of the threshold compensation transistor T3 is located.

[0098] In some embodiments, the pixel driving circuit 1 further comprises: a first light emitting control transistor T4; the control electrode of the first light emitting control transistor T4 is electrically connected with a corresponding light emitting control signal line EM, the first electrode of the first light emitting control transistor T4 is electrically connected with a working voltage transmission line DD, and the second electrode of the first light emitting control transistor T4 is electrically connected with a preset node W. The working voltage transmission line DD provides a working voltage VDD.

[0099] In some embodiments, the working voltage transmission line DD is located in the second conductive layer 9, and the working voltage transmission line DD extends along the second direction Y. That is, the working voltage transmission line DD is a conductive pattern in the second conductive layer 9.

[0100] In some embodiments, the orthogonal projection of the data line Data on the substrate 10 is located at a third side of the orthogonal projection of the active region pattern T2a of the corresponding data write transistor T2 on the substrate 10; the orthogonal projection of the working voltage transmission line DD on the substrate 10 is located at a fourth side of the orthogonal projection of the active region pattern T2a of the corresponding data write transistor T2 on the substrate 10; the third side and the fourth side are opposite sides in the first direction X.

[0101] Referring to Figure 2A In some embodiments, the display panel further comprises a light emitting element E, which comprises, in sequence from the direction away from the substrate 10, a first electrode 16, a light emitting layer, and a second electrode.

[0102] The pixel driving circuit 1 further comprises a first reset transistor T6, a second reset transistor T7, a second light emitting control transistor T5, and a storage capacitor.

[0103] The control electrode of the first reset transistor T6 is electrically connected with the corresponding reset control signal line Rst, the first electrode of the first reset transistor T6 is electrically connected with the reset voltage transmission line, and the second electrode of the first reset transistor T6 is electrically connected with the control electrode of the driving transistor T1. The reset voltage transmission line provides a reset voltage VINIT.

[0104] The control electrode of the second reset transistor T7 is electrically connected with the corresponding reset control signal line Rst, the first electrode of the second reset transistor T7 is electrically connected with the reset voltage transmission line, and the second electrode of the second reset transistor T7 is electrically connected with the first electrode 16.

[0105] The control electrode of the second light emitting control transistor T5 is electrically connected with the light emitting control signal line EM, the first electrode of the second light emitting control transistor T5 is connected with the second electrode of the driving transistor T1, and the second electrode of the second light emitting control transistor T5 is electrically connected with the first electrode 16.

[0106] The first end plate of the storage capacitor is connected with the working voltage transmission line DD, and the second end plate of the storage capacitor is electrically connected with the control electrode of the driving transistor T1.

[0107] In Figure 2A For example, each transistor in the pixel driving circuit 1 is a P-type transistor, Figure 2A The working process of the pixel driving circuit 1 can be divided into three working stages t1-t3, and the specific working process of each transistor in the pixel driving circuit 1 in each working stage can be performed by referring to the timing diagram shown in Figure 2B The specific process will not be described in detail here.

[0108] It should be noted that the pixel driving circuit 1 in the embodiments of the present disclosure adopts Figure 2AThe 7T1C case (7 transistors and 1 capacitor) shown in the figure is only exemplary and does not limit the technical solutions of the present disclosure. In the embodiments of the present disclosure, it is only required to ensure that the pixel driving circuit 1 at least includes the data writing transistor T2, the driving transistor T1, the first light emitting control transistor T4 and the threshold compensation transistor T3, and the pixel driving circuit 1 can also adopt a structure of other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure or a 9T2C structure, which is not limited in the embodiments of the present disclosure.

[0109] Referring to Figure 2A , FIG. 2, Figures 6 to 10 , the driving function layer 2 further includes, sequentially arranged along the direction away from the substrate 10, an active semiconductor layer 7, a first insulating layer 11, a third conductive layer 6, a second insulating layer 12, a fourth conductive layer 5 and a third insulating layer 13, and the first conductive layer 8 is located on the side of the third insulating layer 13 away from the substrate 10.

[0110] Referring to Figure 6 , the active semiconductor layer 7 includes active area patterns (also referred to as channel area) and source-drain doped area patterns of each transistor in the pixel driving circuit 1; in Figure 6 , the part of the active semiconductor layer 7 in the dashed rectangle frame indicated by Tna represents the active area pattern of the transistor Tn, Tns represents the source region of the transistor Tna, and Tnd represents the drain region of the transistor Tna, 1≤n≤7 and n is a positive integer; for example, the part of the active semiconductor layer 7 in the dashed rectangle frame indicated by T1a represents the active area pattern of the driving transistor T1, T1s represents the source region of the driving transistor T1, and T1d represents the drain region T1d of the driving transistor T1; the part of the active semiconductor layer 7 in the dashed rectangle frame indicated by T7a represents the active area pattern of the second reset transistor T7, T7s represents the source region of the second reset transistor T7, and T7d represents the drain region T7d of the second reset transistor T7. The active area patterns and source-drain doped areas of each transistor in the same pixel driving circuit 1 are integrally arranged.

[0111] It should be noted that the active semiconductor layer 7 can include an integrally formed low-temperature polysilicon layer, and the source region and the drain region of each transistor can be conductorized by doping to realize electrical connection of each structure. That is, the active area pattern and the source-drain doped area pattern of each transistor in each pixel driving circuit 1 are an overall pattern formed by p-silicon, and the active layer patterns of different transistors can be separated by a doping structure.

[0112] For example, the active semiconductor layer 7 can be made of amorphous silicon, polysilicon, oxide semiconductor material, etc. The above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities.

[0113] Referring to Figure 7 As shown in FIG. 1, the third conductive layer 6 includes: a control electrode of each transistor in the pixel driving circuit 1, a reset control signal line Rst, a gate line Gate, a second end plate C_2 of a storage capacitor C, and an emission control signal line EM.

[0114] The control electrode of the data writing transistor T2 can be a portion of the gate line Gate overlapping the active semiconductor layer 7; the control electrode of the first emission control transistor T4 can be a first portion of the emission control signal line EM overlapping the active semiconductor layer 7, the control electrode of the second emission control transistor T5 can be a second portion of the emission control signal line EM overlapping the active semiconductor layer 7; the control electrode of the first reset transistor T6 is a first portion of the reset control signal line Rst overlapping the active semiconductor layer 7, the control electrode of the second reset transistor T7 is a second portion of the reset control signal line Rst overlapping the active semiconductor layer 7; the threshold compensation transistor T3 can be a thin film transistor with a double-gate structure, the first control electrode of the threshold compensation transistor T3 can be a portion of the gate line Gate overlapping the active semiconductor layer 7, the second control electrode of the threshold compensation transistor T3 can be a portion of the protrusion P protruding from the gate line Gate overlapping the active semiconductor layer 7, and the control electrode of the driving transistor T1 can be the second end plate C_2 of the storage capacitor C. It should be noted that Figure 6 Each dashed rectangular frame in FIG. 1 also shows each portion of the first conductive layer 8 overlapping the active semiconductor layer 7.

[0115] In some embodiments, the control electrode of the data writing transistor T2, the control electrode of the threshold compensation transistor T3, the control electrode of the first reset transistor T6, and the control electrode of the second reset transistor T7 are all located on a first side of the control electrode of the driving transistor T1, the control electrode of the first emission control transistor T4 and the control electrode of the second emission control transistor T5 are all located on a second side of the control electrode of the driving transistor T1, the first side and the second side are opposite sides in the second direction Y; for example, the first side is the top side in FIG. 1, and the second side is the bottom side in FIG. 1. Figures 6 to 10 In some embodiments, the control electrode of the data writing transistor T2 and the control electrode of the first emission control transistor T4 are both located on a third side of the control electrode of the driving transistor T1, the first control electrode of the threshold compensation transistor T3, the control electrode of the second emission control transistor T5, and the control electrode of the second reset transistor T7 are all located on a fourth side of the control electrode of the driving transistor T1, the third side and the fourth side are opposite sides in the first direction X; for example, the third side is the left side in FIG. 1, and the second side is the right side in FIG. 1. Figures 6 to 10 In some embodiments, the control electrode of the data writing transistor T2 and the control electrode of the first emission control transistor T4 are both located on a third side of the control electrode of the driving transistor T1, the first control electrode of the threshold compensation transistor T3, the control electrode of the second emission control transistor T5, and the control electrode of the second reset transistor T7 are all located on a fourth side of the control electrode of the driving transistor T1, the third side and the fourth side are opposite sides in the first direction X; for example, the third side is the left side in FIG. 1, and the second side is the right side in FIG. 1. Figures 6 to 10 In some embodiments, the control electrode of the data writing transistor T2 and the control electrode of the first emission control transistor T4 are both located on a third side of the control electrode of the driving transistor T1, the first control electrode of the threshold compensation transistor T3, the control electrode of the second emission control transistor T5, and the control electrode of the second reset transistor T7 are all located on a fourth side of the control electrode of the driving transistor T1, the third side and the fourth side are opposite sides in the first direction X; for example, the third side is the left side in FIG. 1, and the second side is the right side in FIG. 1. Figures 6 to 10 In some embodiments, the control electrode of the data writing transistor T2 and the control electrode of the first emission control transistor T4 are both located on a third side of the control electrode of the driving transistor T1, the first control electrode of the threshold compensation transistor T3, the control electrode of the second emission control transistor T5, and the control electrode of the second reset transistor T7 are all located on a fourth side of the control electrode of the driving transistor T1, the third side and the fourth side are opposite sides in the first direction X; for example, the third side is the left side in FIG. 1, and the second side is the right side in FIG. 1.

[0116] Continuing to refer to Figure 7As shown, the reset control signal line Rst, the gate line Gate and the light-emitting control signal line EM all extend along the first direction X. Within the same pixel driving circuit 1, the reset control signal line Rst configured by the pixel driving circuit 1 is located at the first side of the gate line Gate configured by the pixel driving circuit 1, the gate line Gate configured by the pixel driving circuit 1 is located at the first side of the second terminal plate C_2 of the storage capacitor C, and the light-emitting control signal line EM configured by the pixel driving circuit 1 is located at the second side of the second terminal plate C_2 of the storage capacitor C. That is, within the same pixel driving circuit 1, the reset control signal line Rst configured by the pixel driving circuit 1, the gate line Gate configured by the pixel driving circuit 1, the second terminal plate C_2 of the storage capacitor C and the light-emitting control signal line EM configured by the pixel driving circuit 1 are arranged in order from top to bottom.

[0117] Referring to Figure 8 As shown, the fourth conductive layer 5 includes: a reset voltage transmission line Init and a first terminal plate C_1 of the storage capacitor C. The reset voltage transmission line Init extends along the first direction X; and the first terminal plate C_1 of the storage capacitor C and the second terminal plate C_2 of the storage capacitor C overlap to form a capacitor.

[0118] Referring to Figure 9 As shown, the first conductive layer 8 includes: a data line Data extending along the second direction Y; and for any one pixel driving circuit 1, the normal projection of the data line Data corresponding to the pixel driving circuit 1 (i.e. a data line Data directly contacting the first pole of the data writing transistor T2 in the pixel driving circuit 1 through the via hole) on the substrate 10 is located at the third side of the normal projection of the active area pattern T2a of the data writing transistor T2 in the pixel driving circuit 1 on the substrate 10; for example, as shown in the pixel driving circuit 1 in Figure 3 and Figure 4 the normal projection of the data line Data corresponding to the pixel driving circuit 1 on the substrate 10 is located at the left side of the normal projection of the active area pattern T2a of the data writing transistor T2 in the pixel driving circuit 1 on the substrate 10.

[0119] In addition, the third conductive layer 6 is also provided with a first connection part Q1, a second connection part Q2 and a third connection part 15, all extending along the second direction Y; wherein the first connection part Q1 is configured to connect the second pole of the threshold compensation transistor T3 and the control pole of the driving transistor T1, the second connection part Q2 is configured to connect the reset voltage transmission line Rst and the first pole of the second reset transistor T7, and the third connection part 15 is configured to connect the first electrode 16 of the light-emitting element E and the second pole of the second light-emitting control transistor T5.

[0120] Referring to Figure 10As shown, the second conductive layer 9 includes: a working voltage transmission line DD, which extends along the second direction Y; for any pixel driving circuit 1, the orthographic projection of the working voltage transmission line DD corresponding to the pixel driving circuit 1 (i.e., a working voltage transmission line DD that directly contacts the first electrode of the first light-emitting control transistor T4 in the pixel driving circuit 1 through a via) onto the substrate 10 is located on the fourth side of the orthographic projection of the active area pattern T4a of the first light-emitting control transistor T4 in the pixel driving circuit 1 onto the substrate 10; for example, attached Figure 3 and Figure 4 The orthographic projection of the working voltage transmission line DD corresponding to the pixel driving circuit 1 shown on the substrate 10 is located to the right of the orthographic projection of the active area pattern T2a of the first light-emitting control transistor T4 in the pixel driving circuit 1 on the substrate 10.

[0121] In some embodiments, the first electrode 16 in the light-emitting element E may also be located in the second conductive layer 9, that is, the second conductive layer 9 includes the first electrode 16. It should be noted that... Figure 10 The first electrode 16 is not shown in the diagram.

[0122] Figure 11 As described in this embodiment of the disclosure Figure 2A The diagram shows another layout of the pixel driving circuit. Figure 12 for Figure 11 A schematic diagram of a cross-section along the B-B' direction. Figure 13 for Figure 11 One layout of the first conductive layer in the middle. Figure 14 for Figure 11 A layout of the second conductive layer. For example... Figures 11 to 14 As shown, unlike the previous embodiment where the working voltage transmission line DD was located in the second conductive layer 9, in this embodiment, the working voltage transmission line DD is located in the first conductive layer 8. That is, in this embodiment, the working voltage transmission line DD and the data line Data are disposed on the same layer and both are located in the first conductive layer 8.

[0123] Figure 11 The layout structure of the active semiconductor layer 7, the third conductive layer 6, and the fourth conductive layer 5 in the pixel driving circuit 1 shown can be found in [reference needed]. Figures 6 to 8 As shown in the image.

[0124] See Figure 11 and Figure 12As shown, in some embodiments, the orthogonal projection of the data line Data on the substrate 10 is located at the third side of the orthogonal projection of the active area pattern T2a of the corresponding data write transistor T2 on the substrate 10; the orthogonal projection of the working voltage transmission line DD on the substrate 10 is located at the fourth side of the orthogonal projection of the active area pattern T2a of the corresponding data write transistor T2 on the substrate 10; the third side and the fourth side are opposite sides in the first direction X. For example, the third side and the fourth side are respectively the left side and the right side in FIG. 1. Figure 11

[0125] In some embodiments, the plurality of conductive patterns in the second conductive layer 9 comprises: a plurality of first working voltage connection lines 18 and a plurality of second working voltage connection lines 19, the first working voltage connection lines 18 extend along the second direction Y, and the second working voltage connection lines 19 extend along a third direction, which is intersected with the second direction Y.

[0126] In some embodiments, the third direction is the same as the first direction X. Referring to FIG. 1, the third direction is the same as the first direction X. Figure 11 As shown, in some embodiments, the second working voltage connection line 19 extends along the first direction X, and the orthogonal projection of the second working voltage connection line 19 on the substrate 10 overlaps with the orthogonal projection of the gate line Gate on the substrate 10. Of course, the third direction in the embodiments of the present disclosure can also be intersected with the first direction X and the second direction Y, and no corresponding figures are given in this case.

[0127] Each second working voltage connection line 19 is electrically connected with at least two first working voltage transmission lines DD, and any first working voltage connection line 18 is electrically connected with other first working voltage connection lines 18; the working voltage transmission line DD is electrically connected with the first working voltage connection line 18.

[0128] In the embodiments of the present disclosure, the plurality of first working voltage connection lines 18 and the plurality of second working voltage connection lines 19 form a mesh structure and are parallel to each working voltage transmission line DD, so that the working voltage loaded on each working voltage transmission line DD is consistent, and the equivalent resistance of each working voltage transmission line DD is effectively reduced, so as to ensure that the working voltage provided by each working voltage transmission line DD to the corresponding pixel driving circuit 1 is consistent.

[0129] ​It should be noted that even if the second working voltage connection line 19 has an overlap with the active region pattern T2a of the data writing transistor T2 on the substrate 10 in some embodiments, since the line width of the second working voltage connection line 19 is generally narrow and the extension direction of the second working voltage connection line 19 is not the second direction Y, the part of the second working voltage connection line 19 located in the region of the active region pattern T2a of the data writing transistor T2 basically does not produce bending or produces a very small degree of bending, that is, does not produce bending stress or produces a very small degree of bending stress when the display panel is bent along the second direction Y; therefore, the bending stress at the region of the active region pattern T2a of the data writing transistor T2 is not substantially affected.

[0130] In some embodiments, the first working voltage connection line 18 corresponds to the working voltage transmission line DD one by one; the normal projection of the data line Data on the substrate 10 is located on the third side of the normal projection of the active region pattern T2a of the corresponding data writing transistor T2 on the substrate 10; the normal projection of the working voltage transmission line DD on the substrate 10 is located on the fourth side of the normal projection of the active region pattern T2a of the corresponding data writing transistor T2 on the substrate 10; and the normal projection of the first working voltage connection line 18 on the substrate 10 is located on the fourth side of the normal projection of the active region pattern T2a of the corresponding data writing transistor T2 on the substrate 10.

[0131] In some embodiments, the first working voltage connection line 18 and the working voltage transmission line DD corresponding thereto have an overlap on the substrate 10. Further optionally, the first working voltage connection line 18 and the working voltage transmission line DD corresponding thereto completely overlap on the substrate 10.

[0132] Based on the same inventive concept, the display device provided by the embodiments of the present disclosure also includes the display panel in the foregoing embodiments; the description of the display panel can refer to the foregoing embodiments, which will not be repeated here.

[0133] It should be noted that the display device in the embodiments of the present disclosure can be a flexible wearable device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function. Other essential components of the display device should be understood by those skilled in the art, and will not be repeated here, nor should it be considered as a limitation on the present disclosure.

[0134] Further, the display device can also include various types of display devices, such as a liquid crystal display device (the aforementioned display panel is used as a light source for a liquid crystal cell), an organic electroluminescent display device (for example, an OLED display device, a QLED display device), a mini LED display device, without limitation.

[0135] It can be understood that the above embodiments are only exemplary embodiments adopted for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present application, and these modifications and improvements are also considered to be within the scope of protection of the present application.

Claims

1. A display panel, characterized by, The application relates to a display panel, comprising: a substrate; a driving functional layer located on one side of the substrate, comprising a plurality of gate lines, a plurality of data lines and a plurality of pixel driving circuits, the gate lines extend along a first direction, the data lines extend along a second direction, the first direction intersects the second direction, the pixel driving circuit comprises a data writing transistor, the control electrode of the data writing transistor is electrically connected with a corresponding gate line, the first electrode of the data writing transistor is electrically connected with a corresponding data line, the data writing transistor is electrically connected with a preset node in the pixel driving circuit, the driving functional layer comprises a first conductive layer, the first conductive layer comprises a plurality of conductive patterns, and the data lines are located on the first conductive layer; a planarization layer located on the side of the driving functional layer away from the substrate; a second conductive layer located on the side of the planarization layer away from the driving functional layer, the second conductive layer comprises a plurality of conductive patterns; wherein the orthogonal projection of any one conductive pattern extending along the second direction in the first conductive layer and located in the region defined by at least one pixel driving circuit on the substrate does not overlap with the orthogonal projection of the active area pattern of the data writing transistor on the substrate; and / or the orthogonal projection of any one conductive pattern extending along the second direction in the second conductive layer and located in the region defined by at least one pixel driving circuit on the substrate does not overlap with the orthogonal projection of the active area pattern of the data writing transistor on the substrate.

2. The display panel of claim 1, wherein, The orthogonal projection of any one conductive pattern in the first conductive layer and located in the region defined by at least one pixel driving circuit on the substrate does not overlap with the orthogonal projection of the active area pattern of the data writing transistor on the substrate; and / or the orthogonal projection of any one conductive pattern in the second conductive layer and located in the region defined by at least one pixel driving circuit on the substrate does not overlap with the orthogonal projection of the active area pattern of the data writing transistor on the substrate.

3. The display panel of claim 1, wherein, The pixel driving circuit further comprises a driving transistor and a threshold compensation transistor; the control electrode of the driving transistor is electrically connected with the first electrode of the threshold compensation transistor, the first electrode of the driving transistor is electrically connected with the preset node, the second electrode of the driving transistor is electrically connected with the second electrode of the threshold compensation transistor, and the control electrode of the threshold compensation transistor is electrically connected with a corresponding gate line; the orthogonal projection of any one conductive pattern extending along the second direction in the first conductive layer and located in the region defined by at least one pixel driving circuit on the substrate does not overlap with the orthogonal projection of the active area pattern of the threshold compensation transistor on the substrate; and / or the orthogonal projection of any one conductive pattern extending along the second direction in the second conductive layer and located in the region defined by at least one pixel driving circuit on the substrate does not overlap with the orthogonal projection of the active area pattern of the threshold compensation transistor on the substrate.

4. The display panel of claim 3, wherein, Any one of the conductive patterns in the first conductive layer and located in the region defined by at least one pixel driving circuit has no overlap with the positive projection on the substrate of the active region pattern of the threshold compensation transistor; And / or, any one of the conductive patterns in the second conductive layer and located in the region defined by at least one pixel driving circuit has no overlap with the positive projection on the substrate of the active region pattern of the threshold compensation transistor.

5. The display panel of claim 3, wherein, The pixel driving circuit further comprises a first light-emitting control transistor; The control electrode of the first light-emitting control transistor is electrically connected with a corresponding light-emitting control signal line, the first electrode of the first light-emitting control transistor is electrically connected with a working voltage transmission line, and the second electrode of the first light-emitting control transistor is electrically connected with the preset node.

6. The display panel of claim 5, wherein, The working voltage transmission line is located in the second conductive layer, and the working voltage transmission line extends along the second direction.

7. The display panel of claim 6, wherein, The positive projection on the substrate of the data line is located on the third side of the positive projection on the substrate of the active region pattern of the corresponding data write transistor; The positive projection on the substrate of the working voltage transmission line is located on the fourth side of the positive projection on the substrate of the active region pattern of the corresponding data write transistor; The third side and the fourth side are opposite sides in the first direction.

8. The display panel of claim 5, wherein, The working voltage transmission line is located in the first conductive layer, and the working voltage transmission line extends along the second direction.

9. The display panel of claim 8, wherein, The positive projection on the substrate of the data line is located on the third side of the positive projection on the substrate of the active region pattern of the corresponding data write transistor; The positive projection on the substrate of the working voltage transmission line is located on the fourth side of the positive projection on the substrate of the active region pattern of the corresponding data write transistor; The third side and the fourth side are opposite sides in the first direction.

10. The display panel of claim 8, wherein, The plurality of conductive patterns in the second conductive layer comprises a plurality of first working voltage connection lines and a plurality of second working voltage connection lines, the first working voltage connection lines extend along the second direction, and the second working voltage connection lines extend along a third direction intersecting the second direction; Each second working voltage connection line is electrically connected with at least two working voltage transmission lines, and any first working voltage connection line is electrically connected with other first working voltage connection lines. The working voltage transmission line is electrically connected with the first working voltage connection line.

11. The display panel of claim 10, wherein, The first working voltage connection line corresponds to the working voltage transmission line one by one. The positive projection on the substrate of the data line is located on the third side of the positive projection on the substrate of the active region pattern of the corresponding data write transistor; The positive projection on the substrate of the working voltage transmission line is located on the fourth side of the positive projection on the substrate of the active region pattern of the corresponding data write transistor; The positive projection on the substrate of the first working voltage connection line is located on the fourth side of the positive projection on the substrate of the active region pattern of the corresponding data write transistor; The third side and the fourth side are opposite sides in the first direction.

12. The display panel of any one of claims 5 to 11, wherein, The display panel further comprises a light-emitting element, the light-emitting element comprising a first electrode, a light-emitting layer and a second electrode arranged in sequence away from the substrate; The pixel driving circuit further comprises a first reset transistor, a second reset transistor, a second light-emitting control transistor and a storage capacitor; The control electrode of the first reset transistor is electrically connected with a corresponding reset control signal line, the first electrode of the first reset transistor is electrically connected with a reset voltage transmission line, and the second electrode of the first reset transistor is electrically connected with the control electrode of the driving transistor; The control electrode of the second reset transistor is electrically connected with a corresponding reset control signal line, the first electrode of the second reset transistor is electrically connected with a reset voltage transmission line, and the second electrode of the second reset transistor is electrically connected with the first electrode; The control electrode of the second light-emitting control transistor is electrically connected with the light-emitting control signal line, the first electrode of the second light-emitting control transistor is connected with the second electrode of the driving transistor, and the second electrode of the second light-emitting control transistor is electrically connected with the first electrode; The first end plate of the storage capacitor is connected with the working voltage transmission line, and the second end plate of the storage capacitor is electrically connected with the control electrode of the driving transistor.

13. The display panel of claim 12, wherein, The driving functional layer further comprises an active semiconductor layer, a first insulating layer, a third conductive layer, a second insulating layer, a fourth conductive layer and a third insulating layer arranged in sequence away from the substrate, and the first conductive layer is located on the side of the third insulating layer away from the substrate; The active semiconductor layer comprises an active region pattern and a source-drain doped region of each transistor in the pixel driving circuit; The third conductive layer comprises the control electrode of each transistor in the pixel driving circuit, the reset control signal line, the gate line, the second end plate of the storage capacitor and the light-emitting control signal line; The fourth conductive layer comprises the reset voltage transmission line and the first end plate of the storage capacitor.

14. The display panel of claim 13, wherein, The control electrode of the data writing transistor, the control electrode of the threshold value compensation transistor, the control electrode of the first reset transistor and the control electrode of the second reset transistor are all located on the first side of the control electrode of the driving transistor, the control electrode of the first light-emitting control transistor and the control electrode of the second light-emitting control transistor are both located on the second side of the control electrode of the driving transistor, and the first side and the second side are opposite sides in the second direction; The control electrode of the data writing transistor and the control electrode of the first light-emitting control transistor are both located on the third side of the control electrode of the driving transistor, the control electrode of the threshold value compensation transistor, the control electrode of the second light-emitting control transistor and the control electrode of the second reset transistor are all located on the fourth side of the control electrode of the driving transistor, and the third side and the fourth side are opposite sides in the first direction.

15. A display device comprising: The display panel comprises: The display panel according to any one of claims 1 to 14.

Images