Semiconductor device and method of manufacturing the same

Abstract

Embodiments provide a semiconductor device capable of improving characteristics and a method for manufacturing the same. According to the embodiment, the semiconductor device includes a first conductive component, a semiconductor component, a second conductive component, a third conductive component, and a first insulating component. The semiconductor component includes a first semiconductor region disposed on the first conductive component, a second semiconductor region disposed on a portion of the first semiconductor region, and a third semiconductor region disposed on the second semiconductor region. The second semiconductor region includes a first surface opposing a portion of the first semiconductor region. The first surface includes a first contact portion in contact with the first insulating component. The lower end of the first surface is lower than the first contact portion. The third semiconductor region includes a second surface opposing the second semiconductor region. The second surface includes a second contact portion in contact with the first insulating component. The lower end of the second surface is lower than the second contact portion.

Description

[0001] Related Application

[0002] This application claims priority to Japanese Patent Application No. 2020-154752 (Filing date: September 15, 2020). This application incorporates by reference the entire contents of the base application. TECHNICAL FIELD

[0003] Embodiments of the present application relate to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0004] In a semiconductor device, it is desirable to improve characteristics. SUMMARY

[0005] Embodiments of the present application provide a semiconductor device and a manufacturing method thereof capable of improving characteristics.

[0006] According to an embodiment of the present application, a semiconductor device includes a first conductive member, a semiconductor member, a second conductive member, a third conductive member, and a first insulating member. The semiconductor member includes a first semiconductor region of a first conductivity type provided over the first conductive member, a second semiconductor region of a second conductivity type provided over a part of the first semiconductor region, and a third semiconductor region of the first conductivity type provided over the second semiconductor region. An impurity concentration of the first conductivity type in the third semiconductor region is higher than an impurity concentration of the first conductivity type in the first semiconductor region. The second conductive member includes a first conductive portion electrically connected to the second semiconductor region and the third semiconductor region. The third conductive member is provided over the other part of the first semiconductor region. A second direction from the second semiconductor region to the third conductive member intersects a first direction from the first conductive member to the first semiconductor region. At least a part of the first insulating member is located between the semiconductor member and the third conductive member. The at least a part of the first insulating member electrically insulates between the semiconductor member and the third conductive member. The second semiconductor region includes a first face opposed to the part of the first semiconductor region. The first face includes a first contact portion in contact with the first insulating member. A first distance along the first direction between the first conductive member and a lower end portion of the first face is shorter than a second distance along the first direction between the first conductive member and the first contact portion. The third semiconductor region includes a second face opposed to the second semiconductor region. The second face includes a second contact portion in contact with the first insulating member. A third distance along the first direction between the first conductive member and a lower end portion of the second face is shorter than a fourth distance along the first direction between the first conductive member and the second contact portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.

[0008] Figure 2 This is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.

[0009] Figure 3 is a schematic cross-sectional view illustrating a semiconductor device according to a reference example.

[0010] Figure 4 (a) to (d) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0011] Figure 5 This is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.

[0012] Figure 6 This is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.

[0013] Figure 7 This is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.

[0014] Figure 8 This is a schematic cross-sectional view illustrating a portion of a method for manufacturing a semiconductor device according to an embodiment.

[0015] Figure 9 This is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.

[0016] Figures 10-14 This is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.

[0017] Figure 15 This is a flowchart illustrating a method for manufacturing a semiconductor device according to the second embodiment. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0019] In addition, the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as in reality. In addition, even when showing the same part, there are cases where the sizes and ratios shown in the drawings are different.

[0020] In the present specification and drawings, the same elements as those in the drawings that have already appeared are denoted by the same reference numerals, and detailed descriptions thereof are appropriately omitted.

[0021] (First Embodiment)

[0022] Figure 1 and Figure 2 is a schematic cross-sectional view illustrating a semiconductor device of the first embodiment.

[0023] As Figure 1 shown, the semiconductor device 110 of the embodiment includes a first conductive member 51, a second conductive member 52, a third conductive member 53, a semiconductor member 10, and a first insulating member 41.

[0024] The semiconductor member 10 includes a first semiconductor region 11, a second semiconductor region 12, and a third semiconductor region 13. As described later, the semiconductor member 10 can also include a fourth semiconductor region 14 and a fifth semiconductor region 15.

[0025] The first semiconductor region 11 is provided on the first conductive member 51. The first semiconductor region 11 is of a first conductive type. The second semiconductor region 12 is provided on a part 11a of the first semiconductor region 11. The second semiconductor region 12 is of a second conductive type. The third semiconductor region 13 is provided on the second semiconductor region 12. The third semiconductor region 13 is of the first conductive type.

[0026] For example, the first conductive type is n-type, and the second conductive type is p-type. Alternatively, the first conductive type can be p-type, and the second conductive type can be n-type. Hereinafter, it is assumed that the first conductive type is n-type, and the second conductive type is p-type.

[0027] The impurity concentration of the first conductive type in the third semiconductor region 13 is higher than the impurity concentration of the first conductive type in the first semiconductor region 11. The first semiconductor region 11 is, for example, an n-layer (including an n － layer). The third semiconductor region 13 is, for example, an n + layer.

[0028] The second conductive member 52 includes a first conductive portion 52a. The first conductive portion 52a is electrically connected to the second semiconductor region 12 and the third semiconductor region 13. The third conductive member 53 is provided on the other part 11b of the first semiconductor region 11.

[0029] A direction from the first conductive member 51 toward the first semiconductor region 10 is assumed to be a first direction. A direction from the part 11a of the first semiconductor region 11 toward the third semiconductor region 13 is along the first direction. The first direction is assumed to be a Z-axis direction. One direction perpendicular to the Z-axis direction is assumed to be an X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is assumed to be a Y-axis direction.

[0030] A second direction from the second semiconductor region 12 toward the third conductive member 53 is perpendicular to the first direction. The second direction is, for example, the X-axis direction.

[0031] At least a portion of the first insulating member 41 is located between the semiconductor component 10 and the third conductive component 53. This at least a portion of the first insulating member 41 electrically insulates the semiconductor component 10 from the third conductive component 53. For example, the first insulating member 41 includes a first insulating region 41 a and a second insulating region 41 b. The first insulating region 41 a is located between the second semiconductor region 12 and the third conductive component 53 in the second direction (the X-axis direction). The first insulating region 41 b is located between the remaining portion 11 b of the first semiconductor region 11 and the third conductive component 53 in the first direction (the Z-axis direction).

[0032] For example, the current flowing between the first conductive member 51 and the second conductive member 52 can be controlled by the potential of the third conductive member 53. The first conductive member 51 is, for example, a drain electrode. The second conductive member 52 is, for example, a source electrode. The third conductive member 53 is, for example, a gate electrode. The first insulating region 41a of the first insulating member 41 functions as, for example, a gate insulating film. The semiconductor device 110 is, for example, a transistor.

[0033] like Figure 1 As shown, the semiconductor device 110 may also include a fourth semiconductor region 14. The fourth semiconductor region 14 is of the second conductivity type (e.g., p-type). At least a portion of the fourth semiconductor region 14 is located between a portion of the second semiconductor region 12 and the first conductive portion 52a in the first direction (Z-axis direction). The second conductivity type impurity concentration in the fourth semiconductor region 14 is higher than the second conductivity type impurity concentration in the second semiconductor region 12. The second semiconductor region 12 is, for example, a p-layer. The fourth semiconductor region 14 is, for example, a p-type layer. + By providing the fourth semiconductor region 14, for example, the potential of the second semiconductor region 12 is stabilized.

[0034] like Figure 1 As shown, the semiconductor device 110 may further include a fifth semiconductor region 15 of the first conductivity type. The fifth semiconductor region 15 is located between the first conductive component 51 and the first semiconductor region 11 in the first direction (Z-axis direction). The first conductivity type impurity concentration in the fifth semiconductor region 15 is higher than the first conductivity type impurity concentration in the first semiconductor region 11. The first semiconductor region 11 is, for example, an n-layer. The fifth semiconductor region 15 is, for example, an n-layer. + By providing the fifth semiconductor region 15, for example, a lower contact resistance can be obtained in the first conductive component 51. For example, a lower on-resistance can be obtained.

[0035] As explained, the impurity concentration of the first conductive type in the third semiconductor region 13 is higher than the impurity concentration of the first conductive type in the first semiconductor region 11. A lower contact resistance can be obtained in the second conductive member 52. A lower on-resistance can be obtained, for example.

[0036] The second semiconductor region 12 is a base layer, for example. The third semiconductor region 13 is a source layer, for example. The above-described portion 11a of the first semiconductor region 11 is a drift layer.

[0037] As Figure 1 indicated, the second semiconductor region 12 includes a first face F1. The first face F1 opposes the above-described portion 11a of the first semiconductor region 11. The first face F1 includes a first contact portion FC1 that interfaces with the first insulating member 41. A lower end portion FL1 of the first face F1 is lower than the first contact portion FC1.

[0038] The third semiconductor region 13 includes a second face F2. The second face F2 opposes the second semiconductor region 12. The second face F2 includes a second contact portion FC2 that interfaces with the first insulating member 41. A lower end portion FL2 of the second face F2 is lower than the second contact portion FC2.

[0039] As Figure 2 indicated, a distance between the first conductive member 51 and the lower end portion FL1 of the first face F1 along the first direction (Z-axis direction) is set as a first distance d1. A distance between the first conductive member 51 and the first contact portion FC1 along the first direction is set as a second distance d2. In the embodiment, the first distance d1 is shorter than the second distance d2.

[0040] As Figure 2 indicated, a distance between the first conductive member 51 and the lower end portion FL2 of the second face F2 along the first direction (Z-axis direction) is set as a third distance d3. A distance between the first conductive member 51 and the second contact portion FC2 along the first direction is set as a fourth distance d4. In the embodiment, the third distance d3 is shorter than the fourth distance d4.

[0041] The first face F1 is convex, for example. The second face F2 is convex. In one example, the second face F2 is curved convex along the first face F1.

[0042] With this configuration, a semiconductor device that can improve characteristics can be provided.

[0043] Figure 3 is a schematic cross-sectional view of a semiconductor device of a reference example.

[0044] As Figure 3As shown in the semiconductor device 119 of the reference example, the first surface F1 is concave, and the second surface F2 is concave. In this semiconductor device 119, for example, the end portion of the second semiconductor region 12 in the X-axis direction (the portion on the first insulating member 41 side) is extended downward more than the central portion in the X-axis direction. As a result, the parasitic resistance is likely to be high. Thus, the on-resistance is likely to be high. The channel length is likely to be long, and the on-resistance Ron-A has a tendency to be high. Also, in the semiconductor device 119, the lower portion of the second semiconductor region 12 (the portion between the first semiconductor region 11 and the fourth semiconductor region 14) is thin. Thus, breakdown is likely to occur.

[0045] In contrast, in the embodiment, the second surface F2 is convex. Thus, the parasitic resistance can be suppressed, and a lower on-resistance is likely to be obtained. The channel length can be shortened, and a lower on-resistance Ron-A is likely to be obtained. In the embodiment, the first surface F1 is convex, and thus, for example, the lower portion of the second semiconductor region 12 (the portion between the first semiconductor region 11 and the fourth semiconductor region 14) is likely to be maintained thick. Thus, breakdown can be suppressed.

[0046] As shown in the semiconductor device 119 of the reference example, the first surface F1 is concave, and the second surface F2 is concave. In this semiconductor device 119, for example, the end portion of the second semiconductor region 12 in the X-axis direction (the portion on the first insulating member 41 side) is extended downward more than the central portion in the X-axis direction. As a result, the parasitic resistance is likely to be high. Thus, the on-resistance is likely to be high. The channel length is likely to be long, and the on-resistance Ron-A has a tendency to be high. Also, in the semiconductor device 119, the lower portion of the second semiconductor region 12 (the portion between the first semiconductor region 11 and the fourth semiconductor region 14) is thin. Thus, breakdown is likely to occur. Figure 1 As shown in the semiconductor device 119 of the reference example, the first surface F1 is concave, and the second surface F2 is concave. In this semiconductor device 119, for example, the end portion of the second semiconductor region 12 in the X-axis direction (the portion on the first insulating member 41 side) is extended downward more than the central portion in the X-axis direction. As a result, the parasitic resistance is likely to be high. Thus, the on-resistance is likely to be high. The channel length is likely to be long, and the on-resistance Ron-A has a tendency to be high. Also, in the semiconductor device 119, the lower portion of the second semiconductor region 12 (the portion between the first semiconductor region 11 and the fourth semiconductor region 14) is thin. Thus, breakdown is likely to occur. Figure 2 As shown in the semiconductor device 119 of the reference example, the first surface F1 is concave, and the second surface F2 is concave. In this semiconductor device 119, for example, the end portion of the second semiconductor region 12 in the X-axis direction (the portion on the first insulating member 41 side) is extended downward more than the central portion in the X-axis direction. As a result, the parasitic resistance is likely to be high. Thus, the on-resistance is likely to be high. The channel length is likely to be long, and the on-resistance Ron-A has a tendency to be high. Also, in the semiconductor device 119, the lower portion of the second semiconductor region 12 (the portion between the first semiconductor region 11 and the fourth semiconductor region 14) is thin. Thus, breakdown is likely to occur.

[0047] As shown in the semiconductor device 119 of the reference example, the first surface F1 is concave, and the second surface F2 is concave. In this semiconductor device 119, for example, the end portion of the second semiconductor region 12 in the X-axis direction (the portion on the first insulating member 41 side) is extended downward more than the central portion in the X-axis direction. As a result, the parasitic resistance is likely to be high. Thus, the on-resistance is likely to be high. The channel length is likely to be long, and the on-resistance Ron-A has a tendency to be high. Also, in the semiconductor device 119, the lower portion of the second semiconductor region 12 (the portion between the first semiconductor region 11 and the fourth semiconductor region 14) is thin. Thus, breakdown is likely to occur. Figure 1As shown, the semiconductor device 110 may further include a second insulating member 42. In this example, the second conductive member 52 further includes a second conductive portion 52b. The first insulating member 41 includes an upper insulating region 41c. The upper insulating region 41c is provided above the third semiconductor region 13. The second conductive portion 52b is located above the upper insulating region 41c. A portion of the second insulating member 42 is located between the upper insulating region 41c and a portion of the second conductive portion 52b in the first direction (Z-axis direction).

[0048] The boundary between the first insulating part 41 and the second insulating part 42 may be clear or unclear.

[0049] like Figure 1 As shown, the semiconductor device 110 may further include a fourth conductive component 54. At least a portion of the fourth conductive component 54 is located between the other portion 11b of the first semiconductor region 11 and the third conductive component 53. The position of at least a portion of the fourth conductive component 54 in the first direction (Z-axis direction) is located between the position of the other portion 11b of the first semiconductor region 11 in the first direction and the position of the third conductive component 53 in the first direction. A portion 41f of the first insulating component 41 is located between the semiconductor component 10 and the fourth conductive component 54. The portion 41f of the first insulating component 41 electrically insulates the semiconductor component 10 from the fourth conductive component 54. The boundary between the portion 41f of the first insulating component 41 and the first insulating region 41a may be clear or unclear. The boundary between the portion 41f of the first insulating component 41 and the second insulating region 41b may be clear or unclear.

[0050] In one example, the fourth conductive member 54 is electrically connected to one of the second conductive member 52 and the third conductive member 53. Alternatively, the fourth conductive member 54 can be electrically connected to one of the second conductive member 52 and the third conductive member 53.

[0051] In this example, the fourth conductive member 54 is electrically connected to the second conductive member 52 . For example, the semiconductor device 110 may further include a connecting member 54L. The connecting member 54L electrically connects the fourth conductive member 54 to one of the second conductive member 52 and the third conductive member 53 .

[0052] like Figure 1As shown, the semiconductor device 110 may also include a terminal 54T electrically connected to the fourth conductive member 54. The fourth conductive member 54 and the terminal 54T are electrically connected, for example, by a connecting member 54C. The semiconductor device 110 may also include a terminal 52T electrically connected to the second conductive member 52. The second conductive member 52 and the terminal 52T are connected, for example, by a connecting member 52C. The terminal 54T and the terminal 52T may also be electrically connected by a connecting member 54L. When the terminal 54T is provided, the connecting member 54L may not be included in the semiconductor device 110.

[0053] The fourth conductive member 54 functions as a field plate, for example. Providing the fourth conductive member 54 can suppress electric field concentration, thereby achieving, for example, a higher withstand voltage.

[0054] An example of a method for manufacturing the semiconductor device 110 will be described below.

[0055] Figure 4 (a)~ Figure 4 (d) is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0056] like Figure 4 As shown in (a), a structure SB1 is prepared. The structure SB1 includes a semiconductor component 10, a first insulating component 41, and two conductive components (for example, a third conductive component 53). The semiconductor component 10 includes a first semiconductor region 11F of a first conductivity type. The first insulating component 41 includes an upper insulating region 41c. The upper insulating region 41c is provided on a portion 11d of the first semiconductor region 11F. The direction from the portion 11d of the first semiconductor region 11F to the upper insulating region 41c is defined as a first direction. The first direction is, for example, the Z-axis direction. The direction from one of the two conductive components (the third conductive component 53) to the other of the two conductive components (the third conductive component 53) is defined as a second direction. The first direction intersects with the second direction. The second direction is, for example, the X-axis direction. The portion 11d of the first semiconductor region 11F is located between the two conductive components (the third conductive component 53) in the second direction (the X-axis direction).

[0057] like Figure 4As shown in (b), the upper insulating region 41c of the first insulating component 41 includes a first insulating portion 41p and a second insulating portion 41q. The first insulating portion 41p is located above the center portion of the aforementioned portion 11d of the first semiconductor region 11F in the second direction (X-axis direction). The second insulating portion 41q is located above an end portion 11de of the aforementioned portion 11d of the first semiconductor region 11F in the second direction (X-axis direction). The end portion 11de is the end portion in the X-axis direction of the portion (portion 11d) of the first semiconductor region 11F located between two conductive components (e.g., the third conductive component 53). The end portion 11de includes a portion in contact with the first insulating component 41.

[0058] like Figure 4 As shown in (b), the thickness of the first insulating portion 41p along the first direction (Z-axis direction) is set to a first thickness t1. The thickness of the second insulating portion 41q along the first direction is set to a second thickness t2. The first thickness t1 is thinner than the second thickness t2.

[0059] This construction can be used, for example, Figure 4 In (a), a mask having an opening is formed on the first insulating member 41, and a portion of the first insulating member 41 is removed through the opening.

[0060] like Figure 4 As shown in (c), second conductivity type impurities 12i are introduced into the portion 11d of the first semiconductor region 11 via the upper insulating region 41c to form a second conductivity type second semiconductor region 12F. The impurities 12i are introduced by implantation, for example.

[0061] like Figure 4 As shown in (d), first conductivity type impurities 13i are introduced into a portion of the second semiconductor region 12F via the upper insulating region 41c to form a first conductivity type third semiconductor region 13. The impurities 13i are introduced by, for example, implantation. The region not introduced with the impurities 13i becomes the second semiconductor region 12.

[0062] In the above-described manufacturing method, the upper insulating region 41c includes a first insulating portion 41p and a second insulating portion 41q of different thicknesses. For example, the depth of impurities introduced into the region corresponding to the thicker second insulating portion 41q is shallower than the depth of impurities introduced into the region corresponding to the thinner first insulating portion 41p. This makes it easy to stably obtain the convex first surface F1 and second surface F2 (see Figure 4 (d)).

[0063] Thereafter, by forming the second conductive member 52 and the first conductive member 51 , the semiconductor device 110 can be obtained.

[0064] The semiconductor device 119 of the above-described reference example (refer to Figure 3 ) is formed, for example, by introducing impurities into the structure SB1 (refer to Figure 4 (a)) that becomes the first semiconductor region 11, the second semiconductor region 12, and the third semiconductor region 13. In the reference example, the impurities are introduced in the configuration of (a) in which the thickness of the first insulating member 41 is uniform. Figure 4 In this case, for example, depending on the conditions of ion implantation and / or heat treatment conditions, and the like, the degree of diffusion of the introduced impurities easily varies according to the height (depth) of the third conductive member 53 (for example, the gate). Thus, the concave first face F1 and the second face F2 illustrated are easily generated. In this case, the channel length varies depending on the height (depth) of the third conductive member 53 (for example, the gate), and the threshold voltage easily fluctuates. Figure 3

[0065] On the contrary, in the example of the manufacturing method of the embodiment, the impurities are introduced, for example, via the first insulating member 41 including the first insulating portion 41p and the second insulating portion 41q that differ in thickness from each other, so that the concave first face F1 and the second face F2 can be more stably suppressed. For example, the convex first face F1 and the second face F2 are easily obtained. Alternatively, the flat first face F1 and the second face F2 are easily obtained. Thus, for example, a stable threshold voltage is easily obtained. For example, the threshold voltage can be suppressed from varying depending on the height (depth) of the third conductive member 53 (for example, the gate).

[0066] The above-described manufacturing method is an example, and in the embodiment, the structure of the semiconductor device 110 can also be obtained by other methods. For example, the impurities can be introduced by implantation with a particle beam having a certain degree of diffusion via the upper insulating region 41c of the shape illustrated in (a), so that the concave first face F1 and the second face F2 are formed. As described later, a protruding portion can also be provided at the end portion in the X-axis direction of the upper surface of the upper insulating region 41c. Figure 4

[0067] Figure 5 is a schematic cross-sectional view illustrating the semiconductor device of the first embodiment.

[0068] As shown in (a) of Figure 5 , in the semiconductor device 110a of the embodiment, the upper insulating region 41c of the first insulating member 41 includes the first insulating portion 41p and the second insulating portion 41q that differ in thickness from each other. The configuration of the semiconductor device 110a other than this can be the same as that of the semiconductor device 110.

[0069] ​​In the semiconductor device 110a, the upper insulating region 41c of the first insulating member 41 is provided over the third semiconductor region 13, for example. The upper insulating region 41c includes the first insulating portion 41p and the second insulating portion 41q. The first insulating portion 41p is positioned between the first conductive portion 52a and the second insulating portion 41q. The first thickness t1 of the first insulating portion 41p in the first direction (Z-axis direction) is thinner than the second thickness t2 of the second insulating portion 41q in the first direction.

[0070] By introducing impurities through the first insulating member 41 (the upper insulating region 41c) including the first insulating portion 41p and the second insulating portion 41q, the shape of the region into which the impurities are introduced can be more stably controlled. As described later, a protruding portion can be provided at the end portion of the upper surface of the upper insulating region 41c in the X-axis direction.

[0071] Figure 6 is a schematic cross-sectional view illustrating the semiconductor device of the first embodiment.

[0072] As shown in Figure 6 , in the semiconductor device 110b of the embodiment, the upper insulating region 41c of the first insulating member 41 includes the first insulating portion 41p and the second insulating portion 41q having different thicknesses from each other. In the semiconductor device 110b, the first face Fl and the second face F2 are substantially parallel to the X-Y plane. The first face Fl and the second face F2 are substantially flat. In the semiconductor device 110b, the first face Fl and the second face F2 are not concave, and thus the parasitic resistance can be suppressed, and a lower on-resistance Ron-A can be easily obtained.

[0073] Figure 7 is a schematic cross-sectional view illustrating the semiconductor device of the first embodiment.

[0074] As shown in Figure 7 , in the semiconductor device 110c of the embodiment, the first insulating member 41 includes the upper insulating region 41c provided over the third semiconductor region 13. In the semiconductor device 110c, the upper surface 41cd of the upper insulating region 41c includes a protruding portion 41cp provided at the end portion of the upper surface 41cd of the upper insulating region 41c in the second direction (X-axis direction). The other configurations of the semiconductor device 110c can be the same as those of the semiconductor device 110. In the semiconductor device 110c, by introducing impurities through the upper insulating region 41c having the above-described shape, for example, the shape of the region into which the impurities are introduced can be more stably controlled. For example, the first face Fl and the second face F2 can be effectively prevented from being concave.

[0075] Figure 8is a schematic cross-sectional view illustrating a part of a manufacturing method of a semiconductor device of the embodiment.

[0076] As Figure 8 indicated in Figure 4 , in the process corresponding to (b) of Figure 4 , the upper surface 41cd of the upper insulating region 41c includes a protruding portion 41cp provided at an end portion in the second direction (X-axis direction) of the upper surface 41cd of the upper insulating region 41c. By such an upper insulating region 41c, impurities are introduced as explained with respect to (c) of Figure 4 and (d) of , for example, so that the semiconductor device 110c can be obtained. This is because, in the introduction of impurities, the particle beam of impurities has a certain degree of diffusion, for example.

[0077] Figure 9 is a schematic cross-sectional view illustrating a semiconductor device of the first embodiment.

[0078] As Figure 9 indicated in Figure 2 , in the semiconductor device 110d of the embodiment, the first contact portion FC1 is higher than the lower end portion 53a of the third conductive member 53. The second distance d2 (refer to Figure 2 ) is longer than the distance d6 (refer to ), for example. The configuration of the semiconductor device 110d other than this can be the same as that of the semiconductor device 110. In the semiconductor device 110d, a semiconductor device capable of improving characteristics can be provided.

[0079] Figure 10 is a schematic cross-sectional view illustrating a semiconductor device of the first embodiment.

[0080] As Figure 10 indicated in Figure 2 , in the semiconductor device 110e of the embodiment, the first contact portion FC1 is lower than the lower end portion 53a of the third conductive member 53. The second distance d2 (refer to Figure 2 ) is shorter than the distance d6 (refer to ), for example. The configuration of the semiconductor device 110e other than this can be the same as that of the semiconductor device 110. In the semiconductor device 110e, a semiconductor device capable of improving characteristics can be provided.

[0081] Figure 11 is a schematic cross-sectional view illustrating a semiconductor device of the first embodiment.

[0082] As Figure 11As shown in the semiconductor device 110f of the embodiment, the number of the third conductive members 53 provided between the two first conductive portions 52a is one. The semiconductor device 110f can be configured the same as the semiconductor device 110 except for this. In the semiconductor device 110f, a semiconductor device with improved characteristics can be provided.

[0083] Figures 12-14 is a schematic cross-sectional view illustrating a semiconductor device of the first embodiment.

[0084] As Figures 12-14 shown in the semiconductor devices 120, 120a, and 120b of the embodiment, the fourth conductive member 54 is electrically connected to the third conductive member 53. Alternatively, the fourth conductive member 54 can be electrically connected to the third conductive member 53.

[0085] The fourth conductive member 54 is electrically connected to the third conductive member 53, for example, with a connection member 54L. For example, a terminal 54T electrically connected to the fourth conductive member 54 is provided. A terminal 53T electrically connected to the third conductive member 53 is provided. The third conductive member 53 is connected to the terminal 53T, for example, with a connection member 53C. The terminal 54T and the terminal 53T can be electrically connected with the connection member 54L. In the case where the terminal 54T is provided, the connection member 54L can not be included in the semiconductor devices 120, 120a, and 120b. By providing the fourth conductive member 54, concentration of an electric field can be suppressed. For example, a higher withstand voltage can be obtained. In the embodiment, in the case where the fourth conductive member 54 is provided, the number of the third conductive members 53 provided between the two first conductive portions 52a is one. Figures 12-14 In the illustrated cross section, the fourth conductive member 54 can be electrically connected to the third conductive member 53.

[0086] The semiconductor devices 120, 120a, and 120b can be configured the same as the semiconductor devices 110, 110a to 110f except for the above. According to the semiconductor devices 120, 120a, and 120b, a semiconductor device with improved characteristics can be provided.

[0087] In the embodiment, the semiconductor member 10 includes silicon, for example.

[0088] The impurity concentration of the first conductive type (or the carrier concentration of the first conductive type) in the first semiconductor region 11 is 1 x 1015cm-3 or more and 5 x 1018cm-3 or less, for example. 15 cm －3 cm 16 cm －3 cm

[0089] The impurity concentration of the second conductive type (or the carrier concentration of the second conductive type) in the second semiconductor region 12 is 1 x 1015cm-3 or more and 5 x 1018cm-3 or less, for example. 17 cm －3 cm 17 cm－3 The following.

[0090] The impurity concentration of the first conductive type (or the carrier concentration of the first conductive type) in the third semiconductor region 13 is, for example, 1 x 10 19 cm －3 The above 1 x 10 20 cm －3 The following.

[0091] The impurity concentration of the second conductive type (or the carrier concentration of the second conductive type) in the fourth semiconductor region 14 is, for example, 1 x 10 19 cm －3 The above 8 x 10 20 cm －3 .

[0092] The impurity concentration of the first conductive type (or the carrier concentration of the first conductive type) in the fifth semiconductor region 15 is, for example, 1 x 10 19 cm －3 The above 1 x 10 20 cm －3 The following.

[0093] The first conductive member 51 includes, for example, at least one selected from the group consisting of aluminum, copper, nickel, tin, gold, and silver. The first conductive portion 52a of the second conductive member 52 includes, for example, at least one selected from the group consisting of aluminum, copper, titanium, tungsten, and silicon. The second conductive portion 52b of the second conductive member 52 includes, for example, at least one selected from the group consisting of aluminum, copper, tungsten, and silicon. The third conductive member 53 and the fourth conductive member 54 include, for example, polysilicon. The polysilicon can include impurities. In one example, the first insulating member 41 includes silicon and oxygen. In one example, the second insulating member 42 includes, for example, silicon and oxygen. The second insulating member 42 can include nitrogen.

[0094] (Second Embodiment)

[0095] Figure 15 is a flowchart illustrating a manufacturing method of a semiconductor device of the second embodiment.

[0096] As Figure 15 illustrated, the manufacturing method of the semiconductor device of the second embodiment includes a step of preparing a structure SB1 (refer to (b) of Figure 4 ) having: the semiconductor member 10 including the first semiconductor region 11F of the first conductive type, the first insulating member 41, and two conductive members (the third conductive member 53). As regarding Figure 8As described above, for example, the upper surface 41cd of the upper insulating region 41c includes the protrusion 41cp provided at the end portion of the upper surface 41cd of the upper insulating region 41c in the second direction (X-axis direction). Figure 4 As described in (b), the upper insulating region 41c of the first insulating component 41 may also include a first insulating portion 41p and a second insulating portion 41q. The first insulating portion 41p is located above the central portion of a portion 11d of the first semiconductor region 11F in the second direction (Z-axis direction). The second insulating portion 41q is located above the end portion 11de of a portion 11d of the first semiconductor region 11F in the second direction (X-axis direction). The first thickness t1 of the first insulating portion 41p along the first direction (Z-axis direction) is thinner than the second thickness t2 of the second insulating portion 41q along the first direction (see Figure 4 (b)).

[0097] like Figure 15 As shown, the manufacturing method includes the step of introducing the second conductivity type impurity 12i through the first insulating member 41 (step S120). In step S120, the Figure 4 (c) The processing described above.

[0098] like Figure 15 As shown, the manufacturing method includes the step of introducing the first conductive type impurity 13i through the first insulating member 41 (step S130). In step S130, the Figure 4 (d) The processing described above.

[0099] According to the manufacturing method of the embodiment, for example, the concave first surface ( F1 ) and second surface ( F2 ) can be suppressed, and a manufacturing method of a semiconductor device capable of improving characteristics can be provided.

[0100] In an embodiment, information related to the shape of a semiconductor region can be obtained, for example, by electron microscopy. Information related to the concentration of impurities in a semiconductor region can be obtained, for example, by EDX (Energy Dispersive X-ray Spectroscopy) or SIMS (Secondary Ion Mass Spectrometry). Information related to the carrier concentration in a semiconductor region can be obtained, for example, by SCM (Scanning Capacitance Microscopy).

[0101] According to the embodiment, a semiconductor device having improved characteristics and a method for manufacturing the same can be provided.

[0102] In the present application specification, the "state of electrical connection" includes a state in which a plurality of conductive bodies are physically connected and current flows between the plurality of conductive bodies. The "state of electrical connection" includes a state in which other conductive bodies are interposed between the plurality of conductive bodies and current flows between the plurality of conductive bodies.

[0103] The above describes embodiments of the present application with reference to examples. However, the present application is not limited to these examples. For example, the specific configurations of each element such as the conductive member, the semiconductor member, the semiconductor region, and the insulating member included in the semiconductor device are within the scope of the present application as long as a person skilled in the art can implement the present application and obtain the same effects by appropriately selecting from the known range.

[0104] A scheme in which any two or more elements in each example are combined within a technically feasible range is included in the scope of the present application as long as the scheme includes the gist of the present application.

[0105] As an embodiment of the present application, all semiconductor devices and manufacturing methods thereof that a person skilled in the art can appropriately design, change, and implement based on the above-described semiconductor device and manufacturing method thereof also belong to the scope of the present application as long as the semiconductor devices and manufacturing methods thereof include the gist of the present application.

[0106] Within the scope of the idea of the present application, if it is a variety of modification examples and correction examples that a person skilled in the art can conceive, the modification examples and correction examples can be understood to also belong to the scope of the present application.

[0107] Although several embodiments of the present application are described, these embodiments are presented as examples and are not intended to limit the scope of the application. These new embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made within the scope of the gist of the application. These embodiments and modifications thereof are included in the scope, gist of the application, and the scope of the application recited in the claims and equivalents thereof.

Claims

1. A semiconductor device comprising: a first conductive component; a semiconductor component comprising: a first semiconductor region of a first conductivity type provided on the first conductive component, a second semiconductor region of a second conductivity type provided on a portion of the first semiconductor region, and a third semiconductor region of the first conductivity type provided on the second semiconductor region, wherein a concentration of an impurity of the first conductivity type in the third semiconductor region is higher than a concentration of an impurity of the first conductivity type in the first semiconductor region; a second conductive component comprising a first conductive portion electrically connected to the second semiconductor region and the third semiconductor region; a third conductive component disposed on other portions of the first semiconductor region, wherein a second direction from the second semiconductor region to the third conductive component intersects a first direction from the first conductive component to the first semiconductor region; as well as a first insulating component, at least a portion of the first insulating component being located between the semiconductor component and the third conductive component, the at least a portion of the first insulating component electrically insulating the semiconductor component from the third conductive component; The second semiconductor region includes a first surface opposite to the portion of the first semiconductor region, the first surface includes a first contact portion in contact with the first insulating component, a first distance along the first direction between the first conductive component and a lower end portion of the first surface is shorter than a second distance along the first direction between the first conductive component and the first contact portion, The first distance is shorter than the distance between the first conductive component and the lower end of the third conductive component along the first direction, The third semiconductor region includes a second surface opposite to the second semiconductor region, the second surface includes a second contact portion in contact with the first insulating component, and a third distance along the first direction between the first conductive component and a lower end portion of the second surface is shorter than a fourth distance along the first direction between the first conductive component and the second contact portion. The third distance is shorter than the distance between the first conductive component and the upper end of the third conductive component along the first direction, The fourth distance is longer than the distance between the first conductive component and the upper end portion of the third conductive component along the first direction, The first insulating component includes an upper insulating region provided above the third semiconductor region, The upper insulating region includes a first insulating portion and a second insulating portion, The first insulating portion is located between the first conductive portion and the second insulating portion, A first thickness of the first insulating portion along the first direction is thinner than a second thickness of the second insulating portion along the first direction.

2. The semiconductor device according to claim 1, The first insulating component includes an upper insulating region provided above the third semiconductor region, The upper surface of the upper insulating region includes a protrusion provided at an end portion of the upper surface of the upper insulating region in the second direction.

3. The semiconductor device according to claim 1, A fourth semiconductor region of the second conductivity type is provided between a portion of the second semiconductor region and the first conductive portion.

4. The semiconductor device according to any one of claims 1 to 3, further comprising a fourth conductive member, At least a portion of the fourth conductive component is located between the other portion of the first semiconductor region and the third conductive component, A portion of the first insulating component is located between the semiconductor component and the fourth conductive component, and the portion of the first insulating component electrically insulates the semiconductor component from the fourth conductive component. The fourth conductive member is electrically connected to one of the second conductive member and the third conductive member, or is capable of being electrically connected to the one.

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