Storage unit and its operation method

Abstract

This invention relates to a memory cell and a method of operating the memory cell. The memory cell includes: a first electrode; a second electrode; a variable resistance layer located between the first electrode and the second electrode; and a ferroelectric layer located between the variable resistance layer and the second electrode, wherein the variable resistance layer remains in an amorphous state during programming operations.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0111938, filed with the Korean Intellectual Property Office on September 2, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to an electronic device, and more specifically, to a semiconductor device including a memory. Background Technology

[0004] Recently, with the increasing demands for miniaturization, low power consumption, high performance, and versatility in electronic devices, there is a need for semiconductor devices configured to store information in various types of electronic devices, such as computers and portable communication devices. Therefore, semiconductor devices configured to store data by utilizing the characteristic of switching between different resistance states according to applied voltage or current have been investigated. Examples of such semiconductor devices can include resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electronic fuses (E-fuse), among others. Summary of the Invention

[0005] Various embodiments of this disclosure relate to an electronic device capable of improving the operating characteristics and reliability of a memory cell.

[0006] According to one embodiment, a memory cell may include: a first electrode; a second electrode; a variable resistance layer located between the first electrode and the second electrode; and a ferroelectric layer located between the variable resistance layer and the second electrode, wherein the variable resistance layer remains in an amorphous state during programming operations.

[0007] According to one embodiment, a method for operating a memory cell includes a first electrode, a second electrode, a variable resistive layer located between the first electrode and the second electrode, and a ferroelectric layer located between the variable resistive layer and the second resistive layer. The method may include: applying a positive programming voltage to the first electrode, wherein the positive programming voltage causes polarization of the ferroelectric layer; and applying a read voltage to the memory cell, the read voltage not causing polarization of the ferroelectric layer.

[0008] According to an embodiment, a method for operating a memory cell includes a first electrode, a second electrode, a switching layer located between the first electrode and the second electrode, and a ferroelectric layer located between the switching layer and the second electrode. The method may include: applying a positive programming voltage to the first electrode, wherein the positive programming voltage causes polarization of the ferroelectric layer; and applying a read voltage to the memory cell, wherein the read voltage does not cause polarization of the ferroelectric layer. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 2A and Figure 2B This is a graph illustrating the operating characteristics of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 3A and Figure 3B This is a diagram illustrating a method of operating a semiconductor device according to an embodiment of the present disclosure.

[0012] Figures 4A to 4C This is a diagram illustrating a method of operating a semiconductor device according to an embodiment of the present disclosure.

[0013] Figures 5A to 5C This is a diagram illustrating a method of operating a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 6 This is a diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 7 This is a graph showing the operating characteristics of a semiconductor device and a reference semiconductor device according to embodiments of the present disclosure.

[0016] Figure 8 This is a diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0017] Figures 9A to 9C This is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0018] Figure 10 This is a diagram illustrating the configuration of a microprocessor implementing a storage device according to an embodiment of the present disclosure.

[0019] Figure 11 This is a diagram illustrating the configuration of a processor implementing a storage device according to an embodiment of the present disclosure.

[0020] Figure 12This is a diagram illustrating the configuration of a system implementing a storage device according to an embodiment of the present disclosure.

[0021] Figure 13 This is a diagram illustrating the configuration of a data storage system implementing a storage device according to an embodiment of the present disclosure.

[0022] Figure 14 This is a diagram illustrating the configuration of a storage system implementing a storage device according to an embodiment of the present disclosure. Detailed Implementation

[0023] The following description illustrates specific structural or functional descriptions of embodiments of the concepts disclosed in this specification. These descriptions are merely examples of embodiments of the concepts and can be implemented in various forms. These descriptions are not limited to the examples of embodiments described in this specification.

[0024] Figure 1 This is a diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0025] refer to Figure 1 The semiconductor device may include a first electrode 11, a second electrode 12, a switching layer 14, and a ferroelectric layer 13. The semiconductor device may include a memory cell MC. The first electrode 11, the second electrode 12, the switching layer 14, and the ferroelectric layer 13 may form the memory cell MC. The memory cell MC may be a data storage device and may also be used as a selection element.

[0026] The switching layer 14 may be located between the first electrode 11 and the second electrode 12. The switching layer 14 may include a switching material having the following characteristics: when the applied voltage or current amplitude is equal to or less than a threshold, current flows almost no way; and when the voltage or current amplitude exceeds the threshold, current can flow. The switching material may be a chalcogenide-based material, such as arsenic tritelluride (As₂Te₃), arsenic (As₂), or arsenic triselenide (As₂Se₃). In another example, the switching material may include NbO₂ or TiO₂, which are used in metal-insulator transition (MIT) devices. In yet another example, the switching material may include ZrO₂ (Y₂O₃), Bi₂O₃-BaO, or (La₂O₃). x (CeO2) 1-x Examples of hybrid ion-electron conduction (MIEC) devices are described below. In this context, embodiments are described where the switching layer 14 comprises a chalcogenide-based material that remains amorphous.

[0027] Ferroelectric layer 13 may be located between switch layer 14 and second electrode 12. Ferroelectric layer 13 may include a ferroelectric material. The programming voltage applied to the memory cell MC may cause polarization of ferroelectric layer 13, resulting in ferroelectric layer 13 having residual polarization. When a positive programming voltage is applied, ferroelectric layer 13 may have a positive polarization state. When a negative programming voltage is applied, ferroelectric layer 13 may have a negative polarization state. Ferroelectric layer 13 may include a metal oxide. More specifically, ferroelectric layer 13 may include hafnium oxide, zirconium oxide, hafnium zirconium oxide, or combinations thereof. Alternatively, ferroelectric layer 13 may include a ferroelectric material having a perovskite structure, such as PZT(PbZr) x Ti 1-x O3), BaTiO3, or PbTiO3. The ferroelectric layer 13 may include impurities such as Si, Al, Zr, Y, La, Gd, or Sr.

[0028] The first electrode 11 or the second electrode 12 may be electrically coupled to a bit line or a word line. For example, the first electrode 11 may be coupled to a bit line, while the second electrode 12 may be electrically coupled to a word line. However, in another example, the first electrode 11 may be coupled to a word line, while the second electrode 12 may be electrically coupled to a bit line. The first electrode 11 and the second electrode 12 may include, for example, tungsten (W), tungsten nitride (WNx), tungsten silicide (WSix), titanium (Ti), titanium nitride (TiNx), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbonitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), platinum (Pt), or combinations thereof.

[0029] According to the above structure, the threshold voltage of the memory cell MC can be determined based on the residual polarization of the ferroelectric layer 13. By including the ferroelectric layer 13 in the selection element including the switching layer 14, the memory cell MC can achieve switching characteristics that allow data to be stored according to the polarization state of the ferroelectric layer 13.

[0030] Semiconductor devices may include cell arrays, row decoders, column decoders, read and write circuits, control logic circuits, and voltage generators. Semiconductor devices can communicate with a controller. When the controller receives a read / write request from the host, it can control the semiconductor device to write data to or read data stored in the semiconductor device.

[0031] A cell array can be coupled to a row decoder via row lines and to a column decoder via column lines. A cell array may include memory cells (MCs) coupled between the row and column lines. Row lines may be word lines and column lines may be bit lines, or row lines may be bit lines and column lines may be word lines.

[0032] The control logic circuitry can be coupled to the row decoder, column decoder, read and write circuitry, and voltage generator. The control logic circuitry can control the row decoder, column decoder, read and write circuitry, and voltage generator to perform internal operations based on commands from the controller.

[0033] When the control logic circuit receives a programming command, it can control the read and write circuits to perform a positive programming operation. Applying a positive programming voltage to the first electrode 11 of the selected memory cell MC can polarize the ferroelectric layer 13. In a negative programming operation, a negative programming voltage can be applied to the first electrode 11, which can also polarize the ferroelectric layer 13. When the control logic circuit receives a read command, it can control the read and write circuits to perform a read operation by applying a read voltage to the first electrode 11 of the selected memory cell MC. This read voltage will not polarize the ferroelectric layer 13.

[0034] Figure 2A and Figure 2B This is a graph illustrating the operating characteristics of a semiconductor device according to an embodiment of the present disclosure. In the graph, the X-axis represents the voltage (V) applied to the memory cell, and the Y-axis represents the current (I) flowing through the memory cell.

[0035] Figure 2A The threshold voltage variation of a memory cell MC, comprising a switching layer 14 and a ferroelectric layer 13, is shown according to programmed operations. The dashed line (initial) represents the initial state of the unpolarized ferroelectric layer 13. Because the ferroelectric layer 13 is unpolarized, the memory cell MC can have a threshold voltage Vth depending on the material properties of the switching layer 14 and the ferroelectric layer 13.

[0036] The solid line (P_PGM) can represent the threshold voltage L_Vth of the memory cell MC being positively programmed. A positive programming voltage can be applied to the memory cell MC, and the ferroelectric layer 13 can be polarized in the positive direction. Therefore, the memory cell MC can have a threshold voltage L_Vth that reduces the residual polarization Vp of the ferroelectric layer 13 from its initial state. Positive programming can refer to a set operation, and the programmed memory cell MC can have a set state.

[0037] The solid line (N_PGM) represents the threshold voltage H_Vth of the negatively programmed memory cell MC. A negative programming voltage can be applied to the memory cell MC, and the ferroelectric layer 13 can be polarized in the negative direction. Therefore, the memory cell MC can have a threshold voltage H_Vth that increases the residual polarization Vp of the ferroelectric layer 13 from the initial state. Negative programming can refer to a reset operation, and the programmed memory cell MC can have a reset state.

[0038] There can be a 2Vp difference between the threshold voltage L_Vth in the set state and the threshold voltage H_Vth in the reset state. Therefore, a read memory window of up to 2Vp can be ensured.

[0039] refer to Figure 2B The voltage V can be read. READ To read the data stored in the memory cell MC. Read voltage V. READ The voltage level can be higher than the threshold voltage L_Vth in the set state and lower than the threshold voltage H_Vth in the reset state. When reading voltage V... READ When applied to the memory cell MC, the memory cell MC can be turned on or off according to its programming state. When the memory cell MC is in a set state and a read voltage V is applied... READ When the memory cell MC is in a reset state and a read voltage V is applied, it can be turned on, allowing current to flow through it. READ When the current is turned off, the storage cell MC can be shut off, preventing current from flowing through it. Therefore, the data stored in the storage cell MC can be read.

[0040] Figure 3A and Figure 3B This is a diagram illustrating a method of operating a semiconductor device according to an embodiment of the present disclosure. Figure 3A The waveforms of the programming voltage and read voltage associated with the positive programming operation are shown. Figure 3B The waveforms of the programming voltage and read voltage associated with negative programming operations are shown.

[0041] refer to Figure 3A During positive programming operation, the positive programming voltage P_V PGM It can be applied to the memory cell MC. Positive programming voltage P_V PGM It can have a level high enough to cause polarization of the ferroelectric layer 13. According to one embodiment, the positive programming voltage P_V PGM A voltage level higher than the coercive field can cause polarization in ferroelectric materials. Through positive programming, the memory cell MC can be programmed into a set state, in which the memory cell MC has a low threshold voltage. Read voltage V READ It can have a positive voltage level. Read the voltage V. READ It may be too low to induce polarization of ferroelectric layer 13. Read voltage V READ The voltage level can be lower than the positive programming voltage P_V. PGM The level is lower than the level of the coercive field.

[0042] refer to Figure 3B During negative programming operation, the negative programming voltage N_V PGMIt can be applied to the memory cell MC. Negative programming voltage N_V PGM It can have a level high enough to cause polarization of the ferroelectric layer 13. According to one embodiment, the negative programming voltage N_V PGM The absolute value of the coercive field can be greater than the absolute value of the ferroelectric field, leading to polarization of the ferroelectric material. Through negative programming, the memory cell MC can be programmed into a reset state, in which the memory cell MC has a high threshold voltage. Read voltage V READ It can have a positive voltage level. Read the voltage V. READ The voltage level may be too low to cause polarization of ferroelectric layer 13. Read voltage V READ The absolute value can be less than the negative programming voltage N_V PGM The absolute value of the coercive field and the absolute value of the coercive field.

[0043] Figures 4A to 4C These are diagrams illustrating methods of operating a semiconductor device according to embodiments of the present disclosure. Each diagram includes a cross-sectional view and an energy band diagram of a memory cell. The memory cell MC may include a first electrode 11, a second electrode 12, a ferroelectric layer 13, and a switching layer 14. The first electrode 11 or the second electrode 12 may include metal.

[0044] Figure 4A The initial state of the memory cell MC is shown. In the initial state, the ferroelectric layer 13 can have a higher potential than the switching layer 14 and can be used as a barrier to supply electrons to the switching layer 14. The height Vr of the barrier can be determined by the physical properties and thickness of the ferroelectric layer 13. In the initial state, the memory cell MC can have a threshold voltage Vth.

[0045] Figure 4B The setup state of a memory cell MC programmed via a positive programming operation is shown. During the positive programming operation, a voltage difference can be created between the first electrode 11 and the second electrode 12 such that the voltage level of the first electrode 11 is higher than the voltage level of the second electrode 12. According to one embodiment, a positive programming voltage P_V can be applied to the first electrode 11 of the memory cell MC. PGM Furthermore, its second electrode 12 can be grounded. In the ferroelectric layer 13, negative charges can be generated due to the applied positive programming voltage P_V. PGM The ferroelectric layer 13 accumulates at the interface between the switching layer 14 and the ferroelectric layer 13, and the ferroelectric layer 13 can be polarized in the positive direction. Because the ferroelectric layer 13 has a positive polarization state, the threshold voltage of the memory cell MC can reduce the residual polarization Vp of the ferroelectric layer 13. Therefore, in the set state, the threshold voltage Vth' of the memory cell MC can satisfy [Vth-Vp].

[0046] Figure 4CThe reset state of the memory cell MC programmed via a negative programming operation is shown. A negative programming voltage N_V can be applied to the first electrode 11 of the memory cell MC. PGM In ferroelectric layer 13, positive charges can be generated due to the application of a negative programming voltage N_V. PGM The residual polarization Vp of the ferroelectric layer 13 accumulates at the interface between the switching layer 14 and the ferroelectric layer 13, and the ferroelectric layer 13 can be polarized in the negative direction. Because the ferroelectric layer 13 has a negative polarization state, the threshold voltage of the memory cell MC can increase the residual polarization Vp of the ferroelectric layer 13. Therefore, in the reset state, the threshold voltage Vth” of the memory cell MC can satisfy [Vth+Vp].

[0047] Figures 5A to 5C These are diagrams illustrating methods of operating a semiconductor device according to embodiments of the present disclosure. Each diagram includes a cross-sectional view and an energy band diagram of a memory cell. The memory cell MC may include a first electrode 11, a second electrode 12, a ferroelectric layer 13, and a switching layer 14. The first electrode 11 or the second electrode 12 may include a half-metal similar to a semiconductor, or a semiconductor material such as polycrystalline silicon.

[0048] Figure 5A The initial state of the memory cell MC is shown. In the initial state, the ferroelectric layer 13 can have a higher potential than the switching layer 14. When electrons are supplied to the switching layer 14, the ferroelectric layer 13 can be used as a barrier layer.

[0049] Figure 5B This shows the setup status of the memory cell MC programmed via positive programming. Positive programming voltage P_V PGM It can be applied to the first electrode 11 of the memory cell MC. In the ferroelectric layer 13, negative charge can be applied due to the application of a positive programming voltage P_V. PGM Electrons accumulate at the interface between the switching layer 14 and the ferroelectric layer 13, and the ferroelectric layer 13 can be polarized in the positive direction. Because the second electrode 12 is made of a half-metal or semiconductor material, electrons can accumulate in the second electrode 12 at the interface between the ferroelectric layer 13 and the second electrode 12, and the bandgap reduction effect can be increased. Therefore, when a positive programming voltage P_V is applied to the first electrode 11... PGM At this time, electrons can be supplied more easily. As a result, the threshold voltage in the set state can be further reduced compared to embodiments where the second electrode 12 includes metal.

[0050] Figure 5C The reset state of the memory cell MC programmed via negative programming is shown. Negative programming voltage N_V PGM It can be applied to the first electrode 11 of the memory cell MC. In the ferroelectric layer 13, positive charge can be applied due to the application of a negative programming voltage N_V. PGMAccumulation occurs at the interface between the switching layer 14 and the ferroelectric layer 13, and the ferroelectric layer 13 can be polarized in the negative direction. Due to the polarization of the ferroelectric layer 13, a depletion region adjacent to the ferroelectric layer 13 can be formed in the second electrode 12, thus increasing the effective barrier length. Therefore, electrons may find it difficult to tunnel, and the current can be reduced. Compared to embodiments where the second electrode 12 comprises metal, the threshold voltage in the reset state can be further increased.

[0051] Figure 6 This is a diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure. For the sake of brevity, descriptions of certain elements already discussed above are omitted below.

[0052] refer to Figure 6 The semiconductor device may include a first electrode 11, a second electrode 12, a variable resistive layer 15, and a ferroelectric layer 13. The semiconductor device may include a memory cell MC. The first electrode 11, the second electrode 12, the variable resistive layer 15, and the ferroelectric layer 13 may form the memory cell MC. The memory cell MC may be a data storage device and may also be used as a selection element.

[0053] The variable resistance layer 15 may be located between the first electrode 11 and the second electrode 12. The variable resistance layer 15 may include a resistive material and may reversibly switch between different resistance states depending on the applied voltage or current.

[0054] The variable resistance layer 15 may include, for example, transition metal oxides, or metal oxides such as perovskite-based materials. Therefore, when electronic paths are formed or decomposed in the variable resistance layer 15, data can be stored in the storage cell MC.

[0055] The variable resistance layer 15 may have a magnetic tunnel junction (MTJ) structure. The variable resistance layer 15 may include a magnetization fixed layer, a magnetization free layer, and a tunnel barrier layer interposed therebetween. For example, each of the magnetization fixed layer and the magnetization free layer may include a magnetic material, and the tunnel barrier layer may include oxides, such as oxides of magnesium (Mg), aluminum (Al), zinc (Zn), or titanium (Ti). The magnetization direction of the magnetization free layer can be changed according to the spin torque of electrons in the applied current. Therefore, data can be stored in the memory cell MC based on the change in the magnetization direction of the magnetization free layer relative to the magnetization direction of the magnetization fixed layer.

[0056] The variable resistance layer 15 may include phase change materials and chalcogenides. The variable resistance layer 15 may include, for example, chalcogenide glasses and chalcogenide alloys. The variable resistance layer 15 may include silicon (Si), germanium (Ge), antimony (Sb), tellurium (Te), bismuth (Bi), indium (In), tin (Sn), selenium (Se), or combinations thereof. For example, the variable resistance layer 15 may be Ge-Sb-Te (GST), such as Ge2Sb2Te5, Ge2Sb2Te7, Ge1Sb2Te4, or Ge1Sb4Te7. The phase of the variable resistance layer 15 can be changed according to programming operations. Through a set operation, the variable resistance layer 15 may have a low-resistance crystalline state. Through a reset operation, the variable resistance layer 15 may have a high-resistance amorphous state. Therefore, by utilizing the resistance difference depending on the phase of the variable resistance layer 15, data can be stored in the memory cell MC.

[0057] The variable resistance layer 15 may include a variable resistance material whose resistance changes without a phase transition, and may include a chalcogenide-based material. The variable resistance layer 15 may include, for example, germanium (Ge), antimony (Sb), tellurium (Te), arsenic (As), selenium (Se), silicon (Si), indium (In), tin (S), sulfur (S), gallium (Ga), or combinations thereof.

[0058] The variable resistance layer 15 can have a single phase and can maintain that phase during programming operations. According to one embodiment, the variable resistance layer 15 can be a chalcogenide layer that remains amorphous. The variable resistance layer 15 can be amorphous and can remain crystalline during programming operations. Therefore, the threshold voltage of the memory cell MC can be changed according to the programming voltage applied to the memory cell MC, and the memory cell MC can be programmed into at least two states. When a negative programming voltage is applied to the memory cell MC, the variable resistance layer 15 can have a high-resistance amorphous state. When a positive programming voltage is applied to the memory cell MC, the variable resistance layer 15 can have a low-resistance amorphous state. Therefore, by utilizing the resistance difference of the variable resistance layer 15, data can be stored in the memory cell MC.

[0059] The ferroelectric layer 13 may be located between the variable resistance layer 15 and the second electrode 12. The ferroelectric layer 13 may comprise a ferroelectric material. The ferroelectric layer 13 can be polarized by a programming voltage applied to the memory cell MC, and the ferroelectric layer 13 may have residual polarization. When a positive programming voltage is applied, the ferroelectric layer 13 may have a positive polarization state. When a negative programming voltage is applied, the ferroelectric layer 13 may have a negative polarization state. The ferroelectric layer 13 may comprise a metal oxide. The ferroelectric layer 13 may comprise, for example, hafnium oxide, zirconium oxide, hafnium zirconium oxide, or combinations thereof. Alternatively, the ferroelectric layer 13 may comprise a ferroelectric material having a perovskite structure, such as PZT(PbZr) x Ti1-x O3), BaTiO3, or PbTiO3. The ferroelectric layer 13 may include impurities such as Si, Al, Zr, Y, La, Gd, or Sr.

[0060] The first electrode 11 or the second electrode 12 may be electrically coupled to a bit line or a word line. For example, the first electrode 11 may be coupled to a bit line, while the second electrode 12 may be electrically coupled to a word line. However, in another example, the first electrode 11 may be coupled to a word line, while the second electrode 12 may be electrically coupled to a bit line. The first electrode 11 or the second electrode 12 may include, for example, tungsten (W), tungsten nitride (WNx), tungsten silicide (WSix), titanium (Ti), titanium nitride (TiNx), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbonitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), platinum (Pt), or combinations thereof.

[0061] According to the above structure, the threshold voltage of the memory cell MC can be determined based on the resistance state of the variable resistor layer 15 and the polarization state of the ferroelectric layer 13. When the memory cell MC includes the ferroelectric layer 13, it can be programmed to have a lower or higher threshold voltage compared to a memory cell without the ferroelectric layer. As a result, the read margin can be expanded to improve operating characteristics and reliability.

[0062] Figure 7 This is a graph illustrating the operating characteristics of a semiconductor device and a reference semiconductor device according to embodiments of the present disclosure. In this graph, the X-axis represents the voltage (V) applied to the memory cell, and the Y-axis represents the current (I) flowing through the memory cell. For the sake of brevity, descriptions of some elements already discussed above are omitted below.

[0063] refer to Figure 7 The dashed lines (NF_P_PGM and NF_N_PGM) represent the changes in the threshold voltage of the reference memory cell in the reference semiconductor device due to programming operations. The reference memory cell does not include ferroelectric layers such as ferroelectric layer 13. By applying the positive programming operation NF_P_PGM, the reference memory cell can be programmed into a set state, allowing it to have a low threshold voltage NF_L_Vth. By applying the negative programming operation NF_N_PGM, the reference memory cell can be programmed into a reset state, allowing it to have a high threshold voltage NF_H_Vth. A voltage difference ΔV can exist between the high threshold voltage NF_H_Vth and the low threshold voltage NF_L_Vth.

[0064] The solid lines (F_P_PGM and F_N_PGM) illustrate the change in the threshold voltage of the memory cell MC in this embodiment of the disclosure due to programming operations. The memory cell MC may include a variable resistance layer 15 and a ferroelectric layer 13. By applying a positive programming operation F_P_PGM, the memory cell MC can be programmed into a set state, such that the memory cell MC can have a first threshold voltage F_L_Vth. By applying a negative programming operation F_N_PGM, the memory cell MC can be programmed into a reset state, such that the memory cell MC can have a second threshold voltage F_H_Vth. The second threshold voltage F_H_Vth may have a voltage level greater than the first threshold voltage F_L_Vth. A voltage difference (ΔV + 2Vp) may exist between the second threshold voltage F_H_Vth and the first threshold voltage F_L_Vth.

[0065] In embodiments of this disclosure, the memory cell MC in the set state may have a low-resistance amorphous state. Additionally, the ferroelectric layer 13 may be polarized in the positive direction, and its threshold voltage may reduce the residual polarization Vp. In the set state, the memory cell MC may have a first threshold voltage F_L_Vth, which is lower than the threshold voltage NF_L_Vth of a reference memory cell. For example, the absolute value of the first threshold voltage F_L_Vth may be greater than the absolute value of the threshold voltage NF_L_Vth (Vp-Vr). In other cases, the absolute value of the first threshold voltage F_L_Vth may be greater than the absolute value of the threshold voltage NF_L_Vth.

[0066] In embodiments of this disclosure, the variable resistance layer 15 of the memory cell MC in the reset state can have a high-resistivity amorphous state. Additionally, the ferroelectric layer 13 can be polarized in the negative direction, and its threshold voltage can increase the residual polarization Vp. In the reset state, the memory cell MC can have a second threshold voltage F_H_Vth, which is greater than the threshold voltage NF_H_Vth of the reference memory cell. For example, in the reset state, the second threshold voltage F_H_Vth of the memory cell MC can be greater than the threshold voltage NF_H_Vth of the reference memory cell by (Vp + Vr).

[0067] Therefore, the memory cell MC can have a larger read memory window than the reference memory cell. By controlling the positive and negative programming voltages, the memory cell MC can be programmed into two or more states.

[0068] Figure 8 This is a diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure. For the sake of brevity, descriptions of certain elements already discussed above are omitted below.

[0069] refer to Figure 8, a semiconductor device may include a word line WL, a bit line BL, and a memory cell MC. The word line WL may extend in a first direction I. The bit line BL may extend in a second direction II that intersects the first direction I. The bit line BL or the word line WL may include, for example, tungsten (W), tungsten nitride (WNx), tungsten silicide (WSix), titanium (Ti), titanium nitride (TiNx), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbonitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), platinum (Pt), polysilicon, or a combination thereof.

[0070] The memory cell MC may be located in an intersection region between the word line WL and the bit line BL. According to one embodiment, each memory cell MC may include a ferroelectric layer 13 and a switching layer 14. The ferroelectric layer 13 and the switching layer 14 may be stacked in a third direction III. According to one embodiment, each memory cell MC may include a ferroelectric layer 13 and a variable resistance layer 15. The ferroelectric layer 13 and the variable resistance layer 15 may be stacked in a third direction III. The third direction III may refer to a direction protruding from a plane defined by the first direction I and the second direction II, and may protrude perpendicular to the plane.

[0071] The remanent polarization Vp of the ferroelectric layer 13 may increase as the thickness T2 of the ferroelectric layer 13 in the third direction III increases. As a result, the storage margin may also increase. However, when the thickness T2 is too large, the on-current may decrease. Therefore, the thickness of the ferroelectric layer 13 may be less than the thickness of the switching layer 14 or the variable resistance layer 15 (T2 < T1). The ferroelectric layer 13 may have a thickness T2 of several nanometers (nm).

[0072] Although not shown in Figure 8 , each memory cell MC may further include: a first electrode between the word line WL and the variable resistance layer 15 / switching layer 14, or a second electrode between the bit line BL and the ferroelectric layer 13. Alternatively, a part of the word line WL may be the first electrode, or a part of the bit line BL may be the second electrode.

[0073] Figure 8 Memory cells MC arranged in the first direction I and the second direction II are shown. However, the memory cells MC may be stacked in the third direction III. The bit line BL and the word line WL may be provided as layers alternately stacked at intervals in the third direction III, and the memory cells MC may be located between the stacked bit line BL and word line WL.

[0074] Figures 9A to 9CThis is a cross-sectional view illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. For the sake of brevity, descriptions of certain elements already discussed above are omitted below.

[0075] refer to Figures 9A to 9C The semiconductor devices in embodiments of this disclosure may each include a stacked structure ST, a ferroelectric layer 23, and a second conductive layer 22, and may also include a switching layer 24 or a variable resistance layer 25. In some embodiments, the semiconductor device may further include a gap-filling layer 27.

[0076] The stacked structure ST may include a first conductive layer 21 and an insulating layer 26 stacked alternately on top of each other. The first conductive layer 21 may include, for example, tungsten (W), tungsten nitride (WNx), tungsten silicide (WSix), titanium (Ti), titanium nitride (TiNx), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbonitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), platinum (Pt), polycrystalline silicon, or combinations thereof. The first conductive layer 21 may be a word line or a bit line. The insulating layer 26 may be provided to insulate the first conductive layer 21 and may include insulating materials such as oxides or nitrides.

[0077] The second conductive layer 22 can penetrate the stacked structure ST. (See reference) Figure 9A and Figure 9B In some embodiments, the second conductive layer 22 may have an open central region, and in this case, a gap-filling layer 27 may be used to fill the open central region of the second conductive layer 22. However, referring to... Figure 9C In other embodiments, the second conductive layer 22 may not have an open central region and may be filled, so a gap filling layer 27 may not be formed in the second conductive layer 22.

[0078] The second conductive layer 22 may include, for example, tungsten (W), tungsten nitride (WNx), tungsten silicide (WSix), titanium (Ti), titanium nitride (TiNx), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbonitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), platinum (Pt), polycrystalline silicon, or combinations thereof. The second conductive layer 22 may be a word line or a bit line.

[0079] The switching layer 24 or the variable resistance layer 25 may be located between the second conductive layer 22 and the first conductive layer 21. The switching layer 24 or the variable resistance layer 25 may be formed as a sidewall surrounding the second conductive layer 22.

[0080] The ferroelectric layer 23 can be located between the switching layer 24 and the second conductive layer 22, or between the variable resistor layer 25 and the second conductive layer 22. (See reference) Figure 9A and Figure 9C In some embodiments, the ferroelectric layer 23 may surround the outer wall of the second conductive layer 22. The switching layer 24 or the variable resistance layer 25 may surround the outer wall of the ferroelectric layer 23. (See reference...) Figure 9B The switching layer 24 or the variable resistance layer 25 may be located between the ferroelectric layer 23 and the first conductive layer 21, and may extend between the first conductive layer 21 and the insulating layer 26. The switching layer 24 or the variable resistance layer 25 may have a C-shaped cross-section. As a result, the outer wall of the ferroelectric layer 23 may contact the alternating layers composed of the insulating layer 26 and the switching layer 24 or the variable resistance layer 25 in the stacking direction.

[0081] According to the above structure, the memory cell can be located in the intersection region between the first conductive layer 21 and the second conductive layer 22. In one embodiment, the first conductive layer 21 can be a word line, and the second conductive layer 22 can be a bit line. In this embodiment, during a positive programming operation, the memory cell can be programmed to have a relatively low threshold voltage by applying a positive programming voltage to the first conductive layer 21. Furthermore, during a negative programming operation, the memory cell can be programmed to have a relatively high threshold voltage by applying a negative programming voltage to the first conductive layer 21. During a read operation, a positive read voltage can be applied to the first conductive layer 21.

[0082] Figure 10 This is a diagram illustrating the configuration of a microprocessor implementing a storage device according to an embodiment of the present disclosure.

[0083] refer to Figure 10 The microprocessor 1000 can control and adjust a series of processes including receiving data from various types of external devices, processing the data, and sending the results to the external devices. The microprocessor 1000 may include a memory 1010, an arithmetic unit 1020, and a controller 1030. The microprocessor 1000 can be various data processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), and an application processor (AP).

[0084] Memory 1010 may be a processor register or a register, and may store data in microprocessor 1000. Memory 1010 may include various types of registers, including data registers, address registers, and floating-point registers. Memory 1010 may be used to temporarily store data on which operations are to be performed, data corresponding to the results of the operations, and the addresses of the data used to perform the operations.

[0085] The memory 1010 may include at least one of the embodiments of the semiconductor device described above. For example, the memory 1010 may include a memory cell. The memory cell may include: a first electrode; a second electrode; a chalcogenide layer located between the first electrode and the second electrode and remaining amorphous; and a ferroelectric layer located between the chalcogenide layer and the second electrode. Therefore, the integration density and operating characteristics of the memory 1010 can be improved. As a result, the operating characteristics of the microprocessor 1000 can be improved.

[0086] The arithmetic component 1020 can perform various arithmetic or logical operations based on the results obtained by decoding the instructions from the controller 1030. The arithmetic component 1020 may include at least one arithmetic and logic unit (ALU).

[0087] The controller 1030 can receive signals from external devices of the memory 1010, the arithmetic unit 1020 and the microprocessor 1000, extract commands or decode commands, control the signal input and output of the microprocessor 1000, and execute the processing represented by the program.

[0088] According to this disclosure, the microprocessor 1000 may further include a cache memory 1040, which can temporarily store data input from external devices other than the memory 1010 or data to be output to external devices. The cache memory 1040 can exchange data with the memory 1010, the arithmetic unit 1020 and the controller 1030 through a bus interface 1050.

[0089] Figure 11 This is a diagram illustrating the configuration of a processor implementing a storage device according to an embodiment of the present disclosure.

[0090] refer to Figure 11The processor 1100 can improve performance and perform a variety of functions beyond the microprocessor's control and regulation of a series of processes that receive and process data from various external devices and send the results back to those devices. The processor 1100 may include: a core 1110 serving as a microprocessor, a cache memory 1120 for temporary data storage, and a bus interface 1130 for data transfer between internal and external devices. The processor 1100 may include various types of system-on-a-chip (SoC), such as, for example, multi-core processors, graphics processing units (GPUs), and application processors (APs).

[0091] According to embodiments of this disclosure, the core 1110 can perform arithmetic and logical operations on data input from an external device, and may include a memory 1111, an arithmetic unit 1112, and a controller 1113.

[0092] Memory 1111 may be a processor register or a register, and may store data in processor 1100. Memory 1111 may include various types of registers, including data registers, address registers, and floating-point registers. Memory 1111 may be used to temporarily store data to be operated on, data corresponding to the results of the operations, and the address of the data used to perform the operations. Arithmetic Component Unit 1112 may execute operations in processor 1100. More specifically, Arithmetic Component Unit 1112 may perform various basic arithmetic or logical operations based on the results of decoding instructions. Arithmetic Component Unit 1112 may include at least one Arithmetic and Logic Unit (ALU). Controller 1113 may receive signals from memory 1111, Arithmetic Component Unit 1112, and external devices of processor 1100, extract or decode commands, control the signal inputs and outputs of processor 1100, and execute processing represented by a program.

[0093] Cache memory 1120 can temporarily store data to compensate for the difference in data processing speed between the high-speed core 1110 and the low-speed external devices. Cache memory 1120 may include a primary storage section 1121, a secondary storage section 1122, and a tertiary storage section 1123. Typically, cache memory 1120 may include primary storage section 1121 and secondary storage section 1122. When higher capacity is required, cache memory 1120 may further include a tertiary storage section 1123. Cache memory 1120 may include more storage sections if needed. In other words, the number of storage sections included in cache memory 1120 can vary depending on the design. Primary storage section 1121, secondary storage section 1122, and tertiary storage section 1123 may have the same or different processing speeds for storing and storing data. When the storage sections have different processing speeds, among primary storage section 1121, secondary storage section 1122, and tertiary storage section 1123, primary storage section 1121 may have the highest processing speed. At least one of the primary storage portion 1121, the secondary storage portion 1122, and the tertiary storage portion 1123 may include at least one of the embodiments of the semiconductor device described above. For example, the cache memory 1120 may include a memory cell. The memory cell may include: a first electrode; a second electrode; a chalcogenide layer located between the first electrode and the second electrode and maintaining an amorphous state; and a ferroelectric layer located between the chalcogenide layer and the second electrode. As a result, the operating characteristics of the processor 1100 can be improved.

[0094] like Figure 11 As shown, all the primary storage portions 1121, secondary storage portions 1122, and tertiary storage portions 1123 can be included in the cache memory 1120. However, the primary storage portions 1121, secondary storage portions 1122, and tertiary storage portions 1123 of the cache memory 1120 can be located outside the core 1110 to compensate for the difference in processing speed between the core 1110 and external devices. Alternatively, the primary storage portion 1121 of the cache memory 1120 can be located within the core 1110, and the secondary storage portions 1122 and tertiary storage portions 1123 can be located outside the core 1110 to enhance the function of compensating for differences in data processing speed. However, the primary storage portions 1121 and secondary storage portions 1122 can be located within the core 1110, and the tertiary storage portion 1123 can be located outside the core 1110.

[0095] The bus interface 1130 can connect the core 1110, the cache memory 1120 and external devices, enabling efficient data transmission.

[0096] According to embodiments of this disclosure, processor 1100 may include a plurality of cores 1110, which may share a cache memory 1120. The plurality of cores 1110 and cache memory 1120 may be directly coupled to each other or coupled via a bus interface 1130. Each of the plurality of cores 1110 may have the same configuration as described above. When processor 1100 includes a plurality of cores 1110, the number of primary storage portions 1121 of cache memory 1120 may correspond to the number of cores 1110. Each primary storage portion 1121 of cache memory 1120 may be included in each core 1110. Additionally, secondary storage portions 1122 and tertiary storage portions 1123 may be located externally to the plurality of cores 1110 and shared via the bus interface 1130. Primary storage portions 1121 may have a faster processing speed than secondary storage portions 1122 and tertiary storage portions 1123. In another embodiment, the number of primary storage units 1121 and the number of secondary storage units 1122 may correspond to the number of cores 1110. Each primary storage unit 1121 and each secondary storage unit 1122 may be included in each core 1110. The tertiary storage unit 1123 may be located outside the plurality of cores 1110 and shared by the plurality of cores 1110 via a bus interface 1130.

[0097] According to embodiments of this disclosure, processor 1100 may include: embedded memory 1140 for storing data; communication module 1150 for transmitting or receiving data to or from external devices via wired or wireless means; memory controller 1160 for driving external storage devices; and media processor 1170 for processing data processed by processor 1100 or input from external input devices or outputting it to external interface devices. Processor 1100 may further include various modules and devices. Added modules may exchange data with each other and with core 1110 and cache memory 1120 via bus interface 1130.

[0098] Embedded memory 1140 may include non-volatile memory and volatile memory. Volatile memory may include dynamic random access memory (DRAM), mobile DRAM, static random access memory (SRAM), and memory with similar functionality. Non-volatile memory may include read-only memory (ROM), NOR flash memory, NAND flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), spin-transfer torque random access memory (STTMRAM), magnetic random access memory (MRAM), and memory with similar functionality.

[0099] Communication module 1150 may include a module connected to a wired network, a module connected to a wireless network, or both. The wired network module may include a Local Area Network (LAN), Universal Serial Bus (USB), Ethernet, or Power Line Communication (PLC), which transmits and receives data via a transmission line. The wireless network module may include Infrared Data Association (IrDA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Wireless LAN, Zigbee, Ubiquitous Sensor Network (USN), Bluetooth, Radio Frequency Identification (RFID), Long Term Evolution (LTE), Near Field Communication (NFC), Wireless Broadband Internet (Wibro), High-Speed ​​Downlink Packet Access (HSDPA), Wideband CDMA (WCDMA), or Ultra Wideband (UWB), which can transmit and receive data without a transmission line.

[0100] The memory controller 1160 may include various controllers to process and manage data transferred between the processor 1100 and external storage devices operating according to a communication standard different from that of the processor 1100. For example, the memory controller 1160 may include controllers that control Integrated Device Circuits (IDE), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Redundant Array of Independent Disks (RAID), Solid State Drives (SSD), External SATA (eSATA), PCMCIA, USB, Secure Digital (SD) cards, Mini Secure Digital (mSD) cards, Micro SD cards, Secure Digital High Capacity (SDHC) cards, memory stick cards, Smart Media Cards (SM), Multimedia Cards (MMC), Embedded MMC (eMMC), or Compact Flash (CF) cards, etc.

[0101] Media processor 1170 can process data processed by processor 1100 or video, audio, or other forms of data input from external input devices, and can output the processed data to external interface devices. Media processor 1170 may include a graphics processing unit (GPU), a digital signal processor (DSP), a high-definition audio (HD audio) or high-definition multimedia interface (HDMI) controller, etc.

[0102] Figure 12 This is a diagram illustrating the configuration of a system implementing a storage device according to an embodiment of the present disclosure.

[0103] refer to Figure 12System 1200 can refer to a device configured to process data. To perform a series of operations on the data, system 1200 can perform input, processing, output, communication, and storage. System 1200 may include a processor 1210, a main storage device 1220, an auxiliary storage device 1230, and an interface device 1240. According to embodiments of this disclosure, system 1200 may be a computer, server, personal digital assistant (PDA), portable computer, network tablet computer, wireless telephone, mobile phone, smartphone, digital music player, portable multimedia player (PMP), camera, global positioning system (GPS), camcorder, recorder, telematics, audiovisual (AV) system, or smart TV.

[0104] Processor 1210 can control the decoding of input commands and the processing of data stored in system 1200, such as data operations and comparisons. Processor 1210 may include one or more of a microprocessor unit (MPU), a central processing unit (CPU), a single-core / multi-core processor, a graphics processing unit (GPU), an application processor (AP), and a digital signal processor (DSP).

[0105] Main storage device 1220 can refer to a storage device in which program code or data is moved from auxiliary storage device 1230 and stored and executed during program execution. The stored data can be retained even without power. Main storage device 1220 can include at least one of the embodiments of the semiconductor device described above. For example, main storage device 1220 can include a memory cell. The memory cell can include: a first electrode; a second electrode; a chalcogenide layer located between the first and second electrodes and remaining amorphous; and a ferroelectric layer located between the chalcogenide layer and the second electrode. As a result, the operating characteristics of main storage device 1220 can be improved. As a result, the operating characteristics of system 1200 can be improved.

[0106] Furthermore, the main storage device 1220 may also include volatile static random access memory (SRAM) or volatile dynamic random access memory (DRAM), which loses all data when power is cut off. In another example, the main storage device 1220 may not include the semiconductor devices according to the above embodiments, and may include volatile static random access memory (SRAM) or volatile dynamic random access memory (DRAM), which loses all data when power is cut off.

[0107] Auxiliary storage device 1230 can refer to a storage device designed to store program code or data. Although auxiliary storage device 1230 is slower than main storage device 1220, auxiliary storage device 1230 can store more data than main storage device 1220. Auxiliary storage device 1230 can include at least one of the embodiments of the semiconductor device described above. For example, auxiliary storage device 1230 can include a memory cell. The memory cell can include: a first electrode; a second electrode; a chalcogenide layer located between the first electrode and the second electrode and remaining amorphous; and a ferroelectric layer located between the chalcogenide layer and the second electrode. As a result, the integration density and operating characteristics of auxiliary storage device 1230 can be improved. As a result, the operating characteristics of system 1200 can be improved.

[0108] Additionally, the auxiliary storage device 1230 may also include the following: Figure 13 The data storage system 1300 shown includes, for example, magnetic magnetic tape, magnetic disks, optical laser discs, magneto-optical disks utilizing both magnetic and optical technologies, solid-state drives (SSDs), universal serial bus (USB) memory, secure digital cards (SD cards), mini secure digital cards (mSD cards), micro secure digital cards (SD cards), secure digital high-capacity (SDHC) cards, memory stick cards, smart media (SM) cards, multimedia cards (MMC) cards, embedded MMC (eMMC) cards, and compact flash memory (CF) cards, etc. However, in contrast, the auxiliary storage device 1230 may not include the semiconductor devices according to the above embodiments, and may further include, for example, Figure 13 The data storage system 1300 shown includes, for example, magnetic magnetic tape, magnetic disk, optical laser disk, magneto-optical disk that utilizes both magnetic and optical properties, solid-state drive (SSD), universal serial bus (USB) memory, secure digital card (SD), mini secure digital card (mSD), micro secure digital card (SD), secure digital high capacity (SDHC) card, memory stick card, smart media (SM) card, multimedia card (MMC), embedded MMC (eMMC), and compact flash memory (CF) card, etc.

[0109] Interface device 1240 can perform command and data exchange between system 1200 and external devices in this embodiment. Interface device 1240 can be a keypad, keyboard, mouse, speaker, microphone, display, various human-computer interaction (HID) devices, and communication devices, etc. Communication devices can include one or both of modules connected to a wired network and modules connected to a wireless network. Wired network modules can include local area networks (LANs), universal serial buses (USB), Ethernet, power line communication (PLCs), and similar devices that operate in the same manner as various devices that send and receive data via transmission lines. Wireless network modules may include Infrared Data Association (IrDA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Wireless LAN, Zigbee, Ubiquitous Sensor Network (USN), Bluetooth, Radio Frequency Identification (RFID), Long Term Evolution (LTE), Near Field Communication (NFC), Wireless Broadband Internet (Wibro), High-Speed ​​Downlink Packet Access (HSDPA), Wideband CDMA (WCDMA), Ultra Wideband (UWB), and analogues that operate in the same manner as various devices that can send and receive data without transmission lines.

[0110] Figure 13 This is a diagram illustrating the configuration of a data storage system implementing a storage device according to an embodiment of the present disclosure.

[0111] refer to Figure 13 The data storage system 1300 may include: a storage device 1310, which is a component for storing data and has non-volatile characteristics; a controller 1320, which controls the storage device 1310; an interface 1330, which is used for connecting to external devices; and a temporary storage device 1340, which is used for temporarily storing data. The data storage system 1300 may be disk types such as hard disk drives (HDDs), optical disc read-only memories (CDROMs), digital versatile disks (DVDs), and solid-state drives (SSDs), and card types such as universal serial bus (USB) memory, secure digital cards (SD cards), micro secure digital cards (mSD cards), micro secure digital cards (SDHC cards), memory stick cards, smart media (SM) cards, multimedia cards (MMC) cards, embedded MMC (eMMC) cards, and compact flash memory (CF) cards.

[0112] Storage device 1310 may include non-volatile memory that stores data semi-permanently. Non-volatile memory may include read-only memory (ROM), NOR flash memory, NAND flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM).

[0113] The controller 1320 can control the data exchange between the storage device 1310 and the interface 1330. The controller 1320 may include a processor 1321 for performing operations that process commands input from external devices of the data storage system 1300 through the interface 1330.

[0114] Interface 1330 can be configured to exchange commands and data between external devices. When the data storage system 1300 is a card-type device, interface 1330 is compatible with interfaces used in devices such as Universal Serial Bus (USB) memory, Secure Digital (SD) cards, Mini Secure Digital (mSD) cards, Micro Secure Digital (SD) cards, Secure Digital High Capacity (SDHC) cards, memory stick cards, Smart Media (SM) cards, Multimedia Cards (MMC), Embedded MMC (eMMC), and Compact Flash (CF) cards, or with interfaces used in devices similar to those described above. If the data storage system 1300 is a disk-type device, interface 1330 is compatible with interfaces such as IDE (Integrated Device Circuit), SATA (Serial Advanced Technology Attached), SCSI (Small Computer System Interface), eSATA (External SATA), PCMCIA (Personal Computer Memory Card Association), and USB (Universal Serial Bus). Interface 1330 is compatible with interfaces similar to these. Interface 1330 is compatible with one or more different types of interfaces.

[0115] Temporary storage device 1340 can temporarily store data to efficiently transfer data between interface 1330 and storage device 1310, depending on the diversity and high performance of its interfaces with external devices, controllers, and systems. Temporary storage device 1340 may include at least one of the semiconductor devices described above. For example, temporary storage device 1340 may include a storage cell. This storage cell may include: a first electrode; a second electrode; a chalcogenide layer located between the first and second electrodes and remaining amorphous; and a ferroelectric layer located between the chalcogenide layer and the second electrode. Therefore, the operating characteristics of temporary storage device 1340 can be improved. Consequently, the operating characteristics of data storage system 1300 can be improved.

[0116] Figure 14 This is a diagram illustrating the configuration of a storage system implementing a storage device according to an embodiment of the present disclosure.

[0117] refer to Figure 14The storage system 1400 may include: a memory 1410, which is a component for storing data and has non-volatile characteristics; a memory controller 1420, which controls the memory 1410; and an interface 1430, which is used to connect to external devices. The storage system 1400 may be a card-type device such as a solid-state drive (SSD), a universal serial bus (USB) memory, a secure digital card (SD card), a mini secure digital card (mSD card), a micro secure digital card (SD card), a secure digital high-capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), or a compact flash memory (CF) card, etc.

[0118] The memory 1410 for storing data may include at least one of the embodiments of the semiconductor device described above. For example, the memory 1410 may include a memory cell. The memory cell may include: a first electrode; a second electrode; a chalcogenide layer located between the first electrode and the second electrode and remaining amorphous; and a ferroelectric layer located between the chalcogenide layer and the second electrode. Therefore, the operating characteristics of the memory 1410 can be improved. As a result, the operating characteristics of the storage system 1400 can be improved.

[0119] The memory according to this embodiment may include read-only memory (ROM), NOR flash memory, NAND flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM).

[0120] The memory controller 1420 can control data exchange between the memory 1410 and the interface 1430. The memory controller 1420 may include a processor 1421 for performing operations that process commands input from external devices of the storage system 1400 via the interface 1430.

[0121] Interface 1430 can be configured to exchange commands and data between storage system 1400 and external devices. Interface 1430 may be compatible with interfaces used in devices such as Universal Serial Bus (USB) memory, Secure Digital (SD) cards, Mini Secure Digital (mSD) cards, Micro Secure Digital (SD) cards, Secure Digital High Capacity (SDHC) cards, memory stick cards, Smart Media (SM) cards, Multimedia Cards (MMC) cards, Embedded MMC (eMMC) cards, and Compact Flash (CF) cards, or with interfaces used in devices similar to those described above. Interface 1430 may be compatible with one or more different types of interfaces.

[0122] According to this embodiment, the storage system 1400 may further include a buffer memory 1440 to efficiently input and output data between the interface 1430 and the memory 1410 based on the diversity and high performance of interfaces with external devices, memory controllers, and the storage system. The buffer memory 1440, which temporarily stores data, may include at least one of the embodiments of the semiconductor device described above. For example, the buffer memory 1440 may include a storage cell. This storage cell may include: a first electrode; a second electrode; a chalcogenide layer located between the first and second electrodes and remaining amorphous; and a ferroelectric layer located between the chalcogenide layer and the second electrode. As a result, the operating characteristics of the storage system 1400 may be improved.

[0123] Furthermore, according to this embodiment, the buffer memory 1440 may further include static random access memory (SRAM) or dynamic random access memory (DRAM) with volatile characteristics, and read-only memory (ROM), NOR flash memory, NAND flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), spin-transfer torque random access memory (STTMRAM), or magnetic random access memory (MRAM) with non-volatile characteristics. However, in other embodiments, the buffer memory 1440 may not include the semiconductor device according to the above embodiment, and may further include static random access memory (SRAM) or dynamic random access memory (DRAM) with volatile characteristics, and read-only memory (ROM), NOR flash memory, NAND flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), spin-transfer torque random access memory (STTMRAM), or magnetic random access memory (MRAM) with non-volatile characteristics.

[0124] According to embodiments of this disclosure, the operating characteristics and reliability of semiconductor devices can be improved.

[0125] In the embodiments discussed above, all steps may be performed selectively or skipped. Furthermore, the steps in each embodiment may not always be performed in a regular order. Moreover, the embodiments disclosed in this specification and accompanying drawings are intended to help those skilled in the art to better understand this disclosure, rather than to limit its scope. In other words, those skilled in the art will readily understand that various modifications are possible based on the technical scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made to the exemplary embodiments of this disclosure described above without departing from the spirit or scope of the invention. Therefore, this disclosure is intended to cover all such modifications as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A memory cell, comprising: a first electrode; a second electrode; a variable resistance layer between the first electrode and the second electrode; and a ferroelectric layer between the variable resistance layer and the second electrode, wherein, during a program operation, the variable resistance layer is held in an amorphous state and reversibly transitions between different resistance states. after a positive program operation, the memory cell has a first threshold voltage, and after a negative program operation, the memory cell has a second threshold voltage; and 2. The memory cell of claim 1, wherein, wherein the second threshold voltage is greater than the first threshold voltage. a read voltage is between the first threshold voltage and the second threshold voltage.

3. The memory cell of claim 2, wherein, the variable resistance layer has a low resistance amorphous state after a set operation, and the variable resistance layer has a high resistance amorphous state after a reset operation.

4. The memory cell of claim 1, wherein, the variable resistance layer comprises a chalcogenide compound.

5. The memory cell of claim 1, wherein, during a positive program operation, a positive program voltage is applied to the first electrode and causes polarization of the ferroelectric layer.

6. The memory cell of claim 1, wherein, during a negative program operation, a negative program voltage is applied to the first electrode and causes polarization of the ferroelectric layer.

7. The memory cell of claim 1, wherein, 8. A method of operating a memory cell, the memory cell comprising a first electrode, a second electrode, a variable resistance layer between the first electrode and the second electrode and reversibly transitioning between different resistance states, and a ferroelectric layer between the variable resistance layer and the second electrode, the method comprising: applying a positive program voltage to the first electrode, wherein the positive program voltage causes polarization of the ferroelectric layer; and applying a read voltage to the memory cell that does not polarize the ferroelectric layer. after the positive program voltage is applied, the variable resistance layer is held in an amorphous state.

9. The method of claim 8, wherein, the variable resistance layer comprises a chalcogenide compound.

10. The method of claim 8, wherein, the positive program voltage decreases a resistance of the variable resistance layer.

11. The method of claim 8, wherein, 12. The method of claim 8, further comprising the negative program voltage causes polarization of the ferroelectric layer. applying a negative programming voltage to the first electrode, wherein the negative program voltage increases a resistance of the variable resistance layer.

13. The method of claim 12, wherein, 14. A method of operating a memory cell, the memory cell comprising a first electrode, a second electrode, a switching layer between the first electrode and the second electrode, and a ferroelectric layer between the switching layer and the second electrode and having a higher potential than a potential of the switching layer in an initial state, the method comprising: applying a positive program voltage to the first electrode, wherein the positive program voltage causes polarization of the ferroelectric layer; and applying a read voltage to the memory cell that does not polarize the ferroelectric layer.

15. The method of claim 14, further comprising the negative program voltage causes polarization of the ferroelectric layer. applying a negative programming voltage to the first electrode, wherein the switching layer comprises a chalcogenide compound layer and, after the positive program voltage is applied, the switching layer is held in an amorphous state.

16. The method of claim 14, wherein, ​

Images