Semiconductor memory device

Abstract

Embodiments of the present invention provide a semiconductor memory device with relatively high reliability. The semiconductor memory device according to the embodiments of the present invention includes: a first memory string including a first memory cell; a second memory string including a second memory cell; a first bit line connected to the first memory string; and a second bit line connected to the second memory string. In a first programming operation, a first bit line voltage is supplied to the first bit line and the second bit line. In a second programming operation, a second bit line voltage greater than the first bit line voltage or a third bit line voltage greater than the second bit line voltage is supplied to the first bit line and the second bit line. In a third programming operation, the second bit line voltage is supplied to the first bit line and the third bit line voltage is supplied to the second bit line. In a fourth programming operation, the third bit line voltage is supplied to the first bit line and the second bit line voltage is supplied to the second bit line.

Description

[0001] [Related Application]

[0002] This application claims priority based on Japanese Patent Application No. 2020-156406 (filing date: September 17, 2020). This application incorporates the entire contents of the base application by reference thereto. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Art

[0004] A semiconductor memory device including a plurality of memory strings each including a memory transistor is known. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor memory device with higher reliability.

[0006] A semiconductor memory device according to an embodiment includes: a first memory string including a first memory cell; a second memory string including a second memory cell; a first bit line connected to the first memory string; a second bit line connected to the second memory string; a first word line connected to the first memory cell and the second memory cell; and a control circuit electrically connected to the first bit line, the second bit line, and the first word line. The control circuit supplies a first bit line voltage to the first bit line and the second bit line in a first programming operation of a first write sequence for the first memory cell and the second memory cell. Further, in a second programming operation performed after the first programming operation, a second bit line voltage greater than the first bit line voltage or a third bit line voltage greater than the second bit line voltage is supplied to the first bit line and the second bit line. Further, in a third programming operation performed after the second programming operation, the second bit line voltage is supplied to the first bit line and the third bit line voltage is supplied to the second bit line. Further, in a fourth programming operation performed after the third programming operation, the third bit line voltage is supplied to the first bit line and the second bit line voltage is supplied to the second bit line.

[0007] A semiconductor memory device according to an embodiment includes: a first memory string including first memory cells; a second memory string including second memory cells; a first bit line connected to the first memory string; a second bit line connected to the second memory string; a first word line connected to the first memory cells and the second memory cells; a first voltage supply line electrically connected to the first bit line and the second bit line; a second voltage supply line electrically connected to the first bit line and the second bit line; a first voltage transfer circuit that conducts the first bit line and the first voltage supply line according to the input of a first signal and conducts the first bit line and the second voltage supply line according to the input of a second signal; a second voltage transfer circuit that conducts the second bit line and the first voltage supply line according to the input of a third signal and conducts the second bit line and the second voltage supply line according to the input of a fourth signal; and a control circuit electrically connected to the first voltage supply line, the second voltage supply line, the first voltage transfer circuit, the second voltage transfer circuit, and the first word line. In a first programming operation of a first write sequence for the first memory cells and the second memory cells, the control circuit supplies the first signal to the first voltage transfer circuit and supplies the third signal to the second voltage transfer circuit. Further, in a second programming operation performed after the first programming operation, the control circuit supplies the second signal to the first voltage transfer circuit and supplies the fourth signal to the second voltage transfer circuit. Further, in a third programming operation performed after the second programming operation, in a state where the first signal is supplied to the first voltage transfer circuit and the fourth signal is supplied to the second voltage transfer circuit, the signal supplied to the first voltage transfer circuit is switched from the first signal to the second signal. Further, in a fourth programming operation performed after the third programming operation, in a state where the second signal is supplied to the first voltage transfer circuit and the third signal is supplied to the second voltage transfer circuit, the signal supplied to the second voltage transfer circuit is switched from the third signal to the fourth signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. is a schematic block diagram showing the configuration of a memory system 10 according to the first embodiment.

[0009] Figure 2 FIG. is a schematic side view showing a configuration example of the memory system 10.

[0010] Figure 3 FIG. is a schematic top view showing the configuration example.

[0011] Figure 4 FIG. is a schematic block diagram showing the configuration of a memory die MD according to the first embodiment.

[0012] Figure 5 FIG. is a schematic circuit diagram showing a partial configuration of the memory die MD.

[0013] Figure 6It is a schematic circuit diagram showing a part of the memory die MD.

[0014] Figure 7 It is a schematic circuit diagram showing a part of the memory die MD.

[0015] Figure 8 It is a schematic top view of the memory die MD.

[0016] Figure 9 It is a schematic perspective view showing a part of the memory die MD.

[0017] Figure 10 It is Figure 9 a schematic enlarged view of the part shown at A of

[0018] Figure 11 It is a schematic histogram used to explain the threshold voltage of the memory cell MC.

[0019] Figure 12 It is a schematic waveform diagram used to explain the read operation.

[0020] Figure 13 It is a schematic cross-sectional view used to explain the read operation.

[0021] Figure 14 It is a schematic flowchart used to explain the write sequence.

[0022] Figure 15 It is a schematic waveform diagram used to explain the write sequence.

[0023] Figure 16 It is a schematic cross-sectional view used to explain the programming operation.

[0024] Figure 17 It is a schematic cross-sectional view used to explain the verification operation.

[0025] Figure 18 It is a schematic diagram used to explain the write sequence.

[0026] Figure 19 It is a schematic waveform diagram used to explain the write sequence.

[0027] Figure 20 It is a schematic waveform diagram used to explain the write sequence of the second embodiment.

[0028] Figure 21 It is a schematic diagram used to explain the write sequence of the second embodiment.

[0029] Figure 22It is a schematic waveform diagram for explaining the writing sequence of the second embodiment.

[0030] Figure 23 It is a schematic table for explaining the writing sequence of the third embodiment.

[0031] Figure 24 It is a schematic bar chart for explaining the writing sequence of the third embodiment.

[0032] Figure 25 It is a schematic bar chart for explaining the writing sequence of the third embodiment.

[0033] Figure 26 It is a schematic bar chart for explaining the writing sequence of another embodiment.

[0034] Figure 27 It is a schematic bar chart for explaining the writing sequence of another embodiment.

[0035] Figure 28 It is a schematic perspective view for explaining the semiconductor memory device of another embodiment.

[0036] Figure 29 It is a schematic perspective view for explaining the semiconductor memory device of another embodiment.

[0037] Figure 30 It is a schematic perspective view for explaining the semiconductor memory device of another embodiment.

[0038] Figure 31 It is a schematic perspective view for explaining the semiconductor memory device of another embodiment. Detailed Embodiments

[0039] Next, the semiconductor memory device of the embodiment will be described with reference to the accompanying drawings. In addition, the following embodiments are merely examples and are not shown for limiting the present invention. Further, the following drawings are schematic diagrams, and for ease of explanation, some components may be omitted. In addition, for multiple embodiments, the same reference numerals are assigned to common parts, and the description may be omitted sometimes.

[0040] In addition, in this specification, when referred to as "semiconductor memory device", it may refer to a memory die, or a memory chip, a memory card, an SSD (Solid State Drive), etc., a memory system including a controller die. Further, it may also refer to a configuration including a host such as a smartphone, a tablet terminal, or a personal computer.

[0041] In addition, in this specification, when referred to as a "control circuit", it may refer to a peripheral circuit such as a sequencer provided in a memory die, may refer to a controller die or a controller chip connected to the memory die, or may refer to a configuration including both of them.

[0042] In addition, in this specification, when it is stated that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via a wiring, a semiconductor component, a transistor, or the like. For example, in the case of connecting three transistors in series, even if the second transistor is in an off state, the first transistor is "electrically connected" to the third transistor.

[0043] In addition, in this specification, when it is stated that the first configuration is "connected between" the second configuration and the third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and the second configuration is connected to the third configuration via the first configuration.

[0044] In addition, in this specification, when it is stated that a circuit or the like makes two wirings or the like "conductive", for example, it may mean that the circuit or the like includes a transistor or the like, the transistor or the like is provided on a current path between the two wirings, and the transistor or the like is in an on state.

[0045] In addition, in this specification, the specified direction parallel to the upper surface of the substrate is referred to as the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and the direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0046] In addition, in this specification, sometimes the direction along a specified plane is referred to as the first direction, the direction along the specified plane and intersecting the first direction is referred to as the second direction, and the direction intersecting the specified plane is referred to as the third direction. These first direction, second direction, and third direction may correspond to any one of the X direction, Y direction, and Z direction, or may not correspond.

[0047] In addition, in this specification, expressions such as "upper" or "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is referred to as upper, and the direction approaching the substrate along the Z direction is referred to as lower. In addition, when referring to the lower surface or the lower end of a certain configuration, it means the surface or the end on the substrate side of the configuration, and when referring to the upper surface or the upper end, it means the surface or the end on the side opposite to the substrate of the configuration. In addition, the surface intersecting the X direction or the Y direction is referred to as a side surface or the like.

[0048] [First Embodiment]

[0049] [Memory System 10]

[0050] Figure 1It is a schematic block diagram showing the configuration of the memory system 10 according to the first embodiment.

[0051] The memory system 10 reads, writes, erases, etc. user data according to signals sent by the host 20. The memory system 10 is, for example, a memory chip, a memory card, an SSD, or other systems that can store user data. The memory system 10 includes a plurality of memory dies MD that store user data, and a controller die CD connected to the plurality of memory dies MD and the host 20. The controller die CD includes, for example, a processor, a RAM (Random Access Memory), etc., and performs processes such as logical address to physical address conversion, bit error detection / correction, garbage collection (compression), wear leveling, etc.

[0052] Figure 2 It is a schematic side view showing a configuration example of the memory system 10 according to the present embodiment. Figure 3 It is a schematic top view showing the configuration example. For ease of explanation, Figure 2 and Figure 3 a part of the configuration is omitted.

[0053] As Figure 2 shown, the memory system 10 according to the present embodiment includes a mounting substrate MSB, a plurality of memory dies MD stacked on the mounting substrate MSB, and a controller die CD stacked on the memory die MD. Bonding pads P are provided in the Y-direction end regions on the upper surface of the mounting substrate MSB, and another part of the region is bonded to the lower surface of the memory die MD via an adhesive or the like. Bonding pads P are provided in the Y-direction end regions on the upper surface of the memory die MD, and other regions are bonded to the lower surface of another memory die MD or the controller die CD via an adhesive or the like. Bonding pads P are provided in the Y-direction end regions on the upper surface of the controller die CD.

[0054] As Figure 3 shown, the mounting substrate MSB, the plurality of memory dies MD, and the controller die CD each include a plurality of bonding pads P arranged in the X direction. The plurality of bonding pads P provided on the mounting substrate MSB, the plurality of memory dies MD, and the controller die CD are respectively connected to each other via bonding wires B.

[0055] In addition, Figure 2 and Figure 3 the configurations shown are only examples, and the specific configurations can be adjusted as appropriate. For example Figure 2 and Figure 3In the example shown, the controller die CD is stacked on a plurality of memory dies MD, and these components are connected by bonding wires B. In this configuration, the plurality of memory dies MD and the controller die CD are included in one package. However, the controller die CD can also be separately included in a different package from the memory dies MD. Additionally, the plurality of memory dies MD and the controller die CD can also be connected to each other via through electrodes or the like instead of the bonding wires B.

[0056] [Circuit configuration of memory die MD]

[0057] Figure 4 is a schematic block diagram showing the configuration of the memory die MD of the first embodiment. Figures 5 - 7 is a schematic circuit diagram showing a partial configuration of the memory die MD.

[0058] In addition, Figure 4 a plurality of control terminals and the like are illustrated. These plurality of control terminals are sometimes shown as control terminals corresponding to a high-active signal (positive logic signal), sometimes shown as control terminals corresponding to a low-active signal (negative logic signal), and sometimes shown as control terminals corresponding to both a high-active signal and a low-active signal. Figure 4 In, the symbol of the control terminal corresponding to the low-active signal includes an overline (overline). In this specification, the symbol of the control terminal corresponding to the low-active signal includes a slash (" / "). In addition, Figure 4 the description of is an example, and the specific form can be appropriately adjusted. For example, a part or all of the high-active signals can be used as low-active signals, or a part or all of the low-active signals can be used as high-active signals.

[0059] As Figure 4 shown, the memory die MD includes a memory cell array MCA for storing data and a peripheral circuit PC connected to the memory cell array MCA. The peripheral circuit PC includes a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC. Additionally, the peripheral circuit PC includes a cache memory CM, an address register ADR, an instruction register CMR, and a status register STR. Additionally, the peripheral circuit PC includes an input / output control circuit I / O and a logic circuit CTR.

[0060] [Circuit configuration of memory cell array MCA]

[0061] As Figure 5As shown, the memory cell array MCA includes a plurality of memory blocks BLK. Each of these plurality of memory blocks BLK includes a plurality of string components SU. Each of these plurality of string components SU includes a plurality of memory strings MS. One ends of these plurality of memory strings MS are respectively connected to the peripheral circuit PC via bit lines BL. In addition, the other ends of these plurality of memory strings MS are respectively connected to the peripheral circuit PC via a common source line SL.

[0062] The memory string MS includes a drain side selection transistor STD, a plurality of memory cells MC (memory transistors), a source side selection transistor STS, and a source side selection transistor STSb that are connected in series between the bit line BL and the source line SL. Hereinafter, the drain side selection transistor STD, the source side selection transistor STS, and the source side selection transistor STSb may be simply referred to as selection transistors (STD, STS, STSb).

[0063] The memory cell MC is a field effect transistor and includes a semiconductor layer that functions as a channel region, a gate insulating film including a charge storage film, and a gate electrode. The threshold voltage of the memory cell MC changes according to the amount of charge in the charge storage film. The memory cell MC stores 1 bit or multiple bits of data. In addition, word lines WL are respectively connected to the plurality of memory cells MC corresponding to one memory string MS. These word lines WL respectively function as gate electrodes of the memory cells MC included in all the memory strings MS in one memory block BLK.

[0064] The selection transistors (STD, STS, STSb) are field effect transistors and include a semiconductor layer that functions as a channel region, a gate insulating film, and a gate electrode. Selection gate lines (SGD, SGS, SGSb) are respectively connected to the gate electrodes of the selection transistors (STD, STS, STSb). The drain side selection gate line SGD is provided corresponding to the string component SU and functions as the gate electrode of the drain side selection transistor STD included in all the memory strings MS in one string component SU. The source side selection gate line SGS functions as the gate electrode of the source side selection transistor STS included in all the memory strings MS in the plurality of string components SU. The source side selection gate line SGSb functions as the gate electrode of the source side selection transistor STSb included in all the memory strings MS in the plurality of string components SU.

[0065] [Circuit Configuration of Voltage Generation Circuit VG]

[0066] For example, as Figure 5 shown, the voltage generation circuit VG ( Figure 4 ) is connected to a plurality of voltage supply lines 31. The voltage generation circuit VG includes, for example, a step-down circuit such as a regulator and a boost circuit such as a charge pump circuit 32. These step-down circuit and boost circuit are respectively connected to the power supply voltage VCC and the ground voltage V SS ( Figure 4 ) voltage supply lines. These voltage supply lines are connected, for example, to the pad electrodes P described with reference to Figure 2 、 Figure 3 . The voltage generation circuit VG generates various operation voltages, for example, according to a control signal from the sequencer SQC, and outputs them to a plurality of voltage supply lines 31 at the same time. The various operation voltages are voltages applied to the bit lines BL, the source lines SL, the word lines WL, and the selection gate lines (SGD, SGS, SGSb) during a read operation, a write operation, and an erase operation of the memory cell array MCA. The operation voltages output from the voltage supply lines 31 are appropriately adjusted according to a control signal from the sequencer SQC.

[0067] [Circuit configuration of row decoder RD]

[0068] For example, as shown in Figure 5 , the row decoder RD ( Figure 4 ) includes an address decoder 22 that decodes the address data D ADD , and a block selection circuit 23 and a voltage selection circuit 24 that transmit operation voltages to the memory cell array MCA according to the output signal of the address decoder 22.

[0069] The address decoder 22 includes a plurality of block selection lines BLKSEL and a plurality of voltage selection lines 33. The address decoder 22 sequentially refers to the row address RA of the address register ADR ( Figure 4 ) according to a control signal from the sequencer SQC, decodes the row address RA, sets the specified block selection transistor 35 and the voltage selection transistor 37 corresponding to the row address RA to the on state, and sets the other block selection transistors 35 and voltage selection transistors 37 to the off state. For example, the voltages of the specified block selection line BLKSEL and the voltage selection line 33 are set to the "H" state, and the other voltages are set to the "L" state. In addition, when P-channel transistors are used instead of N-channel transistors, opposite voltages are applied to these wirings.

[0070] In addition, in the illustrated example, in the address decoder 22, one block selection line BLKSEL is provided for each memory block BLK. However, this configuration can be appropriately changed. For example, one block selection line BLKSEL may be provided for every two or more memory blocks BLK.

[0071] The block selection circuit 23 includes a plurality of block selection units 34 corresponding to the memory blocks BLK. Each of the plurality of block selection units 34 includes a plurality of block selection transistors 35 corresponding to the word lines WL and the selection gate lines (SGD, SGS, SGSb). The block selection transistors 35 are, for example, field-effect voltage-resistant transistors. The drain electrodes of the block selection transistors 35 are electrically connected to the corresponding word lines WL or selection gate lines (SGD, SGS, SGSb) respectively. The source electrodes are electrically connected to the voltage supply line 31 via the wiring CG and the voltage selection circuit 24 respectively. The gate electrodes are commonly connected to the corresponding block selection lines BLKSEL.

[0072] In addition, the block selection circuit 23 further includes a plurality of transistors (not shown). These plurality of transistors are field-effect voltage-resistant transistors connected between the selection gate lines (SGD, SGS, SGSb) and the voltage supply line supplied with the ground voltage V SS These plurality of transistors supply the ground voltage V to the selection gate lines (SGD, SGS, SGSb) included in the non-selected memory block BLK. SS In addition, the plurality of word lines WL included in the non-selected memory block BLK become floating states.

[0073] The voltage selection circuit 24 includes a plurality of voltage selection units 36 corresponding to the word lines WL and the selection gate lines (SGD, SGS, SGSb). Each of the plurality of voltage selection units 36 includes a plurality of voltage selection transistors 37. The voltage selection transistors 37 are, for example, field-effect voltage-resistant transistors. The drain terminals of the voltage selection transistors 37 are electrically connected to the corresponding word lines WL or selection gate lines (SGD, SGS, SGSb) via the wiring CG and the block selection circuit 23 respectively. The source terminals are electrically connected to the corresponding voltage supply line 31 respectively. The gate electrodes are connected to the corresponding voltage selection lines 33 respectively.

[0074] In addition, in the illustrated example, an example is shown in which the wiring CG is connected to the voltage supply line 31 via one voltage selection transistor 37. However, this configuration is only an illustration, and the specific configuration can be adjusted as appropriate. For example, the wiring CG may also be connected to the voltage supply line 31 via two or more voltage selection transistors 37.

[0075] [Circuit configuration of the sense amplifier module SAM]

[0076] For example, as Figure 6 shown, the sense amplifier module SAM ( Figure 4 ) includes a plurality of sense amplifier assemblies SAU corresponding to a plurality of bit lines BL. Each sense amplifier assembly SAU includes a sense amplifier SA connected to the bit line BL, a wiring LBUS connected to the sense amplifier SA, a latch circuit SDL, DL0 to DLn L (n L(where n is a natural number), and a pre-charge charging transistor 55 connected to the wiring LBUS. Figure 7 The wiring LBUS in the sense amplifier assembly SAU is connected to the wiring DBUS via a switching transistor DSW.

[0077] As Figure 7 shown, the sense amplifier SA includes a sense transistor 41 that discharges the charge of the wiring LBUS according to the current flowing through the bit line BL. The source electrode of the sense transistor 41 is connected to a voltage supply line to which a ground voltage V SS is supplied. The drain electrode is connected to the wiring LBUS via a switching transistor 42. The gate electrode is connected to the bit line BL via a sense node SEN, a discharge transistor 43, a node COM, a clamping transistor 44, and a breakdown voltage transistor 45. In addition, the sense node SEN is connected to an internal control signal line CLKSA via a capacitor 48.

[0078] In addition, the sense amplifier SA includes a voltage transfer circuit that selectively connects the node COM and the sense node SEN to a voltage supply line to which a voltage V DD is supplied or a voltage supply line to which a voltage V SRC is supplied according to the data latched in the latch circuit SDL. The voltage transfer circuit includes a node N1, a charging transistor 46 connected between the node N1 and the sense node SEN, a charging transistor 49 connected between the node N1 and the node COM, a charging transistor 47 connected between the node N1 and the voltage supply line to which a voltage V DD is supplied, and a discharge transistor 50 connected between the node N1 and the voltage supply line to which a voltage V SRC is supplied. In addition, the gate electrodes of the charging transistor 47 and the discharge transistor 50 are commonly connected to the node INV_S of the latch circuit SDL.

[0079] In addition, the sense transistor 41, the switching transistor 42, the discharge transistor 43, the clamping transistor 44, the charging transistor 46, the charging transistor 49, and the discharge transistor 50 are, for example, enhancement-type NMOS (N-channel metal oxidesemiconductor) transistors. The breakdown voltage transistor 45 is, for example, a depletion-type NMOS transistor. The charging transistor 47 is, for example, a PMOS (P-channel metal oxide semiconductor) transistor.

[0080] In addition, the gate electrode of the switching transistor 42 is connected to the signal line STB. The gate electrode of the discharge transistor 43 is connected to the signal line XXL. The gate electrode of the clamping transistor 44 is connected to the signal line BLC. The gate electrode of the breakdown voltage transistor 45 is connected to the signal line BLS. The gate electrode of the charging transistor 46 is connected to the signal line HLL. The gate electrode of the charging transistor 49 is connected to the signal line BLX. These signal lines STB, XXL, BLC, BLS, HLL, BLX are connected to the sequencer SQC.

[0081] The latch circuit SDL includes nodes LAT_S, INV_S, an inverter 51 including an output terminal connected to the node LAT_S and an input terminal connected to the node INV_S, an inverter 52 including an input terminal connected to the node LAT_S and an output terminal connected to the node INV_S, a switching transistor 53 connected to the node LAT_S and the wiring LBUS, and a switching transistor 54 connected to the node INV_S and the wiring LBUS. The switching transistors 53 and 54 are, for example, NMOS transistors. The gate electrode of the switching transistor 53 is connected to the sequencer SQC via the signal line STL. The gate electrode of the switching transistor 54 is connected to the sequencer SQC via the signal line STI.

[0082] Latch circuits DL0 to DLn L are configured substantially the same as the latch circuit SDL. However, as described above, the node INV_S of the latch circuit SDL is in conduction with the gate electrodes of the charging transistor 47 and the discharge transistor 50 in the sense amplifier SA. The latch circuits DL0 to DLn L differ from the latch circuit SDL in this regard.

[0083] The switching transistor DSW is, for example, an NMOS transistor. The switching transistor DSW is connected between the wiring LBUS and the wiring DBUS. The gate electrode of the switching transistor DSW is connected to the sequencer SQC via the signal line DBS( Figure 6 )

[0084] In addition, as Figure 6 illustrated, the signal lines STB, HLL, XXL, BLX, BLC, BLS are commonly connected among all the sense amplifier elements SAU included in the sense amplifier module SAM. Further, the voltage supply line for the supplied voltage V DD and the voltage supply line for the supplied voltage V SRC are commonly connected among all the sense amplifier elements SAU included in the sense amplifier module SAM. Also, the signal line STI and the signal line STL of the latch circuit SDL are commonly connected among all the sense amplifier elements SAU included in the sense amplifier module SAM. Similarly, for the latch circuits DL0 to DLnL Signal lines TI0 to TIn corresponding to signal line STI and signal line STL L and TL0 to TLn L are commonly connected between all sense amplifier components SAU included in the sense amplifier module SAM. On the other hand, a plurality of the signal lines DBS are respectively provided corresponding to all sense amplifier components SAU included in the sense amplifier module SAM.

[0085] [Circuit Configuration of Cache Memory CM]

[0086] The cache memory CM ( Figure 4 ) includes a plurality of latch circuits, and these plurality of latch circuits are connected to latch circuits DL0 to DLn in the sense amplifier module SAM via a wiring DBUS L . Data DAT included in these plurality of latch circuits is sequentially transmitted to the sense amplifier module SAM or the input / output control circuit I / O.

[0087] In addition, a decoding circuit and a switching circuit (not shown) are connected to the cache memory CM. The decoding circuit decodes the column address CA stored in the address register ADR ( Figure 4 ). The switching circuit conducts the latch circuit corresponding to the column address CA and the bus DB ( Figure 4 ) according to the output signal of the decoding circuit.

[0088] [Circuit Configuration of Sequencer SQC]

[0089] The sequencer SQC ( Figure 4 ) outputs internal control signals to the row decoder RD, the sense amplifier module SAM, and the voltage generation circuit VG according to the instruction data D stored in the instruction register CMR CMD . In addition, the sequencer SQC appropriately outputs status data D indicating its own status ST to the status register STR.

[0090] In addition, the sequencer SQC generates a standby / busy signal and outputs it to the terminal RY / / BY. During the period when the terminal RY / / BY is in the "L" state (busy period), access to the memory die MD is basically prohibited. In addition, during the period when the terminal RY / / BY is in the "H" state (standby period), access to the memory die MD is allowed. Furthermore, the terminal RY / / BY is realized, for example, by referring to the pad electrode P described in Figure 2 and Figure 3 .

[0091] [Circuit Configuration of Input / Output Control Circuit I / O]

[0092] The input / output control circuit I / O has data signal input / output terminals DQ0 to DQ7, clock signal input / output terminals DQS, / DQS, and input circuits such as comparators connected to the data signal input / output terminals DQ0 to DQ7 and output circuits such as OCD (Off Chip Driver) circuits. In addition, the input / output circuit I / O has a shift register and a buffer circuit connected to these input and output circuits. The input circuit, output circuit, shift register, and buffer circuit are respectively connected to terminals supplied with the power supply voltage V CCQ and the ground voltage V SS The data signal input / output terminals DQ0 to DQ7, the clock signal input / output terminals DQS, / DQS, and the terminals supplied with the power supply voltage V CCQ The terminals are realized, for example, by referring to the pad electrodes P described in Figure 2 , Figure 3 . The data input via the data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, the address register ADR, or the instruction register CMR according to the internal control signal from the logic circuit CTR. In addition, the data output via the data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or the status register STR to the buffer circuit according to the internal control signal from the logic circuit CTR.

[0093] [Circuit configuration of the logic circuit CTR]

[0094] The logic circuit CTR ( Figure 4 ) receives external control signals from the controller die CD via the external control terminals / CEn, CLE, ALE, / WE, RE, / RE, and outputs internal control signals to the input / output control circuit I / O accordingly. In addition, the external control terminals / CEn, CLE, ALE, / WE, RE, / RE are realized, for example, by referring to the pad electrodes P described in Figure 2 , Figure 3 .

[0095] [Structure of the memory die MD]

[0096] Figure 8 is a schematic top view of the memory die MD. Figure 9 is a schematic perspective view showing a part of the structure of the memory die MD. Figure 10 is a schematic enlarged view showing the part shown at A of Figure 9 .

[0097] As shown in Figure 8 , the memory die MD has a semiconductor substrate 100. In the illustrated example, two memory cell array regions R arranged in the X direction are provided on the semiconductor substrate 100MCA . In the memory cell array region R MCA , a plurality of memory blocks BLK arranged in the Y direction are provided. An inter-block structure ST ( Figure 9 ) is provided between two adjacent memory blocks BLK in the Y direction. In addition, in these two memory cell array regions R MCA , a peripheral circuit region R is provided in a region other than PC ( Figure 8 ).

[0098] The semiconductor substrate 100 is, for example, a semiconductor substrate, and includes P-type silicon (Si) containing P-type impurities such as boron (B). On the surface of the semiconductor substrate 100, an N-type well region containing N-type impurities such as phosphorus (P), a P-type well region containing P-type impurities such as boron (B), a semiconductor substrate region where no N-type well region and P-type well region are provided, and an insulating region are provided, for example. The N-type well region, the P-type well region, and the semiconductor substrate region each function as a part of a plurality of transistors and a plurality of capacitors constituting the peripheral circuit PC, respectively.

[0099] For example, as Figure 9 shown, the memory block BLK includes a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 respectively provided between the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0100] The conductive layer 110 is a substantially plate-shaped conductive layer extending in the X direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W), etc. In addition, the conductive layer 110 may also include polysilicon containing impurities such as phosphorus (P) or boron (B), for example. An insulating layer 101 such as silicon oxide (SiO 2 ) is provided between the plurality of conductive layers 110 arranged in the Z direction.

[0101] A conductive layer 111 is provided below the conductive layer 110. The conductive layer 111 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W), etc., for example. In addition, an insulating layer 101 such as silicon oxide (SiO 2 ) is provided between the conductive layer 111 and the conductive layer 110.

[0102] The conductive layer 111 functions as a source-side selection gate line SGSb ( Figure 5 ) and a gate electrode of a plurality of source-side selection transistors STSb connected thereto. The conductive layer 111 is electrically independent in each memory block BLK.

[0103] In addition, one or more of the conductive layers 110 located at the lowermost layer among the plurality of conductive layers 110 serve as a source-side selection gate line SGS ( Figure 5) and the gate electrodes of a plurality of source side selection transistors STS connected thereto function.

[0104] In addition, a plurality of conductive layers 110 located above it function as word lines WL ( Figure 5 ) and the gate electrodes of a plurality of memory cells MC ( Figure 5 ) connected thereto. These plurality of conductive layers 110 are electrically connected to a plurality of conductive layers 110 adjacent in the X direction respectively. In addition, these plurality of conductive layers 110 are electrically independent in each memory block BLK.

[0105] In addition, one or more conductive layers 110 located above it function as a drain side selection gate line SGD and the gate electrodes of a plurality of drain side selection transistors STD ( Figure 5 ) connected thereto. For example, as Figure 9 shown, an inter-string component insulating layer SHE is provided between two conductive layers 110 adjacent in the Y direction. These plurality of conductive layers 110 are electrically independent in each string component SU respectively.

[0106] In addition, connection portions to a plurality of contacts CC are provided at the X-direction ends of these plurality of conductive layers 110. These plurality of contacts CC extend in the Z direction and are connected to the conductive layer 110 at the lower end. The contact CC may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0107] The semiconductor layer 120 is arranged in a specified pattern in the X direction and the Y direction. The semiconductor layer 120 functions as the channel regions of a plurality of memory cells MC and selection transistors (STD, STS, STSb) included in one memory string MS ( Figure 1 ). The semiconductor layer 120 is, for example, a semiconductor layer such as polysilicon (Si). The semiconductor layer 120 has, for example, a substantially bottomed cylindrical shape, and an insulating layer 125 such as silicon oxide is provided in the central portion. In addition, the outer peripheral surfaces of the semiconductor layer 120 are surrounded by the conductive layer 110 and face the conductive layer 110.

[0108] An impurity region 121 containing an N-type impurity such as phosphorus (P) is provided at the upper end portion of the semiconductor layer 120. The impurity region 121 is connected to a bit line BL extending in the Y direction via a contact Ch and a contact Cb.

[0109] The lower end portion of the semiconductor layer 120 is connected to the P-type well region of the semiconductor substrate 100 via a semiconductor layer 122 containing single crystal silicon (Si) etc. The semiconductor layer 122 functions as the channel region of the source side selection transistor STSb. The outer peripheral surface of the semiconductor layer 122 is surrounded by the conductive layer 111 and faces the conductive layer 111. An insulating layer 123 such as silicon oxide is provided between the semiconductor layer 122 and the conductive layer 111.

[0110] The gate insulating film 130 has a substantially cylindrical shape covering the outer peripheral surface of the semiconductor layer 120.

[0111] For example, as Figure 10 shown, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 laminated between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the block insulating film 133 are insulating films such as silicon oxide (SiO 2 ). The charge storage film 132 is a film capable of storing charges such as silicon nitride (Si 3 N 4 ). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120.

[0112] In addition, Figure 10 an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride is shown. However, the gate insulating film 130 may include, for example, a floating gate such as polysilicon containing N-type or P-type impurities.

[0113] For example, as Figure 9 shown, the inter-block structure ST includes a conductive layer 140 extending in the Z direction and the X direction, and an insulating layer 141 provided on the side surface of the conductive layer 140. The conductive layer 140 is connected to an N-type impurity region provided in the P-type well region of the semiconductor substrate 100. The conductive layer 140 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 140 functions as a part of the source line SL ( Figure 5 ).

[0114] [Threshold voltage of the memory cell MC]

[0115] Next, the threshold voltage of the memory cell MC will be described with reference to Figure 11 .

[0116] As described above, the memory cell array MCA includes a plurality of memory cells MC. When a write sequence is performed on these plurality of memory cells MC, the threshold voltages of these memory cells MC are controlled to multiple states.

[0117] Figure 11 is a schematic bar graph for explaining the threshold voltage of the memory cell MC for recording 4-bit data. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC.

[0118] Figure 11In the example, the threshold voltage of the memory cell MC is controlled to 16 states. For example, the threshold voltage of the memory cell MC controlled to the S1 state is greater than Figure 11 the read voltage V CG1R and the verification voltage V VFY1 , and less than the read voltage V CG2R and the verification voltage V VFY2 . In addition, the threshold voltage of all memory cells MC is less than Figure 11 the read path voltage V READ .

[0119] For example, the Er state corresponds to the lowest threshold voltage (the threshold voltage of the memory cell MC in the erased state). For example, the data "1111" can be assigned to the memory cell MC corresponding to the Er state.

[0120] In addition, the S1 state corresponds to a threshold voltage higher than the threshold voltage corresponding to the Er state. For example, the data "1011" can be assigned to the memory cell MC corresponding to the S1 state.

[0121] In addition, the S2 state corresponds to a threshold voltage higher than the threshold voltage corresponding to the S1 state. For example, the data "0011" can be assigned to the memory cell MC corresponding to the S2 state.

[0122] Similarly hereinafter, the S3 state to S15 state in the figure correspond to threshold voltages higher than the threshold voltages corresponding to the S2 state to S14 state. For example, 4-bit data other than the "1111", "1011", and "0011" can be assigned to the memory cell MC corresponding to these distributions.

[0123] In addition, the number of bits, the number of states, the data assignment to each state, etc. of the data recorded in the memory cell MC can be appropriately changed.

[0124] For example, when "1" is assigned to all the fourth bits of the Er state and the S1 state to S7 state, and "0" is assigned to all the fourth bits of the S8 state to S15 state, when reading the fourth-bit data, the read voltage V CG8R is supplied to the word line WL.

[0125] In addition, for example, when "1" is assigned to all the third bits of the Er state and the S1 state to S3 state, "0" is assigned to all the third bits of the S4 state to S11 state, and "1" is assigned to all the third bits of the S12 state to S15 state, when reading the third-bit data, the read voltages V CG4R and V CG12R are supplied to the word line WL.

[0126] [Read operation]

[0127] Next, refer to Figure 12 and Figure 13 A read operation of the semiconductor memory device according to this embodiment will be described. Figure 12 This is a schematic waveform diagram for explaining the read operation. Figure 13 It is a schematic cross-sectional view for explaining the read operation.

[0128] In the following description, the word line WL to be the target of the operation may be referred to as the selected word line WL. S The other word lines WL are called non-selected word lines WL U In the following description, an example is described in which, among a plurality of memory cells MC included in the string unit SU to be operated, the memory cells connected to the selected word line WL S The read operation is performed on the selected memory cell MC (hereinafter sometimes referred to as "selected memory cell MC"). In addition, the structure including all memory cells MC belonging to one string unit SU and corresponding to the same word line WL is sometimes referred to as a page PG.

[0129] When executing a read operation, a command set for executing the read operation is input from the controller die CD to the memory die MD. The command set includes command data D for executing the read operation. CMD , and address data D specifying the page PG, memory block BLK, memory die MD, etc., which are the objects of the read operation. ADD .

[0130] At the time t101 of the read operation, the terminal RY / / BY ( Figure 4 ) becomes "L" state. In addition, at time t101, for example, charging of the bit line BL is performed. For example, the "H" latch is made Figure 7 The latch circuit SDL sets the states of the signal lines STB, XXL, BLC, BLS, HLL, and BLX to "L, L, H, H, H, H". As a result, the voltage V is supplied to the bit line BL and the sense node SEN. DD , and start charging them. In addition, for example, to the source line SL ( Figure 5 ) Supply voltage V SRC , start charging them. Voltage V SRC For example, the size of the ground voltage V SS The voltage V SRC For example, greater than the ground voltage V SS , which is less than the voltage V DD .

[0131] At the time point t102 of the read operation, for example Figure 12 As shown, the word line WL is selected S and non-selected word lines WLU Supply the read path voltage V READ to turn on all the memory cells MC. In addition, supply the voltage V SG to the selection gate lines (SGD, SGS, SGSb) to turn on the selection transistors (STD, STS, STSb).

[0132] At the time point t103 of the read operation, supply the read voltage V S to the selection word line WL CGR (any one of V CG1R to V CG15R ). As a result, for example, as shown in Figure 13 , some of the selection memory cells MC are turned on, and the remaining selection memory cells MC are turned off.

[0133] At the time points t104 to t105 of the read operation, for example, as shown in Figure 12 , use the sense amplifier module SAM ( Figure 6 ) to detect the on / off state of the selection memory cell MC. For example, charge the wiring LBUS through the charging transistor 55 of Figure 7 . In addition, at the time point t104, set the states of the signal lines STB, XXL, BLC, BLS, HLL, BLX to "L, H, H, H, L, H", and release the charge of the sense node SEN to the bit line BL. Here, the voltage of the sense node SEN connected to the bit line BL corresponding to the on-state memory cell MC decreases relatively significantly. On the other hand, the voltage of the sense node SEN connected to the bit line BL corresponding to the off-state memory cell MC decreases less. In addition, at the time point t105, set the states of the signal lines STB, XXL, BLC, BLS, HLL, BLX to "H, L, H, H, L, H", and release or maintain the charge of the wiring LBUS. In addition, set the signal line STL to the "H" state to latch the data representing the state of the selection memory cell MC in any one of the latch circuits DL0 to DLn L .

[0134] At the time points t106 to t108 of the read operation, supply another read voltage V S to the selection word line WL CGR (any one of V CG1R to V CG15R ), use the sense amplifier module SAM ( Figure 6 ) to detect the on / off state of the selection memory cell MC, and obtain the data representing the state of the selection memory cell MC. At this time, the signal line XXL becomes the "H" state at the time point t106 and the "L" state at the time point t107.

[0135] At the time t108 of the read operation, the word line WL is selected. S and non-selected word lines WL U Supply voltage V to the read path READ , making all memory cells MC in the on state. In addition, the voltage V is supplied to the select gate lines (SGD, SGS, SGSb). SG , making the selection transistors (STD, STS, STSb) turned on.

[0136] At the time t109 of the read operation, the word line WL is selected. S , non-selected word line WL U and select gate lines (SGD, SGS, SGSb) to supply ground voltage V SS .

[0137] Then, by latching the latch circuits DL0 to DLn, L The data is appropriately processed by logical operations such as AND and OR, and the data recorded in the storage unit MC is calculated and transferred to the cache memory CM ( Figure 4 ).

[0138] also, Figure 12 The example shows that the read operation selects the word line WL S Provides 2 types of read voltage V CGR However, in the read operation, the selected word line WL S The read voltage V CGR The number of species may be 1 or 3 or more.

[0139] [Write sequence]

[0140] Next, refer to Figures 14 - 17 The write sequence of the semiconductor memory device will be described. Figure 14 is a schematic flow chart used to illustrate the write sequence. Figure 15 is a schematic waveform diagram used to illustrate the write sequence. Figure 16 It is a schematic cross-sectional view used to explain the programming action included in the write sequence. Figure 17 This is a schematic cross-sectional view for explaining a verification operation included in a write sequence.

[0141] When executing a write sequence, a command set intended to cause the memory die MD to execute the write sequence is input from the controller die CD to the memory die MD. The command set includes command data D intended to cause the memory die MD to execute the write sequence. CMD , specifying address data D of the page PG, memory block BLK, memory die MD, etc., which are the objects of the write sequence ADD, and the data DAT written into the memory cell MC in the page PG. Along with this, at time point t201, the terminal RY / / BY becomes the "L" state ( Figure 15 ).

[0142] In step S101 ( Figure 14 ), the loop count n W is set to 1. The loop count n W is a variable representing the number of write cycles (including the processes of step S102 and step S103). The loop count n W is recorded in a register or the like. Also, in this step, the number of bit lines BL of the selected memory cell MC recorded in the write sequence × 4-bit data is latched in the latch circuits DL0 to DLn L .

[0143] In step S102, a programming operation is performed.

[0144] At the time point t211 of the programming operation ( Figure 15 ), for example, a voltage V W is supplied to the bit line BL SRC , a voltage V P is supplied to the bit line BL DD , the bit line BL W is connected to the selected memory cell MC (hereinafter sometimes referred to as "write memory cell MC") for threshold voltage adjustment among the plurality of selected memory cells MC, and the bit line BL P is connected to the selected memory cell MC (hereinafter sometimes referred to as "forbidden memory cell MC") that does not perform threshold voltage adjustment among the plurality of selected memory cells MC. For example, "L" is latched in the latch circuit SDL ( W ) corresponding to the bit line BL Figure 7 ), and "H" is latched in the latch circuit SDL ( P ) corresponding to the bit line BL Figure 7 ). Also, the states of the signal lines STB, XXL, BLC, BLS, HLL, BLX are set to "L, L, H, H, L, H".

[0145] At the time point t212 of the programming operation ( Figure 15 ), the write memory cell MC is selectively turned on to the bit line BL W . For example, a voltage V SGD is supplied to the drain-side select gate line SGD. The voltage V SGD is, for example, less than Figure 12 the voltage V SG . Thus, the drain-side select transistor STD corresponding to the bit line BL SRC to which the voltage V W is supplied becomes on state, and the drain-side select transistor STD corresponding to the bit line BL DDBit line BL P The corresponding drain side selection transistor STD becomes an off state.

[0146] In addition, at the time point t212 of the programming operation, a write path voltage V S is supplied to the selected word line WL U and the non-selected word line WL PASS to turn on all the memory cells MC. The write path voltage V PASS is, for example, greater than Figure 12 the read path voltage V READ .

[0147] At the time point t213 of the programming operation, a voltage V QPW is supplied to the bit line BL QPW . The bit line BL QPW is connected to the memory cells MC to be written in which the threshold voltages are close to the target value to a certain extent among the plurality of memory cells MC to be written (hereinafter, sometimes referred to as "weak memory cells MC to be written"). For example, the gate voltage of the clamping transistor 44 is adjusted in advance before the time point t213. Figure 7 At this time, the voltage V W is supplied to the bit line BL SRC via the discharge transistor 50, so the voltage of the bit line BL W does not change. In addition, the bit line BL P is separated from the sense amplifier SA ( Figure 7 ) by the clamping transistor 44. Next, at the time point t213, the data latched in the latch circuit SDL ( QPW ) corresponding to the bit line BL Figure 7 is switched from "L" to "H". As a result, the voltage of the node COM ( Figure 7 ) of the sense amplifier SA corresponding to the weak memory cell MC is switched from the voltage V SRC to the voltage V DD . In addition, the voltage of the corresponding bit line BL is clamped by the clamping transistor 44 and switched from the voltage V SRC to the voltage V QPW .

[0148] At the time point t214 of the programming operation, a programming voltage V S is supplied to the selected word line WL PGM . The programming voltage V PGM is greater than the write path voltage V PASS .

[0149] Here, for example, as Figure 16 shown, a voltage V W is supplied to the channel of the semiconductor layer 120 connected to the bit line BL SRC . In such a semiconductor layer 120 and the selected word line WLS A relatively large electric field is generated therebetween. Accordingly, electrons in the channel of the semiconductor layer 120 tunnel through the tunnel insulating film 131 ( Figure 10 ) into the charge storage film 132 ( Figure 10 ). Accordingly, the threshold voltage of the write memory cell MC increases relatively significantly.

[0150] In addition, a voltage V QPW is supplied to the channel of the semiconductor layer 120 connected to the bit line BL QPW . In this case, an electric field smaller than the above-described electric field is generated between the semiconductor layer 120 and the select word line WL S . Accordingly, electrons in the channel of the semiconductor layer 120 tunnel through the tunnel insulating film 131 ( Figure 10 ) into the charge storage film 132 ( Figure 10 ). Accordingly, the threshold voltage of the weak write memory cell MC increases relatively slightly.

[0151] In addition, the channel of the semiconductor layer 120 connected to the bit line BL P is in an electrically floating state, and the potential of this channel rises to the write path voltage V U level by capacitive coupling with the non-select word line WL PASS . In this case, only an electric field smaller than any of the above-described electric fields is generated between the semiconductor layer 120 and the select word line WL S . Therefore, electrons in the channel of the semiconductor layer 120 do not tunnel into the charge storage film 132 ( Figure 10 ). Therefore, the threshold voltage of the prohibit memory cell MC does not increase.

[0152] At the time point t215 of the programming operation, the write path voltage V S is supplied to the select word line WL U and the non-select word line WL PASS , turning on all the memory cells MC.

[0153] At the time point t216 of the programming operation, the ground voltage V S is supplied to the select word line WL U , the non-select word line WL SS and the select gate lines (SGD, SGS, SGSb).

[0154] In step S103 ( Figure 14 ), a verification operation is performed.

[0155] At the time point t221 of the verification operation, for example, as Figure 15 shown, the read path voltage V S is supplied to the select word line WL U and the non-select word line WL READ, turn on all memory cells MC. Additionally, supply voltage V to the select gate lines (SGD, SGS, SGSb). SG , turn on the select transistors (STD, STS, STSb).

[0156] At time point t222 of the verification operation, supply a specified verification voltage to the select word line WL S ( Figure 15 In the example of, it is the verification voltage V VFY1 ). As a result, for example, as Figure 17 shown, some of the selected memory cells MC turn on, and the remaining selected memory cells MC turn off.

[0157] Additionally, at time point t222, perform charging of the bit line BL, for example. At this time, for example, based on the data in the latch circuits DL0 to DLn L , supply voltage V Figure 15 ( Figure 15 In the example of, it is bit line BL S1 ) to the bit line BL connected to the memory cell MC corresponding to a specific state ( BL +V SL ), and supply voltage V SRC to other bit lines BL.

[0158] At time points t223 to t224 of the verification operation, for example, as Figure 15 shown, use the sense amplifier module SAM ( Figure 6 ) to detect the on / off state of the memory cell MC connected to the bit line BL S1 , and obtain data representing the state of this memory cell MC. At this time, data representing the on / off state of the memory cell MC can be latched in the latch circuits DL0 to DLn L .

[0159] At time points t225 to t226 of the verification operation, for example, as Figure 15 shown, use the sense amplifier module SAM ( Figure 6 ) to detect the on / off state of the memory cell MC connected to the bit line BL S1 , and obtain data representing the state of this memory cell MC. At this time, data representing the on / off state of the memory cell MC can be latched in the latch circuits DL0 to DLn L .

[0160] In addition, the time t1 during time points t223 to t224 is shorter than the time t2 during time points t225 to t226. Therefore, at time points t223 to t224, from the sense node SEN ( Figure 7) The amount of charge released is less than the amount of charge released from the sensing node SEN at time point t225 to time point t226 Figure 7 ).

[0161] For example, among the memory cells MC determined to be in the off state in the data detected during the time period from time point t225 to time point t226, the threshold voltage is more likely to reach the target value. At least a part of such memory cells MC are used as prohibited memory cells MC in the subsequent write cycles.

[0162] In addition, for example, among the memory cells MC determined to be in the on state in the data detected during the time period from time point t225 to time point t226 and determined to be in the off state in the data detected during the time period from time point t223 to time point t224, the threshold voltage is more likely to be close to the target value to a certain extent. At least a part of such memory cells MC are used as weak write memory cells MC in the next write cycle.

[0163] In addition, for example, among the memory cells MC determined to be in the on state in the data detected during the time period from time point t223 to time point t224, the threshold voltage is more likely to deviate from the target value to a certain extent. At least a part of such memory cells MC are used as write memory cells MC in the next write cycle.

[0164] At the time points t227 to t231 of the verification operation, the same processing as that at the time points t222 to t226 is performed on the memory cells MC in other states ( Figure 15 in the example, it is the S2 state). In addition, Figure 15 the bit line BL connected to the memory cell MC corresponding to the S2 state is denoted as bit line BL S2 .

[0165] At the time points t232 to t236 of the verification operation, the same processing as that at the time points t222 to t226 is performed on the memory cells MC in other states ( Figure 15 in the example, it is the S3 state). In addition, Figure 15 the bit line BL connected to the memory cell MC corresponding to the S3 state is denoted as bit line BL S3 .

[0166] At time point t237, a readout path voltage V S is supplied to the selected word line WL U and the non-selected word line WL READ to turn on all the memory cells MC. In addition, a voltage V SG is supplied to the selection gate lines (SGD, SGS, SGSb) to turn on the selection transistors (STD, STS, STSb).

[0167] At the time point t238 of the verification operation, a ground voltage V S is supplied to the selected word line WL U , the non-selected word line WL SS , and the selected gate lines (SGD, SGS, SGSb).

[0168] Thereafter, the data latched in the latch circuit SDL is transferred to a counting circuit (not shown), and the number of memory cells MC whose threshold voltage has reached the target value or the number of memory cells MC whose threshold voltage has not reached the target value is counted.

[0169] In addition, Figure 15 an example is shown in which three verification voltages V S are supplied to the selected word line WL VFY during the verification operation. However, the number of types of verification voltage V S supplied to the selected word line WL VFY during the verification operation may be two or less, or may be four or more, and can be changed according to the number of cycles n W .

[0170] In step S104 ( Figure 14 ), the result of the verification operation is determined. For example, when the number of memory cells MC whose threshold voltage has not reached the target value is equal to or more than a fixed number with reference to the counting circuit, it is determined that the verification has failed (FAIL), and the process proceeds to step S105. On the other hand, when the number of memory cells MC whose threshold voltage has not reached the target value is less than the fixed number, it is determined that the verification has passed (PASS), and the process proceeds to step S107.

[0171] In step S105, it is determined whether the number of cycles n W has reached the specified number N W . When the specified number N W has not been reached, the process proceeds to step S106. When the specified number N W has been reached, the process proceeds to step S108.

[0172] In step S106, 1 is added to the number of cycles n W , and the process proceeds to step S102. In addition, in step S106, for example, a specified voltage ΔV is added to the programming voltage V PGM . Therefore, the programming voltage V PGM increases as the number of cycles n W increases.

[0173] In step S107, the status data D ST indicating that the write sequence has normally ended is stored in the status register STR ( Figure 4 ), and the write sequence is terminated. In addition, the status data D STOutput to the controller die CD through the status read operation( Figure 1 ).

[0174] In step S108, the status data D indicating that the write sequence has not ended normally ST is stored in the status register STR( Figure 2 ), and the write sequence ends.

[0175] [Method for determining threshold voltage]

[0176] Next, with reference to Figure 18 and Figure 19 , the method for determining the threshold voltage in the write sequence and the like will be described. Figure 18 is a diagram illustrating this method. Figure 19 is a schematic waveform diagram for explaining this method.

[0177] Figure 18 α-1 to α-3, β-1 to β-3, and γ of Figure 19 are each one of the memory cells MC corresponding to the S1 state. Additionally, α-1 the bit lines BL α-3 to bit line BL Figure 19 the bit line BL γ is the bit line BL connected to γ.

[0178] In the programming operation of the k-th (k is a natural number) write cycle (cycle (Loop) k), as Figure 18 shown, α-1 to α-3, β-1 to β-3, and γ are all used as the write memory cell MC. Therefore Figure 19 in the example of α-1 to bit line BL α-3 and bit line BL γ supply voltage V SRC at the time points t310 to t311 corresponding to this programming operation.

[0179] In the verification operation of the k-th write cycle (cycle k), for example, as Figure 19 illustrated in S supply the verification voltage V VFY1 to the select word line WL BL +V SL is supplied to the bit lines BL corresponding to α-1 to α-3, β-1 to β-3, and γ at the time points t312 to t313. Additionally, at the time points t313 to t315 when the verification voltage V S and the verification voltage V VFY2 are supplied to the select word line WL VFY3 supply voltage V SRC. In addition, as Figure 18 shown, in the process (VL) corresponding to time points t223 to t224 ([[]] Figure 15 ) in the k-th write cycle, α-1 to α-3 and β-1 to β-3 are determined to be in the off state, and γ is determined to be in the on state. Additionally, in the process (VH) corresponding to time points t225 to t226 ([[]] Figure 15 ), α-1 to α-3 are determined to be in the off state, and β-1 to β-3 and γ are determined to be in the on state.

[0180] In the programming operation of the (k + 1)-th write cycle (cycle k + 1), as Figure 18 shown, α-1 to α-3 and β-1 to β-3 are temporarily used as prohibited memory cells MC, and γ is used as a write memory cell MC. Therefore Figure 19 in the example of , at time points t320 to t321 corresponding to this programming operation, a voltage V α-1 ~ bit line BL α-3 is supplied, and a voltage V DD is supplied to bit line BL γ and a voltage V SRC is supplied to bit line BL

[0181] In the verification operation of the (k + 1)-th write cycle (cycle k + 1), for example, as Figure 19 illustrated, at time points t322 to t323 when a verification voltage V S is supplied to the select word line WL VFY1 , a voltage V BL + V SL is supplied to the bit lines BL corresponding to α-1 to α-3, β-1 to β-3, and γ. Additionally, at time points t323 to t326 when a verification voltage V S ~ verification voltage V VFY2 is supplied to the select word line WL VFY4 , a voltage V SRC is supplied to these bit lines BL. In addition, as Figure 18 shown, in the process (VL) corresponding to time points t223 to t224 ([[]] Figure 15 ) in the (k + 1)-th write cycle, α-1, α-2, β-1, and β-2 are determined to be in the off state, and α-3, β-3, and γ are determined to be in the on state. Additionally, in the process (VH) corresponding to time points t225 to t226 ([[]] Figure 15 ), α-1 and β-1 are determined to be in the off state, and α-2, α-3, β-2, β-3, and γ are determined to be in the on state.

[0182] In the programming operation of the (k + 2)-th write cycle (cycle k + 2), as Figure 18As shown, α-1 serves as the prohibited storage cell MC, α-2, β-1, and β-2 serve as the weak write storage cells MC, α-3 and β-3 temporarily serve as the prohibited storage cell MC, and γ serves as the write storage cell MC. Therefore Figure 19 In the example of α-1 and bit line BL α-3 supply voltage V DD , to bit line BL α-2 supply voltage V QPW , to bit line BL γ supply voltage V SRC .

[0183] In the verification operation of the (k + 2)-th write cycle (cycle k + 2), for example, as Figure 19 illustrated in S supply the verification voltage V VFY1 to the selected word line WL at time points t332 - t333, supply voltage V SRC to the bit lines BL corresponding to α-1 - α-3, β-1 - β-3, and supply voltage V BL + V SL to the bit line BL corresponding to γ. Additionally, at time points t333 - t337 when supplying the verification voltage V S to the selected word line WL VFY2 - the verification voltage V VFY5 , supply voltage V SRC to these bit lines BL. Furthermore, in the process (VL) corresponding to time points t223 - t224 ( Figure 15 ) in the (k + 2)-th write cycle, γ is determined to be in the on state. Additionally, in the process (VH) corresponding to time points t225 - t226 ( Figure 15 ), γ is determined to be in the on state.

[0184] In the programming operation of the (k + 3)-th write cycle (cycle k + 3), as Figure 18 shown, α-1, α-2, β-1, and β-2 serve as the prohibited storage cells MC, α-3 and β-3 serve as the weak write storage cells MC, and γ serves as the write storage cell MC. Therefore Figure 19 in the example of α-1 and bit line BL α-2 supply voltage V DD , to bit line BL α-3 supply voltage V QPW , to bit line BL γ supply voltage V SRC .

[0185] In the verification operation of the (k + 3)-th write cycle (cycle k + 3), for example, as illustrated in Figure 19 , at time points t342 to t343 when supplying the verification voltage V S to the selected word line WL VFY1 , the voltage V SRC is supplied to the bit lines BL corresponding to α-1 to α-3, β-1 to β-3, and the voltage V BL + V SL is supplied to the bit line BL corresponding to γ. In addition, at time points t343 to t348 when supplying the verification voltage V S to the selected word line WL VFY2 to the verification voltage V VFY6 , the voltage V SRC is supplied to these bit lines BL. Further, in the process (VL) corresponding to time points t223 to t224 ( Figure 15 ) in the (k + 3)-th write cycle, γ is determined to be in the on state. In addition, in the process (VH) corresponding to time points t225 to t226 ( Figure 15 ), γ is determined to be in the on state.

[0186] Here, α-1 is determined to be in the off state in both the process ( Figure 18 VL) corresponding to time points t223 to t224 and the process ( Figure 18 VH) corresponding to time points t225 to t226 in the verification operation of the k-th write cycle. In addition, α-1 is determined to be in the off state in both the process ( Figure 18 VL) corresponding to time points t223 to t224 and the process ( Figure 18 VH) corresponding to time points t225 to t226 in the verification operation of the (k + 1)-th write cycle. In such a memory cell MC, the threshold voltage is highly likely to actually reach the target value. Therefore, in the present embodiment, α-1 is used as a prohibited memory cell MC in the subsequent process in the write sequence.

[0187] In addition, α-2 is determined to be in the off state in both the process ( Figure 18 VL) corresponding to time points t223 to t224 and the process ( Figure 18 VH) corresponding to time points t225 to t226 in the verification operation of the k-th write cycle. In addition, α-2 is determined to be in the off state in the process ( Figure 18 VL) corresponding to time points t223 to t224 in the verification operation of the (k + 1)-th write cycle, but is determined to be in the on state in the process ( Figure 18is determined to be in the ON state in the VH of). In such a memory cell MC, there is a high probability that the threshold voltage is close to the target value to a certain extent. However, the threshold voltage may not actually reach the target value. Therefore, in the present embodiment, α-2 is used as a weak write memory cell MC in the programming operation of the (k + 2)-th write cycle, and α-2 is used as a prohibited memory cell MC in the subsequent processing.

[0188] In addition, α-3 is determined to be in the OFF state in the processes corresponding to time points t223 to t224 and t225 to t226 in the verification operation of the k-th write cycle ( Figure 18 of VL) and the processes corresponding to time points t225 to t226 ( Figure 18 of VH). However, α-3 is determined to be in the ON state in the processes corresponding to time points t223 to t224 and t225 to t226 in the verification operation of the (k + 1)-th write cycle ( Figure 18 of VL) and the processes corresponding to time points t225 to t226 ( Figure 18 of VH). In such a memory cell MC, for example, compared with γ, the probability that the threshold voltage is close to the target value is higher. However, there is a high probability that the threshold voltage does not actually reach the target value. Therefore, in the present embodiment, α-3 is temporarily used as a prohibited memory cell MC in the (k + 2)-th programming operation, α-3 is used as a weak write memory cell MC in the programming operation of the (k + 3)-th write cycle, and α-3 is used as a prohibited memory cell MC in the subsequent processing. As Figure 19 shown, the programming voltage V in the (k + 3)-th write cycle PGM is greater than the programming voltage V in the (k + 2)-th write cycle PGM . Therefore, more charges are accumulated in the charge storage film 132 of α-3 than in the charge storage film 132 of α-2.

[0189] In addition, in the present embodiment, the same processing as that for α-2 is performed on β-1 and β-2. In addition, the same processing as that for α-3 is performed on β-3.

[0190] [Read Disturbance]

[0191] Figure 11 In the example of), 4-bit data is recorded in one memory cell MC by controlling the threshold voltage of the memory cell MC to 16 states. In such a form, it is preferable to accurately control the threshold voltage of the memory cell MC.

[0192] Here, in the verification operation ( Figure 14 step S103), a threshold voltage higher than the actual threshold voltage of the memory cell MC or a threshold voltage lower than the actual threshold voltage of the memory cell MC may be detected. Hereinafter, this phenomenon is sometimes referred to as "read disturbance".

[0193] When a read disturbance occurs, for example, a determination may be made that the threshold voltage has reached the target value for a memory cell MC whose threshold voltage has not reached the target value. There is a case where the threshold voltage of such a memory cell MC does not fall within the desired threshold distribution range exemplified in Figure 11 . When the number of such memory cells MC increases, there is a case where the threshold distribution range expands as exemplified in Figure 11 , and the bit error rate increases.

[0194] [Improving the Bit Error Rate by Using Multiple Verification Operations]

[0195] To improve the bit error rate, for example, it is conceivable to execute the verification operation ( Figure 14 step S103) multiple times. However, for example, when increasing the number of executions of the verification operation in one write cycle, there is a concern that the time required for the write sequence will increase significantly.

[0196] To execute the verification operation multiple times without increasing the time required for the write sequence, for example, it is conceivable to execute the verification operation across multiple write cycles. For example, when it is determined in the verification operation corresponding to the k-th write cycle that the threshold voltage of a certain memory cell MC has reached the target value, the memory cell MC is temporarily regarded as a prohibited memory cell MC in the programming operation corresponding to the (k + 1)-th write cycle, and the verification operation is executed again on the memory cell MC in the verification operation corresponding to the (k + 1)-th write cycle. In addition, when it is determined in the verification operation corresponding to the (k + 1)-th write cycle that the threshold voltage of the memory cell MC has not reached the target value, the memory cell MC is regarded as a write memory cell MC in the programming operation corresponding to the (k + 2)-th write cycle.

[0197] However, the programming voltage V PGM increases as the number of cycles n W increases. Therefore, in the above-described case, there is a concern that in the programming operation corresponding to the (k + 2)-th write cycle, a programming voltage V PGM exceeding an appropriate magnitude will be supplied to the memory cell MC, causing the threshold voltage of the memory cell MC to increase beyond the desired range. If the number of such memory cells MC increases, there is a case where the threshold distribution range expands as exemplified in Figure 11 , and the bit error rate increases.

[0198] To suppress this phenomenon, for example, it is conceivable to regard the above-described memory cell MC as a weak write memory cell MC instead of a write memory cell MC in the programming operation corresponding to the (k + 2)-th write cycle. In addition, it is conceivable to reduce the voltage V QPW supplied to the bit line BL QPWSet it to a relatively large voltage. Additionally, it is contemplated that in the case where it is determined that the threshold voltage of the weak write memory cell MC has reached the target value in a certain write cycle, this memory cell MC is regarded as a prohibited memory cell MC in subsequent write cycles. According to this method, the number of electrons tunneling into the charge storage film 132 of the memory cell MC as described above is significantly reduced in the programming operation corresponding to the (k + 2)-th write cycle. Therefore, an increase in the threshold voltage beyond the desired range can be suppressed.

[0199] However, in this method, for a memory cell MC whose threshold voltage is close to the target value to a certain extent, multiple verification operations are performed. When a read disturbance occurs in this state, there is a high possibility of determining that the threshold voltage of such a memory cell MC has reached the target value.

[0200] [Effects of the First Embodiment]

[0201] In the write sequence of the first embodiment, since the verification operation is performed multiple times, the influence of read disturbance can be suppressed as compared with the case where the verification operation is performed only once.

[0202] In addition, in the write sequence of this embodiment, since the verification operation is performed across multiple write cycles, the time required for the write sequence does not increase significantly as described above.

[0203] In addition, in the write sequence of this embodiment, the memory cells MC are classified into several types according to the results of multiple verification operations, and writing is performed at appropriate times according to these classifications, thereby adjusting the writing intensity. According to this method, the influence of read disturbance can be well suppressed, and an appropriate amount of charge is accumulated in the charge storage film 132 of the memory cell MC whose threshold voltage is close to the target value to a certain extent.

[0204] [Second Embodiment]

[0205] Next, a semiconductor memory device according to the second embodiment will be described with reference to Figures 20 - 22 FIG. is a schematic waveform diagram for explaining the write sequence of the second embodiment. Figure 20 FIG.

[0206] The write sequence of the second embodiment is basically executed in the same manner as that of the first embodiment.

[0207] However, as shown in Figure 20 FIG., in the second embodiment, the signal corresponding to the signal line XXL (the signal input to the gate electrode of the discharge transistor 43 in Figure 7 is controlled according to two patterns (XXL_A, XXL_B). For example, in this embodiment, such a signal is configured according to the latch in the latch circuits DL0 to DLn LIt is controlled in two ways according to any one of the data. For example, the sense amplifier SA of the second embodiment may include a switching circuit such as a MOS (metal oxide semiconductor) transistor connected between the gate electrode of the discharge transistor 43 and the sequencer SQC, and a MOS transistor connected between the gate electrode of the discharge transistor 43 and the latch circuits DL0 to DLn L and a switching circuit such as a MOS transistor.

[0208] In pattern XXL_A, the signal input to the gate electrode of the discharge transistor 43 is controlled in the same manner as the signal line XXL of the first embodiment. That is, at the time points t223 to t224, t228 to t229, and t233 to t234 during the verification operation, the time t1 period becomes the "H" state. In addition, at the time points t225 to t226, t230 to t231, and t235 to t236 during the verification operation, the time t2 period becomes the "H" state.

[0209] In addition, in pattern XXL_B, the signal input to the gate electrode of the discharge transistor 43 is basically controlled in the same manner as the signal line XXL of the first embodiment. In addition, in pattern XXL_B, the signal input to the gate electrode of the discharge transistor 43 also becomes the "H" state at the time points t223, t228, and t233 during the verification operation, in the same manner as the signal line XXL of the first embodiment. However, in pattern XXL_B, the time t1' from when the signal input to the gate electrode of the discharge transistor 43 becomes the "H" state to when it becomes the "L" state is shorter than the time t1. In addition, in pattern XXL_B, the signal input to the gate electrode of the discharge transistor 43 also becomes the "H" state at the time points t225, t230, and t235 during the verification operation, in the same manner as the signal line XXL of the first embodiment. However, in pattern XXL_B, the time t2' from when the signal input to the gate electrode of the discharge transistor 43 becomes the "H" state to when it becomes the "L" state is shorter than the time t2.

[0210] In this embodiment, at the time of starting to execute the write sequence, the signal input to the gate electrode of the discharge transistor 43 corresponding to all the write memory cells MC is controlled in pattern XXL_B. When any one of the memory cells MC is determined to be in the off state in the processes corresponding to the time points t223, t228, and t233 during the verification operation corresponding to any one of the write cycles, the data in the latch circuits DL0 to DLn corresponding to these memory cells MC L is inverted. In addition, in this write cycle, the signal input to the gate electrode of the discharge transistor 43 corresponding to these memory cells MC is controlled in pattern XXL_A.

[0211] Next, with reference to Figure 21 and Figure 22 a method for determining the threshold voltage in the write sequence of the second embodiment and the like will be described. Figure 21 is a diagram illustrating this method. Figure 22 is a schematic waveform diagram for explaining this method.

[0212] As shown in the figure, the method for determining the threshold voltage in the second embodiment is basically executed in the same manner as in the first embodiment.

[0213] However, in the programming operation of the (k + 1)-th write cycle (cycle k + 1) in the second embodiment, as Figure 21 shown, α-1 to α-3 and β-1 to β-3 are weak write memory cells MC instead of prohibited memory cells MC. Therefore Figure 22 in the example of, at the time points t320 to t321 corresponding to this programming operation, a voltage V α-1 is supplied to bit line BL α-3 to QPW .

[0214] [Deviation of the threshold voltage of the drain side selection transistor STD]

[0215] In the first embodiment, it is preferable to set the voltage V QPW supplied to bit line BL QPW to a relatively large voltage. Thus, even when the programming voltage V S supplied to the select word line WL PGM becomes a relatively large voltage to some extent during the programming operation, the voltage between the semiconductor layer 120 connected to bit line BL QPW and the select word line WL S becomes small, and an increase amount of the threshold voltage of the memory cell MC can be suppressed. Thereby, in, for example Figure 18 the (k + 2)-th write cycle, an increase in the threshold voltage of the memory cell MC exceeding a desired range can be suppressed.

[0216] However, when the voltage V QPW is set to a relatively large voltage, it may be necessary to more strictly control the deviation of the threshold voltage of the drain side selection transistor STD.

[0217] That is to say, as described above, at the time point t212 ( Figure 15 ) during the programming operation, in a state where the voltage V SRC has been supplied to bit line BL W and the voltage V DD has been supplied to bit line BL P , a voltage V SGD is supplied to the drain side select gate line SGD. Thus, the drain-side selection transistor STD corresponding to the supplied voltage V SRC of the bit line BL W is turned on, and the drain-side selection transistor STD corresponding to the supplied voltage V DD of the bit line BL P is turned off.

[0218] To achieve this state, for the multiple drain-side selection transistors STD included in the memory cell array MCA, the magnitude obtained by subtracting the threshold voltage of the drain-side selection transistor STD from the voltage V SGD must be adjusted to the range between the voltage V SRC and the voltage V DD .

[0219] Further, at the time point t213 of the programming operation, the voltage V QPW is supplied to the bit line BL QPW , and the voltage V QPW is also supplied to the semiconductor layer 120 connected thereto.

[0220] To achieve this state, for the multiple drain-side selection transistors STD included in the memory cell array MCA, the magnitude obtained by subtracting the threshold voltage of the drain-side selection transistor STD from the voltage V SGD must be adjusted to the range between the voltage V QPW and the voltage V DD . Therefore, the larger the voltage V QPW , the more strictly the deviation of the threshold voltage of the drain-side selection transistor STD needs to be controlled.

[0221] [Effect of the Second Embodiment]

[0222] In the write sequence of the second embodiment, as described with reference to Figure 22 , at the time of starting the execution of the write sequence, the signal input to the gate electrode of the discharge transistor 43 corresponding to all the write memory cells MC is controlled by the pattern XXL_B. Here, the time t1' corresponding to the pattern XXL_B is shorter than the time t1 corresponding to the pattern XXL_A. Therefore, the memory cell MC controlled by the pattern XXL_B is likely to be determined as the off state in the verification operation. That is, the threshold voltage of the memory cell MC controlled by the pattern XXL_B observed through the verification operation appears to be larger than the actual threshold voltage on the surface.

[0223] Further, in the write sequence of the second embodiment, when any memory cell MC is determined to be in the off state in the processing corresponding to the time points t223, t228, and t233 of the verification operation corresponding to any write cycle, as described with reference to Figure 21As described, in this write cycle (the write cycle corresponding to cycle k+1 of Figure 21 ), these memory cells MC, as weak write memory cells MC, perform writing to these memory cells MC. As a result, the threshold voltage of these memory cells MC increases.

[0224] In addition, in the write sequence of the second embodiment, in the write cycle corresponding to cycle k+1 of Figure 21 , the signal input to the gate electrode of the discharge transistor 43 corresponding to the memory cell MC is controlled by pattern XXL_A. Here, the threshold voltage of the memory cell MC controlled by pattern XXL_A observed through the verification operation is equal to the actual threshold voltage. Therefore, the threshold voltage observed through the verification operation in this write cycle appears to be smaller on the surface. As a result, the increase in the threshold voltage in the immediately previous programming operation is canceled. Therefore, in the verification operation corresponding to cycle k+1 of Figure 21 , the threshold voltage of these memory cells MC appears to be unchanged on the surface.

[0225] According to this method, memory cells MC whose threshold voltage is close to the target value to a certain extent can be detected with a smaller number of write cycles than in the first embodiment. Therefore, each memory cell MC can be used as a weak write memory cell MC before the programming voltage V PGM becomes greater than the required voltage. Therefore, compared with the first embodiment, the voltage V QPW supplied to the bit line BL QPW can be reduced.

[0226] [Third Embodiment]

[0227] Next, a semiconductor memory device according to the third embodiment will be described with reference to Figures 23 - 25 .

[0228] The semiconductor memory device according to the third embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment or the second embodiment. However, in the semiconductor memory device according to the third embodiment, fuzzy fine writing is performed. In fuzzy fine writing, fuzzy writing and fine writing are performed.

[0229] As Figure 23 shown, fuzzy writing and fine writing are performed in the following order. That is, first, fuzzy writing is performed on page PG0. Then, fuzzy writing is performed on page PG1, and fine writing is performed on page PG0. Next, fuzzy writing is performed on page PG2, and fine writing is performed on page PG1. Similarly hereinafter, fuzzy writing on page PGn P is performed as the 2n F (n F is a natural number)th write sequence, and fine writing on page PGn PFine writing of -1 is the 2n F +1st write sequence.

[0230] As Figure 24 shown, the fuzzy writing is performed on the page PG in the erased state. In the fuzzy writing, as Figure 24 shown, the threshold voltages of the memory cells MC in the page PG are controlled to the threshold voltages corresponding to the fuzzy S1 state to the fuzzy S15 state through 1 write sequence.

[0231] The fuzzy writing is basically performed in the same manner as the write sequence of the first embodiment or the second embodiment.

[0232] However, the verification voltages V VFY1 ' to the verification voltages V VFY15 ' are less than the verification voltages V Figure 11 described in the reference VFY1 to the verification voltages V VFY15 .

[0233] In addition, in the fuzzy writing, Figure 14 the voltage ΔV added to the programming voltage V PGM in step S106 can be greater than the voltage ΔV in the fine writing.

[0234] In addition, for example, Figure 15 in the example of

[0235] Figure 25 the on / off states of the memory cells MC corresponding to each state are each detected 2 times in the verification operation. On the other hand, in the fuzzy writing, the on / off states of the memory cells MC corresponding to each state can be each detected 2 times, or can be detected only 1 time. In the latter case, the voltage supplied to the bit line BL in the programming operation can be either the voltage V DD or the voltage V SRC these two kinds.

[0235] As Figure 25 shown, the fine writing is performed on the page PGn P and the page PGn P +1 after the fuzzy writing has been performed. In the fine writing, as Figure 25 shown, the memory cells MC in the fuzzy S1 state to the fuzzy S15 state in the page PGn P are respectively controlled to the S1 state to the S15 state. P

[0236] The fine writing is performed in the same manner as the write sequence of the first embodiment or the second embodiment.

[0237]

[0237] In addition, in the semiconductor memory device of the third embodiment, fuzzy fine writing is used during data writing. However, even if a writing method other than fuzzy fine writing is adopted, and the threshold voltages of the selected memory cell MC and the adjacent memory cells MC are adjusted to some extent in advance, a method such as adjusting the threshold voltage of the selected memory cell MC can be adopted thereafter.

[0238] For example Figure 26 and Figure 27 show an example in which the method exemplified in the third embodiment is applied to two-stage writing instead of fuzzy fine writing. In two-stage writing, the first-stage writing and the second-stage writing are performed.

[0239] The first-stage writing and the second-stage writing are performed, for example, in the same order as the order of the fuzzy writing and the fine writing exemplified in Figure 23 For example, the first-stage writing of the page PGn P is performed as the 2n-th writing sequence, and the second-stage writing of the page PGn P -1 is performed as the 2n P +1-th writing sequence.

[0240] As Figure 26 shown, the first-stage writing is performed on the erased page PG. In the first-stage writing, as Figure 26 shown, the memory cells MC S8 to S15 in the page PG are controlled to the threshold voltage corresponding to the M state through the first writing sequence.

[0241] The first-stage writing is performed by substantially the same method as the above-described fuzzy writing. However, in the first-stage writing, only one verification voltage is used in each writing cycle. This verification voltage is, for example, less than the verification voltage V VFY8 corresponding to the S8 state.

[0242] For example, as Figure 27 shown, the second-stage writing is performed in the same manner as the above-described fine writing.

[0243] [Other Embodiments]

[0244] The semiconductor memory devices of the first to third embodiments have been described above. However, such a configuration is merely an example, and the specific configuration, method, etc. can be appropriately adjusted.

[0245] For example Figure 18 and Figure 21In the example, a memory cell MC determined to be in a disconnected state during the verification operation in the k-th write cycle is used as a prohibited memory cell MC in write cycles after the (k + 2)-th cycle, or as a weak write memory cell MC in the (k + 2)-th or (k + 3)-th write cycle. However, this method is only an example, and the specific method can be adjusted as appropriate. For example, these memory cells MC can also be used as weak write memory cells MC in any write cycle after the (k + 4)-th cycle, rather than in the (k + 2)-th or (k + 3)-th cycle. Additionally, these memory cells MC can also be used as weak write memory cells in two or more write cycles.

[0246] In addition, for example Figure 18 and Figure 21 in the example, the verification operation of the (k + 1)-th write cycle is further performed on the memory cell MC determined to be in a disconnected state during the verification operation in the k-th write cycle, and the memory cell MC is classified into multiple types according to the results of these two verification operations. However, this method is only an example, and the specific method can be adjusted as appropriate. For example, the verification operations of two or more write cycles after the (k + 1)-th cycle can also be performed on the memory cell MC determined to be in a disconnected state during the verification operation in the k-th write cycle, and the memory cell MC is classified into multiple types according to the results of these three or more verification operations.

[0247] In addition, in the semiconductor memory devices of the first to third embodiments, the lower end of the semiconductor layer 120 is connected to the semiconductor substrate 100. Additionally, all the transistors included in the peripheral circuit PC are formed on the upper surface of the semiconductor substrate 100. However, this configuration is only an example. The methods such as the write sequence described above can also be applied to semiconductor memory devices having other structures. Hereinafter, the structure of such a semiconductor memory device is illustrated.

[0248] For example, Figure 28 the semiconductor memory device shown includes a semiconductor substrate 100, a transistor layer L provided above the semiconductor substrate 100 TR , and a memory cell array layer L provided above the transistor layer L TR . MCA .

[0249] The transistor layer L TR includes a plurality of transistors Tr. These plurality of transistors Tr are field-effect transistors having the upper surface of the semiconductor substrate 100 as a channel region. In the illustrated configuration, the peripheral circuit PC is constituted by these plurality of transistors Tr.

[0250] The structure of the memory cell array layer L MCA is basically the same as the structure on the semiconductor substrate 100 described with reference to Figure 9 etc. However, the memory cell array layer L MCAThere is a conductive layer 112 disposed below a plurality of conductive layers 110. In addition, the lower end of the semiconductor layer 120 is connected to the conductive layer 112 instead of the semiconductor substrate 100.

[0251] In addition, for example Figure 29 the memory die MD' illustrated in MCA has chips C TR and chips C MCA and chips C TR have a plurality of bonding electrodes P including copper (Cu), etc. I and are physically electrically connected via these plurality of bonding electrodes P. I

[0252] For example, as Figure 30 shown, the chip C MCA may include the structure on the semiconductor substrate 100 described with reference to Figure 9 or may also include the structure in the Figure 28 memory cell array layer L MCA . In addition, the chip C MCA may or may not include the transistor Tr. When the chip C MCA does not include the transistor Tr, the chip C MCA may or may not include the semiconductor substrate 100. In addition, when the chip C MCA includes the transistor Tr, as Figure 31 shown, the chip C MCA may include the transistor layer L and the memory cell array layer L described with reference to Figure 28 as TR and MCA .

[0253] The chip C TR has a semiconductor substrate 200 and a plurality of transistors Tr'. The semiconductor substrate 200 may be configured substantially the same as the semiconductor substrate 100, for example. The plurality of transistors Tr' are field-effect transistors having the upper surface of the semiconductor substrate 200 as the channel region. Figure 30 and Figure 31 in the example of, the peripheral circuit PC is constituted by the plurality of transistors Tr, Tr' included in the chip C MCA and the chip C TR .

[0254] In addition, in the case of adopting the structure as Figure 31 shown, for example, the structures in the row decoder RD and the voltage generation circuit VG described with reference to MCA etc. may also be implemented by the transistor Tr in the chip C Figure 4 . In addition, for example, the structures in the row decoder RD and the voltage generation circuit VG described with reference to TR etc. may also be implemented by the transistor Tr' in the chip CFigure 4 The sense amplifier module SAM, sequencer SQC, cache memory CM, address register ADR, instruction register CMR, status register STR, input / output control circuit I / O, and logic circuit CTR described, etc.

[0255] [Others]

[0256] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments or their variations are included within the scope or gist of the invention and are also included within the invention described in the claims and its equivalents.

[0257] [Description of Symbols]

[0258] MC: Memory cell

[0259] MCA: Memory cell array

[0260] BL: Bit line

[0261] WL: Word line.

Claims

1. A semiconductor memory device includes: A first memory string including a first memory cell; A second memory string including a second memory cell; A first bit line connected to the first memory string; A second bit line connected to the second memory string; A first word line connected to the first memory cell and the second memory cell; and A control circuit electrically connected to the first bit line, the second bit line, and the first word line; and In a first programming operation of a first write sequence for the first memory cell and the second memory cell, the control circuit supplies a first bit line voltage to the first bit line and the second bit line. In a second programming operation performed after the first programming operation, the control circuit supplies a second bit line voltage greater than the first bit line voltage or a third bit line voltage greater than the second bit line voltage to the first bit line and the second bit line. In a third programming operation performed after the second programming operation, the control circuit supplies the second bit line voltage to the first bit line and the third bit line voltage to the second bit line. In a fourth programming operation performed after the third programming operation, the control circuit supplies the third bit line voltage to the first bit line and the second bit line voltage to the second bit line.

2. The semiconductor memory device according to claim 1 includes: A third memory string including a third memory cell; and A third bit line connected to the third memory string; and The first word line is connected to the third memory cell, The control circuit is electrically connected to the third bit line, The control circuit In the first programming operation, supplies the first bit line voltage to the third bit line. In the second programming operation, supplies the second bit line voltage or the third bit line voltage to the third bit line. In the third programming operation, supplies the third bit line voltage to the third bit line. In the fourth programming operation, supplies the third bit line voltage to the third bit line.

3. The semiconductor memory device according to claim 1 or 2 Includes a first wiring electrically connected to the first word line, and The control circuit In the first programming operation, supplies a first programming voltage to the first wiring. In the second programming operation, supplies a second programming voltage greater than the first programming voltage to the first wiring. In the third programming operation, supplies a third programming voltage greater than the second programming voltage to the first wiring. In the fourth programming operation, supplies a fourth programming voltage greater than the third programming voltage to the first wiring.

4. The semiconductor memory device according to claim 3, wherein The control circuit In a first verification operation performed after the first programming operation and before the second programming operation, supplies a fourth bit line voltage greater than the second bit line voltage to the first bit line and the second bit line, and supplies a verification voltage less than the first programming voltage to the first wiring. In a second verification operation performed after the second programming operation and before the third programming operation, supplies the fourth bit line voltage to the first bit line and the second bit line, and supplies the verification voltage to the first wiring. In a third verification operation performed after the third programming operation and before the fourth programming operation, a first bit line voltage is supplied to the first bit line and the second bit line, and a verification voltage is supplied to the first wiring.

5. The semiconductor memory device according to claim 4, comprising a third memory string including third memory cells; and a third bit line connected to the third memory string; and the first word line is connected to the third memory cell, the control circuit is electrically connected to the third bit line, the control circuit in the first verification operation, supplies the fourth bit line voltage to the third bit line, in the second verification operation, supplies the fourth bit line voltage to the third bit line, in the third verification operation, supplies the first bit line voltage to the third bit line.

6. A semiconductor memory device, comprising: a first memory string including first memory cells; a second memory string including second memory cells; a first bit line connected to the first memory string; a second bit line connected to the second memory string; a first word line connected to the first memory cell and the second memory cell; a first voltage supply line electrically connected to the first bit line and the second bit line; a second voltage supply line electrically connected to the first bit line and the second bit line; a first voltage transfer circuit that conducts the first bit line to the first voltage supply line according to the input of a first signal and conducts the first bit line to the second voltage supply line according to the input of a second signal; a second voltage transfer circuit that conducts the second bit line to the first voltage supply line according to the input of a third signal and conducts the second bit line to the second voltage supply line according to the input of a fourth signal; and a control circuit electrically connected to the first voltage supply line, the second voltage supply line, the first voltage transfer circuit, the second voltage transfer circuit, and the first word line; and the control circuit, in a first programming operation of a first write sequence for the first memory cell and the second memory cell, supplies the first signal to the first voltage transfer circuit, supplies the third signal to the second voltage transfer circuit, in a second programming operation performed after the first programming operation, supplies the second signal to the first voltage transfer circuit, supplies the fourth signal to the second voltage transfer circuit, in a third programming operation performed after the second programming operation, in a state where the first signal has been supplied to the first voltage transfer circuit and the fourth signal has been supplied to the second voltage transfer circuit, switches the signal supplied to the first voltage transfer circuit from the first signal to the second signal, and in a fourth programming operation performed after the third programming operation, in a state where the second signal has been supplied to the first voltage transfer circuit and the third signal has been supplied to the second voltage transfer circuit, switches the signal supplied to the second voltage transfer circuit from the third signal to the fourth signal.

7. The semiconductor memory device according to claim 6, wherein the control circuit In the second programming operation, after the first signal has been supplied to the first voltage transfer circuit and in a state where the third signal is supplied to the second voltage transfer circuit, the signal supplied to the first voltage transfer circuit is switched from the first signal to the second signal, and the signal supplied to the second voltage transfer circuit is switched from the third signal to the fourth signal.

8. The semiconductor memory device according to claim 7, comprising: a third memory string including third memory cells; a third bit line connected to the third memory string; and a third voltage transfer circuit that conducts the third bit line to the first voltage supply line according to an input of a fifth signal and conducts the third bit line to the second voltage supply line according to an input of a sixth signal; and the first word line is electrically connected to the third memory cell, the control circuit in the first programming operation, supplies the fifth signal to the third voltage transfer circuit, in the second programming operation, supplies the sixth signal to the third voltage transfer circuit, in the third programming operation, supplies the sixth signal to the third voltage transfer circuit, in the fourth programming operation, supplies the sixth signal to the third voltage transfer circuit.

9. The semiconductor memory device according to any one of claims 6 to 8, comprises a first wiring electrically connected to the first word line, and the control circuit in the first programming operation, supplies a first programming voltage to the first wiring, in the second programming operation, supplies a second programming voltage greater than the first programming voltage to the first wiring, in the third programming operation, supplies a third programming voltage greater than the second programming voltage to the first wiring, in the fourth programming operation, supplies a fourth programming voltage greater than the third programming voltage to the first wiring.

10. The semiconductor memory device according to claim 9, wherein the control circuit in a first verification operation performed after the first programming operation and before the second programming operation, supplies the second signal to the first voltage transfer circuit, supplies the fourth signal to the second voltage transfer circuit, supplies a verification voltage less than the first programming voltage to the first wiring, in a second verification operation performed after the second programming operation and before the third programming operation, supplies the second signal to the first voltage transfer circuit, supplies the fourth signal to the second voltage transfer circuit, supplies the verification voltage to the first wiring, in a third verification operation performed after the third programming operation and before the fourth programming operation, supplies the first signal to the first voltage transfer circuit, supplies the third signal to the second voltage transfer circuit, supplies the verification voltage to the first wiring.

11. The semiconductor memory device according to claim 10, comprising: a third memory string including third memory cells; a third bit line connected to the third memory string; and A third voltage transfer circuit that conducts the third bit line to the first voltage supply line according to the input of a fifth signal and conducts the third bit line to the second voltage supply line according to the input of a sixth signal; and The first word line is electrically connected to the third memory cell, The control circuit In the first verification operation, Supplies the sixth signal to the third voltage transfer circuit, In the second verification operation, Supplies the sixth signal to the third voltage transfer circuit, In the third verification operation, Supplies the fifth signal to the third voltage transfer circuit.

12. The semiconductor memory device according to claim 10, comprising: A first transistor having a first gate electrode connected to the first bit line; A second transistor having a second gate electrode connected to the second bit line; A first latch circuit electrically connected to the first transistor; and A second latch circuit electrically connected to the second transistor; and In the first verification operation or the second verification operation, only one of the data latched in the first latch circuit and the data latched in the second latch circuit is switched.

13. The semiconductor memory device according to claim 11, comprising: A first transistor having a first gate electrode connected to the first bit line; A second transistor having a second gate electrode connected to the second bit line; A first latch circuit electrically connected to the first transistor; and A second latch circuit electrically connected to the second transistor; and In the first verification operation or the second verification operation, only one of the data latched in the first latch circuit and the data latched in the second latch circuit is switched.

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