Memory test circuit

Abstract

The present invention provides a memory test circuit, comprising: a first latched circuit for receiving a first input address and an error indication signal to generate a first address; a first electronic fuse bank for receiving the first address to generate an output address; a second latched circuit for receiving the error indication signal; a second electronic fuse bank for generating a damage indication signal according to the output after the second latched circuit receives the error indication signal; and a comparison circuit for starting the second latched circuit according to the relationship between the first address and a second input address and the state of the first latched circuit or the first electronic fuse bank.

Description

Technical Field

[0001] The present invention relates to a memory test circuit, and particularly to a memory test circuit capable of automatically testing the types of errors. Background Art

[0002] The testing of a memory can generally be divided into a pre-packaging test mode (chip probe, CP) and a final test mode (Final Test, FT). The pre-packaging test is also called a bare die test, and the final test mode is performed after the memory is packaged. A memory usually has multiple redundant word lines. When an error is found in a word line of the memory, a redundant word line is used to replace the faulty word line. However, in the final test mode, the memory can only store a very small number of word line error addresses, that is, only a very small number of redundant word lines can be used. When the number of faulty word lines is greater than the number of word line error addresses that can be stored, the memory is determined to be irreparable.

[0003] However, when a memory has an error, it may be because the number of faulty word lines is greater than the number of word line error addresses that can be stored, but it may also be due to other reasons. And the current memory test methods require a large amount of manpower and time to confirm what type of error it is when the memory has an error. Summary of the Invention

[0004] Therefore, an object of the present invention is to provide a memory test circuit that can automatically provide information on the types of errors.

[0005] A memory test circuit includes: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first electronic fuse bank for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal; a second electronic fuse bank for generating a damage indication signal according to the output after the second latch circuit receives the error indication signal; and a comparison circuit for activating the second latch circuit according to the relationship between the first address and a second input address and the state of the first latch circuit or the first electronic fuse bank.

[0006] According to the foregoing embodiments, the memory test circuit provided by the present invention can provide reference information on the types of errors, thus improving the problem in the prior art that a large amount of manpower and time are required to confirm what type of error it is. Brief Description of the Drawings

[0007] Figure 1 Shows a block diagram of a memory test circuit according to an embodiment of the present invention.

[0008] Figure 2 and Figure 3 illustrates Figure 1 the operation diagrams of the memory test circuit shown in different states.

[0009] Figure 4 illustrates the fault analysis status of multiple memory elements.

[0010]

Symbol Explanation

[0011] 10, 10’, 10_1, 10_2…10_m Memory elements

[0012] 12 Memory test circuit

[0013] 14 Decoder

[0014] 16 Memory array

[0015] 122 Comparison circuit

[0016] C1 Memory cell

[0017] LA_1, LA_2 Latch circuit

[0018] EG_1, EG_2 Electronic fuse group

[0019] WL_1 - WL_r Word line

[0020] RWL_1 Redundant word line

[0021] XA Receiver Detailed implementation

[0022] The content of the present invention will be described below with multiple embodiments. Please also note that the components in each embodiment can be implemented by hardware (such as devices or circuits) or firmware (such as writing at least one program in a microprocessor). In addition, the "first", "second" and similar descriptions in the following descriptions are only used to define different components, parameters, data, signals or steps, and are not used to limit their order.

[0023] Figure 1 Illustrates the block diagram of the memory test circuit according to an embodiment of the present invention. The detailed operation will be described below. Moreover, the memory test circuit described in the following embodiments is used in the final test mode, but the memory test circuit provided by the present invention can also be used in different modes. In addition, the memory test circuit provided by the present invention can also be used on other types of semiconductor devices.

[0024] The memory element 10 includes a memory test circuit 12, a decoder 14, and a memory array 16. The memory array 16 includes a plurality of memory cells C1. The memory cells C1 are arranged in a matrix and are electrically coupled to corresponding word lines and bit lines.

[0025] In this embodiment, the memory array 16 is configured with at least one redundant word line RWL_1. When the memory element 10 enters the final test mode and a damaged normal word line is detected, the damaged word line is replaced by the redundant word line in the normal mode. For example, when the word line WL_1 among the word lines WL_1 to WL_r is detected as a damaged word line, when the memory element 10 performs access in the normal mode, the decoder 14 selects the redundant word line RWL1 to replace the damaged word line WL_1. Since the area of the memory element 10 is limited, the number of redundant word lines configured in the memory array 16 is limited. If the number of damaged word lines exceeds the number of redundant word lines, the memory element 10 is considered irreparable.

[0026] Refer to Figure 1 , the memory test circuit 12 includes latch circuits LA_1, LA_2, an electronic fuse bank EG_1, an electronic fuse bank EG_2, and a comparison circuit 122. The electronic fuse banks EG_1 and EG_2 each include at least one electronic fuse (E-fuse). The latch circuit LA_1 is composed of a plurality of latches (not shown), which is used to receive a first input address ADD1 and an error indication signal EAIO via a receiving end XA (such as an address pin) to generate a first address AD1 and a latch circuit status signal AAIO[0], where the error indication signal EAIO is used to indicate whether the first input address ADD1 is an incorrect address (i.e., whether the address corresponds to a damaged word line). The electronic fuses (not shown) in the first electronic fuse bank EG_1 are used to receive the first address AD1 and the latch circuit status signal AAIO[0] to generate an output address ADDR and a fuse indication signal EN in the burn mode. When the memory element 10 performs access in the normal mode, the memory array 16 uses the redundant word line based on the output address ADDR to replace the damaged word line.

[0027] In one embodiment, the error indication signal EAIO is generated by sending a test pattern to the input end XA. Then, after activating a corresponding word line, a data reading operation is performed, and then the data is transmitted to the receiving end XA for output. A circuit (not shown) is used to compare whether the output data is indeed the written data, and the error indication signal EAIO is the result of the comparison.

[0028] The latch circuit LA_2 is composed of a latch (not shown), which is used to receive the error indication signal EAIO to generate a latch circuit status signal AAIO[1]. The electronic fuse bank EG_2 is used to receive the latch circuit status signal AAIO[1] to generate a damage indication signal OV. The comparison circuit 122 is used to compare the first address AD1 with a second input address received via the receiving terminal XA, so as to generate a comparison signal cmpen to activate the latch circuit LA_2. The damage indication signal OV is used to indicate whether the number of damaged word lines found in the final test mode exceeds the configured number of redundant word lines.

[0029] Referring Figure 1 to, the decoder 14 can be a row decoder or a column decoder, that is, the redundant word line RWL1 can be a row redundant word line or a column redundant word line. The operation mode of the memory element 10 according to the embodiments of the present invention will be described below with a more detailed example. For the sake of simplicity, Figure 2 and Figure 3 the memory element 10' in

[0030] The final test mode includes two stages: a staging / comparison stage and a burn-in stage. In the staging / comparison stage, the latch circuit LA_1 receives the serially input input address ADD1 and the error indication signal EAIO via the receiving terminal XA, where the error indication signal EAIO is used to indicate whether the input address ADD1 is an incorrect address. In the burn-in stage, the electronic fuse bank EG_1 fuses the corresponding electronic fuses according to the address AD1 and the latch circuit status signal AAIO[0].

[0031] In the final test mode, there are three situations for the latch circuit LA_1 and the electronic fuse bank EG_1. In the first situation, no signals are input to the latch circuit LA_1 and the electronic fuse bank EG_1. At this time, as Figure 2 shown, if the latch circuit LA_1 receives a new input address ADD1[3:12], and the error indication signal EAIO indicates that the address ADD1[3:12] is an incorrect address, then the latch circuit LA_1 stores the address ADD1[3:12] and the error indication signal EAIO, and correspondingly generates a first address AD1[3:12] and a latch circuit status signal AAIO[0], where the latch circuit status signal AAIO[0] represents the usage status (used) of the latch circuit LA_1, and the latch circuit status signal AAIO[0] will be sent to the comparison circuit 122 to enable the comparison operation.

[0032] In this embodiment, the electronic fuse group EG_1 includes 11 electronic fuses (not shown). After receiving the first address AD1[3:12] and the latch circuit status signal AAIO[0], these electronic fuses generate an output address ADDR[3:12] and a fuse status signal EN during the programming phase, where the fuse status signal EN indicates that the 11 electronic fuses of the electronic fuse group EG_1 have been used. When the memory element 10 accesses in the normal mode, if the input address INA is the same as the address ADDR[3:12], the decoder 14 will select and activate the redundant word line RWL1 instead of the original normal word line.

[0033] In the second situation, the latch circuit LA_1 has stored the input address ADD1[3:12] and the error indication signal EAIO, and generates the first address AD1[3:12] and the latch circuit status signal AAIO[0]. At this time, as Figure 3 shown, when the latch circuit LA_1 receives a new input address ADD2[3:12], the comparison circuit 122 can start comparing the first address AD1[3:12] and the new input address ADD2[3:12] because it has been enabled by the latch circuit status signal AAIO[0]. If the new input address ADD2[3:12] is the same as the first address AD1[3:12], the comparison circuit 122 does not generate a comparison signal cmpen, so the latch circuit LA_2 is not activated. If the new input address ADD2[3:12] is different from the address AD1[3:12], the comparison circuit 122 generates a comparison signal cmpen, so the latch circuit LA_2 is activated. At this time, if the error indication signal EAIO received by the latch circuit LA_2 indicates that the input address ADD2[3:12] is an incorrect address, the latch circuit LA_2 generates a latch circuit status signal AAIO[1], where the latch circuit status signal AAIO[1] indicates the usage status (used) of the latch circuit LA_2.

[0034] During the programming phase, after the electronic fuse group EG_1 receives the first address AD1[3:12] and the latch circuit status signal AAIO[0], it generates an output address ADDR[3:12] and a fuse status signal EN. The electronic fuse EG_2 generates a damage indication signal OV after receiving the latch circuit status signal AAIO[1], where the damage indication signal OV indicates that two normal word lines in the memory array 16 are damaged. Since the memory element 10' is only configured with one redundant word line RWL_1, when the tester reads the damage indication signal OV via the XIO terminal, it can be clearly known that the number of damaged word lines in the memory element 10' exceeds the number of configured redundant word lines, so no further fault analysis is required.

[0035] In the third scenario, 11 electronic fuses of the electronic fuse group EG_1 have been used, so the fuse status signal EN has changed its logic level. As Figure 3 shown, when the fuse status signal EN changes its logic level, it forces the comparison circuit 122 to generate a comparison signal cmpen, so the latch circuit LA_2 is activated. At this time, if the error indication signal EAIO received by the latch circuit LA_2 indicates that the new input address ADD2[3:12] is an error address, the latch circuit LA_2 generates a latch circuit status signal AAIO[1]. During the programming phase, after receiving the latch circuit status signal AAIO[1], the electronic fuse EG_2 generates a damage indication signal OV, where the damage indication signal OV represents that the number of damaged word lines in the memory element 10' exceeds the configured number of redundant word lines.

[0036] Accordingly, when performing a final test on the memory element 10', if the damage indication signal OV has a first logic level (e.g., 0) and the memory element 10' shows an error status, it means that the error in the memory element 10' is not due to the number of damaged word lines exceeding the configured number of redundant word lines (i.e., exceeding a predetermined number of redundant word lines), that is, there may still be available redundant word lines. Therefore, further analysis of the memory element is required to confirm whether there are other errors. For example, confirm whether the error address is not completely written into the electronic fuse group, or the quality of the redundant word lines is poor, or the test pattern is incorrect. On the contrary, when the damage indication signal OV has a second logic level (e.g., 1) and the memory element 10 shows an error status, it means that the number of damaged word lines exceeds the configured number of redundant word lines, that is, there are no available redundant word lines but the normal word lines are still damaged. Therefore, it can be directly determined that the memory element 10' is irreparable.

[0037] As mentioned above, the electronic fuse group EG_1 is not limited to storing only one set of error addresses. In an embodiment, the electronic fuse group EG_1 can store multiple sets of error addresses. In such an embodiment, multiple comparison circuits are required to compare whether the new input address is the same as multiple sets of stored error addresses. Finally, the tester reads the damage indication signal OV through the XIO terminal to know whether the number of damaged word lines in the memory element 10' exceeds the configured number of redundant word lines, and then performs further fault analysis.

[0038] According to the foregoing description, the memory test circuit of the present application can be briefly described as follows: A memory circuit includes a plurality of latch circuits and a plurality of electronic fuse groups. At least one of the latch circuits (for example, the first latch circuit LA_1) and at least one of the electronic fuse groups (for example, the first electronic fuse group EG_1) determine whether to store the first input address according to whether the first input address is an error address. And at least one of the other latch circuits (for example, the second latch circuit LA_2) and at least one of the other electronic fuse groups (for example, the second electronic fuse group EG_2) in the latch circuit generate a damage indication signal based on the states of the latch circuit and the electronic fuse group that store the first input address and the relationship between the first input address and the second input address. The damage indication signal is used to indicate whether the number of damaged word lines exceeds a predetermined redundant word line number.

[0039] Figure 4 Show the failure analysis status of a plurality of memory elements (after the memory IC is packaged) 10_1, 10_2,..., 10_m. The tester first reads and writes data to the cells in 10_1, 10_2,..., 10_m. When the output data is equal to the input data, the memory element shows pass; when the output data is not equal to the input data, the memory element shows fail (or an error state). At this time, the tester reads the damage indication signal OV from the XIO terminal leads of each memory element, and can clearly know that the number of damaged word lines in those memory elements is less than the configured redundant word line number. Since the number of damaged word lines in those memory elements is less than the configured redundant word line number, but the memory element still shows an error state, the tester will perform further failure analysis on it.

[0040] The foregoing are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims

1. A memory test circuit, comprising: A first latch circuit, configured to receive a first input address and an error indication signal to generate a first address, where the error indication signal is used to indicate whether the first input address is an error address; A first electronic fuse bank, configured to receive the first address to generate an output address; A second latch circuit, configured to receive the error indication signal; A second electronic fuse bank, configured to generate a damage indication signal according to the output after the second latch circuit receives the error indication signal, where the damage indication signal is used to indicate whether the number of damaged word lines exceeds a predetermined redundant word line number; And A comparison circuit, configured to compare the first address and a second input address, and generate a comparison signal according to the relationship between the first address and the second input address and the state of the first latch circuit or the first electronic fuse bank to activate the second latch circuit.

2. The memory test circuit according to claim 1, used in a memory element including a memory array. When the memory element performs access in a normal mode, the memory array uses redundant word lines to replace damaged word lines based on the output address.

3. The memory test circuit according to claim 1, where the first latch circuit further generates a first latch circuit status signal according to the first input address and the error indication signal, and the first latch circuit status signal represents the usage state of the first latch circuit and is used to enable the comparison circuit.

4. The memory test circuit according to claim 1, where the second latch circuit further outputs a second latch circuit status signal according to the error indication signal, and the second latch circuit status signal represents the usage state of the second latch circuit and the second electronic fuse bank generates the damage indication signal according to the second latch circuit status signal.

5. The memory test circuit according to claim 1, where when at least one electronic fuse in the first electronic fuse bank has been used to record an error address, the second latch circuit is forced to be activated.

6. The memory test circuit according to claim 5, where the first electronic fuse bank further generates a fuse indication signal, and the fuse indication signal is used to indicate the usage state of the first electronic fuse bank, and the comparison circuit receives the fuse indication signal; where when at least one electronic fuse in the first electronic fuse bank has been used to record an error address, the fuse indication signal causes the comparison circuit to forcefully activate the second latch circuit.

7. The memory test circuit according to claim 5, after the second latch circuit is forced to be activated, if the error indication signal received by the second latch circuit indicates that the second input address is an error address, the second latch circuit generates a second latch circuit status signal, and the second latch circuit status signal represents the usage state of the second latch circuit and the second electronic fuse bank generates the damage indication signal according to the second latch circuit status signal.

8. The memory test circuit according to claim 1, wherein if the first latch circuit receives the first input address and there is no signal input to the first latch circuit and the first electronic fuse bank yet, and the error indication signal indicates that the first input address is an error address, the first latch circuit stores the first input address and the error indication signal to generate the first address.

9. The memory test circuit according to claim 1, wherein when the first latch circuit has stored the first input address and the error indication signal and generated the first address, the comparison circuit compares the second input address with the first address; if the second input address is different from the first address, the comparison circuit activates the second latch circuit, and if the second input address is the same as the first address, the comparison circuit does not activate the second latch circuit.

10. A memory test circuit, comprising: a plurality of latch circuits and a plurality of electronic fuse banks: at least one of these latch circuits and at least one of these electronic fuse banks determine whether to store the first input address according to whether the first input address is an error address; at least one other of these latch circuits and at least one other of these electronic fuse banks generate a damage indication signal based on the states of the latch circuit and the electronic fuse bank that store the first input address and the relationship between the first input address and the second input address, and the damage indication signal is used to indicate whether the number of damaged word lines exceeds a predetermined redundant word line number.

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