Page buffer, memory, three-dimensional memory and memory system

Abstract

The present application discloses a page buffer, a memory, a three-dimensional memory and a memory system, wherein the page buffer includes first transistor regions and second transistor regions arranged alternately along a first direction; each first transistor region includes at least two first sub-regions arranged along a second direction, and each second transistor region includes at least two second sub-regions arranged along the second direction; at least two well contact structures extending along the first direction, the well contact structures being respectively located between adjacent first sub-regions and between adjacent second sub-regions; at least two electrical connection layers extending along the second direction, the electrical connection layers being used to connect all well contact structures within each first transistor region; the electrical connection layers are also used to connect all well contact structures within each second transistor region; the first direction is perpendicular to the second direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a page buffer, a memory, a three-dimensional memory, and a memory system. Background Art

[0002] In 3D NAND technology, as the number of stacked layers continues to increase, the size of the array wafer on a chip of the same capacity continues to decrease. Therefore, the size of the peripheral circuit (CMOS) wafer that matches the array wafer also needs to be reduced accordingly. Within the entire peripheral circuit wafer, the page buffer occupies a large area of ​​the wafer. Therefore, reducing the size of the page buffer can greatly help reduce the size of the entire wafer. How to optimize the structure of the page buffer and reduce its size has become an urgent problem in this field. Summary of the Invention

[0003] In view of this, the present application provides a page buffer, a memory, a three-dimensional memory, and a memory system to solve at least one technical problem in the prior art.

[0004] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0005] According to a first aspect of an embodiment of the present application, a page buffer is provided, comprising:

[0006] First transistor regions and second transistor regions are alternately arranged along a first direction; each of the first transistor regions includes at least two first sub-regions arranged along a second direction, and each of the second transistor regions includes at least two second sub-regions arranged along the second direction;

[0007] at least two well contact structures extending along the first direction, the well contact structures being located between adjacent first sub-regions and between adjacent second sub-regions respectively;

[0008] at least two electrical connection layers extending along the second direction, the electrical connection layers being used to connect all well contact structures in each first transistor region; the electrical connection layers being further used to connect all well contact structures in each second transistor region;

[0009] The first direction is different from the second direction.

[0010] Optionally, the first direction is perpendicular to the second direction.

[0011] Optionally, a width of the electrical connection layer in the first direction is smaller than a width of the well contact structure in the second direction.

[0012] Optionally, the page buffer further includes: an array common source region, the array common source region is located between adjacent first sub-regions and between adjacent second sub-regions, and the well contact structure is provided in the array common source region.

[0013] Optionally, the well contact structure in each of the first transistor regions is arranged along the second direction; and the well contact structure in each of the second transistor regions is arranged along the second direction.

[0014] Optionally, the electrical connection layer is disposed above the first transistor region and the second transistor region, and the at least two electrical connection layers are arranged along a first direction.

[0015] Optionally, the electrical connection layer above each first transistor region is connected to the well contact structure within the first transistor region through multiple contacts; the electrical connection layer above each second transistor region is connected to the well contact structure within the second transistor region through multiple contacts.

[0016] Optionally, a distance between adjacent first transistor regions and second transistor regions is less than 0.8 um.

[0017] Optionally, the length of the well contact structure located in the first transistor region in the first direction is smaller than the width of the first transistor region in the first direction; the length of the well contact structure located in the second transistor region in the first direction is smaller than the width of the second transistor region in the first direction.

[0018] Optionally, the first transistor region is an N-type transistor region; and the second transistor region is a P-type transistor region.

[0019] A second aspect of an embodiment of the present application provides a memory, characterized in that it includes a page buffer as described in the first aspect.

[0020] A third aspect of an embodiment of the present application provides a three-dimensional memory, including the page buffer as described in the first aspect.

[0021] A fourth aspect of an embodiment of the present application provides a memory system, comprising the memory as described in the second aspect or the three-dimensional memory as described in the third aspect; and a storage controller coupled to the memory or the three-dimensional memory.

[0022] The present application discloses a page buffer, a memory, a three-dimensional memory, and a memory system, wherein the page buffer includes first and second transistor regions arranged alternately along a first direction; each first transistor region includes at least two first sub-regions arranged along a second direction, and each second transistor region includes at least two second sub-regions arranged along the second direction; at least two well contact structures extending along the first direction, the well contact structures being located between adjacent first sub-regions and between adjacent second sub-regions, respectively; at least two electrical connection layers extending along the second direction, the electrical connection layers being used to connect all well contact structures within each first transistor region; and the electrical connection layers being used to connect all well contact structures within each second transistor region; the first direction being perpendicular to the second direction. In embodiments of the present application, well contact structures are provided by utilizing gaps between adjacent first sub-regions and gaps between adjacent second sub-regions, and the well contact structures of each first transistor region and each second transistor region are connected via the electrical connection layers, thereby achieving electrical connection between the well contact structures of each first transistor region and the well contact structures of each second transistor region. By changing the distribution of the well contact structures, the present application reduces the width of the page buffer in the first direction, meeting the requirements of chip miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the structure of a traditional page buffer provided in an embodiment of the present application;

[0024] Figure 2 A schematic diagram of the structure of a page buffer provided in an embodiment of the present application Figure 1 ;

[0025] Figure 3 A schematic diagram of the structure of a page buffer provided in an embodiment of the present application Figure 2 ;

[0026] Figure 4 A schematic diagram of a partial structure of a page buffer provided in an embodiment of the present application;

[0027] Figure 5A A schematic diagram of the structure of a memory system provided in an embodiment of the present application Figure 1 ;

[0028] Figure 5B A schematic diagram of the structure of a memory system provided in an embodiment of the present application Figure 2 . DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0030] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0031] In addition, the accompanying drawings are merely schematic illustrations of the present application and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the blocks shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0032] In 3D NAND technology, all control circuits are located on the peripheral circuit wafer, and the storage cells are located on the array wafer. After the peripheral circuit wafer and the array wafer are bonded, electrical leads are made from the array wafer side. As the number of layers of the memory array in the array wafer continues to increase, the size of the array wafer continues to decrease. Therefore, the size of the peripheral circuit wafer bonded to it also needs to be continuously reduced accordingly. The page buffer occupies a large part of the space in the peripheral circuit wafer. Therefore, reducing the size of the page buffer will greatly help reduce the size of the entire chip.

[0033] See also Figure 1 , Figure 1 A schematic structural diagram of a conventional page buffer is provided for an embodiment of the present application, wherein the page buffer is composed of first transistor regions 101 and second transistor regions 102 alternately arranged along a first direction, and a well contact structure 103 extending along a second direction is provided between adjacent first transistor regions 101 and second transistor regions 102. The well contact structure 103 is used to lead out the wells of all transistor units in each first transistor region 101 and to lead out the wells of all transistor units in each second transistor region.

[0034] Exemplarily, the first transistor region 101 can be a P-type transistor region, and the second transistor region 102 can be an N-type transistor region. Of course, the first transistor region 101 can also be an N-type transistor region. In this case, the second transistor region 102 is a P-type transistor region. The P-type transistor region and the N-type transistor region are arranged alternately along the first direction, and a well contact structure 103 is set between adjacent P-type transistor regions and N-type transistor regions to lead out the wells of the P-type transistor region and the N-type transistor region to achieve electrical connection between each transistor unit in the P-type transistor region and the N-type transistor region. The above structure is a traditional page buffer structure. However, this connection method is not conducive to improving the size of the page buffer and cannot meet the needs of chip miniaturization. Here, the first direction is the Y-axis direction, and the second direction is the X-axis direction.

[0035] Based on this, the following embodiments of this application are proposed.

[0036] See also Figure 2 , Figure 2 A schematic diagram of the structure of a page buffer provided in an embodiment of the present application Figure 1 , the page buffer comprises:

[0037] First transistor regions 201 and second transistor regions 202 are alternately arranged along a first direction; each first transistor region 201 includes at least two first sub-regions 2011 arranged along a second direction, and each second transistor region 202 includes at least two second sub-regions 2021 arranged along the second direction;

[0038] at least two well contact structures 203 extending along the first direction, the well contact structures 203 being located between adjacent first sub-regions 2011 and between adjacent second sub-regions 2021 ;

[0039] At least two electrical connection layers (not shown in the figure) extending along the second direction, the electrical connection layers are used to connect all well contact structures 203 in each first transistor region 201; the electrical connection layers are also used to connect all well contact structures 203 in each second transistor region 202; the first direction is different from the second direction.

[0040] Here, the first direction is the Y-axis direction, and the second direction is the X-axis direction.

[0041] It should be noted that Figure 2 Only one first transistor region and one second transistor region are illustrated.

[0042] In this embodiment, the first direction is perpendicular to the second direction. The first transistor region 201 may be a P-type transistor region, and the second transistor region 202 may be an N-type transistor region. Of course, the first transistor region 201 may also be an N-type transistor region, in which case the second transistor region 202 is a P-type transistor region. Here, the first transistor region 201 and the second transistor region 202 are transistor regions of different types. Specifically, the first transistor region 201 may include a plurality of P-type transistor units, and these P-type transistor units may be arranged in an array, and the second transistor region 202 may include a plurality of N-type transistor units, and these N-type transistor units may be arranged in an array.

[0043] Each well contact structure 203 is used to lead out the electrical wells in two adjacent first sub-regions 2011, or to lead out the electrical wells in two adjacent second sub-regions 2021, thereby achieving electrical connections between the transistor units in the first sub-region 2011 and between the transistor units in the second sub-region 2021. The electrical connection layer corresponding to each first transistor region 201 is used to electrically connect all the well contact structures 203 located in the first transistor region 201, thereby achieving electrical connections between all the well contact structures 203 in the first transistor region 201. The electrical connection layer corresponding to each second transistor region 202 is used to electrically connect all the well contact structures 203 located in the second transistor region 202, thereby achieving electrical connections between all the well contact structures 203 in the second transistor region 202.

[0044] In this embodiment, the electrical connection layer is disposed above the first transistor region and the second transistor region, and the at least two electrical connection layers are arranged along a first direction. Here, the electrical connection layer may be a metal layer.

[0045] Here, the electrical connection layer is located on a different layer from the first transistor region 201 and the second transistor region 202. In the first direction, the first transistor regions 201 and the second transistor regions 202 are arranged alternately, with at least two electrical connection layers arranged at equal intervals along the first direction. The intervals can be equal to the width of the first transistor region 201 or the second transistor region 202 in the first direction. The electrical connection layer corresponding to each first transistor region 201 is used to electrically connect all well contact structures 203 located in that first transistor region 201; the electrical connection layer corresponding to each second transistor region 202 is used to electrically connect all well contact structures 203 located in that second transistor region 202. This enables electrical connection between all well contact structures in each first transistor region, allowing electrical control of all well contact structures in that first transistor region through the electrical connection layer corresponding to each first transistor region. Similarly, electrical connection between all well contact structures in each second transistor region is also achieved, allowing electrical control of all well contact structures in that second transistor region through the electrical connection layer corresponding to each second transistor region.

[0046] This embodiment utilizes the gaps between adjacent first sub-regions and the gaps between adjacent second sub-regions to provide well contact structures. Furthermore, an electrical connection layer is provided to connect the well contact structures of each first transistor region and the well contact structures of each second transistor region. This achieves electrical connection between the well contact structures of each first transistor region and the well contact structures of each second transistor region. This reduces the width of the page buffer in the first direction, meeting the requirements of chip miniaturization. Because the electrical connection layer is provided above the first and second transistor regions, there is no need to reserve a gap between the first and second transistor regions, meaning there is no need to increase the width of the page buffer in the first direction.

[0047] In this embodiment, the electrical connection layer above each first transistor region is connected to a well contact structure within the first transistor region via multiple contacts; and the electrical connection layer above each second transistor region is connected to a well contact structure within the second transistor region via multiple contacts. Here, the electrical connection layer may be a metal layer, and the contacts may be metal vias.

[0048] In some embodiments, see Figure 3 , Figure 3 A schematic diagram of the structure of a page buffer provided in an embodiment of the present application Figure 2. Among them, the page buffer also includes: an array common source (ACS) region 204, the array common source region 204 is located between adjacent first sub-regions 2011 and between adjacent second sub-regions 2021, and the well contact structure 203 is provided in the array common source region 204. It should be noted that the width of the array common source region 204 is sufficient to accommodate the well contact structure 203. In the second direction of the page buffer, there are two arrangements, namely, the first sub-region 2011-array common source region 204-first sub-region 2011, or the second sub-region 2021-array common source region 204-second sub-region 2021. The number of alternating arrangements is determined according to actual needs and is not limited to this.

[0049] In one embodiment, the first sub-region 2011 and the second sub-region 2021 have the same width in the first direction, approximately 40 μm. This means that the spacing between two adjacent array common source regions 204 is approximately 40 μm. The maximum distance between the transistor cells in the first sub-region 2011 and the second sub-region 2021 and the array common source region 204 is approximately 20 μm. This ensures both the electrical stability of the transistor cells in the first sub-region 2011 and the second sub-region 2021 and the compactness of the overall page buffer structure.

[0050] In one embodiment, Figure 4 As shown, Figure 4 A schematic diagram of a partial structure of a page buffer provided in an embodiment of the present application is shown. Figure 4 It is used to illustrate the structure of the transistor units on both sides of the array common source region 204. Each transistor unit includes an active area 206 (Active Area, AA) and a gate 205 (Gate). In the figure, a1 represents the width of the well contact structure 203 in the second direction, a2 represents the length of the gate 205 of the left transistor unit extending toward the well contact structure 203 in the second direction, a3 represents the spacing between the active areas of two adjacent transistor units, a4 represents the distance from the gate 205 to the well contact structure 203; and a5 represents the length of the gate 205 of the right transistor unit extending toward the well contact structure 203 in the second direction. It should be noted that in actual applications, the values ​​of a2 and a5 are usually the same.

[0051] In this embodiment, the sum of the width of the well contact structure 203 in the second direction, the length of the gates 205 on both sides extending toward the well contact structure 203 in the second direction, and the distance between the gates 205 on both sides and the well contact structure 203 is equal to the active area spacing between two adjacent transistor units, that is, a1, a2, a3, a4, and a5 satisfy the following relationship:

[0052] a3=a1+a2+2a4+a5;

[0053] In a specific example, when 12 columns of transistor units are provided in the second direction in the first sub-region 2011 or the second sub-region 2021, the values ​​of the parameters may be: a1=0.2um, a2=0.072um, a3=0.716um, a4=0.186um, a5=a2=0.072um.

[0054] In another specific example, when 8 columns of transistor units are provided in the second direction in the first sub-region 2011 or the second sub-region 2021, the values ​​of the parameters may be: a1=0.15um, a2=0.03um, a3=0.478um, a4=0.134um, a5=a2=0.03um.

[0055] In this embodiment, the width of the array common source region 204 is sufficient to accommodate the well contact structure 203, and the specific width can be flexibly set according to actual needs. When the first sub-region 2011 and the second sub-region 2021 have more transistor units arranged in the second direction, the width of the array common source region 204 can be adaptively increased; when the first sub-region 2011 and the second sub-region 2021 have fewer transistor units arranged in the second direction, the width of the array common source region 204 can be adaptively reduced. Therefore, the size of the page buffer can be further reduced while ensuring stable electrical connections between the various structures.

[0056] In some embodiments, the distance between adjacent first transistor regions 201 and second transistor regions 202 is less than 0.8 um.

[0057] In a traditional page buffer, the distance between adjacent first transistor regions and second transistor regions with a well contact structure is usually 1.2um or 1um, while the distance between adjacent first transistor regions and second transistor regions without a well contact structure is usually 0.93um. The traditional page buffer sets a well contact structure in the gap area between the adjacent first transistor regions and the second transistor regions. The well contact structure is used to lead out the wells in the two adjacent first transistor regions and the wells in the two adjacent second transistor regions, thereby realizing electrical connection between the transistor units in the first transistor region and electrical connection between the transistor units in the second transistor region.

[0058] Compared with the traditional page buffer, the page buffer provided in the embodiment of the present application has a well contact structure provided in the existing array common source region between the adjacent first sub-regions and the existing array common source region between the adjacent second sub-regions, without the need to provide a well contact structure between the adjacent first transistor region and the second transistor region. Therefore, the size of the page buffer provided in the embodiment of the present application in the first direction can be greatly reduced. For example, in order to provide a well contact structure between the adjacent first transistor region and the second transistor region, the distance between the adjacent first transistor region and the second transistor region in the traditional page buffer is usually 1-1.2um, while the distance between the adjacent first transistor region and the second transistor region in the page buffer provided in the embodiment of the present application is less than 0.8um. ​​The distance between each pair of adjacent first transistor regions and second transistor regions can be reduced by at least 0.2-0.4um.

[0059] In this embodiment, a well contact structure 203 is set in the gap between adjacent first sub-regions 201 and the gap between adjacent second sub-regions 202. Each well contact structure 203 leads out the electric wells in two adjacent first sub-regions 2011, or leads out the electric wells in two adjacent second sub-regions 2021, and all the well contact structures 203 in each first transistor region and each second transistor region are electrically connected by setting an electrical connection layer. In the embodiment of the present application, the size of the page buffer is reduced by changing the distribution position of the well contact structure 203.

[0060] In a specific example, the distance between the adjacent first transistor region 201 and the adjacent second transistor region 202 is typically 0.73 um.

[0061] Taking the distance between adjacent first and second transistor regions in a conventional page buffer as 1 μm, and the distance between adjacent first and second transistor regions 201 and 202 in the page buffer provided in an embodiment of the present application as 0.73 μm as an example, for a page buffer consisting of four planes and including a total of 416 sets of repeating regions in the first direction (each set of repeating regions includes a first transistor region 201 and a second transistor region 202), the total length that can be reduced in the first direction of the page buffer of the present application compared to the conventional page buffer can be calculated as follows:

[0062] L = ((k1 + k2) / 2 - k3) * N;

[0063] Among them, k1 is the first distance between adjacent first transistor regions and second transistor regions in a traditional page buffer in which a well contact structure is set; k2 is the second distance between adjacent first transistor regions and second transistor regions in a traditional page buffer in which a well contact structure is not set; k3 is the distance between adjacent first transistor regions 201 and second transistor regions 202 in the page buffer provided in an embodiment of the present application; N is the number of repeated region groups of the first transistor region 201 and the second transistor region 202 in the first direction.

[0064] In a specific example, if k1=1 um, k2=0.93 um, k3=0.73 um, and N=416, then it can be obtained that L=97.76 um.

[0065] Compared with traditional page buffers, the page buffer provided in the embodiment of the present application can reduce the size in the first direction without increasing the size in the second direction. For example, according to the calculation method provided in the above specific implementation method, the page buffer provided in the embodiment of the present application has a total width reduction of approximately 97.76um in the first direction, accounting for approximately 1.5% of the total size.

[0066] This embodiment utilizes the gaps between adjacent first sub-regions and the gaps between adjacent second sub-regions to provide well contact structures, and provides an electrical connection layer to connect the well contact structures of each first transistor region and the well contact structures of each second transistor region, thereby achieving electrical connection between the well contact structures of each first transistor region and the well contact structures of each second transistor region. By changing the distribution position of the well contact structures, this application reduces the width of the page buffer in the first direction, meeting the requirements of chip miniaturization.

[0067] In some embodiments, the width of the electrical connection layer in the first direction is smaller than the width of the well contact structure 203 in the second direction.

[0068] Please continue reading Figure 2 and Figure 3 In the second direction, adjacent first sub-regions are separated by the array common source region 204, and adjacent second sub-regions are separated by the array common source region 204. In the first direction, a gap region also exists between adjacent first transistor regions 201 and second transistor regions 202. Because the width of the electrical connection layer in the first direction is smaller than the width of the well contact structure 203 in the second direction, the width requirement for the gap region between adjacent first transistor regions 201 and second transistor regions 202 in the first direction is reduced compared to conventional page buffers. This means that the width of the gap region between the first transistor region 201 and the second transistor region 202 can be reduced, thereby reducing the width of the page buffer in the first direction.

[0069] In some embodiments, the well contact structures 203 in each first transistor region 201 are arranged along the second direction; and the well contact structures 203 in each second transistor region 202 are arranged along the second direction.

[0070] In some embodiments, the array common source regions 204 in each first transistor region 201 are arranged along the second direction; and the array common source regions 204 in each second transistor region 202 are arranged along the second direction.

[0071] Here, in the second direction of the page buffer, there are two arrangement methods, namely the arrangement method of the well contact structure 203-first sub-region 2011-well contact structure 203, or the arrangement method of the well contact structure 203-second sub-region 2021-well contact structure 203. The number of alternating arrangements is determined according to actual needs and there is no restriction on this.

[0072] In some embodiments, the length of the well contact structure 203 located in the first transistor region in the first direction is smaller than the width of the first transistor region 201 in the first direction; the length of the well contact structure 203 located in the second transistor region in the first direction is smaller than the width of the second transistor region 202 in the first direction.

[0073] Here, the well contact structure 203 needs to meet the requirements of electrically leading out the well of the transistor unit in the first transistor region 201, and electrically leading out the well of the transistor unit in the second transistor region 202. Its length in the first direction may not be fixed. In this embodiment, it is preferred that the length of the well contact structure 203 in the first direction is smaller than the width of the first transistor region 201 in the first direction, and smaller than the width of the second transistor region 202 in the first direction.

[0074] The embodiment of the present application sets up a well contact structure by utilizing the gaps between adjacent first sub-regions and the gaps between adjacent second sub-regions, and sets up an electrical connection layer to connect the well contact structures of each first transistor region and the well contact structures of each second transistor region, so as to realize the electrical connection of the well contact structures of each first transistor region and the electrical connection of the well contact structures of each second transistor region, thereby reducing the width of the page buffer in the first direction and meeting the requirements of chip miniaturization.

[0075] The present application also provides a memory including the above-mentioned page buffer. Specific examples are as described in the above-mentioned page buffer examples, which will not be described in detail here. Here, the memory can be not only a three-dimensional memory but also a two-dimensional memory, without limitation.

[0076] An embodiment of the present application further provides a three-dimensional memory, which includes the above-mentioned page buffer. Specific examples are as described in the above-mentioned page buffer examples, and will not be repeated here.

[0077] An embodiment of the present application also provides a memory system 500, which includes the above-mentioned three-dimensional memory or memory 501, and a storage controller 502. The storage controller 502 is coupled to the three-dimensional memory or memory 500 and can be used to control the storage process of the three-dimensional memory or memory 500. The specific example is as described in the above-mentioned page buffer example, and will not be repeated here.

[0078] In one example, if Figure 5A As shown, the memory system 500 may include only one memory 501 and one corresponding memory controller 502 .

[0079] In another example, Figure 5B As shown, the memory system 500 may include multiple memories 501 and a corresponding memory controller 502 .

[0080] Of course, in other examples, the memory system may also include multiple memories and corresponding multiple memory controllers, which are not enumerated here.

[0081] In some embodiments, the memory system may be implemented as a storage device such as a Universal Flash Storage (UFS) device, a solid-state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type, a Foreign Component Interconnect (PCI) type storage device, a PCI-Express (PCI-E) type storage device, a Compact Flash (CF) card, a smart media card or a memory stick, etc.

[0082] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0083] The devices disclosed in the several device embodiments provided in this application can be arbitrarily combined without conflict to obtain new device embodiments.

[0084] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A page buffer, characterized in that: The page buffer includes: First transistor regions and second transistor regions are alternately arranged along a first direction; each of the first transistor regions includes at least two first sub-regions arranged along a second direction, and each of the second transistor regions includes at least two second sub-regions arranged along the second direction; at least two well contact structures extending along the first direction, the well contact structures being located between adjacent first sub-regions and between adjacent second sub-regions respectively; at least two electrical connection layers extending along the second direction, the electrical connection layers being used to connect all well contact structures in each first transistor region; the electrical connection layers being further used to connect all well contact structures in each second transistor region; The first direction is different from the second direction.

2. The page buffer according to claim 1, wherein: The first direction is perpendicular to the second direction.

3. The page buffer according to claim 2, wherein: A width of the electrical connection layer in the first direction is smaller than a width of the well contact structure in the second direction.

4. The page buffer according to claim 2, wherein: The page buffer further includes an array common source region, the array common source region is located between adjacent first sub-regions and between adjacent second sub-regions, and the well contact structure is provided in the array common source region.

5. The page buffer according to claim 2, wherein: The well contact structure in each of the first transistor regions is arranged along the second direction; and the well contact structure in each of the second transistor regions is arranged along the second direction.

6. The page buffer according to claim 2, wherein: The electrical connection layer is disposed above the first transistor region and the second transistor region, and the at least two electrical connection layers are arranged along a first direction.

7. The page buffer according to claim 6, wherein: The electrical connection layer above each first transistor region is connected to the well contact structure in the first transistor region through multiple contacts; the electrical connection layer above each second transistor region is connected to the well contact structure in the second transistor region through multiple contacts.

8. The page buffer according to claim 2, wherein: The distance between adjacent first transistor regions and second transistor regions is less than 0.8 um.

9. The page buffer according to claim 2, wherein: The length of the well contact structure located in the first transistor region in the first direction is smaller than the width of the first transistor region in the first direction; A length of the well contact structure located in the second transistor region in the first direction is smaller than a width of the second transistor region in the first direction.

10. The page buffer according to claim 2, wherein: The first transistor region is an N-type transistor region; the second transistor region is a P-type transistor region.

11. A memory, characterized in that: The method comprises the page buffer according to any one of claims 1 to 10.

12. A three-dimensional memory, characterized in that: The method comprises the page buffer according to any one of claims 1 to 10.

13. A memory system, characterized in that: include: The memory according to claim 11 or the three-dimensional memory according to claim 12; and a memory controller coupled to the memory or the three-dimensional memory.

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