Active matrix OLED display panel and preparation method thereof

Abstract

The present application provides an active-matrix OLED display panel and a method for manufacturing the same. The active-matrix OLED display panel comprises a display area and a non-display area surrounding the display area. The active-matrix OLED display panel includes a cathode layer, a drive circuit, and a cathode wiring layer. The cathode layer is located in the display area, while the drive circuit and the cathode wiring layer are both located in the non-display area. The cathode wiring layer is located on top of the drive circuit and is electrically connected to the cathode layer. The active-matrix OLED display panel provided in the present application can reduce the width occupied by the non-display area and achieve a narrow bezel, thereby enhancing the display quality of the active-matrix OLED display panel.

Description

Technical Field

[0001] The present application relates to the field of display panels, and in particular to an active matrix OLED display panel and a method for preparing the same. Background Art

[0002] Organic Light Emitting Display (OLED) displays offer advantages such as self-luminescence, fast response time, and a wide operating temperature range, and are considered an emerging technology for the next generation of flat-panel displays. OLED displays are categorized by their driving method: passive matrix OLED (PMOLED) and active matrix OLED (AMOLED).

[0003] Active-matrix OLED display panels, driven by thin-film transistors (TFTs), have numerous advantages, including thinness, power efficiency, vibrant colors, and superior image quality. They have been widely adopted and are gradually becoming a dominant force in the display industry. With the rapid adoption of active-matrix OLED display panels, users are increasingly favoring displays with narrow or even borderless bezels, meaning they desire a smaller proportion of non-display area. However, reducing the bezel by reducing the size of the TFTs can reduce the stability of the drive circuit itself and can cause quality issues such as crosstalk within the active-matrix OLED display panel. Summary of the Invention

[0004] The purpose of this application is to provide an active matrix OLED display panel and a preparation method thereof, which can reduce the width occupied by the non-display area and achieve a narrow frame, thereby improving the display effect of the active matrix OLED display panel.

[0005] The present application provides an active matrix OLED display panel having a display area and a non-display area surrounding the display area; the active matrix OLED display panel includes a cathode layer, a driving circuit and a cathode wiring layer, the cathode layer is located in the display area, the driving circuit and the cathode wiring layer are both located in the non-display area, and the cathode wiring layer is located on the top surface of the driving circuit and is electrically connected to the cathode layer.

[0006] Among them, the active matrix OLED display panel also includes a substrate, a flat layer and a conductive layer, the cathode layer is stacked on the top surface of the substrate, the flat layer is stacked on the cathode layer and the substrate, the flat layer is provided with a first contact hole, the cathode wiring layer is located on the top surface of the flat layer, the conductive layer is located in the first contact hole, and is electrically connected between the cathode wiring layer and the cathode layer.

[0007] Among them, the active matrix OLED display panel also includes a gate insulating layer, a gate layer, an active layer, a source layer and a drain layer. The gate layer is stacked on the top surface of the substrate, the gate insulating layer covers the gate layer and the substrate, the active layer is stacked on the top surface of the gate insulating layer, the active layer is stacked on the top surface of the gate insulating layer, the source layer and the drain layer respectively cover the opposite ends of the active layer and are spaced from each other, and the flat layer covers the active layer, the source layer and the drain layer.

[0008] The active matrix OLED display panel further includes an etch stop layer stacked on the top surface of the active layer. The source layer and the drain layer respectively cover opposite ends of the etch stop layer and are separated from each other.

[0009] The flat layer is provided with a second contact hole, and an electron transport layer, a light-emitting layer, a hole transport layer and an anode layer are sequentially stacked in the second contact hole, and the electron transport layer is stacked on the cathode layer.

[0010] Among them, the active matrix OLED display panel also includes a substrate, a gate insulating layer, a flat layer and a conductive layer. The gate insulating layer is stacked on the top surface of the substrate, the gate insulating layer is provided with a first contact hole, the cathode layer is stacked on the top surface of the gate insulating layer, the flat layer covers the cathode layer and the gate insulating layer, the flat layer is provided with a second contact hole connected to the first contact hole, the cathode wiring layer is located on the top surface of the flat layer, the conductive layer is located in the first contact hole and the second contact hole, and is electrically connected between the cathode wiring layer and the cathode layer.

[0011] Among them, the active matrix OLED display panel also includes a buffer layer, an active layer, a source layer, a drain layer and a gate layer. The buffer layer is stacked on the top surface of the substrate, the active layer is stacked on the top surface of the buffer layer, and the source layer and the drain layer respectively cover the opposite ends of the active layer; the gate insulating layer covers the buffer layer, the source layer, the drain layer and the active layer, the gate layer is stacked on the top surface of the gate insulating layer, and the flat layer covers the gate insulating layer and the gate layer.

[0012] Among them, the gate insulating layer is provided with a third contact hole, and the flat layer is provided with a fourth contact hole connected to the third contact hole. The electron transport layer, the light-emitting layer, the hole transport layer and the anode layer are stacked in sequence in the third contact hole and the fourth contact hole, and the electron transport layer is stacked on the cathode layer.

[0013] Wherein, the thickness of the flat layer is 3.5 μm to 7.7 μm.

[0014] The present application also provides a method for preparing an active matrix OLED display panel, comprising the following steps:

[0015] A substrate is provided, the substrate having a display area and a non-display area surrounding the display area

[0016] stacking a cathode layer on the top surface of the substrate, wherein the cathode layer is located in the display area;

[0017] forming a flat layer covering the cathode layer and the substrate;

[0018] forming a cathode wiring layer on the top surface of the planar layer, wherein the cathode wiring layer is located in the non-display area;

[0019] The cathode trace layer and the cathode layer are electrically connected.

[0020] In summary, the present application provides an active-matrix OLED display panel that utilizes a drive circuit to drive the horizontal scan lines. The drive circuit is located around the display area, replacing the traditional integrated circuit (IC) to drive the horizontal scan lines. This reduces the soldering process for the external IC, helps improve production capacity, and reduces product costs. By locating the cathode wiring layer on the drive circuit in the non-display area, the width occupied by the cathode wiring layer in the non-display area can be completely saved, thereby achieving a narrow frame and improving the display effect of the OLED display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 A schematic structural diagram of a display device provided in an embodiment of the present application;

[0023] Figure 2 for Figure 1 A schematic cross-sectional view of the active matrix OLED display panel in the display device shown;

[0024] Figure 3 This is a schematic structural diagram of an organic matrix OLED display panel in the first embodiment of the present application;

[0025] Figure 4 This is a schematic structural diagram of an organic matrix OLED display panel in the second embodiment of the present application;

[0026] Figure 5 This is a structural diagram of the organic matrix OLED display panel in the third embodiment of the present application. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0028] See also Figure 1 , Figure 1 A schematic structural diagram of a display device 1000 provided in an embodiment of the present application is shown.

[0029] The display device 1000 can be a mobile phone, tablet computer, laptop computer, television, monitor, wearable device, etc. The wearable device can be a smartwatch, glasses, helmet, smart bracelet, etc. For ease of description, the width direction of the display device 1000 is defined as the X-axis direction, the length direction as the Y-axis direction, and the thickness direction as the Z-axis direction. The X-axis direction, the Y-axis direction, and the Z-axis direction are mutually perpendicular.

[0030] In this embodiment, a display device 1000 includes an active-matrix OLED display panel 100 and a housing 200. The active-matrix OLED display panel 100 is mounted in the housing 200 and can display images. The active-matrix OLED display panel 100 includes a display area 10 and a non-display area 20 surrounding the display area 10. The display area 10 is used to display images.

[0031] See also Figure 2 , Figure 2 Shown Figure 1 The cross-sectional structure diagram of the active matrix OLED display panel 100 in the display device 1000 is shown.

[0032] In this embodiment, the active matrix OLED display panel 100 includes a cathode layer 11, a driving circuit 21, and a cathode wiring layer 22. The cathode layer 11 is located in the display area 10, and the driving circuit 21 and the cathode wiring layer 22 are located in the non-display area 20. The non-display area 20 surrounds the display area 10. In this embodiment, only the portion of the non-display area 20 located on the left and right sides of the display area 10 is shown. The non-display area 20 includes a first non-display area 210 located on the left side of the display area 10 and a second non-display area 220 located on the right side of the display area 10. The driving circuit 21 and the cathode wiring layer 22 in the first non-display area 210 and the driving circuit 21 and the cathode wiring layer 22 in the second non-display area 220 are mirror-symmetrical about the plane formed by the first direction and the second direction. In this example, the first direction is the Y-axis direction and the second direction is the Z-axis direction. The driving circuit 21 in the non-display area 20 is provided on the left and right sides of the display area 10, and can replace the traditional integrated circuit (IC) to complete the driving of the horizontal scan line. At the same time, it can also reduce the bonding process of the external IC, which helps to improve production capacity and reduce product costs.

[0033] Taking the drive circuit 21 and cathode wiring layer 22 in the first non-display area 210 as an example, the drive circuit 21 is used to drive horizontal scanning, driving the display area 10 to display an image. The cathode wiring layer 22 is located on the top surface of the drive circuit 21 and is electrically connected to the cathode layer 11 in the display area 10 to achieve electrical conduction between the cathode layer 11 and the negative electrode of the external power supply. In this embodiment, the cathode wiring layer 22 is located on the top surface of the drive circuit 21 and reuses the width space along the X-axis with the drive circuit 21. This reduces the width occupied by the non-display area 20 in the X-axis width direction, helping to improve the screen-to-body ratio of the active matrix OLED display panel 100 and achieve a narrow bezel effect.

[0034] It should be noted that the directional terms such as “top”, “bottom”, “left” and “right” in this application are referenced to the attached Figure 2 The description of the orientation of the device or element does not indicate or imply that the device or element must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the present application. The positive direction of the X axis represents the left direction, the negative direction of the X axis represents the right direction, the positive direction of the Z axis represents the bottom side, and the negative direction of the Z axis represents the top side.

[0035] In the organic matrix OLED display panel 100 provided in this embodiment, the drive circuit 21 is arranged around the display area 10, which can replace the traditional integrated circuit board (IC) to complete the driving of the horizontal scan line, reducing the welding process of the external IC, helping to improve production capacity and reduce product costs. In addition, in existing display panels, the cathode wiring layer 22 usually occupies width in the X-axis width direction. The material of the cathode wiring layer 22 itself has a high resistivity, and the effect of reducing the border by reducing the width of the cathode wiring layer 22 is limited. In this embodiment, by adopting the method of arranging the cathode wiring layer 22 on the drive circuit 21, the width occupied by the cathode wiring layer 22 in the X-axis width direction can be completely saved, thereby achieving the purpose of reducing the width occupied by the non-display area 20, thereby achieving the effect of improving the screen-to-body ratio of the active matrix OLED display panel 100 and achieving a narrow border effect. In the embodiment of the present application, by adopting the method of arranging the cathode wiring layer 22 on the drive circuit 21, it is possible to improve the resolution of the display area 10, thereby improving the pixel resolution (Pixel per inch, PPI), and thus improving the display effect of the display area 10.

[0036] See Figure 3 , Figure 3 FIG. 1 is a schematic cross-sectional structural diagram of an organic matrix OLED display panel 100 in a first embodiment of the present application.

[0037] The organic matrix OLED display panel 100 includes a substrate 211, a gate layer 212, a gate insulating layer 213, an active layer 214, a source electrode layer 215, a drain electrode layer 216, a planar layer 217, and a cathode wiring layer 22. The substrate 211, the gate insulating layer 213, and the planar layer 217 are located in both the display area 10 and the non-display area 20, respectively. The gate layer 212, the active layer 214, the source electrode layer 215, the drain electrode layer 216, and the cathode wiring layer 22 are located in the non-display area 20. The portion of the substrate 211 located in the non-display area 20, the portions of the gate layer 212 and the gate insulating layer 213 located in the non-display area 20, and the portions of the active layer 214, the source electrode layer 215, the drain electrode layer 216, and the planar layer 217 located in the non-display area 20 constitute a driving circuit 21. The cathode wiring layer 22 is located on top of the driving circuit 21. The driving circuit 21 includes multiple thin-film transistors, only one of which is shown in the figure.

[0038] The non-display area 20 includes a first non-display area 210 and a second non-display area 220. The driving circuit 21 and cathode wiring layer 22 in the first non-display area 210 and the driving circuit 21 and cathode wiring layer 22 in the second non-display area 220 are mirror-symmetrical about the Y-axis direction and the Z-axis direction.

[0039] Take the driving circuit 21 and cathode wiring layer 22 in the first non-display area 210 as an example. In the driving circuit 21 of this embodiment, the gate layer 212 is stacked on the top surface of the substrate 211, and the gate insulation layer 213 covers the substrate 211 and the gate layer 212. The active layer 214 is stacked on the top surface of the gate insulation layer 213. The active layer 214 is located on top of the gate layer 212, and its projection in the Z-axis direction covers the gate layer 212, that is, the projection of the active layer 214 in the thickness direction covers the gate layer 212. The source layer 215 and the drain layer 216 are respectively stacked on opposite ends of the active layer 214. Specifically, along the X-axis extension direction, the active layer 214 has two opposite ends, including a first end 2141 facing the positive direction of the X-axis and a second end 2142 facing the negative direction of the X-axis. The source layer 215 covers the first end 2141 of the active layer 214, and the drain layer 216 covers the second end 2142 of the active layer 214, with the source layer 215 and the drain layer 216 spaced apart from each other. The planar layer 217 covers the active layer 214, the source layer 215, and the drain layer 216. In this application, "stacked" means direct contact between layers, or indirect contact between layers through other components. "Covering" means full or partial coverage, and the relevant descriptions below shall be understood in the same way.

[0040] The cathode wiring layer 22 is stacked on the top surface of the flat layer 217. Specifically, the flat layer 217 has a first surface 2171 and a second surface 2172 arranged opposite to each other. The first surface 2171 is attached to the gate insulating layer 213, and the cathode wiring layer 22 is stacked on the second surface 2172. Taking into account the parasitic capacitance of the cathode wiring layer 22 and the driving circuit 21, the parasitic capacitance can be reduced by thickening the flat layer 217. In some embodiments, the thickness of the flat layer 217 is 3.5μm to 7.7μm, where "thickness" refers to the thickness of the thickest part of the flat layer. In other embodiments, the thickness of the flat layer 217 is 3.6μm to 3.9μm. The thickness of the flat layer in the existing design is about 1.2μm to 1.3μm (12000A to 13000A). The embodiment of the present application increases the thickness of the flat layer 217 to achieve the effect of reducing parasitic capacitance. For example, the thickness of the planar layer 217 is increased by 2.4 μm to 2.6 μm. Assuming that the area S of the cathode trace layer 22 is 50 μm * 372 μm, capacitance simulation experiments were conducted with different thicknesses of the planar layer 217. The results showed that when the thickness of the planar layer 217 was 1.3 μm, the parasitic capacitance was 1.5 pf, and when the thickness of the planar layer 217 was 3.9 μm, the parasitic capacitance was 0.4 pf. The experimental results show that by increasing the thickness of the planar layer 217, the parasitic capacitance can be reduced, thereby reducing the impact of the parasitic capacitance.

[0041] The planar layer 217 defines a first contact hole 2173 . The first contact hole 2173 opens on the top surface of the planar layer 217 , that is, the opening of the first contact hole 2173 is located on the second surface 2172 .

[0042] The organic matrix OLED display panel 100 further includes a cathode layer 11, an electron transport layer 12, a light-emitting layer 13, a hole transport layer 14, and an anode layer 15, which are stacked sequentially along the negative direction of the Z axis. The cathode layer 11, the electron transport layer 12, the light-emitting layer 13, the hole transport layer 14, and the anode layer 15 are all located in the display area 10. The cathode layer 11 is stacked on the gate insulating layer 213. The planarization layer 217 also covers the cathode layer 11. The planarization layer 217 is also provided with a second contact hole 2174, which is located in the display area 10 and exposes the cathode layer 11. The electron transport layer 12, the light-emitting layer 13, the hole transport layer 14, and the anode layer 15 are sequentially stacked on the hole wall of the second contact hole 2174.

[0043] The organic matrix OLED display panel 100 also includes a conductive layer 231, which is electrically connected between the cathode wiring layer 22 and the cathode layer 11. The conductive layer 231 in the first non-display area 210 and the second non-display area 220 is mirror-symmetrical about the plane formed by the Y-axis and the Z-axis. Taking the conductive layer 231 in the first non-display area 210 as an example, the opening of the first contact hole 2173 is opened on the second surface 2172 and is located between the cathode wiring layer 22 and the cathode layer 11. The first contact hole 2173 opens from the top surface of the planar layer 217 and extends to connect with the cathode layer 11. The conductive layer 231 is located within the first contact hole 2173 and has two free ends: one end is connected to the cathode wiring layer 22, and the other end is connected to the cathode layer 11. The conductive layer 231 is connected between the cathode wiring layer 22 and the cathode layer 11, acting as a bridge to achieve electrical connection between the cathode wiring layer 22 and the cathode layer 11.

[0044] During use, the cathode wiring layer 22 in the first non-display area 210 is electrically connected to the cathode wiring layer 22 in the second non-display area 220, and then connected to the cathode layer 11. When the organic matrix OLED display panel 100 is powered on, the negative electrode of the power supply is electrically connected to the cathode wiring layer 22, thereby achieving electrical conduction between the cathode layer 11 in the display area 10 and the negative electrode of the power supply. The positive electrode of the power supply is electrically connected to the anode layer 15 in the display area 10, thereby enabling the organic matrix OLED display panel 100 to operate.

[0045] Exemplarily, the substrate 211 may be a transparent substrate, such as a glass substrate. The gate layer 212 is made of a metal, such as silver, copper, or aluminum. The gate insulating layer 213 is made of silicon oxide, silicon nitride (SiNx), or the like. The active layer 214 is made of a metal oxide semiconductor or an amorphous silicon semiconductor. Examples of metal oxides include indium gallium zinc oxide (IGZO). In this embodiment, the active layer 214 is made of IGZO. The source layer 215 and the drain layer 216 are made of a metal, such as silver, copper, or aluminum. The planar layer 217 may be made of silicon nitride (SiNx). The cathode wiring layer 22 is made of an opaque material, such as silver (Ag), magnesium (Mg), or aluminum (Al).

[0046] This embodiment provides an organic matrix OLED display panel 100, which uses a driving circuit 21 located in the non-display area 20 to drive the horizontal scan lines. The driving circuit 21 has a small parasitic capacitance, which reduces the impact of the parasitic capacitance on the driving performance of the non-display area 20. The cathode wiring layer 22 is arranged on the driving circuit 21, which can completely save the width occupied by the cathode wiring layer 22 in the X-axis width direction, thereby achieving the purpose of reducing the width occupied by the non-display area 10, thereby achieving the effect of improving the screen-to-body ratio of the organic matrix OLED display panel 100 and achieving a narrow bezel. At the same time, it can also achieve the goal of improving the pixel resolution of the display area 10, thereby improving the display effect of the display area 10. In addition, compared with traditional amorphous silicon thin film transistors, the IZGO used in this embodiment has high electron mobility. The organic matrix OLED display panel 100 made of thin film transistors using IGZO as the semiconductor material has the advantages of high precision, low power consumption and high touch performance.

[0047] See Figure 4 , Figure 4 FIG. 1 shows a structural diagram of an organic matrix OLED display panel 100 in a second embodiment of the present application.

[0048] The organic matrix OLED display panel 100 of this embodiment differs from the organic matrix OLED display panel 100 of the first embodiment in that the driving circuit 21 of the organic matrix OLED display panel 100 of this embodiment further includes an etch stop layer 218. The etch stop layer 218 may be made of silicon oxide, silicon nitride, or the like.

[0049] Specifically, in the active-matrix OLED display panel 100 of this embodiment, the non-display area 20 includes a first non-display area 210 and a second non-display area 220. The drive circuit 21 in the first non-display area 210 and the drive circuit 21 in the second non-display area 220 are mirror-symmetric about the plane formed by the Y-axis and the Z-axis. Taking the first non-display area 210 located to the left of the display area 10 as an example, in the drive circuit 21 in the first non-display area 210, the gate layer 212 is stacked on the portion of the substrate 211 located in the non-display area 20, and the gate insulating layer 213 covers the substrate 211 and the gate layer 212. The active layer 214 is stacked on top of the gate insulating layer 213.

[0050] An etch stop layer 218 is stacked on the top surface of the active layer 214. The source layer 215 and the drain layer 216 cover the active layer 214 and the etch stop layer 218 at opposite ends, respectively. Specifically, along the X-axis, the active layer 214 includes a first end 2141 facing the positive X-axis direction, a second end 2142 facing the negative X-axis direction, and a middle portion 2143 connected between the first end 2141 and the second end 2142. The first end 2141 and the second end 2142 are arranged opposite each other. The etch stop layer 218 is provided on the middle portion 2143 of the active layer 214. The source layer 215 is stacked between the second end 2142 and one end of the active layer 214. The drain layer 216 is stacked between the first end 2141 and the other end of the active layer 214. The etch stop layer 218 is used to protect the channel between the source layer 215 and the drain layer 216 to prevent over-etching of the channel. The planarization layer 217 covers the source layer 215 , the drain layer 216 and the etch stop layer 218 .

[0051] In the driving circuit 21 of the second non-display area 220, the active layer 214 includes a first end 2141 facing the positive direction of the X-axis, a second end 2142 facing the negative direction of the X-axis, and a middle portion 2143 connected between the first end 2141 and the second end 2142. The etch stop layer 218 is stacked on the middle portion 2143. The drain layer 216 covers the first end 2141 of the active layer 214 and one end of the etch stop layer 218. The source layer 215 covers the second end 2142 of the active layer 214 and the other end of the etch stop layer 218, and the source layer 215 and the drain layer 216 are spaced apart from each other.

[0052] This embodiment provides an organic matrix OLED display panel 100, in which an etch stop layer 218 is provided in the drive circuit 21 of the non-display area 20. The etch stop layer 218 protects the active layer 214, effectively reducing leakage current in the drive circuit 21, thereby improving the display quality of the organic matrix OLED display panel 100. In addition, by disposing the cathode wiring layer 22 on the drive circuit 21, the width occupied by the cathode wiring layer 22 in the X-axis direction can be completely reduced, thereby reducing the width occupied by the non-display area and achieving a narrow frame. At the same time, it can also improve the pixel resolution of the display area 10, thereby improving the display quality of the display area 10.

[0053] See Figure 5 , Figure 5 FIG. 1 is a schematic structural diagram of an organic matrix OLED display panel 100 in a third embodiment of the present application.

[0054] The organic matrix OLED display panel 100 of this embodiment is different from the organic matrix OLED display panel 100 of the first embodiment in that the driving circuit 21 in the organic matrix OLED display panel 100 of this embodiment is different from the driving circuit 21 in the organic matrix OLED display panel 100 of the first embodiment.

[0055] The organic matrix OLED display panel 100 of this embodiment includes a display area 10 and a non-display area 20. The organic matrix OLED display panel 100 includes a substrate 221, a buffer layer 222, an active layer 223, a source electrode layer 224, a drain electrode layer 225, a gate insulating layer 226, a gate layer 227, and a planarizing layer 228. The substrate 221, the buffer layer 222, the gate insulating layer 226, and the planarizing layer 228 are all located in both the display area 10 and the non-display area 20. The active layer 223, the source electrode layer 224, the drain electrode layer 225, and the gate layer 227 are located in the non-display area 20. The substrate 221 in the non-display area 20, the buffer layer 222 in the non-display area 20, the active layer 223, the source layer 224, the drain layer 225, the gate insulating layer 226 in the non-display area 20, the gate layer 227, and the planar layer 228 in the non-display area 20 constitute the driving circuit 21. The cathode wiring layer 22 is located on the top surface of the driving circuit 21. In this embodiment, the buffer layer 222 is made of silicon nitride.

[0056] The non-display area 20 includes a first non-display area 210 and a second non-display area 220. The driving circuit 21 and cathode wiring layer 22 in the first non-display area 210 and the driving circuit 21 and cathode wiring layer 22 in the second non-display area 220 are mirror-symmetrical about the Y-axis direction and the Z-axis direction.

[0057] Taking the driving circuit 21 and cathode wiring layer 22 in the first non-display area 210 as an example, in the driving circuit 21 of this embodiment, the buffer layer 222 is stacked on the top surface of the substrate 221, and the active layer 223 is stacked on the top surface of the buffer layer 222. The active layer 223 includes a third end 2231 facing the positive direction of the X-axis and a fourth end 2232 facing the negative direction of the X-axis. The third end 2231 and the fourth end 2232 are arranged opposite each other. The source layer 224 and the drain layer 225 respectively cover the opposite ends of the active layer 223. In this embodiment, the source layer 224 covers the third end 2231, and the drain layer 225 covers the fourth end 2232. The gate insulating layer 226 covers the buffer layer 222, the source layer 224, the drain layer 225, and the active layer 223. In this embodiment, the gate insulating layer 226 includes a first sub-gate insulating layer 2261 and a second sub-gate insulating layer 2262. The first sub-gate insulating layer 2261 is stacked on the active layer 223, and the second sub-gate insulating layer 2262 covers the buffer layer 222, the source layer 224, the drain layer 225, and the first sub-gate insulating layer 2261. The gate layer 227 is stacked on top of the second sub-gate insulating layer 2262, and the planarization layer 228 covers the second sub-gate insulating layer 2262 and the gate layer 227.

[0058] The cathode wiring layer 22 is stacked on the top surface of the planar layer 228. Specifically, the planar layer 228 has a first surface 2281 and a second surface 2282 that are opposite each other. The first surface 2281 is in contact with the gate insulation layer 226, and the cathode wiring layer 22 is stacked on the second surface 2282. The second sub-gate insulation layer 2262 is provided with a first contact hole 2283, and the planar layer 227 is provided with a second contact hole 2284. The first contact hole 2283 is connected to the second contact hole 2284. The second contact hole 2284 opens on the top surface of the planar layer 228, that is, the opening of the first contact hole 2283 is located on the second surface 2282, and the second contact hole 2284 extends through the planar layer 228.

[0059] The organic matrix OLED display panel 100 further includes a cathode layer 11, an electron transport layer 12, a light-emitting layer 13, a hole transport layer 14, and an anode layer 15, which are stacked in sequence along the negative direction of the Z axis. These layers are all located in the display area 10, with the cathode layer 11 stacked on the buffer layer 222. The second sub-gate insulating layer 2262 is further provided with a third contact hole 2285, and the planar layer 228 is further provided with a fourth contact hole 2286. The third contact hole 2285 and the fourth contact hole 2286 are both located in the display area 10 and are interconnected. The fourth contact hole 2286 penetrates the planar layer 228, and the third contact hole 2285 is connected to the cathode layer 11. The electron transport layer 12, the light-emitting layer 13, the hole transport layer 14, and the anode layer 15 are located within the third contact hole 2285 and the fourth contact hole 2286, and the electron transport layer 12 is stacked on the cathode layer 11.

[0060] The organic matrix OLED display panel 100 also includes a conductive layer 232, which is electrically connected between the cathode wiring layer 22 and the cathode layer 11. The conductive layer 232 in the first non-display area 210 and the second non-display area 220 is mirror-symmetrical about the plane formed by the Y-axis and the Z-axis. Taking the conductive layer 232 in the first non-display area 210 as an example, the opening of the first contact hole 2273 is opened on the second surface 2282 and is located between the cathode wiring layer 22 and the cathode layer 11. The first contact hole 2283 is connected to the cathode layer 11, and the second contact hole 2284 penetrates the planar layer 228 and is connected to the first contact hole 2283. The conductive layer 232 is located within the first contact hole 2283 and the second contact hole 2284. The conductive layer 232 has two free ends, one end connected to the cathode wiring layer 22, and the other end connected to the cathode layer 11. The conductive layer 232 is connected between the cathode wiring layer 22 and the cathode layer 11 , and acts as a bridge to achieve electrical connection between the cathode wiring layer 22 and the cathode layer 11 .

[0061] This embodiment provides an organic matrix OLED display panel 100. The second gate layer 227 of the driving circuit 21 is located above the source layer 224 and the drain layer 225, adopting a top-gate structure. The cathode trace 11 is disposed on the planar layer 228 of the driving circuit 21, thereby reducing the width occupied by the cathode trace layer 22 in the X-axis width direction. This reduces the width occupied by the non-display area and achieves a narrow frame, thereby improving the display quality of the display area 10. The organic matrix OLED display panel 100 provided in this embodiment also has the advantages of high pixel resolution and an aesthetically pleasing appearance.

[0062] The present application also provides a method for preparing an organic matrix OLED display panel 100, which is described by taking the preparation of the organic matrix OLED display panel 100 shown in the second embodiment as an example. The method for preparing the organic matrix OLED display panel 100 includes the following steps:

[0063] Step S1: providing a substrate 211, the substrate 211 having a display area 10 and a non-display area 20 surrounding the display area 10; sputtering a metal film on the substrate 211, and forming a gate layer 212 by a first photolithography process; then, depositing silicon nitride on the substrate 211 and the gate layer 212 by plasma enhanced chemical vapor deposition (PCVD) to form a gate insulating layer 213;

[0064] Step S2: stacking a cathode layer 11 on the top surface of the substrate 211, wherein the cathode layer is located in the display area 10. In this embodiment, step S2 can be implemented through steps S201 to S203.

[0065] Step S201: depositing an IGZO thin film on the gate insulating layer 213, and then forming a thin film transistor (TFT) channel by a second photolithography process to form an active layer 214;

[0066] Step S202 : depositing a silicon dioxide film on the active layer 214 , and preparing an etch stop layer 218 by a third photolithography process.

[0067] Step S203, sputtering metal material on the gate insulating layer 213, the active layer 214 and the etching stop layer 218, and preparing the source layer 215, the drain layer 216 and the cathode layer 11 through the fourth photolithography, wherein the source layer 215 and the drain layer 216 are located in the non-display area 20, and the cathode layer 11 is located in the display area 10.

[0068] Step S3: forming a planar layer 217 covering the cathode layer 11 and the substrate 211. Specifically, silicon nitride is covered on the source layer 215, the drain layer 216, the etch stop layer 218 and the cathode layer 11 to form the planar layer 217;

[0069] Step S4: forming a cathode wiring layer 22 on the top surface of the planar layer 217, wherein the cathode wiring layer 22 is located in the non-display area 20. Specifically, metal is sputtered on the planar layer 217, and the cathode wiring layer 22 is formed on the planar layer 217 by a fifth photolithography process.

[0070] Step S5: electrically connect the cathode wiring layer 22 and the cathode layer 11. Specifically, the planar layer 217 is etched to form a first contact hole 2173 and a second contact hole 2174. Then, a conductive layer 231 is formed in the first contact hole 2173 and electrically connected to the cathode wiring layer 22 and the cathode layer 11.

[0071] In addition, the method for manufacturing the organic matrix OLED display panel 100 further includes step S6.

[0072] Step S6: In a vacuum environment, an electron transport layer 12 , a light emitting layer 13 , a hole transport layer 14 and an anode layer 15 are sequentially deposited in the second contact hole 2174 by an evaporation machine, and the electron transport layer 12 is stacked on the cathode layer 11 .

[0073] The method for fabricating an organic matrix OLED display panel 100 provided in the embodiments of the present application simultaneously forms the cathode layer 11 on the gate insulating layer 213 by photolithography while fabricating the source electrode layer 215 and the drain electrode layer 216, thereby improving production efficiency and achieving high fabrication precision. By forming a conductive layer 231 within the first contact hole 2173, good electrical contact between the cathode wiring layer 22 and the cathode layer 11 is ensured, thereby improving the quality of the fabricated organic matrix OLED display panel 100.

[0074] The above disclosure is only a preferred embodiment of the present application, and it is certainly not intended to limit the scope of the rights of the present application. A person skilled in the art can understand that all or part of the processes of the above embodiments and equivalent changes made in accordance with the claims of the present application are still within the scope of the invention.

Claims

1. An active matrix OLED display panel, characterized in that: The active matrix OLED display panel comprises a display area and a non-display area surrounding the display area; the active matrix OLED display panel comprises a cathode layer, a driving circuit, and a cathode wiring layer, wherein the cathode layer is located in the display area, the driving circuit and the cathode wiring layer are both located in the non-display area, and the cathode wiring layer is located on top of the driving circuit and is electrically connected to the cathode layer; The active matrix OLED display panel also includes a flat layer and a conductive layer, the flat layer covers the cathode layer, the driving circuit includes a portion of the flat layer located in the non-display area, the cathode wiring layer is stacked on the top surface of the flat layer, and the conductive layer is located in the contact hole of the flat layer and is electrically connected between the cathode wiring layer and the cathode layer.

2. The active matrix OLED display panel according to claim 1, wherein: The active matrix OLED display panel also includes a substrate, the cathode layer is stacked on the top surface of the substrate, the planar layer is stacked on the cathode layer and the substrate, the planar layer is provided with a first contact hole, the cathode wiring layer is located on the top surface of the planar layer, the conductive layer is located in the first contact hole, and is electrically connected between the cathode wiring layer and the cathode layer.

3. The active matrix OLED display panel according to claim 2, wherein: The active matrix OLED display panel also includes a gate insulating layer, a gate layer, an active layer, a source layer and a drain layer. The gate layer is stacked on the top surface of the substrate, the gate insulating layer covers the gate layer and the substrate, the active layer is stacked on the top surface of the gate insulating layer, the source layer and the drain layer respectively cover the opposite ends of the active layer and are spaced apart from each other, and the planar layer covers the active layer, the source layer and the drain layer.

4. The active matrix OLED display panel according to claim 3, wherein: The active matrix OLED display panel further includes an etch stop layer stacked on the top surface of the active layer. The source electrode layer and the drain electrode layer respectively cover opposite ends of the etch stop layer and are spaced apart from each other.

5. The active matrix OLED display panel according to claim 2, wherein: The flat layer is provided with a second contact hole, in which an electron transport layer, a light emitting layer, a hole transport layer and an anode layer are sequentially stacked, and the electron transport layer is stacked on the cathode layer.

6. The active matrix OLED display panel according to claim 1, wherein: The active matrix OLED display panel also includes a substrate and a gate insulating layer, the gate insulating layer is stacked on the top surface of the substrate, the gate insulating layer is provided with a first contact hole, the cathode layer is stacked on the top surface of the gate insulating layer, the flat layer covers the cathode layer and the gate insulating layer, the flat layer is provided with a second contact hole connected to the first contact hole, the cathode wiring layer is located on the top surface of the flat layer, the conductive layer is located in the first contact hole and the second contact hole, and is electrically connected between the cathode wiring layer and the cathode layer.

7. The active matrix OLED display panel according to claim 6, wherein: The active matrix OLED display panel also includes a buffer layer, an active layer, a source layer, a drain layer and a gate layer. The buffer layer is stacked on the top surface of the substrate, the active layer is stacked on the top surface of the buffer layer, and the source layer and the drain layer respectively cover the opposite ends of the active layer; the gate insulating layer covers the buffer layer, the source layer, the drain layer and the active layer, the gate layer is stacked on the top surface of the gate insulating layer, and the flat layer covers the gate insulating layer and the gate layer.

8. The active matrix OLED display panel according to claim 7, wherein: The gate insulating layer is provided with a third contact hole, the flat layer is provided with a fourth contact hole connected to the third contact hole, the electron transport layer, the light-emitting layer, the hole transport layer and the anode layer are stacked in sequence in the third contact hole and the fourth contact hole, and the electron transport layer is stacked on the cathode layer.

9. The active matrix OLED display panel according to any one of claims 2 to 8, wherein: The thickness of the flat layer is 3.5 μm to 7.7 μm.

10. A method for preparing an active matrix OLED display panel, characterized in that: The following steps are involved: A substrate is provided, the substrate having a display area and a non-display area surrounding the display area stacking a cathode layer on the top surface of the substrate, wherein the cathode layer is located in the display area; forming a flat layer covering the cathode layer and the substrate; forming a cathode wiring layer on the top surface of the planar layer, wherein the cathode wiring layer is located in the non-display area; A contact hole is formed in the planar layer, a conductive layer is prepared in the contact hole of the planar layer, and the conductive layer is electrically connected to the cathode wiring layer and the cathode layer.

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