Semiconductor Structure and Method for Forming the Same
By introducing auxiliary gate structure and side wall gate structure into floating gate sub-gate flash memory devices, the problem of limited thickness of the selection gate dielectric layer is solved, lower operating voltage and higher control capabilities are achieved, and the short channel effect is delayed.
Patent Information
- Application Number
- CN202111494126.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-08
- Publication Date
- 2025-08-05
- Estimated Expiration
- 2041-12-08
AI Technical Summary
In existing floating gate split-gate flash memory devices, the thickness of the gate dielectric layer of the selected gate is limited by the erase operation voltage, resulting in insufficient control capabilities, and thinning the dielectric layer thickness will lead to a short channel effect.
An auxiliary gate structure is introduced, and an erasing operation is performed through the auxiliary gate structure. The select gate structure only retains the read operation function, and a side wall gate structure is formed on both sides of the select gate structure and the auxiliary gate structure, including a control gate and a floating gate structure, forming an L-shaped floating gate structure to achieve longitudinal and lateral coupling.
Thinning the gate dielectric layer thickness of the selected gate structure does not affect the control ability, delays the short channel effect, improves the control ability of the selected gate, and increases the overlap area of the control gate and the floating gate, thereby enhancing the control ability.
Smart Images
Figure CN114203827B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] Floating-gate split-gate flash memory devices are widely used in various embedded electronic products such as financial IC cards and automotive electronics. Increasing storage integration density helps save chip area and reduce manufacturing costs.
[0003] In the prior art, in a floating gate split-gate flash memory device, an erase operation and a read operation are performed by applying an operating voltage on a select gate, and the operating voltage of the erase operation is greater than the operating voltage of the read operation.
[0004] However, in the above method, the lower limit of the thickness of the gate dielectric layer of the select gate depends on the operating voltage of the erase operation. The thicker the gate dielectric layer of the select gate, the lower the control ability of the select gate. Summary of the Invention
[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, and to introduce an auxiliary gate structure to delay the short channel effect, improve the control capability of the selection gate structure, and enhance the control capability of the control gate structure.
[0006] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a selection gate structure located on the substrate; an auxiliary gate structure located on the selection gate structure; a sidewall gate structure located on the substrate on both sides of the selection gate structure and the auxiliary gate structure, the sidewall gate structure including a control gate structure and a floating gate structure, the floating gate structure being located between the sidewall of the control gate structure and the sidewalls of the selection gate structure and the auxiliary gate structure, and between the control gate structure and the substrate.
[0007] Optionally, the select gate structure includes: a first gate dielectric layer located on the substrate; and a select gate layer located on the first gate dielectric layer.
[0008] Optionally, the thickness of the first gate dielectric layer ranges from 30 angstroms to 80 angstroms.
[0009] Optionally, the material of the first gate dielectric layer includes silicon oxide; and the material of the select gate layer includes polysilicon.
[0010] Optionally, the auxiliary gate structure includes: a second gate dielectric layer located on the select gate structure; and an auxiliary gate layer located on the second gate dielectric layer.
[0011] Optionally, the structure of the second gate dielectric layer includes: a first oxide layer located on the surface of the select gate structure, a first nitride layer located on the surface of the first oxide layer, and a second oxide layer located on the surface of the first nitride layer.
[0012] Optionally, the material of the auxiliary gate layer includes polysilicon.
[0013] Optionally, each floating gate structure includes a third sidewall spacer and a floating gate layer, the third sidewall spacer is located between the sidewall of the floating gate layer and the sidewalls of the selection gate structure and the auxiliary gate structure, and the floating gate layer is located between the sidewall of the third sidewall spacer and the sidewall of the control gate structure.
[0014] Optionally, the material of the third sidewall spacer includes silicon oxide; and the material of the floating gate layer includes polysilicon.
[0015] Optionally, each of the control gate structures includes a fourth spacer and a control gate layer, the fourth spacer is located between the sidewall of the floating gate structure and the sidewall of the control gate layer, and the control gate layer is located on the sidewall surface of the fourth spacer.
[0016] Optionally, the structure of the fourth spacer includes: a third oxide layer located on the sidewall surface of the floating gate structure, a second nitride layer located on the surface of the third oxide layer, and a fourth oxide layer located on the surface of the second nitride layer.
[0017] Optionally, the material of the control gate layer is polysilicon.
[0018] Optionally, it also includes: a fifth sidewall located on the sidewall surface of each control gate structure, and the structure of the fifth sidewall includes: a fifth oxide layer located on the sidewall surface of the control gate structure; and a third nitride layer located on the sidewall surface of the fifth oxide layer.
[0019] Optionally, it further includes: source and drain regions in the substrate located on both sides of the select gate structure, the spacer gate structure and the fifth spacer.
[0020] Optionally, the method further includes: lightly doped regions in the substrate located on both sides of the select gate structure, and part of the lightly doped regions is located at the bottom of the sidewall gate structure.
[0021] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, which is characterized in that it includes: providing a substrate; forming a selection gate structure and an auxiliary gate structure located on the selection gate structure on the substrate; forming a sidewall gate structure on the substrate on both sides of the selection gate structure and the auxiliary gate structure, the sidewall gate structure including a control gate structure and a floating gate structure, and the floating gate structure is located between the side wall of the control gate structure and the side walls of the selection gate structure and the auxiliary gate structure, and between the control gate structure and the substrate.
[0022] Optionally, the select gate structure includes: a first gate dielectric layer located on the substrate, wherein the thickness of the first gate dielectric layer is in a range of 30 angstroms to 80 angstroms; and a select gate layer located on the first gate dielectric layer.
[0023] Optionally, the auxiliary gate structure includes: a second gate dielectric layer located on the select gate structure; and an auxiliary gate layer located on the second gate dielectric layer.
[0024] Optionally, the structure of the second gate dielectric layer includes: a first oxide layer located on the surface of the select gate structure, a first nitride layer located on the surface of the first oxide layer, and a second oxide layer located on the surface of the first nitride layer.
[0025] Optionally, each floating gate structure includes a third sidewall spacer and a floating gate layer, the third sidewall spacer is located between the sidewall of the floating gate layer and the sidewalls of the selection gate structure and the auxiliary gate structure, and the floating gate layer is located between the sidewall of the third sidewall spacer and the sidewall of the control gate structure.
[0026] Optionally, each of the control gate structures includes a fourth spacer and a control gate layer, the fourth spacer is located between the sidewall of the floating gate structure and the sidewall of the control gate layer, and the control gate layer is located on the sidewall surface of the fourth spacer.
[0027] Optionally, the structure of the fourth spacer includes: a third oxide layer located on the sidewall surface of the floating gate structure, a second nitride layer located on the surface of the third oxide layer, and a fourth oxide layer located on the surface of the second nitride layer.
[0028] Optionally, it also includes: after forming the sidewall gate structure on the substrate on both sides of the selection gate structure and the auxiliary gate structure, forming a lightly doped region in the substrate on both sides of the selection gate structure, and part of the lightly doped region is located at the bottom of the sidewall gate structure.
[0029] Optionally, after the lightly doped region is formed in the substrate of the selection gate structure, a fifth sidewall is formed on the sidewall surface of the sidewall gate structure; the structure of the fifth sidewall includes: a fifth oxide layer located on the sidewall surface of the control gate structure; and a third nitride layer located on the sidewall surface of the fifth oxide layer.
[0030] Optionally, after the fifth spacer is formed on the sidewall surface of the spacer gate structure, source and drain regions are formed in the substrate on both sides of the select gate structure, the spacer gate structure and the fifth spacer.
[0031] Optionally, the method for forming the sidewall gate structure includes: forming the floating gate structure material layer on the sidewall surface of the selection gate structure, the sidewall surface of the auxiliary gate structure, and the substrate; forming a control gate structure material layer on the surface of the floating gate structure material layer; and etching back the floating gate structure material layer and the control gate structure material layer until the substrate surface is exposed to form the floating gate structure and the control gate structure.
[0032] Optionally, the method for forming the selection gate structure and the auxiliary gate structure includes: forming a selection gate structure material layer on the surface of the substrate; forming an auxiliary gate structure material layer on the selection gate structure material layer; forming a patterned layer on a portion of the auxiliary gate structure material layer; etching the auxiliary gate structure material layer using the patterned layer as a mask to form the auxiliary gate structure; etching the selection gate structure material layer using the patterned layer and the auxiliary gate structure as masks to form the selection gate structure.
[0033] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0034] The technical solution of the present invention provides a semiconductor structure comprising a select gate structure located on a substrate; and an auxiliary gate structure located on the select gate structure. The auxiliary gate structure introduced on the select gate structure replaces the select gate structure for performing an erase operation, and the select gate structure only retains the read operation function. The lower limit of the thickness of the gate dielectric layer in the select gate structure depends on the maximum operating voltage applied to the select gate structure. The thicker the gate dielectric layer in the select gate structure, the lower the control capability of the select gate structure. Since the technical solution of the present invention only requires applying an operating voltage for a read operation lower than the operating voltage for an erase operation to the select gate structure, further thinning the thickness of the gate dielectric layer in the select gate structure will not lead to a decrease in the channel control capability, and therefore the lower limit of the thickness of the gate dielectric layer in the select gate structure can be reduced. By thinning the thickness of the gate dielectric layer in the select gate structure, the short channel effect can be delayed and the control capability of the select gate structure can be increased. In addition, in the semiconductor structure, sidewall gate structures are located on the substrate on both sides of the select gate structure and the auxiliary gate structure. The sidewall gate structures include a control gate structure and a floating gate structure. The floating gate structure is located between the sidewalls of the control gate structure and the sidewalls of the select gate structure and the auxiliary gate structure, and between the control gate structure and the substrate. Due to the introduction of the auxiliary gate structure into the floating gate structure, the floating gate structure can be made L-shaped, thereby achieving both longitudinal and transverse coupling between the control gate structure and the floating gate structure, increasing the overlap area between the control gate structure and the floating gate structure, reducing the coupling coefficient from the select gate structure to the floating gate structure, and improving the control capability of the control gate structure.
[0035] Accordingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, in which a selection gate structure and an auxiliary gate structure located on the selection gate structure are formed on a substrate. The auxiliary gate structure introduced on the selection gate structure replaces the selection gate structure for performing an erase operation, and the selection gate structure only retains the read operation function. The lower limit of the thickness of the gate dielectric layer in the selection gate structure depends on the maximum operating voltage applied to the selection gate structure. The thicker the gate dielectric layer in the selection gate structure, the lower the control capability of the selection gate structure. Since the technical solution of the present invention only requires applying an operating voltage for a read operation lower than the operating voltage for an erase operation to the selection gate structure, further thinning the thickness of the gate dielectric layer in the selection gate structure will not lead to a decrease in channel control capability, so the lower limit of the thickness of the gate dielectric layer in the selection gate structure can be reduced. By thinning the thickness of the gate dielectric layer in the selection gate structure, the short channel effect can be delayed and the control capability of the selection gate structure can be increased. In addition, in the method for forming the semiconductor structure, sidewall gate structures are formed on the substrate on both sides of the select gate structure and the auxiliary gate structure. The sidewall gate structures include a control gate structure and a floating gate structure. The floating gate structure is located between the sidewalls of the control gate structure and the sidewalls of the select gate structure and the auxiliary gate structure, and between the control gate structure and the substrate. Due to the introduction of the auxiliary gate structure into the floating gate structure, the floating gate structure can be made L-shaped, thereby achieving both longitudinal and transverse coupling between the control gate structure and the floating gate structure, increasing the overlap area between the control gate structure and the floating gate structure, reducing the coupling coefficient from the select gate structure to the floating gate structure, and improving the control capability of the control gate structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] Figure 1 A schematic diagram of a semiconductor structure;
[0037] Figures 2 to 11 Schematic diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION
[0038] As described in the background, since the operating voltage for the erase operation is higher than the operating voltage for the read operation, the lower limit of the thickness of the gate dielectric layer of the select gate depends on the operating voltage for the erase operation. The thicker the gate dielectric layer of the select gate, the lower the control capability of the select gate.
[0039] Figure 1The present invention is a schematic diagram of a semiconductor structure. The semiconductor structure includes: a substrate 101; a floating gate dielectric layer 102 located on the substrate 101; a floating gate layer 103 located on each of the floating gate dielectric layers 102; an ONO dielectric layer 104 located on each of the floating gate layers 103; a control gate layer 105 located on each of the ONO dielectric layers 104; a select gate opening between the floating gate layer 103 and the control gate layer 105; a select gate dielectric layer 107 located within the select gate opening; a select gate layer 108 located on the select gate dielectric layer 107; a metal silicide layer 113 located on the select gate layer 108; second spacers 106 located on the floating gate layer 103 on both sides of the select gate dielectric layer 107; and first spacers 112 located on the sidewall surfaces of each of the second spacers 106 and on the control gate layer 105.
[0040] In this embodiment, the thickness of the select gate dielectric layer 107 ranges from 80 angstroms to 180 angstroms.
[0041] Applying an operating voltage to the select gate layer 108 allows for erase and read operations. The erase operating voltage is greater than the read operating voltage. The lower limit of the thickness of the select gate dielectric layer 107 is determined by the higher erase operating voltage. The thicker the select gate dielectric layer 107, the lower the control capability of the select gate layer 108. However, if the select gate dielectric layer 107 is thinned to increase its control capability, applying the erase operating voltage to the select gate layer 108 may damage the select gate dielectric layer 107, hindering the mitigation of short channel effects.
[0042] In this embodiment, an erase operation is performed by applying an operating voltage of 8V to the select gate layer 108. The lower limit of the thickness of the select gate dielectric layer 107 is determined by the operating voltage of 8V. If the thickness of the select gate dielectric layer 107 is reduced to increase the control capability of the select gate 108, the select gate dielectric layer 107 will be damaged when the erase operation is performed by applying an operating voltage of 8V to the select gate layer 108, which is not conducive to slowing down the short channel effect.
[0043] The lower limit of the operating voltage of the read operation applied to the select gate layer 108 depends on the thickness of the select gate dielectric layer 107 .
[0044] In this embodiment, the operating voltage of the read operation applied to the select gate layer 108 is 4V.
[0045] Furthermore, the method for forming the floating gate layer 103, the control gate layer 105, and the select gate layer 108 includes: forming the floating gate layer 103 on the substrate 101; forming the control gate layer 105 on the floating gate layer 103; forming a select gate opening between the floating gate layer 103 and the control gate layer 105; and forming the select gate layer 108 within the select gate opening. The floating gate layer 103 and the control gate layer 105 are only longitudinally coupled (i.e., coupled perpendicular to the surface of the substrate 101). As devices are further scaled down, the overlapping area between the floating gate layer 103 and the control gate layer 105 decreases, resulting in a significant decrease in the coupling coefficient between the control gate layer 105 and the floating gate layer 103 and an increase in the coupling coefficient between the select gate layer 108 and the floating gate layer 103, thereby reducing the control capability of the control gate layer 105.
[0046] In order to solve the technical problem, the technical solution of the present invention replaces the select gate structure with the auxiliary gate structure introduced on the select gate structure to perform the erase operation, while the select gate structure only retains the read operation function. Therefore, the operating voltage of the select gate structure can be reduced, and the thickness of the gate dielectric layer in the structural gate can also be thinned. By thinning the thickness of the gate dielectric layer in the structural gate, the short channel effect can be delayed and the control capability of the select gate structure can be increased. In addition, due to the introduction of the auxiliary gate structure, the floating gate structure can be L-shaped, so that the control gate structure and the floating gate structure can simultaneously achieve longitudinal coupling and transverse coupling, increase the overlapping area of the control gate structure and the floating gate structure, reduce the coupling coefficient of the select gate structure, and increase the control capability of the control gate structure.
[0047] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0048] Figures 2 to 11 Schematic diagram of the semiconductor structure forming process in an embodiment of the present invention.
[0049] Please refer to Figure 2 , providing a substrate 200.
[0050] The substrate 200 includes: a P-type substrate and an N-type substrate. In this embodiment, the substrate 200 is a P-type substrate.
[0051] In this embodiment, a selection gate structure and an auxiliary gate structure located on the selection gate structure are subsequently formed on the substrate; the method for forming the selection gate structure and the auxiliary gate structure includes: forming a selection gate structure material layer on the surface of the substrate; forming an auxiliary gate structure material layer on the selection gate structure material layer; forming a patterned layer on a portion of the auxiliary gate structure material layer; etching the auxiliary gate structure material layer using the patterned layer as a mask to form the auxiliary gate structure; etching the selection gate structure material layer using the patterned layer and the auxiliary gate structure as masks to form the selection gate structure. For the method for forming the selection gate structure and the auxiliary gate structure, please refer to Figures 3 to 5 .
[0052] Please refer to Figure 3 , a selection gate structure material layer 210 is deposited on the surface of the substrate 200 ; an auxiliary gate structure material layer 220 is deposited on the selection gate structure material layer 210 ; and a first patterned layer 223 is formed on a portion of the auxiliary gate structure material layer 220 .
[0053] The select gate structure material layer 220 includes: a first gate dielectric material layer 211 located on the substrate 200 ; and a select gate material layer 212 located on the first gate dielectric material layer 211 .
[0054] The material of the first dielectric material layer 211 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the first dielectric material layer 211 includes silicon oxide.
[0055] The material of the select gate material layer 212 includes polysilicon.
[0056] In this embodiment, the thickness of the first gate dielectric material layer 211 ranges from 30 angstroms to 80 angstroms.
[0057] The auxiliary gate structure material layer 220 includes: a second gate dielectric material layer 221 located on the select gate structure material layer 210 ; and an auxiliary gate material layer 222 located on the second gate dielectric material layer 221 .
[0058] The second gate dielectric material layer 221 has an ONO structure and includes a first oxide layer located on a surface of the select gate structure material layer 210, a first nitride layer located on a surface of the first oxide layer, and a second oxide layer located on a surface of the nitride layer. In this embodiment, the first oxide layer includes silicon oxide, the first nitride layer includes silicon nitride, and the second oxide layer includes silicon oxide.
[0059] The auxiliary gate material layer 222 is made of polysilicon.
[0060] In this embodiment, the thickness of the auxiliary gate material layer 222 is 0.1 micrometer to 0.5 micrometer.
[0061] The material of the first patterned layer 223 includes photoresist.
[0062] Please refer to Figure 4 The auxiliary gate structure material layer 220 is photolithographically etched using the first patterned layer 223 as a mask to form an auxiliary gate structure 230 .
[0063] The auxiliary gate structure 230 includes: a second gate dielectric layer 231 located on the select gate structure material layer 210 ; and an auxiliary gate layer 232 located on the second gate dielectric layer 231 .
[0064] In this embodiment, the thickness of the auxiliary gate layer 232 is 0.1 micrometer to 0.5 micrometer.
[0065] Please refer to Figure 5 The select gate structure material layer 210 is photolithographically etched using the first patterned layer 223 as a mask to form a select gate structure 240 .
[0066] The select gate structure 240 includes: a first gate dielectric layer 241 located on the substrate 200 ; and a select gate layer 242 located on the first gate dielectric layer 241 .
[0067] In this embodiment, the thickness of the first gate dielectric layer 241 ranges from 30 angstroms to 80 angstroms.
[0068] The erase operation is performed by introducing the auxiliary gate structure 230 on the select gate structure 240 to replace the select gate layer 242, while the select gate layer 242 only retains the read operation function. The lower limit of the thickness of the first gate dielectric layer 241 depends on the maximum operating voltage applied to the select gate layer 242. The thicker the first gate dielectric layer 241, the lower the control ability of the select gate layer 242. Since the technical solution of the present invention only requires applying an operating voltage of the read operation lower than the operating voltage of the erase operation to the select gate layer 242, further thinning the thickness of the first gate dielectric layer 241 will not lead to a decrease in the channel control ability, so the lower limit of the thickness of the first gate dielectric layer 241 can be reduced. By thinning the thickness of the first gate dielectric layer 241, the short channel effect can be delayed and the control ability of the select gate layer 242 can be increased.
[0069] In this embodiment, an erase operation is performed by applying an operating voltage of 8V to the auxiliary gate structure 230 .
[0070] Since the thickness of the first gate dielectric layer 241 can be reduced, and the lower limit of the operating voltage of the read operation applied on the select gate layer 242 depends on the thickness of the first gate dielectric layer 241, the operating voltage of the read operation applied on the select gate layer 242 can also be further reduced.
[0071] In this embodiment, the operating voltage of the read operation applied to the select gate layer 242 is 2.5V.
[0072] In this embodiment, a spacer gate structure is subsequently formed on the substrate 200 on both sides of the select gate structure 240 and the auxiliary gate structure 230. The spacer gate structure includes a control gate structure and a floating gate structure. The floating gate structure is located between the sidewall of the control gate structure and the sidewalls of the select gate structure and the auxiliary gate structure 230, and between the control gate structure and the substrate 200. The method for forming the spacer gate structure is as follows. Figures 6 to 8 shown.
[0073] Please refer to Figure 6 , the floating gate structure material layer 250 is deposited on the sidewall surface of the select gate structure 240 and the sidewall surface of the auxiliary gate structure 230 and the substrate 200 ; and the control gate structure material layer 260 is deposited on the surface of the floating gate structure material layer 250 .
[0074] The floating gate structure material layer 250 includes a third spacer material layer 251 and a floating gate material layer 252 .
[0075] The material of the third spacer material layer 251 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the third spacer material layer 251 includes silicon oxide.
[0076] The floating gate material layer 252 is made of polysilicon.
[0077] The control gate structure material layer 260 includes a fourth spacer material layer 261 and a control gate material layer 262 .
[0078] The fourth spacer material layer 261 has an ONO structure and includes a third oxide layer located on the sidewall surface of the floating gate structure material layer 250, a second nitride layer located on the surface of the third oxide layer, and a fourth oxide layer located on the surface of the second nitride layer. In this embodiment, the third oxide layer includes silicon oxide, the second nitride layer includes silicon nitride, and the fourth oxide layer includes silicon oxide.
[0079] The control gate material layer 262 is made of polysilicon.
[0080] In this embodiment, the floating gate structure material layer 250 and the control gate structure material layer 260 are subsequently etched back until the substrate surface is exposed to form the floating gate structure and the control gate structure; the control gate structure includes a fourth sidewall and a control gate layer, the fourth sidewall is located between the sidewall of the floating gate structure and the sidewall of the control gate layer, and the control gate layer is located on the sidewall surface of the fourth sidewall; the floating gate structure includes a third sidewall and a floating gate layer, the third sidewall is located between the sidewall of the floating gate layer and the sidewalls of the select gate structure and the auxiliary gate structure, and the floating gate layer is located between the sidewall of the third sidewall and the sidewall of the control gate structure. The method of etching back the floating gate structure material layer 250 and the control gate structure material layer 260 is as follows: Figures 7 and 8 shown.
[0081] Please refer to Figure 7 , the control gate material layer 262 is etched back until the surface of the fourth spacer material layer 261 is exposed, thereby forming the control gate layer 272 .
[0082] Please refer to Figure 8 After forming the control gate layer 272, the fourth spacer material layer 261, the floating gate material layer 252 and the third spacer material layer 251 are etched back until the surface of the substrate 200 is exposed to form a fourth spacer 271, a floating gate layer 282 and a third spacer 281.
[0083] Since the auxiliary gate structure 230 is introduced into the floating gate structure 280, the floating gate structure 280 can be made L-shaped, so that the control gate structure 270 and the floating gate structure 280 can simultaneously achieve longitudinal coupling and transverse coupling, increase the overlapping area of the control gate structure 270 and the floating gate structure 280, reduce the coupling coefficient from the selection gate structure 240 to the floating gate structure 280, and increase the control capability of the control gate structure 270.
[0084] Please refer to Figure 9 , further comprising: after forming the sidewall gate structure 290 on the substrate on both sides of the selection gate structure 240 and the auxiliary gate structure 230, forming a lightly doped region 201 in the substrate on both sides of the selection gate structure 240, and part of the lightly doped region 201 is located at the bottom of the sidewall gate structure 290.
[0085] In this embodiment, the method of forming the lightly doped region 201 includes lightly doped drain implantation (LDD) and HALO implantation.
[0086] Please refer to Figure 10After the lightly doped regions 201 are formed in the substrate 200 on both sides of the select gate structure 240 , a fifth spacer 291 is formed on the sidewall surface of the spacer gate structure 290 .
[0087] In this embodiment, the structure of the fifth spacer 291 includes: a fifth oxide layer located on the sidewall surface of the control gate structure 270; and a third nitride layer located on the sidewall surface of the fifth oxide layer.
[0088] Please refer to Figure 11 After the fifth spacer 291 is formed on the sidewall surface of the spacer gate structure 290 , source and drain regions 202 are formed in the substrate on both sides of the select gate structure 240 , the spacer gate structure 290 and the fifth spacer 291 .
[0089] In this embodiment, the method of forming the source and drain regions 202 includes heavily doped ion implantation.
[0090] Correspondingly, the embodiment of the present invention also provides a schematic diagram of a semiconductor structure formed by the above method. Figure 11 ,include:
[0091] A substrate 200; a select gate structure 240 located on the substrate; an auxiliary gate structure 230 located on the select gate structure 240; a sidewall gate structure 290 located on the substrate on both sides of the select gate structure 240 and the auxiliary gate structure 230, the sidewall gate structure 290 including a control gate structure 270 and a floating gate structure 280, the floating gate structure 280 being located between the sidewalls of the control gate structure 270 and the sidewalls of the select gate structure 240 and the auxiliary gate structure 230, and between the control gate structure 270 and the substrate 200.
[0092] The substrate 200 includes: a P-type substrate and an N-type substrate. In this embodiment, the substrate 200 is a P-type substrate.
[0093] The select gate structure 240 includes: a first gate dielectric layer 241 located on the substrate; and a select gate layer 242 located on the first gate dielectric layer 241 .
[0094] The material of the first gate dielectric layer 241 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the first gate dielectric layer 241 includes silicon oxide.
[0095] The material of the select gate layer 242 includes polysilicon.
[0096] In this embodiment, the thickness of the first gate dielectric layer 241 ranges from 30 angstroms to 80 angstroms.
[0097] Please continue to refer to Figure 11 The auxiliary gate structure 230 includes: a second gate dielectric layer 231 located on the select gate structure 240 ; and an auxiliary gate layer 232 located on the second gate dielectric layer 231 .
[0098] The second gate dielectric layer 231 has an ONO structure and includes a first oxide layer located on a surface of the select gate structure 240, a first nitride layer located on a surface of the first oxide layer, and a second oxide layer located on a surface of the nitride layer. In this embodiment, the first oxide layer includes silicon oxide, the first nitride layer includes silicon nitride, and the second oxide layer includes silicon oxide.
[0099] The auxiliary gate layer 232 is made of polysilicon.
[0100] In this embodiment, the thickness of the auxiliary gate layer 232 is 0.1 micrometer to 0.5 micrometer.
[0101] The erase operation is performed by introducing the auxiliary gate structure 230 on the select gate structure 240 to replace the select gate layer 242, while the select gate layer 242 only retains the read operation function. The lower limit of the thickness of the first gate dielectric layer 241 depends on the maximum operating voltage applied to the select gate layer 242. The thicker the first gate dielectric layer 241, the lower the control ability of the select gate layer 242. Since the technical solution of the present invention only requires applying an operating voltage of the read operation lower than the operating voltage of the erase operation to the select gate layer 242, further thinning the thickness of the first gate dielectric layer 241 will not lead to a decrease in the channel control ability, so the lower limit of the thickness of the first gate dielectric layer 211 can be reduced. By thinning the thickness of the first gate dielectric layer 241, the short channel effect can be delayed and the control ability of the select gate layer 242 can be increased.
[0102] In this embodiment, an erase operation is performed by applying an operating voltage of 8V to the auxiliary gate structure 230 .
[0103] Since the thickness of the first gate dielectric layer 241 can be reduced, and the lower limit of the operating voltage of the read operation applied on the select gate layer 242 depends on the thickness of the first gate dielectric layer 241, the operating voltage of the read operation applied on the select gate layer 242 can also be further reduced.
[0104] In this embodiment, the operating voltage of the read operation applied to the select gate layer 242 is 2.5V.
[0105] Please continue to refer to Figure 11 Each floating gate structure 280 includes a third sidewall spacer 281 and a floating gate layer 282. The third sidewall spacer 281 is located between the sidewall of the floating gate layer 282 and the sidewalls of the selection gate structure 240 and the auxiliary gate structure 230. The floating gate layer 282 is located between the sidewall of the third sidewall spacer 281 and the sidewall of the control gate structure 270.
[0106] Since the auxiliary gate structure 230 is introduced into the floating gate structure 280, the floating gate structure 280 can be made L-shaped, so that the control gate structure 270 and the floating gate structure 280 can simultaneously achieve longitudinal coupling and transverse coupling, increase the overlapping area of the control gate structure 270 and the floating gate structure 280, reduce the coupling coefficient from the selection gate structure to the floating gate structure 280, and increase the control capability of the control gate structure 270.
[0107] The material of the third spacer 281 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the third spacer 281 includes silicon oxide.
[0108] The floating gate layer 282 is made of polysilicon.
[0109] Please continue to refer to Figure 11 Each of the control gate structures 270 includes a fourth sidewall 271 and a control gate layer 272 . The fourth sidewall 271 is located between the sidewall of the floating gate structure 280 and the sidewall of the control gate layer 272 . The control gate layer 272 is located on the sidewall surface of the fourth sidewall 271 .
[0110] The fourth sidewall spacer 271 has an ONO structure and includes a third oxide layer located on the sidewall surface of the floating gate structure 280, a second nitride layer located on the surface of the third oxide layer, and a fourth oxide layer located on the surface of the second nitride layer. In this embodiment, the third oxide layer is made of silicon oxide, the second nitride layer is made of silicon nitride, and the fourth oxide layer is made of silicon oxide.
[0111] The control gate layer 272 is made of polysilicon.
[0112] Please continue to refer to Figure 11 , also includes: a fifth sidewall 291 located on the sidewall surface of each control gate structure 270, and the structure of the fifth sidewall 291 includes: a fifth oxide layer located on the sidewall surface of the control gate structure 270; and a third nitride layer located on the sidewall surface of the fifth oxide layer.
[0113] Please continue to refer to Figure 11 , further comprising: lightly doped regions 201 in the substrate 200 located on both sides of the select gate structure 240 , and part of the lightly doped regions 201 located at the bottom of the sidewall gate structure 290 .
[0114] Please continue to refer to Figure 11 , further comprising: a source and drain region 202 in the substrate located on both sides of the select gate structure 240 , the spacer gate structure 290 and the fifth spacer 291 .
[0115] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that include: substrate; a select gate structure located on the substrate; an auxiliary gate structure located on the select gate structure; A sidewall gate structure is located on the substrate on both sides of the select gate structure and the auxiliary gate structure, the sidewall gate structure includes a control gate structure and a floating gate structure, the floating gate structure is located between the sidewall of the control gate structure and the sidewalls of the select gate structure and the auxiliary gate structure, and between the control gate structure and the substrate, the floating gate structure is L-shaped, the select gate structure and the auxiliary gate structure are located on the sidewalls of the floating gate structure, the top of the floating gate structure is flush with the top of the auxiliary gate structure, and the top of the control gate structure is lower than the top of the floating gate structure.
2. The semiconductor structure according to claim 1, wherein The select gate structure includes: a first gate dielectric layer located on the substrate; and a select gate layer located on the first gate dielectric layer.
3. The semiconductor structure according to claim 2, wherein: The thickness of the first gate dielectric layer ranges from 30 angstroms to 80 angstroms.
4. The semiconductor structure according to claim 2, wherein: The material of the first gate dielectric layer includes silicon oxide; the material of the select gate layer includes polysilicon.
5. The semiconductor structure according to claim 1, wherein The auxiliary gate structure includes: a second gate dielectric layer located on the select gate structure; and an auxiliary gate layer located on the second gate dielectric layer.
6. The semiconductor structure according to claim 5, wherein: The structure of the second gate dielectric layer includes: a first oxide layer located on the surface of the select gate structure, a first nitride layer located on the surface of the first oxide layer, and a second oxide layer located on the surface of the first nitride layer.
7. The semiconductor structure according to claim 5, wherein: The material of the auxiliary gate layer includes polysilicon.
8. The semiconductor structure according to claim 1, wherein: Each floating gate structure includes a third sidewall spacer and a floating gate layer. The third sidewall spacer is located between the sidewall of the floating gate layer and the sidewalls of the select gate structure and the auxiliary gate structure. The floating gate layer is located between the sidewall of the third sidewall spacer and the sidewall of the control gate structure.
9. The semiconductor structure according to claim 8, wherein: The material of the third sidewall spacer includes silicon oxide; the material of the floating gate layer includes polysilicon.
10. The semiconductor structure according to claim 1, wherein: Each of the control gate structures includes a fourth spacer and a control gate layer. The fourth spacer is located between the sidewall of the floating gate structure and the sidewall of the control gate layer. The control gate layer is located on the sidewall surface of the fourth spacer.
11. The semiconductor structure according to claim 10, wherein: The structure of the fourth sidewall spacer includes: a third oxide layer located on the sidewall surface of the floating gate structure, a second nitride layer located on the surface of the third oxide layer, and a fourth oxide layer located on the surface of the second nitride layer.
12. The semiconductor structure according to claim 11, wherein The material of the control gate layer is polysilicon.
13. The semiconductor structure according to claim 1, wherein: Also includes: A fifth spacer located on the sidewall surface of each of the control gate structures, wherein the structure of the fifth spacer comprises: a fifth oxide layer located on the sidewall surface of the control gate structure; A third nitride layer is located on the sidewall surface of the fifth oxide layer.
14. The semiconductor structure according to claim 13, wherein: Also includes: The source and drain regions are located in the substrate on both sides of the select gate structure, the spacer gate structure and the fifth spacer.
15. The semiconductor structure according to claim 1, wherein Also includes: The lightly doped regions are located in the substrate on both sides of the select gate structure, and part of the lightly doped regions is located at the bottom of the sidewall gate structure.
16. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a select gate structure and an auxiliary gate structure on the select gate structure on the substrate; A sidewall gate structure is formed on the substrate on both sides of the select gate structure and the auxiliary gate structure. The sidewall gate structure includes a control gate structure and a floating gate structure. The floating gate structure is located between the sidewall of the control gate structure and the sidewalls of the select gate structure and the auxiliary gate structure, and between the control gate structure and the substrate. The floating gate structure is L-shaped. The select gate structure and the auxiliary gate structure are located on the sidewalls of the floating gate structure. The top of the floating gate structure is flush with the top of the auxiliary gate structure, and the top of the control gate structure is lower than the top of the floating gate structure.
17. The method for forming a semiconductor structure according to claim 16, wherein: The select gate structure includes: a first gate dielectric layer located on the substrate, wherein the thickness of the first gate dielectric layer ranges from 30 angstroms to 80 angstroms; and a select gate layer located on the first gate dielectric layer.
18. The method for forming a semiconductor structure according to claim 16, wherein: The auxiliary gate structure includes: a second gate dielectric layer located on the select gate structure; and an auxiliary gate layer located on the second gate dielectric layer.
19. The method for forming a semiconductor structure according to claim 18, wherein: The structure of the second gate dielectric layer includes: a first oxide layer located on the surface of the select gate structure, a first nitride layer located on the surface of the first oxide layer, and a second oxide layer located on the surface of the first nitride layer.
20. The method for forming a semiconductor structure according to claim 16, wherein: Each floating gate structure includes a third sidewall spacer and a floating gate layer. The third sidewall spacer is located between the sidewall of the floating gate layer and the sidewalls of the select gate structure and the auxiliary gate structure. The floating gate layer is located between the sidewall of the third sidewall spacer and the sidewall of the control gate structure.
21. The method for forming a semiconductor structure according to claim 16, wherein: Each of the control gate structures includes a fourth spacer and a control gate layer. The fourth spacer is located between the sidewall of the floating gate structure and the sidewall of the control gate layer. The control gate layer is located on the sidewall surface of the fourth spacer.
22. The method for forming a semiconductor structure according to claim 21, wherein: The structure of the fourth sidewall spacer includes: a third oxide layer located on the sidewall surface of the floating gate structure, a second nitride layer located on the surface of the third oxide layer, and a fourth oxide layer located on the surface of the second nitride layer.
23. The method for forming a semiconductor structure according to claim 16, wherein: Also includes: After forming the sidewall gate structure on the substrate on both sides of the select gate structure and the auxiliary gate structure, lightly doped regions are formed in the substrate on both sides of the select gate structure, and part of the lightly doped regions is located at the bottom of the sidewall gate structure.
24. The method for forming a semiconductor structure according to claim 23, wherein: After forming the lightly doped region in the substrate of the select gate structure, forming a fifth spacer on the sidewall surface of the spacer gate structure; The structure of the fifth spacer includes: a fifth oxide layer located on the sidewall surface of the control gate structure; A third nitride layer is located on the sidewall surface of the fifth oxide layer.
25. The method for forming a semiconductor structure according to claim 24, wherein: After the fifth spacer is formed on the sidewall surface of the spacer gate structure, source and drain regions are formed in the substrate on both sides of the select gate structure, the spacer gate structure and the fifth spacer.
26. The method for forming a semiconductor structure according to claim 16, wherein: The method for forming the sidewall gate structure includes: forming the floating gate structure material layer on the sidewall surface of the selection gate structure, the sidewall surface of the auxiliary gate structure and the substrate; forming a control gate structure material layer on the surface of the floating gate structure material layer; and etching back the floating gate structure material layer and the control gate structure material layer until the substrate surface is exposed to form the floating gate structure and the control gate structure.
27. The method for forming a semiconductor structure according to claim 16, wherein: The method for forming the selection gate structure and the auxiliary gate structure includes: forming a selection gate structure material layer on the surface of the substrate; forming an auxiliary gate structure material layer on the selection gate structure material layer; forming a patterned layer on a portion of the auxiliary gate structure material layer; etching the auxiliary gate structure material layer using the patterned layer as a mask to form the auxiliary gate structure; etching the selection gate structure material layer using the patterned layer and the auxiliary gate structure as masks to form the selection gate structure.
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