Display device and method of manufacturing the same

Abstract

An object is to suppress a change in characteristics of a transistor. A display device includes a metal layer (30) which is formed of a plurality of layers, an ionization tendency of a lowermost layer (30L) of the plurality of layers is lower than an ionization tendency of an intermediate layer (30M), and the lowermost layer (30L) is provided in contact with an oxide semiconductor layer (22). Each of channel regions (24) is positioned between a corresponding one of a plurality of first electrodes (26) and a corresponding one of a plurality of second electrodes (28) and constitutes a corresponding one of a plurality of thin film transistors (14). The oxide semiconductor layer (22) is continuous between a pair of channel regions (24A, 24B) included in a pair of thin film transistors (14A, 14B) adjacent to each other. The metal layer (30) is continuous between a pair of first electrodes (26A, 26B) included in the pair of thin film transistors (14A, 14B) adjacent to each other.

Description

TECHNICAL FIELD

[0001] The present application relates to a display device and a manufacturing method thereof. BACKGROUND

[0002] In a thin film transistor (TFT), there is a case where an oxide semiconductor is used instead of low-temperature polysilicon which has a high off current and is difficult to suppress a leak current (Patent Documents 1 and 2). In a bottom gate type TFT, a drain / source electrode is formed so as to exceed an end portion of an oxide semiconductor layer which constitutes a channel.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT DOCUMENTS

[0005] Patent Document 1: Japanese Patent Application Publication No. 2016-100521

[0006] Patent Document 2: Japanese Patent Application Publication No. 2012-104639 SUMMARY

[0007] PROBLEMS TO BE SOLVED BY THE INVENTION

[0008] When the end surface of the oxide semiconductor layer is steep, layer disconnection of the drain / source electrode is likely to occur. If the drain / source electrode is composed of a plurality of layers, when layer disconnection occurs in the lowermost layer, the intermediate layer thereon comes into contact with the oxide semiconductor layer. When the lowermost layer is composed of titanium, molybdenum, nickel or the like and the intermediate layer is composed of aluminum, the oxide semiconductor layer is reduced by aluminum, and there is a case where the threshold voltage is lowered (depletion).

[0009] An object of the present application is to suppress a change in characteristics of a transistor.

[0010] TECHNICAL MEANS FOR SOLVING THE PROBLEM

[0011] The display device of the present application is a display device having a plurality of thin film transistors of a bottom-gate type, characterized by comprising: a plurality of gate electrodes; a gate insulating layer covering the plurality of gate electrodes; an oxide semiconductor layer mounted on the gate insulating layer; and a metal layer composed of a plurality of layers, the lowest layer of which has a lower ionization tendency than the intermediate layer, the metal layer being mounted on the oxide semiconductor layer with the lowest layer in contact with the oxide semiconductor layer, the oxide semiconductor layer including a plurality of channel regions each positioned between a corresponding one of the plurality of first electrodes and a corresponding one of the plurality of second electrodes, constituting a corresponding one of the plurality of thin film transistors, the oxide semiconductor layer being continuous between a pair of the channel regions included in a pair of the thin film transistors adjacent to each other, the metal layer being continuous between a pair of the first electrodes included in the pair of the thin film transistors adjacent to each other.

[0012] According to the present application, the oxide semiconductor layer is continuous between a pair of channel regions included in a pair of thin film transistors adjacent to each other. That is, there is no end portion of the oxide semiconductor layer under the metal layer. Therefore, since layer disconnection of the metal layer does not occur, variation in characteristics of the transistor can be suppressed.

[0013] The manufacturing method of the display device of the present application is a manufacturing method of a display device having a plurality of thin film transistors of a bottom-gate type, characterized by comprising: a step of forming a plurality of gate electrodes; a step of forming a gate insulating layer so as to cover the plurality of gate electrodes; a step of forming an oxide semiconductor layer so as to be mounted on the gate insulating layer; a step of forming a metal layer composed of a plurality of layers, the lowest layer of which has a lower ionization tendency than the intermediate layer, the metal layer being mounted on the oxide semiconductor layer with the lowest layer in contact with the oxide semiconductor layer; a step of patterning the metal layer into a shape including a plurality of first electrodes and a plurality of second electrodes; and a step of patterning the oxide semiconductor layer into a shape including a plurality of channel regions each positioned between a corresponding one of the plurality of first electrodes and a corresponding one of the plurality of second electrodes, constituting a corresponding one of the plurality of thin film transistors, the shape of the oxide semiconductor layer being continuous between a pair of the channel regions included in the thin film transistors adjacent to each other, the shape of the metal layer being continuous between a pair of the first electrodes included in the thin film transistors adjacent to each other.

[0014] According to the present application, the oxide semiconductor layer is continuous between a pair of channel regions included in a pair of thin film transistors adjacent to each other. That is, there is no end portion of the oxide semiconductor layer under the metal layer. Therefore, layer separation of the metal layer does not occur, and variation in characteristics of the transistor can be suppressed. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a plan view of a display device of an embodiment.

[0016] Figure 2 is a plan view of an element configuration of each pixel.

[0017] Figure 3 is Figure 2 is a III-III line cross-sectional view of the configuration shown in FIG. 1.

[0018] Figure 4 is Figure 2 is a IV-IV line cross-sectional view of the configuration shown in FIG. 1.

[0019] Figure 5 is Figure 2 is a V-V line cross-sectional view of the configuration shown in FIG. 1.

[0020] Figure 6 is Figure 2 is another longitudinal cross-sectional view of the configuration shown in FIG. 1.

[0021] Figure 7 is a view indicating a formation process of a plurality of gate electrodes.

[0022] Figure 8 is a view indicating a formation process of an oxide semiconductor layer.

[0023] Figure 9 is a view indicating a patterning process of a metal layer.

[0024] Figure 10 is a view indicating a patterning process of an oxide semiconductor layer.

[0025] Figure 11 is a cross-sectional view of a display device of a modification example. DETAILED DESCRIPTION

[0026] Hereinafter, embodiments of the present application will be described with reference to the drawings. However, the present application can be implemented in various ways without departing from the gist thereof, and is not construed as being limited to the description of the following embodiments.

[0027] The drawings are schematically shown in terms of the width, thickness, shape, etc. of each part, for the purpose of making the explanation clearer, and are not intended to limit the explanation of the present application. In the present specification and drawings, elements having the same function as that described with reference to the drawings are designated by the same reference numerals, and repeated explanation is omitted.

[0028] Also, in the detailed explanation of the present application, the so-called "on" and "under" when specifying the positional relationship of a certain constituent and other constituents includes not only the case where it is positioned directly above or directly below the certain constituent, but also the case where there is another constituent therebetween, unless otherwise specified.

[0029] Figure 1 is a plan view of a display device of an embodiment. The display device includes a display DP. The display DP is bent in a bending corresponding region BA on the outside of a display region DA where an image is displayed, in a case where it has flexibility. An integrated circuit chip CP for driving an element for displaying an image is mounted in the display DP. A flexible printed board FP is connected on the outside of the display region DA in the display DP. The display device is, for example, an organic electroluminescent display device. In the display region DA, for example, pixels (sub-pixels) of multiple colors composed of red, green, and blue are combined, and a full-color image is displayed. Also, the display device can be electronic paper.

[0030] Figure 2 is a plan view of a configuration of each pixel. Figure 3 is a plan view of a configuration of each pixel. Figure 2 is a III-III line cross-sectional view of the configuration shown in Figure 4 is a III-III line cross-sectional view of the configuration shown in Figure 2 is a IV-IV line cross-sectional view of the configuration shown in Figure 5 is a IV-IV line cross-sectional view of the configuration shown in Figure 2 is a V-V line cross-sectional view of the configuration shown in

[0031] The substrate 10 can be composed of glass, and if flexibility is required, it can be composed of a resin such as polyimide. A primer layer 12 is layered on the substrate 10. The primer layer 12 is composed of an insulating film such as a silicon oxide film, and can be multilayered or single-layered.

[0032] The display device includes a plurality of thin film transistors 14 of a bottom gate type. The plurality of thin film transistors 14 each includes a plurality of gate electrodes 16. The plurality of gate electrodes 16 are each integrated with a corresponding one of a plurality of scan lines 18. The display device has a gate insulating layer 20 that covers the plurality of gate electrodes 16. The gate insulating layer 20 is a silicon oxide film.

[0033] The thin film transistor 14 has an oxide semiconductor layer 22. The oxide semiconductor layer 22 is composed of, for example, IGZO (Indium Gallium Zinc Oxide) or IZO (Indium Zinc Oxide). The oxide semiconductor layer 22 is mounted on the gate insulating layer 20. The oxide semiconductor layer 22 is present above the gate electrode 16. The thin film transistor 14 has the oxide semiconductor layer 22 as a channel region 24, and thus can reduce current unevenness and can suppress off current to be very low.

[0034] The oxide semiconductor layer 22 includes a plurality of channel regions 24. The plurality of channel regions 24 are each located between a corresponding one of the plurality of first electrodes 26 and a corresponding one of the plurality of second electrodes 28, constituting a corresponding one of the plurality of thin film transistors 14. The oxide semiconductor layer 22 is continuous between a pair of channel regions 24A, 24B included in a pair of thin film transistors 14A, 14B adjacent to each other.

[0035] The display device has a metal layer 30. The metal layer 30 is composed of a plurality of layers. A lowermost layer 30L is mounted on the oxide semiconductor layer 22 in contact with the oxide semiconductor layer 22. In the ionization tendency, the lowermost layer 30L is lower than an intermediate layer 30M. As an example, the lowermost layer 30L is formed of titanium. The intermediate layer 30M is formed of aluminum. The intermediate layer 30M is located between the lowermost layer 30L and an uppermost layer 30U. The uppermost layer 30U is formed of the same material as the lowermost layer 30L.

[0036] Here, the film thickness of the lowermost layer 30L constituting the metal layer 30 is 50 nm, the film thickness of the intermediate layer 30M is 400 nm, and the film thickness of the oxide semiconductor layer 22 is about 75 nm.

[0037] The metal layer 30 includes the plurality of first electrodes 26. The plurality of first electrodes 26 are each integrated with a corresponding one of the plurality of image signal lines 32. The metal layer 30 is continuous between a pair of first electrodes 26A, 26B included in a pair of thin film transistors 14A, 14B adjacent to each other. The metal layer 30 includes the plurality of second electrodes 28. The plurality of second electrodes 28 are each connected to a corresponding one of the plurality of pixel electrodes 34.

[0038] According to this embodiment, the oxide semiconductor layer 22 is continuous between the pair of channel regions 24A and 24B included in the pair of thin film transistors 14A and 14B adjacent to each other. That is, there is no end portion of the oxide semiconductor layer 22 under the metal layer 30. Thus, layer disconnection of the metal layer 30 does not occur, and thus the characteristics of the thin film transistor 14 can be prevented from changing. As described above, in the case where the film thickness of the lowermost layer 30L is thinner than that of the oxide semiconductor layer 22, layer disconnection is particularly likely to occur if there is an end portion of the oxide semiconductor layer 22 under the metal layer 30, and thus the structure of this embodiment is effective. Of course, in the case where the film thickness of the lowermost layer 30L is thicker than that of the oxide semiconductor layer 22, layer disconnection is likely to occur, and thus the structure of this embodiment is also effective.

[0039] Each of the plurality of thin film transistors 14 includes a corresponding first electrode 26 and second electrode 28 as a drain electrode and a source electrode. The channel width W (width of the channel region 24) of the thin film transistor 14 is smaller than the width of either of the drain electrode and the source electrode.

[0040] The passivation layer 36 is provided over the metal layer 30. The passivation layer 36 is a silicon oxide film and a silicon nitride film. The passivation layer 36 is covered with a planarization layer 38. The planarization layer 38 is formed of a resin such as photosensitive acrylic, which is superior in planarity of a surface to an inorganic insulating material formed by CVD (Chemical Vapor Deposition) or the like.

[0041] The plurality of pixel electrodes 34 are arranged over the planarization layer 38. The pixel electrodes 34 are formed as reflective electrodes. The pixel electrodes 34 are connected to the second electrodes 28 through the planarization layer 38 and the passivation layer 36.

[0042] An insulating layer 40, which is a partition wall between pixel regions adjacent to each other and is called a dam (rib), is formed over the planarization layer 38 and provided around the periphery of the pixel electrode 34. As the insulating layer 40, photosensitive acrylic or the like can be used like the planarization layer 38. The insulating layer 40 is opened so that the surface of the pixel electrode 34 is exposed as a light emitting region, and the opening end thereof is preferably tapered gently. If the opening end is formed in a steep shape, coverage of the electroluminescent layer 42 formed thereover is likely to be poor.

[0043] The electroluminescent layer 42 is layered over the pixel electrode 34 and is formed of, for example, an organic material. The electroluminescent layer 42 has a structure in which a hole injection / transport layer, a light emitting layer, and an electron injection / transport layer are layered in this order from the side of the pixel electrode 34. For example, a plurality of light emitting layers are provided corresponding to the plurality of pixel electrodes 34 and are separated, and at least one layer of the hole injection / transport layer and at least one layer of the electron injection / transport layer are continuously overlapped with the plurality of light emitting layers.

[0044] A counter electrode 44 is provided on the electroluminescent layer 42. Because a top-emission structure is employed, the counter electrode 44 is transparent. For example, the Mg layer and the Ag layer are formed as thin films sufficiently thin to allow light emitted from the electroluminescent layer 42 to pass through. Following the formation sequence of the electroluminescent layer 42, described later, the pixel electrode 34 becomes the anode, and the counter electrode 44 becomes the cathode. The plurality of pixel electrodes 34, the counter electrode 44, and the electroluminescent layer 42 located between the center portions of each pixel electrode 34 and the counter electrode 44 constitute a light-emitting element.

[0045] A sealing layer 46 is formed on the relative electrode 44. One of the functions of the sealing layer 46 is to prevent moisture from invading the electroluminescent layer 42 from the outside, so high gas resistance is required. The sealing layer 46 is formed into a stacked structure of an organic film 48 and a pair of inorganic films 50 (for example, silicon nitride films) that sandwich the organic film 48 from top to bottom. The pair of inorganic films 50 overlap in contact with the periphery of the organic film 48. A silicon oxide film or an amorphous silicon layer may also be provided between the inorganic film 50 and the organic film 48 for the purpose of improving adhesion. A reinforcing organic film 52 is stacked on the sealing layer 46. A polarizing plate 56 (for example, a circularly polarizing plate) is adhered to the reinforcing organic film 52 via an adhesive layer 54.

[0046] Figure 6 yes Figure 2 Another longitudinal cross-sectional view of the structure shown. The scanning line 18 formed as one piece with the gate electrode 16 is formed in Figure 1 The outside of the display area DA is connected to the wiring 58 included in the metal layer 30. An oxide semiconductor layer 22 is present between the scanning line 18 and the wiring 58. Its relatively thin film thickness, approximately 100 nm or less, ensures conductivity. This allows voltage to be applied from the wiring 58 to the scanning line 18 (gate electrode 16).

[0047] Figures 7 to 10 These are diagrams for explaining a method for manufacturing a display device according to an embodiment.

[0048] like Figure 7 As shown, a plurality of gate electrodes 16 are formed. Each of the plurality of gate electrodes 16 is formed in such a manner as to be integrated with a corresponding one of the plurality of scanning lines 18. The pattern of the gate electrode 16 is performed by dry etching with a fluorine-based material. Furthermore, a plurality of gate electrodes 16 are covered by forming a plurality of gate electrodes 16. Figures 4 to 6 The gate insulating layer 20 ( Figure 7 omitted).

[0049] like Figure 8 As shown, an oxide semiconductor layer 22 is formed. Next, a metal layer 30 is formed on the oxide semiconductor layer 22. The oxide semiconductor layer 22 and the metal layer 30 are formed on the entire surface of the substrate 10. The metal layer 30 is composed of a plurality of layers, and the details are as described above.

[0050] As Figure 9 shown, the metal layer 30 is patterned. Specifically, the metal layer 30 is patterned into a shape including a plurality of first electrodes 26 and a plurality of second electrodes 28. For example, chlorine gas is used in the patterning. The plurality of first electrodes 26 are each formed in a manner integrated with a corresponding one of the plurality of image signal lines 32. The patterned metal layer 30 is continuous between a pair of first electrodes 26A, 26B included in the thin film transistors 14A, 14B (see Figure 10 ) adjacent to each other.

[0051] As Figure 10 shown, after the patterning of the metal layer 30, the oxide semiconductor layer 22 is patterned. Specifically, the oxide semiconductor layer 22 is patterned into a shape including a plurality of channel regions 24. In the patterning, an etching mask not shown, for example, an etching liquid including oxalic acid is used. At the time of the patterning of the oxide semiconductor layer 22, the already patterned metal layer 30 functions as an etching mask in addition to the above-described etching mask not shown, and thus a pair of channel regions 24A, 24B included in the thin film transistors 14A, 14B adjacent to each other are continuous.

[0052] The plurality of channel regions 24 are each located between a corresponding one of the plurality of first electrodes 26 and a corresponding one of the plurality of second electrodes 28, and constitute a corresponding one of the plurality of thin film transistors 14. The plurality of thin film transistors 14 are each formed in a manner having a channel width W smaller than a width of either of a drain electrode and a source electrode.

[0053] According to the present embodiment, the oxide semiconductor layer 22 is continuous between a pair of channel regions 24A, 24B included in a pair of thin film transistors 14A, 14B adjacent to each other. That is, there is no end portion of the oxide semiconductor layer 22 under the metal layer 30. Thus, layer breakage of the metal layer 30 does not occur, and thus variation in characteristics of the transistor can be suppressed.

[0054] Figure 11 is a cross-sectional view of a display device which is a modification. In the above-described embodiment, an organic electroluminescent display device is described, and in the modification, a liquid crystal display device is described.

[0055] The liquid crystal display device is of a vertical electric field type. Thus, both of a pixel electrode 134 and a common electrode 144 are located under a liquid crystal layer 160. The liquid crystal layer 160 is sandwiched by upper and lower orientation films 162, and the pixel electrode 134 is located at a position further below the lower orientation film 162. An insulating film 164 is present between the pixel electrode 134 and the common electrode 144. A protective film 166 is provided above the upper orientation film 162. Other contents are the same as those of the above-described embodiment.

[0056] The present application is not limited to the above-described embodiments and can be variously modified. For example, the structures described in the embodiments can be replaced with substantially the same structures, structures that achieve the same effects, or structures that achieve the same objects.

Claims

1. A display device having a plurality of bottom-gate thin film transistors, characterized in that: having: a plurality of gate electrodes; a gate insulating layer covering the plurality of gate electrodes; an oxide semiconductor layer mounted on the gate insulating layer; and a metal layer composed of a plurality of layers, an ionization tendency of a lowermost layer of the plurality of layers being lower than an ionization tendency of an intermediate layer, the metal layer being mounted on the oxide semiconductor layer with the lowermost layer in contact with the oxide semiconductor layer, the oxide semiconductor layer including a plurality of channel regions, the metal layer including a plurality of first electrodes and a plurality of second electrodes, each of the plurality of channel regions being positioned between a corresponding one of the plurality of first electrodes and a corresponding one of the plurality of second electrodes, constituting a corresponding one of the plurality of thin film transistors, the oxide semiconductor layer being continuous between a pair of the channel regions included in a pair of the thin film transistors adjacent to each other, the metal layer being continuous between a pair of the first electrodes included in the pair of the thin film transistors adjacent to each other, a film thickness of the lowermost layer of the metal layer being smaller than a film thickness of the oxide semiconductor layer, each of the plurality of thin film transistors having a channel width smaller than a width of either of a drain electrode and a source electrode, and the channel width being uniform between the drain electrode and the source electrode.

2. The display device according to claim 1, wherein: each of the plurality of gate electrodes is integrated with a corresponding one of a plurality of scan lines, each of the plurality of first electrodes is integrated with a corresponding one of a plurality of image signal lines.

3. The display device according to claim 1, wherein: each of the plurality of second electrodes is connected to a corresponding one of a plurality of pixel electrodes.

4. The display device according to claim 1, wherein: an uppermost layer of the metal layer is formed of the same material as the lowermost layer, the intermediate layer is positioned between the lowermost layer and the uppermost layer.

5. The display device according to claim 1, wherein: the lowermost layer is formed of titanium, the intermediate layer is formed of aluminum.

6. A manufacturing method of a display device having a plurality of thin film transistors of a bottom-gate type, the manufacturing method of the display device comprising: a step of forming a plurality of gate electrodes; a step of forming a gate insulating layer in a manner covering the plurality of gate electrodes; a step of forming an oxide semiconductor layer in a manner mounted on the gate insulating layer; a step of forming a metal layer composed of a plurality of layers, an ionization tendency of a lowermost layer of the plurality of layers being lower than an ionization tendency of an intermediate layer, the metal layer being mounted on the oxide semiconductor layer with the lowermost layer in contact with the oxide semiconductor layer; a step of patterning the metal layer into a shape including a plurality of first electrodes and a plurality of second electrodes; and a step of patterning the oxide semiconductor layer into a shape including a plurality of channel regions after the patterning of the metal layer, each of the plurality of channel regions is positioned between a corresponding one of the plurality of first electrodes and a corresponding one of the plurality of second electrodes, and constitutes a corresponding one of the plurality of thin film transistors, the shape of the oxide semiconductor layer is continuous between a pair of the channel regions included in the thin film transistors adjacent to each other, the shape of the metal layer is continuous between a pair of the first electrodes included in the thin film transistors adjacent to each other, the film thickness of the lowermost layer of the metal layer is smaller than the film thickness of the oxide semiconductor layer, each of the plurality of thin film transistors is formed in a manner that has a channel width smaller than the width of either of a drain electrode and a source electrode and is equal between the drain electrode and the source electrode.

7. The method according to claim 6, wherein: each of the plurality of gate electrodes is integrated with a corresponding one of a plurality of scan lines, each of the plurality of first electrodes is integrated with a corresponding one of a plurality of image signal lines.

8. The method according to claim 6, wherein: the uppermost layer of the metal layer is formed of the same material as the lowermost layer, the intermediate layer is formed between the lowermost layer and the uppermost layer.

9. The method according to claim 6, wherein: the lowermost layer is formed using titanium, the intermediate layer is formed using aluminum.

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