A micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure

Abstract

A micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure, the structure is mainly composed of three layers of wafer-level conductor silicon and two layers of insulating materials, including: a base layer, which is made with grooves and multiple vertical interconnection structures, and a first insulating layer is deposited on the surface. The base layer is connected to the ground through an etched window on the first insulating layer and the grounded vertical interconnection structure to reduce coupling crosstalk noise; a device layer, which is etched with a sensing structure, a closed sealing ring and a shielding beam, and the grounded shielding beam reduces the coupling noise within the layer; a capping layer, which is insulated from the device layer by a second insulating layer, and a small gap is formed between the hollow area of ​​the second insulating layer and the sensing structure to enhance the electric field strength around the sensing structure and thus improve the sensitivity of the sensor. The present invention can realize the wafer-level packaging of electric field sensors, has the characteristics of sensitivity enhancement and noise reduction, and has a simple manufacturing process.

Description

Technical Field

[0001] The present disclosure relates to the field of sensor manufacturing technology, and in particular to a micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure. Background Art

[0002] Electric field sensors are devices that detect electric field strength and are widely used in many fields such as meteorological detection, aerospace, petrochemicals, and electricity. Micro electric field sensors based on MEMS technology have become a research hotspot and development direction for electric field sensors due to their small size, low cost, and mass production. At present, micro electric field sensors have problems such as small output signal, low signal-to-noise ratio, and small Q value, which restrict their application and development.

[0003] The existing packaging structure of micro electric field sensors needs to be installed and sealed one by one, which is not conducive to mass production. The packaging process cost is high, and the volume after packaging is much larger than the chip volume, which restricts the mass production and large-scale application of sensors. Wafer-level packaging technology can complete the electrical and mechanical connections between different levels of structures at one time, and at the same time realize the airtight or vacuum packaging of the structure on the entire wafer, with high product consistency, yield and reliability. The difficulty of wafer-level packaging of electric field sensors lies in the construction of the electric field sensing channel. So far, there has been no report on wafer-level packaging of electric field sensors.

[0004] Early MEMS devices mostly used silicon-glass structure to achieve wafer-level packaging, but there was a thermal mismatch problem between silicon and glass. The use of an all-silicon structure can solve the stress problem caused by thermal mismatch in the silicon-glass structure and avoid the interference of charge accumulation on the glass surface on the output signal. The all-silicon structure wafer-level packaging technology is an inevitable choice to improve device performance, achieve high-density integration with ICs, and then realize microsystems.

[0005] In the wafer-level packaging solution based on bonding, the electrical signals in the sealed cavity need to be led out horizontally through the planar electrodes or vertically through the TSV electrodes. In order to be compatible with other process steps, not affect the performance of the device, and ensure the airtightness of the device, there is often a problem of complex process flow. In addition, if the substrate needs to be grounded, additional process steps need to be added, and additional pads or metal leads need to be made. Summary of the invention

[0006] In view of the above problems, the present invention provides a micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure to solve the above technical problems.

[0007] One aspect of the present disclosure provides a micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure, including: a base layer, which is made with grooves and multiple vertical interconnection structures, and a first insulating layer is deposited on the surface, and a window for grounding the base layer is etched on the first insulating layer; a device layer, which is etched with a sensing structure, a closed sealing ring and a shielding beam; a cap layer, which is insulated from the device layer by a second insulating layer, and a gap is formed between the hollow area of ​​the second insulating layer and the sensing structure; the device layer and the base layer are connected by bonding insulation; the device layer, the cap layer and the base layer are all made of wafer-level conductive silicon.

[0008] Optionally, the sensing structure includes: a first anchor point, a second anchor point, a sensing structure, a driving structure, and an elastic beam; the first anchor point fixes the elastic beam to the surface of the second insulating layer, and the second anchor point fixes the sensing structure and the driving structure to the surface of the second insulating layer.

[0009] Optionally, the first anchor point, the second anchor point and the plurality of vertical interconnect structures are bonded one-to-one via a bonding dielectric layer, wherein the first anchor point is connected to an external ground circuit via the corresponding vertical interconnect structure.

[0010] Optionally, the window is etched in the first insulating layer corresponding to the first anchor point, and the base layer is connected to the grounded vertical interconnect structure while bonding or preparing the vertical interconnect structure.

[0011] Optionally, the shielding beam is connected to the first anchor point and grounded through the closed sealing ring.

[0012] At least one of the above technical solutions adopted in the embodiments of the present disclosure can achieve the following beneficial effects:

[0013] (1) The gap between the capping layer and the sensing structure of the structure provided by the present disclosure is in the micrometer range, which can change the distribution of the electric field to be measured above the sensing structure, effectively enhance the electric field strength around the sensing structure, increase the output sensing current, and thus improve the sensitivity of the sensor;

[0014] (2) The structure provided by the present invention can achieve noise reduction on multiple noise coupling channels, greatly improving the noise reduction performance: the substrate layer is connected to the grounded vertical interconnection structure via a window etched on the surface of the first insulating layer, which can reduce the crosstalk noise of the driving signal coupled to the output signal through the substrate; the grounded shielding beam can reduce the noise of the driving structure in the layer coupled to the sensing structure; the same-frequency noise of the input driving signal coupled to the surface of the sensing structure via the capping layer is modulated into double-frequency noise by the same-frequency vibration of the movable part of the sensing structure, which can be eliminated in the subsequent filtering circuit.

[0015] (3) The present invention can ground the substrate while bonding or preparing a vertical interconnection structure without the need for additional process steps, and the substrate is grounded through a grounded straight interconnection structure without the need to make additional pads or metal leads at other locations on the substrate, thereby reducing the surface area of ​​the substrate.

[0016] (4) The present disclosure realizes the wafer-level packaging of electric field sensors for the first time, and the manufacturing process is simple and effective. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] For a more complete understanding of the present disclosure and its advantages, reference will now be made to the following description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 A schematic diagram of a micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure provided by an embodiment of the present disclosure is schematically shown;

[0019] Figure 2 A three-dimensional schematic diagram of a device layer of a micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure provided by an embodiment of the present disclosure is schematically shown;

[0020] Figure 3 A three-dimensional schematic diagram of a substrate layer of a micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure provided by an embodiment of the present disclosure is schematically shown;

[0021] Figure 4 A schematic diagram of micro-nano processing of a device layer and a second insulating layer of a micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure provided by an embodiment of the present disclosure is shown;

[0022] Figure 5 A schematic diagram of micro-nano processing of a substrate layer of a micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure provided by an embodiment of the present disclosure is shown;

[0023] Figure 6 A schematic diagram of micro-nano processing of the overall device bonding of a micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure provided by an embodiment of the present disclosure is shown;

[0024] Figure 7 A schematic diagram of micro-nano processing of a substrate layer of a second micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure provided by an embodiment of the present disclosure is shown;

[0025] Figure 8 A schematic diagram of micro-nano processing of overall device bonding of a second micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure provided by an embodiment of the present disclosure is shown;

[0026] Fig. 9A schematic diagram of micro-nano processing of overall device bonding of a third micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure provided by an embodiment of the present disclosure is shown; Description of the drawings:

[0028] 100-capping layer; 200-second insulating layer; 300-device layer; 400-base layer; 310-sensing structure; 3111-first anchor point; 3112-second anchor point; 312-sensing structure; 313-driving structure; 314-elastic beam; 320-closed sealing ring; 330-shielding beam; 410-groove; 420-vertical interconnection structure, 4211-through hole of the vertical interconnection structure 420 corresponding to the first anchor point 3111, 4212-through hole of the vertical interconnection structure 420 corresponding to the second anchor point 3112; 422-metal pad; 423-conductive silicon column; 424-metal lead; 430-first insulating layer; 440-first insulating layer etching window corresponding to the first anchor point 3111; 450-getter; 460-bonding dielectric layer. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0030] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0031] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification, and should not be interpreted in an idealized or overly rigid manner.

[0032] See also Figure 1 , Figure 2 , Figure 3 and Figure 4 The present disclosure provides a micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure, including: a base layer 400, a device layer 300, a capping layer 100, a first insulating layer 430, and a second insulating layer 200.

[0033] The base layer 400 is provided with a groove 410 and a plurality of vertical interconnect structures 420 , and a first insulating layer 430 is deposited on the surface. A window 440 for grounding the base layer 400 is etched on the first insulating layer 430 .

[0034] The device layer 300 is etched with a sensing structure 310 , a closed sealing ring 320 and a shielding beam 330 .

[0035] The capping layer 100 is insulated from the device layer 300 by the second insulating layer 200 , and a gap is formed between the hollowed-out area of ​​the second insulating layer 200 and the sensing structure 310 .

[0036] The device layer 300 is insulatedly connected to the base layer 400 through bonding.

[0037] The device layer 300 , the capping layer 100 , and the base layer 400 are all made of wafer-level conductive silicon.

[0038] Optionally, the device layer 300 , the capping layer 100 , and the base layer 400 may be made of new materials such as gallium arsenide, iron-based materials, etc. in addition to being made of silicon-based materials.

[0039] In one embodiment of the present disclosure, refer to Figure 1 , Figure 2 and Figure 4 The sensing structure 310 and the shielding beam 330 are arranged in the rectangular closed sealing ring 320. The sensing structure 310 includes: a first anchor point 3111, a second anchor point 3112, a sensing structure 312, a driving structure 313, and an elastic beam 314. The first anchor point 3111 fixes the elastic beam 314 to the surface of the second insulating layer 200, and the second anchor point 3112 fixes the sensing structure 312 and the driving structure 313 to the surface of the second insulating layer 200. The sensing structure 312 includes at least one pair of sensing electrodes and a shielding electrode; the driving structure 313 includes at least one pair of driving electrodes; the shielding electrode and one of the driving electrodes in each pair of driving electrodes are connected to the elastic beam 314, and the sensing electrode and the other driving electrode in each pair of driving electrodes are fixed to the second insulating layer 200 through a second anchor point 3112. The shielding beam 330 is arranged between the sensing structure 312 and the driving structure 313, and one end is connected to the rectangular closed sealing ring 320.

[0040] See also Figure 1 and Figure 4, on the second insulating layer 200, in the rectangular area corresponding to the inner circle of the rectangular sealing ring 320, except for the positions corresponding to the first anchor point 3111 and the second anchor point 3112, the insulating material in the remaining areas is hollowed out, so that a small gap is formed between the sensing structure 310 and the capping layer 100. On the one hand, the gap provides a movement space for the sensing structure 310; on the other hand, when the gap is small enough, the gap can redistribute the electric field to be measured above the sensing structure 312, effectively enhance the electric field strength around the sensing structure 312, and thus improve the sensitivity of the sensor. The electric field sensor of the general device-level package cannot accurately achieve a gap of the order of microns between the sensing structure 310 and the capping layer 100. Since the micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure provided by the present disclosure is a wafer-level packaging structure, the base layer 400, the device layer 300, and the capping layer 100 are all made of wafer-level conductor silicon, which can make the gap distance between the sensing structure 310 and the capping layer 100 accurately controlled at the order of microns.

[0041] See also Figure 2 and Figure 3 , Figure 2 Schematically shows six second anchor points 3112 and two first anchor points 3111. Figure 3 Near the groove 410 of the base layer 400 shown on the left, a vertical interconnection structure 420 corresponding to the positions of the second anchor point 3112 and the first anchor point 3111 is provided. Figure 3 The right figure in the figure shows a cross-sectional schematic diagram of the base layer 400. It should be noted that the cross-sectional schematic diagram is not a true cross-sectional diagram of the base layer 400, but is only used to illustrate the difference between the positions corresponding to the second anchor point 3112 and the first anchor point 3111. In the cross-sectional schematic diagram, the through hole 4212 on the left indicates the through hole of the vertical interconnection structure 420 corresponding to the second anchor point 3112, and the through hole 4211 on the right indicates the through hole of the vertical interconnection structure 420 corresponding to the first anchor point 3111. Figures 5 to 9 The through holes on the left and right of the cross-sectional view represent the same Figure 3 The same is true and will not be repeated in the following description.

[0042] See also Figure 2 and Figure 3 , the middle of the base layer 400 is a groove 410, which provides a movement space for the sensing structure 310. A first insulating layer 430 is formed on the surface of the side with the groove or the entire surface of the base by thermal oxidation, CVD or PVD. Around the groove 410 of the base layer 400, vertical interconnection structures 420 are provided at positions corresponding to the second anchor point 3112 and the first anchor point 3111. The first anchor point 3111 and the second anchor point 3112 are bonded to the multiple vertical interconnection structures 420 in a one-to-one correspondence, wherein the first anchor point 3111 is connected to the external grounding circuit through the corresponding vertical interconnection structure 420. See Figure 3 In the right figure, the first insulating layer corresponding to the first anchor point 3111 is etched with the window 440, and the base layer 400 is connected to the grounded vertical interconnection structure 420 while bonding or preparing the vertical interconnection structure to reduce the crosstalk noise of the drive signal coupled to the output signal through the base. In addition, the vertical interconnection structure 420 bonded to the second anchor point 3112 corresponding to the sensing electrode is used to connect to the external detection circuit, and the vertical interconnection structure 420 bonded to the second anchor point 3112 corresponding to the driving electrode is used to connect to the external driving circuit. In addition to the second anchor point 3112 and the first anchor point 3111, the rectangular closed sealing ring 320 is also bonded to the first insulating layer 430.

[0043] Optionally, the bonding between the substrate layer and the device layer can be achieved through a bonding dielectric layer 460, and the bonding dielectric layer 460 is made on the surface of the substrate layer with the groove at a position corresponding to the rectangular closed sealing ring 320, the first anchor point 3111, and the second anchor point 3112, wherein the bonding dielectric layer 460 covers the window 440. Optionally, the bonding dielectric layer can be glass paste, polymer, metal or alloy, etc. Optionally, the metal or alloy bonding dielectric layer may include an adhesion barrier layer and a metal eutectic solder layer, the adhesion barrier layer may be Cr, Ti, Ni, W, etc., and the metal eutectic solder layer may be Au, AuIn, AuSn, CuSn, AuGe, AlGe, etc.

[0044] Optionally, the vertical interconnect structure 420 may include a through hole and a conductive structure vertically passing through the base layer 400, wherein the cross-sectional area of ​​the through hole is smaller than the area of ​​the corresponding anchor point, and the conductive structure may include a metal pad 422, a conductive silicon column 423 or a metal lead 424, etc.

[0045] Optionally, the first insulating layer etching window 440 can be made on the surface of the side of the substrate layer with the groove, and the electrical connection between the substrate and the grounded vertical interconnection structure is completed while the metal eutectic bonding is performed, thereby grounding the substrate; the first insulating layer etching window 440 can also be made on the surface of the side of the substrate layer without the groove, and the electrical connection between the substrate and the grounded vertical interconnection structure is completed while depositing metal to form a pad, etc. (i.e., preparing the conductive structure of the vertical interconnection structure). The electrical connection between the substrate and the grounded vertical interconnection structure is achieved through the etching window, and the substrate can be grounded while bonding or preparing the vertical interconnection structure, without the need for additional process steps, and the substrate is grounded through the grounded straight interconnection structure, and there is no need to make additional pads or metal leads at other locations on the substrate, thereby reducing the surface area of ​​the substrate, which is very necessary for many small-area sensor devices.

[0046] Optionally, a getter 450 is deposited in the groove 410 of the base layer 400. The getter 450 is used to realize vacuum packaging of the base layer 400 and the device layer 300. Optionally, the getter 450 can be composed of active metals such as Zr, Ti, V and alloys thereof, and these materials can also be doped with metal elements such as Co, Ni or Fe to improve the performance of the getter 450. For example, a Ti-based non-evaporable getter 450 can be used to make a Ti getter 450 film with a thickness of several hundred microns, and Au with a thickness of several tens of microns can be made thereon as a protective layer.

[0047] For further information, see Figure 2 and 3 Since the shielding electrode of the sensing structure 312 is connected to the elastic beam 314, the shielding electrode is actually connected to the external grounding circuit through the elastic beam 314, the first anchor point 3111 and the vertical interconnection structure 420, and similarly, the driving electrode connected to the elastic beam 314 is also grounded through the first anchor point 3111 and the vertical interconnection structure 420. The shielding beam 330 is located between the sensing structure 312 and the driving structure 313, one end of which is connected to the rectangular closed sealing ring 320, and the first anchor point 3111 is connected inside the rectangular closed sealing ring 320. The shielding beam 330 is connected to the first anchor point 3111 through the closed sealing ring and is grounded, which can reduce the noise of the driving structure 313 in the layer coupled to the sensing structure 312.

[0048] In the micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure provided by the present invention, the noise reduction effect is achieved through three structural designs: first, a window 440 is etched at a position corresponding to the first anchor point 3111 on the first insulating layer 430, and the substrate layer is connected to the grounded vertical interconnection structure while bonding or preparing the vertical interconnection structure to reduce the crosstalk noise of the driving signal coupled to the output signal through the substrate; second, the shielding beam 330 is grounded through the rectangular closed sealing ring 320, through the first anchor point 3111, the vertical interconnection structure 420 and the external grounding circuit. , to reduce the lateral noise of the driving structure 313 in the layer coupled to the sensing structure 312; thirdly, the wafer-level manufacturing process can make the mismatch of the capacitance between the capping layer 100 and the device layer 300 extremely small, reducing the error caused by the mismatch in the subsequent differential output, and the noise of the input driving signal coupled to the capping layer 100 is the same frequency noise of the input driving signal, but when the noise acts on the surface of the sensing structure 312, due to the modulation effect brought by the same frequency vibration of the shielding electrode, the noise will become a double frequency output, which will be eliminated in the subsequent filtering circuit. This structural design achieves noise reduction in multiple noise coupling channels and can significantly reduce noise interference.

[0049] Traditional electric field sensors use leads on the surface of the sensing structure to achieve signal transmission. Since there is air between the input drive lead and the output sensing lead, the drive signal is inevitably coupled to the sensing lead, forming coupling noise. Different from the traditional lead solution, the micro electric field sensor wafer-level package sensitivity enhancement and noise reduction structure provided in the present disclosure realizes signal transmission on the substrate layer. The grounded substrate can greatly reduce the noise of the drive signal coupled to the sensing signal.

[0050] Embodiment 1

[0051] The manufacturing process steps of the wafer-level packaging sensitivity enhancement and noise reduction structure of a micro electric field sensor disclosed in the present invention are as follows.

[0052] See also Figure 4 , using the support layer of the SOI wafer as the capping layer 100, and processing the structural silicon layer and the buried oxide layer of the SOI wafer into the device layer 300 and the second insulating layer 200 in sequence, including: etching a first anchor point 3111, a second anchor point 3112, a sensing structure 312, a driving structure 313, an elastic beam 314, a rectangular closed sealing ring 320 and a shielding beam 330 on the structural silicon layer of an SOI wafer to obtain the device layer 300; releasing the buried oxide layer in the rectangular area corresponding to the inner circle of the rectangular sealing ring 320 and excluding the positions corresponding to the first anchor point 3111 and the second anchor point 3112 to obtain the second insulating layer 200; using the support layer of the SOI wafer as the capping layer 100.

[0053] See also Figure 5 , etching a groove 410 on a conductive silicon wafer, and etching through holes 4211 and 4212 of a vertical interconnect structure 420 on the conductive silicon wafer to obtain a base layer 400; growing a first insulating layer 430 on the surface of the base layer 400 and on the inner wall of the through hole; etching a window 440 on the first insulating layer 430 next to the through hole 4211; growing a bonding dielectric layer 460 on the first insulating layer 430 at positions corresponding to the rectangular closed sealing ring 320 of the device layer 300, the first anchor point 3111, and the second anchor point 3112 and on the inner walls of the through holes 4211 and 4212; and growing a thin layer of getter 450 in the groove 410 of the base layer 400.

[0054] See also Figure 6, in a vacuum environment, the rectangular closed sealing ring 320, the first anchor point 3111, and the second anchor point 3112 prepared on the SOI wafer are bonded to the prepared conductor silicon wafer, and the activation of the getter 450 is completed at the same time; a metal seed layer is sputtered at the bottom of the base layer 400 and in the through holes 4211, 4212, and a metal layer several microns thick is electroplated in the through holes to form a conformal through silicon via (TSV); the deposited metal layer is patterned by photolithography and etching to form a metal pad 422. At this time, the through holes 4211, 4212 of the base layer 400 and the metal pad 422 form a vertical interconnection structure 420. After completing the above steps, the rectangular closed sealing ring 320 is diced along the periphery to obtain a micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure provided in the embodiment of the present disclosure.

[0055] Embodiment 2

[0056] The steps for preparing another micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure disclosed in the present invention are as follows.

[0057] In this embodiment, the method of preparing the device layer 300 , the second insulating layer 200 , and the capping layer 100 is the same as that in the first embodiment.

[0058] See also Figure 7 , a groove 410 is etched on a conductive silicon wafer to obtain a base layer 400; a first insulating layer 430 is grown on the upper surface of the base layer 400; a window 440 is etched on the first insulating layer 430 at a position corresponding to the first anchor point 3111 and the second anchor point 3112; a bonding dielectric layer 460 is grown on the first insulating layer 430 at a position corresponding to the rectangular closed sealing ring 320 of the device layer 300, the first anchor point 3111, and the second anchor point 3112, wherein the bonding dielectric layer 460 covers the window 440 on the first insulating layer 430; a thin layer of getter 450 is grown in the groove 410 of the base layer 400.

[0059] See also Figure 8In a vacuum environment, the rectangular closed sealing ring 320, the first anchor point 3111, and the second anchor point 3112 prepared on the SOI wafer are bonded to the prepared conductor silicon wafer, and the activation of the getter 450 is completed at the same time; a metal pad 422 is made at the bottom of the base layer 400 at a position corresponding to the window 440; then silicon etching is performed at this position, the cross-sectional area of ​​the through hole 4211 corresponding to the first anchor point 3111 is smaller than the area of ​​the corresponding window 440, and the cross-sectional area of ​​the through hole 4212 corresponding to the second anchor point 3111 is larger than the area of ​​the corresponding window 440, forming a conductive silicon column 423 with a metal pad 422, the conductive silicon column 423 is vertically connected to the bonding medium layer 460, and the conductive silicon column 423 can be filled with insulating material. At this time, the metal pad 422, the conductive silicon column 423 and the through holes 4211 and 4212 constitute a vertical interconnection structure 420. After completing the above steps, the rectangular closed sealing ring 320 is sliced ​​along its periphery to obtain another micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure provided by an embodiment of the present disclosure.

[0060] Embodiment 3

[0061] Based on the second embodiment, this embodiment provides another method for manufacturing a vertical interconnection structure 420 .

[0062] In this embodiment, as in the second embodiment, refer to Figure 4 The device layer 300, the second insulating layer 200, and the capping layer 100 are prepared by the method shown in FIG. Figure 7 The method shown prepares a base layer 400, a first insulating layer 430, a bonding dielectric layer 460, and a getter 450 thin layer, etc.

[0063] See also Fig. 9 First, as in the second embodiment, in a vacuum environment, the rectangular closed sealing ring 320, the first anchor point 3111, and the second anchor point 3112 prepared on the SOI wafer are bonded to the prepared conductor silicon wafer, and the getter 450 is activated at the same time; then, silicon is etched at the corresponding positions of the first anchor point 3111 and the second anchor point 3112 at the bottom of the base layer 400 to form columnar through holes 4211 and 4212, which are perpendicular to the bonding The dielectric layer 460 is connected to the bonding dielectric layer 460, the cross-sectional area of ​​the through hole 4211 is smaller than the area of ​​the corresponding window 440, and the cross-sectional area of ​​the through hole 4212 is larger than the area of ​​the corresponding window 440; a metal lead 424 is made in the through hole, one end of the lead is connected to the bonding dielectric layer 460, and the other end extends out of the through holes 4211 and 4212 for connecting to an external circuit. At this time, the metal lead 424 and the through holes 4211 and 4212 constitute a vertical interconnection structure 420. After completing the above steps, the wafer-level package sensitivity enhancement and noise reduction structure of a micro electric field sensor provided in the embodiment of the present disclosure is obtained by dicing along the periphery of the rectangular closed sealing ring 320.

[0064] In the above embodiments, a window 440 is etched out of the first insulating layer 430 corresponding to the first anchor point 3111 to expose the base layer 400, and the base layer 400 is grounded to the grounded vertical interconnection structure 420 while bonding or preparing the vertical interconnection structure. No additional process is required, and no additional pads or metal leads are required to be made at other locations on the substrate.

[0065] The micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure provided by the present invention has a small gap between the cap layer 100 and the sensing structure 310, which can effectively enhance the electric field strength around the sensing structure 312, increase the output sensing current, and thus improve the sensor sensitivity; the design of the base layer 400 being grounded, the shielding beam 330 being grounded, and the cap layer 100 can all reduce the noise of the sensing signal; this structure can ground the substrate while bonding or preparing a vertical interconnection structure, and there is no need to make additional pads or metal leads at other locations on the substrate; the entire process realizes the wafer-level packaging of electric field sensors for the first time, and the manufacturing process is simple.

[0066] It will be appreciated by those skilled in the art that the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways, even if such combinations and / or combinations are not explicitly described in the present disclosure. In particular, the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways without departing from the spirit and teachings of the present disclosure. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0067] Although the present disclosure has been shown and described with reference to specific exemplary embodiments of the present disclosure, it should be understood by those skilled in the art that various changes in form and details may be made to the present disclosure without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-mentioned embodiments, but should be determined not only by the appended claims, but also by the equivalents of the appended claims.

Claims

1. A micro electric field sensor wafer-level packaging sensitivity enhancement and noise reduction structure, characterized in that: include: A base layer is provided with grooves and a plurality of vertical interconnect structures, a first insulating layer is deposited on the surface, and a window for grounding the base layer is etched on the first insulating layer; A device layer, on which a sensing structure, a closed sealing ring and a shielding beam are etched, wherein the closed sealing ring is connected to the shielding beam and is in a grounded state; A capping layer is insulated from the device layer through a second insulating layer, and a gap is formed between the second insulating layer and the sensing structure through a hollowed-out area, wherein the gap is a gap of micrometer order; The device layer is insulated and connected to the substrate layer by bonding; The device layer, the capping layer and the base layer are all made of wafer-level conductive silicon.

2. The structure according to claim 1, characterized in that: The sensing structure comprises: A first anchor point, a second anchor point, a sensing structure, a driving structure, and an elastic beam; The first anchor point fixes the elastic beam on the surface of the second insulating layer, and the second anchor point fixes the sensing structure and the driving structure on the surface of the second insulating layer.

3. The structure according to claim 2, characterized in that: The first anchor point and the second anchor point are bonded to the plurality of vertical interconnect structures in a one-to-one correspondence, wherein the first anchor point is connected to an external ground circuit through a corresponding vertical interconnect structure.

4. The structure according to claim 2, characterized in that: The first insulating layer corresponding to the first anchor point is etched with the window, and the base layer is connected to the grounded vertical interconnection structure while bonding or preparing the vertical interconnection structure.

5. The structure according to claim 3, characterized in that: The shielding beam is connected to the first anchor point and grounded through the closed sealing ring.

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