Display device

Abstract

A display apparatus is provided. The display apparatus includes a display panel, a contrast analyzer, a contrast processor, and a data driver. The display panel includes a plurality of sub-display regions. The display panel is configured to display an image based on input image data. The contrast analyzer is configured to analyze the input image data in a time-division method. The contrast processor is configured to adjust a contrast of the input image data based on an analysis result of the contrast analyzer. The data driver is configured to generate a data voltage based on output data of the contrast processor. A number of contrast analysis cores of the contrast analyzer is determined according to a number of the sub-display regions and a frame rate.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device and a method for driving the display device. More specifically, embodiments of the present invention relate to a display device that operates a contrast analysis core in a time-division manner to reduce the number of contrast analysis cores, and a method for driving the display device. Background Technology

[0002] Display devices can include flexible display panels. Flexible display panels can be used to realize foldable display devices, rollable display devices, bendable display devices, and sliding display devices.

[0003] Typically, a display device includes a display panel and a display panel driver. The display panel includes multiple gate lines and multiple data lines. The display panel driver includes a gate driver, a data driver, and a drive controller. The gate driver outputs gate signals to the gate lines. The data driver outputs data voltages to the data lines. The drive controller controls the gate driver and the data driver.

[0004] The drive controller may include a contrast compensator for enhancing the contrast of the image. A display device including a flexible display panel may include multiple sub-display areas. To compensate for the contrast for each sub-display area, the number of contrast compensator cores increases, resulting in an increase in the size of the display panel driver and an increase in the power consumption of the display device. Summary of the Invention

[0005] An embodiment of the present invention provides a display device that operates a contrast analysis core in a time-division manner to reduce the size of the display panel driver and the power consumption of the display device.

[0006] Embodiments of the present invention also provide a method for driving a display device.

[0007] In an embodiment of the display device according to the present invention, the display device includes a display panel, a contrast analyzer, a contrast processor, and a data driver. The display panel includes a plurality of sub-display areas. The display panel is configured to display an image based on an input image. The contrast analyzer is configured to analyze the input image data using a time-division multiplexing method. The contrast processor is configured to adjust the contrast of the input image data based on the analysis results of the contrast analyzer. The data driver is configured to generate a data voltage based on the output data of the contrast processor. The number of contrast analysis cores in the contrast analyzer is determined according to the number of sub-display areas and the frame rate.

[0008] In this embodiment, the number of contrast analysis kernels can be increased as the number of sub-display areas increases.

[0009] In this embodiment, the number of contrast analysis kernels can be reduced as the frame rate increases.

[0010] In an embodiment, the number of contrast processor cores in the contrast processor can be equal to the number of sub-display areas.

[0011] In this embodiment, the number of contrast analysis cores may be less than the number of contrast processor cores.

[0012] In one embodiment, the display device may further include a switch that connects a contrast analysis core to a plurality of contrast processor cores.

[0013] In an embodiment, the display device may further include a multiplexer configured to selectively output one of the outputs of a plurality of contrast processor cores.

[0014] In an embodiment, when the number of sub-display areas is two and the frame rate is 60Hz, the number of contrast analysis cores can be one, and the number of contrast processor cores can be two.

[0015] In an embodiment, when the number of sub-display areas is four and the frame rate is 60Hz, the number of contrast analysis cores can be two, and the number of contrast processor cores can be four.

[0016] In an embodiment, when the number of sub-display areas is four and the frame rate is 120Hz, the number of contrast analysis cores can be one, and the number of contrast processor cores can be four.

[0017] In an embodiment, when the number of sub-display areas is eight and the frame rate is 120Hz, the number of contrast analysis cores can be two, and the number of contrast processor cores can be eight.

[0018] In an embodiment, when the number of sub-display areas is sixteen and the frame rate is 240Hz, the number of contrast analysis cores can be two, and the number of contrast processor cores can be sixteen.

[0019] In an embodiment, the contrast analyzer can be configured to convert a first color coordinate of the input image data into a second color coordinate to extract the luminance component of the input image data, generate a luminance histogram based on the luminance component of the input image data, generate a low luminance group, a medium luminance group, and a high luminance group based on the luminance histogram, and determine a first threshold between the low luminance group and the medium luminance group and a second threshold between the medium luminance group and the high luminance group.

[0020] In this embodiment, the first threshold and the second threshold can be updated for each frame.

[0021] In an embodiment, when the grayscale data included in the mid-brightness group is greater than a reference value, the contrast processor can be configured to compensate the input image data to increase its contrast. When the grayscale data included in the mid-brightness group is less than a reference value, the contrast processor can be configured to compensate the input image data to decrease its contrast.

[0022] In an embodiment of a method for driving a display device according to the present invention, the method includes: analyzing input image data applied to a display panel comprising a plurality of sub-display areas using a time-division multiplexing method; adjusting the contrast of the input image data based on the analysis results; and generating a data voltage based on the image data having the adjusted contrast. The number of contrast analysis kernels for analyzing the input image data is determined according to the number of sub-display areas and the frame rate.

[0023] In this embodiment, the number of contrast analysis kernels can be increased as the number of sub-display areas increases.

[0024] In this embodiment, the number of contrast analysis kernels can be reduced as the frame rate increases.

[0025] In an embodiment, the step of analyzing input image data may include converting a first color coordinate of the input image data into a second color coordinate to extract the luminance component of the input image data; generating a luminance histogram based on the luminance component of the input image data; generating a low luminance group, a medium luminance group, and a high luminance group based on the luminance histogram; and determining a first threshold between the low luminance group and the medium luminance group and a second threshold between the medium luminance group and the high luminance group.

[0026] In this embodiment, when the grayscale data included in the mid-brightness group is greater than a reference value, the input image data can be compensated to increase its contrast. When the grayscale data included in the mid-brightness group is less than a reference value, the input image data can be compensated to decrease its contrast.

[0027] According to the display device and the method of driving the display device, in a display device including a display panel containing multiple sub-display areas, the contrast analysis core can be operated in a time-division manner, thereby reducing the number of contrast analysis cores.

[0028] Reducing the number of contrast analysis cores allows for a smaller display panel driver and reduced power consumption in the display device. Attached Figure Description

[0029] The above and other features and advantages of the present invention will become more apparent from the detailed description of embodiments of the present invention with reference to the accompanying drawings, in which:

[0030] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention;

[0031] Figure 2 It is shown Figure 1 A block diagram of the drive controller;

[0032] Figure 3 and Figure 4 It is shown Figure 2 A graph showing the operation of the contrast processor;

[0033] Figure 5 It shows when Figure 1 A conceptual diagram illustrating an example of input and source image data when the display device has a frame rate of 50Hz;

[0034] Figure 6 It shows when Figure 1 A conceptual diagram illustrating an example of input and source image data when the frame rate of the display device is 60Hz;

[0035] Figure 7 It is shown Figure 1 A conceptual diagram of an example display panel comprising four areas;

[0036] Figure 8 It is shown that it is used for Figure 7 A conceptual diagram of a contrast analyzer and contrast processor for a display panel;

[0037] Figure 9 It is shown that it is used for Figure 7 A block diagram of the contrast analyzer and contrast processor of the display panel;

[0038] Figure 10 It is shown Figure 1 A conceptual diagram of an example display panel comprising eight areas;

[0039] Figure 11 and Figure 12 It is shown that it is used for Figure 10 A conceptual diagram of a contrast analyzer and contrast processor for a display panel;

[0040] Figure 13 It is shown that it is used for Figure 10 A block diagram of the contrast analyzer and contrast processor of the display panel;

[0041] Figure 14 It is shown that it is used for Figure 10 A conceptual diagram of a contrast analyzer and contrast processor for a display panel;

[0042] Figure 15 It is shown that it is used for Figure 10A block diagram of the contrast analyzer and contrast processor of the display panel;

[0043] Figure 16 It is shown Figure 1 A conceptual diagram of an example display panel comprising eight areas;

[0044] Figure 17 and Figure 18 It is shown that it is used for Figure 16 A conceptual diagram of a contrast analyzer and contrast processor for a display panel;

[0045] Figure 19 It is shown that it is used for Figure 16 A block diagram of the contrast analyzer and contrast processor of the display panel;

[0046] Figure 20 It is shown Figure 1 A conceptual diagram of an example display panel comprising 16 zones;

[0047] Figure 21 and Figure 22 It is shown that it is used for Figure 20 A conceptual diagram of a contrast analyzer and contrast processor for a display panel;

[0048] Figure 23 It shows the basis Figure 1 A table showing the number of sub-display areas and the number of contrast analysis cores for the frame rate of the display panel; and

[0049] Figure 24 It shows the basis Figure 1 A table showing the number of sub-display areas and the number of contrast analysis cores for the display panel. Detailed Implementation

[0050] The concept of the present invention will be described in detail below with reference to the accompanying drawings.

[0051] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention.

[0052] Reference Figure 1 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500. The display panel driver may also include a transmitter driver 600.

[0053] The drive controller 200 and the data driver 500 can be embedded in a single integrated circuit (IC) chip. For example, the drive controller 200, the gamma reference voltage generator 400, and the data driver 500 can be embedded in a single integrated circuit (IC) chip. A drive module that includes at least the drive controller 200 and the data driver 500 embedded in a single integrated circuit (IC) chip can be referred to as a timing controller embedded data driver (TED).

[0054] The display panel 100 has a display area AA in which an image is displayed and a peripheral area PA adjacent to the display area AA.

[0055] The display panel 100 includes multiple gate lines GL, multiple data lines DL, and multiple pixels P connected to the gate lines GL and the data lines DL. The gate lines GL extend in a first direction D1, and the data lines DL extend in a second direction D2 that intersects the first direction D1.

[0056] Display panel 100 may include multiple areas. These multiple areas may include sub-display areas and sub-off areas. Input image data may be provided to the corresponding sub-display area. Conversely, input image data may not be provided to the sub-off area. Display panel 100 may be a flexible display panel. For example, the display device may be a foldable display device. For example, the display device may be a rollable display device. The display device may be a bendable display device. The display device may be a flexible display device. The display device may be a sliding display device.

[0057] The drive controller 200 receives input image data IMG and input control signals CONT from an external device. The input image data IMG may include red, green, and blue image data. The input image data IMG may also include white, magenta, yellow, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0058] The drive controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0059] The drive controller 200 generates a first control signal CONT1 based on the input control signal CONT for controlling the operation of the gate driver 300, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0060] The drive controller 200 generates a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver 500, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0061] The drive controller 200 generates a data signal DATA based on the input image data IMG. The drive controller 200 outputs the data signal DATA to the data driver 500.

[0062] The drive controller 200 generates a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and outputs the third control signal CONT3 to the gamma reference voltage generator 400.

[0063] The drive controller 200 generates a fourth control signal CONT4 based on the input control signal CONT for controlling the operation of the transmitter driver 600, and outputs the fourth control signal CONT4 to the transmitter driver 600.

[0064] The gate driver 300 generates a gate signal for driving the gate line GL in response to a first control signal CONT1 received from the drive controller 200. The gate driver 300 outputs the gate signal to the gate line GL. For example, the gate driver 300 may sequentially output the gate signal to the gate line GL.

[0065] In one embodiment, the gate driver 300 may be integrated into the peripheral area PA of the display panel 100.

[0066] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA.

[0067] In an embodiment, the gamma reference voltage generator 400 may be located in the drive controller 200 or the data driver 500.

[0068] The data driver 500 receives a second control signal CONT2 and a data signal DATA from the drive controller 200, and receives a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 uses the gamma reference voltage VGREF to convert the data signal DATA into a data voltage of analog type. The data driver 500 outputs the data voltage to the data line DL.

[0069] Transmit driver 600 can generate a transmit signal to drive transmit line EL. Transmit driver 600 can also output the transmit signal to transmit line EL. For example, transmit driver 600 can be integrated into display panel 100. For example, transmit driver 600 can be mounted on display panel 100. Although in Figure 1 In this embodiment, the gate driver 300 applies a gate signal to the pixel P from a first side of the display panel 100, and the emitter driver 600 applies an emitter signal to the pixel P from a second side of the display panel 100. However, the present invention is not limited to this. Optionally, the gate driver 300 and the emitter driver 600 can apply the gate signal and the emitter signal to the pixel P from the first side of the display panel 100. Optionally, the gate driver 300 and the emitter driver 600 can apply the gate signal and the emitter signal to the pixel P from both sides of the display panel 100.

[0070] Figure 2 It is shown Figure 1 Block diagram of the drive controller 200. Figure 3 and Figure 4 It is shown Figure 2 A graph showing the operation of the contrast processor 240.

[0071] Reference Figures 1 to 4 The drive controller 200 may include a contrast analyzer 220 and a contrast processor 240. When the drive controller 200 is integrally formed with the data driver 500, the contrast analyzer 220 and the contrast processor 240 may also be integrally formed with the data driver 500.

[0072] The contrast analyzer 220 can analyze the input image data IMG in a time-division manner. For example, the contrast analyzer 220 can analyze the input image data corresponding to the first sub-display area of ​​the display panel 100 in the first frame, and can analyze the input image data corresponding to the second sub-display area of ​​the display panel 100 in the second frame.

[0073] The contrast processor 240 can adjust the contrast of the input image data IMG based on the analysis results of the contrast analyzer 220. The output image data IMG2 of the contrast processor 240 can be image data with adjusted contrast from the input image data IMG.

[0074] The data driver 500 can generate a data voltage based on the output image data IMG2 of the contrast processor 240.

[0075] The contrast analyzer 220 can convert the first color coordinates of the input image data IMG to second color coordinates to extract the luminance component of the input image data IMG. The contrast analyzer 220 can generate a luminance histogram based on the luminance component of the input image data IMG. The contrast analyzer 220 can generate low-luminance, medium-luminance, and high-luminance groups based on the luminance histogram, and can determine a first threshold between the low-luminance and medium-luminance groups and a second threshold between the medium-luminance and high-luminance groups.

[0076] For example, the first color coordinates can be RGB color coordinates. The second color coordinates can be YCbCr color coordinates. The contrast analyzer 220 can extract the color components (Y components) of the input image data IMG, which have been converted to YCbCr color coordinates. The contrast analyzer 220 can generate low-brightness groups, medium-brightness groups, and high-brightness groups by arranging the luminance components (Y components) of all image data in the frames of the input image data IMG. The contrast analyzer 220 can generate low-brightness groups, medium-brightness groups, and high-brightness groups for each frame.

[0077] The first and second thresholds can be updated for each frame based on the analysis results of previous frames. For example, the first and second thresholds for the current frame can be determined based on the analysis results of the frame immediately preceding the current frame. Alternatively, the first and second thresholds for the current frame can be determined by accumulating the analysis results of the previous frames.

[0078] When the grayscale data included in the mid-brightness group is greater than the reference value, the contrast processor 240 can compensate the input image data IMG to increase the contrast of the input image data IMG. When the grayscale data included in the mid-brightness group is less than the reference value, the contrast processor 240 can compensate the input image data IMG to decrease the contrast of the input image data IMG.

[0079] For example, when the input image data IMG represents a landscape in cloudy weather, the grayscale data, including in the mid-brightness group, will be larger than the reference value. In this case, by increasing the contrast of the input image data IMG, the image quality of the input image data IMG can be improved to resemble a landscape in sunny weather.

[0080] For example, when the grayscale data included in the medium brightness group is less than a reference value, the input image data IMG can primarily consist of the high brightness group, primarily consist of the low brightness group, or primarily consist of both the high brightness group and the low brightness group. In this case, reducing the contrast of the input image data IMG can enhance image quality.

[0081] Figure 3 The first curve C1, which has an S-shape, illustrates the case of increasing the contrast of the input image data IMG. Figure 3 The interval between the first output brightness LO1, the second output brightness LO2 and the third output brightness LO3 is larger than the interval between the first input brightness LI1, the second input brightness LI2 and the third input brightness LI3, so that the contrast of the output image data IMG2 can be increased compared with the contrast of the input image data IMG.

[0082] Figure 4 The case of reducing the contrast of the input image data IMG is illustrated using a second curve C2 with an inverted S-shape. Figure 4 The interval between the first output brightness LO1, the second output brightness LO2 and the third output brightness LO3 is smaller than the interval between the first input brightness LI1, the second input brightness LI2 and the third input brightness LI3, so that the contrast of the output image data IMG2 can be reduced compared with the contrast of the input image data IMG.

[0083] Figure 5 It shows when Figure 1 A conceptual diagram of an example of input image data (IMG) and source image data when the display device has a frame rate of 50Hz. Figure 6 It shows when Figure 1 A conceptual diagram of an example of input image data (IMG) and source image data when the display device has a frame rate of 60Hz.

[0084] Reference Figure 5 The source image data can have a frame rate of 25Hz, and the input image data IMG of the display device can have a frame rate of 50Hz. The display device has a frame rate of 50Hz, allowing the host to convert the 25Hz source image data frame rate to 50Hz to provide the input image data IMG with a 50Hz frame rate to the display device's drive controller 200. Each frame image in the source image data can be copied to form two consecutive identical frame images. For example, the first frame image F1 and the second frame image F2 of the source image data are copied twice to form the first and second frame images F1-F1 and the third and fourth frame images F2-F2. This image conversion method can be referred to as the 2-2 pull-down method.

[0085] Reference Figure 6The source image data can have a frame rate of 24Hz, and the input image data IMG of the display device can have a frame rate of 60Hz. The display device has a frame rate of 60Hz, allowing the host to convert the 24Hz source image data frame rate to 60Hz to provide the input image data IMG with a 60Hz frame rate to the display device's drive controller 200. For this purpose, odd-numbered frames of the source image data can be copied to form two consecutive identical frame images, and even-numbered frames can be copied to form three consecutive identical frame images. For example, the first frame image F1 of the source image data is copied twice, and the second frame image F2 of the source image data is copied three times to form the first and second frame images F1-F1, and the third, fourth, and fifth frame images F2-F2-F2. This image conversion method can be referred to as the 2-3 pull-down method.

[0086] Figure 7 It is shown Figure 1 The following is a conceptual diagram of a display panel 100 comprising four zones. The four zones include two sub-display zones A1 and A2 and two sub-off zones OFF and OFF. Figure 8 It is shown that it is used for Figure 7 A concept diagram of the contrast analyzer 220 and contrast processor 240 of the display panel 100. Figure 9 It is shown that it is used for Figure 7 A block diagram of the contrast analyzer 220 and contrast processor 240 of the display panel 100.

[0087] Reference Figures 1 to 9 In this embodiment, the display panel 100 may include four regions: OFF, A1, OFF, and A2. Two of the four regions are sub-display regions A1 and A2 that have input image data (IMG), and the other two are sub-off regions OFF and OFF that do not have input image data (IMG). In this embodiment, the frame rate can be 60Hz.

[0088] exist Figure 7 In this context, the two sub-off regions OFF and OFF can represent areas where images are not displayed to the user depending on the specific structure of the display device (e.g., foldable display device, rollable display device, bendable display device, flexible display device, and sliding display device).

[0089] In addition, depending on the structural changes of the display device (e.g., foldable display device, rollable display device, bendable display device, flexible display device, and sliding display device), the positions of the four regions OFF, A1, OFF, and A2 can be switched, the positions of the boundaries between the four regions OFF, A1, OFF, and A2 can be moved, or the sizes of the four regions OFF, A1, OFF, and A2 can be changed. Figure 7 The display panel 100 includes two sub-display areas A1 and A2. Therefore, the input image data IMG includes sub-input image data corresponding to the first sub-display area A1 and sub-input image data corresponding to the second sub-display area A2.

[0090] The contrast analyzer 220 may include a single contrast analysis core or multiple contrast analysis cores. The contrast processor 240 may include multiple contrast processor cores.

[0091] A contrast analysis core represents a unit module that analyzes the contrast of the input image data (IMG). When the drive controller 200 is an IC chip, each of the contrast analysis cores can be included within the IC chip.

[0092] A contrast processor core represents a unit module that adjusts the contrast of the input image data IMG based on the analysis results of the contrast analyzer 220. When the drive controller 200 is an IC chip, each of the contrast processor cores can be included in the IC chip.

[0093] In this embodiment, the number of contrast analysis cores in the contrast analyzer 220 can be determined based on the number of sub-display areas and the frame rate.

[0094] As the number of sub-display regions increases, the number of contrast analysis kernels can increase. As the frame rate increases, the number of contrast analysis kernels can decrease. For example... Figure 5 and Figure 6 As shown, although the frame rate of the input image data IMG is 50Hz or 60Hz, the frame rate of the source image data can be 25Hz or 24Hz, which is lower than the frame rate of the input image data IMG. Therefore, even if the contrast analyzer 220 operates in a time-division manner and the number of contrast analysis cores of the contrast analyzer 220 is reduced, the display quality of the display device will not be affected. Furthermore, the user's eye may not be able to readily perceive changes in the image within 1 / 30th of a second. Consequently, even if the contrast analysis period of the contrast analyzer 220 is reduced to 1 / 30th of a second, the display quality of the display device will not be affected.

[0095] In this embodiment, the number of contrast processor cores in the contrast processor 240 can be set to be equal to the number of sub-display areas. The number of contrast analysis cores can be less than the number of contrast processor cores.

[0096] In this embodiment, there can be two sub-display areas A1 and A2, and the frame rate can be 60Hz. There can be one contrast analysis core and two contrast processor cores.

[0097] exist Figure 8 In the reference frame index, the contrast analysis kernel can analyze the input image data (i.e., sub-input image data) of sub-display area A1 in the first frame, and the input image data (i.e., sub-input image data) of sub-display area A2 in the second frame. The contrast analysis kernel can analyze the input image data of sub-display area A1 in the third frame, and the input image data of sub-display area A2 in the fourth frame.

[0098] The contrast analysis kernel analyzes the input image data of display areas A1 and A2 at a period of 1 / 30 of a second. The contrast analysis kernel can divide the input image data, provided at a frame rate of 60Hz, into two parts to operate using a time-division multiplexing method.

[0099] The drive controller 200 may also include a switch AS for connecting the contrast analysis core to multiple contrast processor cores (see...). Figure 9 In this embodiment, the switch AS can selectively connect the contrast analysis core to two contrast processor cores. In the second frame, the switch AS is connected to the first contrast processor core, causing the contrast analysis core to output the analysis results of the input image data of sub-display area A1 in the first frame to the first contrast processor core. In the third frame, the switch AS is connected to the second contrast processor core, causing the contrast analysis core to output the analysis results of the input image data of sub-display area A2 in the second frame to the second contrast processor core.

[0100] The drive controller 200 may further include a multiplexer that selectively outputs one of the outputs of the contrast processor cores. In this embodiment, the multiplexer may, in response to the output selection signal SEL, output one of the outputs of the first contrast processor core and the second contrast processor core as output image data IMG2.

[0101] Figure 10 It is shown Figure 1 The following is a conceptual diagram of a display panel 100 comprising eight zones. The eight zones include four sub-display zones A1, A2, A3, and A4, and four sub-off zones OFF, OFF, OFF, and OFF. Figure 11 and Figure 12It is shown that it is used for Figure 10 A concept diagram of the contrast analyzer 220 and contrast processor 240 of the display panel 100. Figure 13 It is shown that it is used for Figure 10 A block diagram of the contrast analyzer 220 and contrast processor 240 of the display panel 100.

[0102] Reference Figures 1 to 6 and Figures 10 to 13 In this embodiment, the display panel 100 may include eight regions: OFF, A1, OFF, A2, OFF, A3, OFF, and A4. Four of the eight regions are sub-display regions A1, A2, A3, and A4 that have input image data (IMG), and the other four of the eight regions are sub-off regions OFF, OFF, OFF, and OFF that do not have input image data (IMG). In this embodiment, the frame rate may be 60Hz.

[0103] In this embodiment, the number of sub-display areas A1, A2, A3, and A4 can be four, and the frame rate can be 60Hz. The number of contrast analysis cores can be two, and the number of contrast processor cores can be four.

[0104] exist Figure 11 In this process, the first contrast analysis kernel can analyze the input image data of sub-display area A1 in the first frame and the input image data of sub-display area A2 in the second frame. The first contrast analysis kernel can analyze the input image data of sub-display area A1 in the third frame and the input image data of sub-display area A2 in the fourth frame.

[0105] The first contrast analysis kernel analyzes the input image data of display areas A1 and A2 at a period of 1 / 30 of a second. The first contrast analysis kernel can divide the input image data provided at a frame rate of 60Hz into two parts to operate using a time-division multiplexing method.

[0106] exist Figure 12 In this process, the second contrast analysis kernel can analyze the input image data of sub-display area A3 in the first frame and the input image data of sub-display area A4 in the second frame. The second contrast analysis kernel can analyze the input image data of sub-display area A3 in the third frame and the input image data of sub-display area A4 in the fourth frame.

[0107] The second contrast analysis kernel analyzes the input image data of display areas A3 and A4 at a period of 1 / 30 second. The second contrast analysis kernel can divide the input image data provided at a frame rate of 60Hz into two parts to operate using a time-division multiplexing method.

[0108] The drive controller 200 may further include switches AS1 and AS2 for connecting the contrast analysis core to multiple contrast processor cores. In this embodiment, the first switch AS1 can selectively connect the first contrast analysis core to the first contrast processor core and the second contrast processor core, and the second switch AS2 can selectively connect the second contrast analysis core to the third contrast processor core and the fourth contrast processor core.

[0109] The drive controller 200 may also include a multiplexer that selectively outputs one of the outputs of the contrast processor cores. In this embodiment, the multiplexer may, in response to the output selection signal SEL, output one of the outputs of the first to the fourth contrast processor cores as output image data IMG2.

[0110] Figure 14 It is shown that it is used for Figure 10 A concept diagram of the contrast analyzer 220 and contrast processor 240 of the display panel 100. Figure 15 It is shown that it is used for Figure 10 A block diagram of the contrast analyzer 220 and contrast processor 240 of the display panel 100.

[0111] Reference Figures 1 to 6 , Figure 10 , Figure 14 and Figure 15 In this embodiment, the display panel 100 may include eight regions: OFF, A1, OFF, A2, OFF, A3, OFF, and A4. Four of these eight regions are sub-display regions A1, A2, A3, and A4 that have input image data (IMG), while the other four are sub-off regions OFF, OFF, OFF, and OFF that do not have input image data (IMG). In this embodiment, the frame rate may be 120Hz.

[0112] In this embodiment, the number of sub-display areas A1, A2, A3, and A4 can be four, and the frame rate can be 120Hz. The number of contrast analysis cores can be one, and the number of contrast processor cores can be four.

[0113] exist Figure 14 In this process, the contrast analysis kernel can analyze the input image data of sub-display area A1 in the first frame and the input image data of sub-display area A2 in the second frame. The contrast analysis kernel can analyze the input image data of sub-display area A3 in the third frame and the input image data of sub-display area A4 in the fourth frame.

[0114] The contrast analysis kernel analyzes the input image data in the sub-display areas A1 to A4 at a period of 1 / 30 of a second. The contrast analysis kernel can divide the input image data, provided at a frame rate of 120Hz, into four parts for time-division multiplexing.

[0115] The drive controller 200 may also include a switch AS for connecting the contrast analysis core to a plurality of contrast processor cores. In this embodiment, the switch AS may selectively connect the contrast analysis core to a first contrast processor core, a second contrast processor core, a third contrast processor core, and a fourth contrast processor core.

[0116] The drive controller 200 may also include a multiplexer that selectively outputs one of the outputs of the contrast processor cores. In this embodiment, the multiplexer may, in response to the output selection signal SEL, output one of the outputs of the first to the fourth contrast processor cores as output image data IMG2.

[0117] Figure 16 It is shown Figure 1 A conceptual diagram of a display panel 100 that includes eight sub-display areas. Figure 17 and Figure 18 It is shown that it is used for Figure 16 A concept diagram of the contrast analyzer 220 and contrast processor 240 of the display panel 100. Figure 19 It is shown that it is used for Figure 16 A block diagram of the contrast analyzer 220 and contrast processor 240 of the display panel 100.

[0118] Reference Figures 1 to 6 and Figures 16 to 19 In this embodiment, the display panel 100 may include eight regions A1, A2, A3, A4, A5, A6, A7, and A8. All of these eight regions are sub-display regions A1, A2, A3, A4, A5, A6, A7, and A8 that contain input image data (IMG). In this embodiment, the frame rate may be 120Hz.

[0119] In this embodiment, the number of sub-display areas A1, A2, A3, A4, A5, A6, A7, and A8 can be eight, and the frame rate can be 120Hz. The number of contrast analysis cores can be two, and the number of contrast processor cores can be eight.

[0120] exist Figure 17In this process, the first contrast analysis kernel can analyze the input image data of sub-display area A1 in the first frame, and can analyze the input image data of sub-display area A2 in the second frame. The first contrast analysis kernel can analyze the input image data of sub-display area A3 in the third frame, and can analyze the input image data of sub-display area A4 in the fourth frame.

[0121] The first contrast analysis kernel analyzes the input image data of the sub-display areas A1 to A4 at a period of 1 / 30 of a second. The first contrast analysis kernel can divide the input image data provided at a frame rate of 120Hz into four parts to operate using a time-division multiplexing method.

[0122] exist Figure 18 In this process, the second contrast analysis kernel can analyze the input image data of sub-display area A5 in the first frame and the input image data of sub-display area A6 in the second frame. The second contrast analysis kernel can analyze the input image data of sub-display area A7 in the third frame and the input image data of sub-display area A8 in the fourth frame.

[0123] The second contrast analysis kernel analyzes the input image data in the sub-display areas A5 to A8 at a period of 1 / 30 of a second. The second contrast analysis kernel can divide the input image data provided at a frame rate of 120Hz into four parts to operate using a time-division multiplexing method.

[0124] The drive controller 200 may further include switches AS1 and AS2 for connecting the contrast analysis core to a plurality of contrast processor cores. In this embodiment, the first switch AS1 may selectively connect the first contrast analysis core to the first contrast processor core, the second contrast processor core, the third contrast processor core, and the fourth contrast processor core, and the second switch AS2 may selectively connect the second contrast analysis core to the fifth contrast processor core, the sixth contrast processor core, the seventh contrast processor core, and the eighth contrast processor core.

[0125] The drive controller 200 may also include a multiplexer that selectively outputs one of the outputs of the contrast processor cores. In this embodiment, the multiplexer may, in response to the output selection signal SEL, output one of the outputs of the first to the eighth contrast processor cores as output image data IMG2.

[0126] Figure 20 It is shown Figure 1 The following is a conceptual diagram of an example display panel 100 comprising sixteen zones. The 16 zones include 16 display areas A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, and A16. Figure 21and Figure 22 It is shown that it is used for Figure 20 A concept diagram of the contrast analyzer 220 and contrast processor 240 of the display panel 100.

[0127] Reference Figures 1 to 6 and Figures 20 to 22 In this embodiment, the display panel 100 may include sixteen regions A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, and A16. All of these sixteen regions are sub-display regions A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, and A16 that contain input image data (IMG). In this embodiment, the frame rate may be 240Hz.

[0128] In this embodiment, the number of sub-display areas A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, and A16 can be sixteen, and the frame rate can be 240Hz. The number of contrast analysis cores can be two, and the number of contrast processor cores can be sixteen.

[0129] exist Figure 21 In this process, the first contrast analysis kernel can analyze the input image data of sub-display area A1 in the first frame and the input image data of sub-display area A2 in the second frame. The first contrast analysis kernel can analyze the input image data of sub-display area A3 in the third frame and the input image data of sub-display area A4 in the fourth frame. The first contrast analysis kernel can analyze the input image data of sub-display area A5 in the fifth frame and the input image data of sub-display area A6 in the sixth frame. The first contrast analysis kernel can analyze the input image data of sub-display area A7 in the seventh frame and the input image data of sub-display area A8 in the eighth frame.

[0130] The first contrast analysis kernel analyzes the input image data of the sub-display areas A1 to A8 at a period of 1 / 30 of a second. The first contrast analysis kernel can divide the input image data provided at a frame rate of 240Hz into eight parts to operate using a time-division multiplexing method.

[0131] exist Figure 22In this process, the second contrast analysis kernel can analyze the input image data of sub-display area A9 in the first frame and the input image data of sub-display area A10 in the second frame. The second contrast analysis kernel can analyze the input image data of sub-display area A11 in the third frame and the input image data of sub-display area A12 in the fourth frame. The second contrast analysis kernel can analyze the input image data of sub-display area A13 in the fifth frame and the input image data of sub-display area A14 in the sixth frame. The second contrast analysis kernel can analyze the input image data of sub-display area A15 in the seventh frame and the input image data of sub-display area A16 in the eighth frame.

[0132] The second contrast analysis kernel analyzes the input image data in display areas A9 to A16 at a period of 1 / 30 of a second. The second contrast analysis kernel can divide the input image data, provided at a frame rate of 240Hz, into eight parts using a time-division multiplexing method.

[0133] Figure 23 It shows the basis Figure 1 A table showing the number of sub-display areas and the number of contrast analysis cores for the frame rate of the display panel 100.

[0134] exist Figure 23 In this scenario, the number of sub-display areas varies, but the frame rate remains fixed at 60Hz. At a frame rate of 60Hz, setting the analysis period of the contrast analysis kernel to 1 / 30th of a second might be appropriate, allowing the contrast analysis kernel to operate in half-times. In this case, for example, the number of contrast analysis kernels could be half the number of sub-display areas.

[0135] When there are two sub-display areas and the frame rate is 60Hz, the number of contrast analysis cores is one. The number of contrast processor cores can be two, equal to the number of sub-display areas.

[0136] When there are four sub-display areas and the frame rate is 60Hz, the number of contrast analysis cores is two. The number of contrast processor cores can be four, the same as the number of sub-display areas.

[0137] When the number of sub-display areas is eight and the frame rate is 60Hz, the number of contrast analysis cores is four. The number of contrast processor cores can be eight, the same as the number of sub-display areas.

[0138] When the number of sub-display areas is sixteen and the frame rate is 60Hz, the number of contrast analysis cores is eight. The number of contrast processor cores can be sixteen, the same as the number of sub-display areas.

[0139] Figure 24It shows the basis Figure 1 A table showing the number of sub-display areas and the number of contrast analysis cores for the frame rate of the display panel 100.

[0140] exist Figure 24 In this model, the number of sub-display areas varies, and the frame rates are set to 60Hz, 60Hz, 120Hz, and 240Hz, respectively. At a frame rate of 60Hz, setting the analysis period of the contrast analysis kernel to 1 / 30 second might be appropriate, allowing the contrast analysis kernel to operate in half-time divisions. When the contrast analysis kernel operates in half-time divisions, the number of contrast analysis kernels can be half the number of sub-display areas.

[0141] At a frame rate of 120Hz, setting the analysis period of the contrast analysis core to 1 / 30 second may be appropriate, allowing the contrast analysis core to operate in 1 / 4 time-division mode. When the contrast analysis core operates in 1 / 4 time-division mode, the number of contrast analysis cores can be one-quarter of the number of sub-display areas.

[0142] At a frame rate of 240Hz, setting the analysis period of the contrast analysis core to 1 / 30 of a second may be appropriate, allowing the contrast analysis core to operate at 1 / 8 of a time interval. When the contrast analysis core operates at 1 / 8 of a time interval, the number of contrast analysis cores can be 1 / 8 of the number of sub-display areas.

[0143] When there are two sub-display areas and the frame rate is 60Hz, the number of contrast analysis cores is one. The number of contrast processor cores can be two, equal to the number of sub-display areas.

[0144] When there are four sub-display areas and the frame rate is 60Hz, the number of contrast analysis cores is two. The number of contrast processor cores can be four, the same as the number of sub-display areas.

[0145] When the number of sub-display areas is eight and the frame rate is 120Hz, the number of contrast analysis cores is two. The number of contrast processor cores can be eight, equal to the number of sub-display areas.

[0146] When the number of sub-display areas is sixteen and the frame rate is 240Hz, the number of contrast analysis cores is two. The number of contrast processor cores can be sixteen, the same as the number of sub-display areas.

[0147] According to this embodiment, in a display device including a display panel 100 containing multiple sub-display areas, the contrast analysis cores can be operated in a time-division manner, thereby reducing the number of contrast analysis cores.

[0148] Reducing the number of contrast analysis cores allows for a smaller display panel driver and reduced power consumption in the display device.

[0149] The display device and the method for driving the display device according to the present invention can reduce the size of the display panel driver and reduce the power consumption of the display device.

[0150] The foregoing is illustrative of the inventive concept and is not to be construed as limiting it. Although some embodiments of the inventive concept have been described, it will be readily understood by those skilled in the art that many modifications are possible in the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the device plus function clause is intended to cover structures described herein that perform the functions described herein, and not only structural equivalents but also equivalent structures. Therefore, it will be understood that the foregoing is illustrative of the inventive concept and is not to be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the claims and their equivalents included therein.

Claims

1. A display device, the display device comprising: The display panel includes multiple sub-display areas and is configured to display images based on the input image. A contrast analyzer is configured to analyze the input image data in a time-division manner, wherein the contrast analyzer analyzes only the input image data corresponding to one of the plurality of sub-display areas during each frame. A contrast processor is configured to adjust the contrast of the input image data based on the analysis results of the contrast analyzer. as well as The data driver is configured to generate a data voltage based on the output data of the contrast processor. The number of contrast analysis cores in the contrast analyzer is determined based on the number of the plurality of sub-display areas and the frame rate. As the number of the plurality of sub-display areas increases, the number of contrast analysis kernels also increases.

2. The display device according to claim 1, wherein, As the frame rate increases, the number of contrast analysis kernels decreases.

3. The display device according to claim 1, wherein, The number of contrast processor cores in the contrast processor is equal to the number of the plurality of sub-display areas.

4. The display device according to claim 3, wherein, The number of contrast analysis cores is less than the number of contrast processor cores.

5. The display device according to claim 4, further comprising a switch for connecting a contrast analysis core to a plurality of the contrast processor cores.

6. The display device of claim 5, further comprising a multiplexer configured to selectively output one of the outputs of the plurality of contrast processor cores.

7. The display device according to claim 4, wherein, When the number of the plurality of sub-display areas is two and the frame rate is 60Hz, the number of contrast analysis cores is one and the number of contrast processor cores is two.

8. The display device according to claim 4, wherein, When the number of the plurality of sub-display areas is four and the frame rate is 60Hz, the number of contrast analysis cores is two and the number of contrast processor cores is four.

9. The display device according to claim 4, wherein, When the number of the plurality of sub-display areas is four and the frame rate is 120Hz, the number of contrast analysis cores is one and the number of contrast processor cores is four.

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