Shielded-gate trench power device with superjunction and process method

Abstract

The present invention discloses a shielded gate trench-type power device with a super junction, which combines the super junction with the shielded gate. The substrate contains trenches, with a shielded gate in the lower half and a gate in the upper half of the trenches. The surface layer of the substrate has a body region and a source region of the power device. A super junction structure is provided in the drift region, and the P-columns of the super junction structure are in a floating state and are staggered from the trenches to increase the width of the drift region between the P-columns and the trenches. Through the RESURF effect of the shielded gate and the charge coupling effect of the columnar thin layer, the gate-drain capacitance Cgd is reduced, the breakdown voltage BV of the device is maximized, and the on-resistance of the device is reduced by decreasing the resistivity of the drift region. The present invention also discloses a process method for the shielded gate trench-type power device with a super junction. The floating P-columns are formed by multiple high-energy ion implantations, and the mask used for the P-column implantation can be shared with the mask for the implantation of the body region lead-out region of the device, without the need to fabricate an additional mask.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device design and manufacturing, and particularly to a shielded gate trench power device with a super junction.

[0002] The present invention also relates to a manufacturing process method for the above device. Background Art

[0003] The super junction power device is a new type of power semiconductor device that has developed rapidly and is widely used. It is based on the double-diffused metal oxide semiconductor (DMOS), and by introducing a super junction structure, in addition to having the characteristics of high input impedance, fast switching speed, high operating frequency, good thermal stability, simple drive circuit, and easy integration of DMOS, it also overcomes the disadvantage that the on-resistance of DMOS increases with the breakdown voltage to the power of 2.5. Currently, the super junction DMOS has been widely used in the power supplies or adapters of consumer electronic products such as personal computers, laptops, netbooks, mobile phones, lighting (high-pressure gas discharge lamps), and televisions (liquid crystal or plasma televisions) and game consoles.

[0004] The super junction device adopts a new breakdown voltage layer structure, that is, a series of alternately arranged P-type and N-type semiconductor thin layers are used to deplete the P-type and N-type regions composed of the P-type and N-type semiconductor thin layers (pillar regions) at a lower voltage in the off state, realizing charge mutual compensation. By combining the super junction device with the well-known VDMOS process in the industry, a MOSFET with a super junction structure can be fabricated. It can significantly reduce the on-resistance of the device by using an epitaxial layer with low resistivity while the reverse breakdown voltage is the same as that of the traditional VDMOS. The carrier distribution of the P-type impurities and the carrier distribution of the N-type impurities in this thin layer and their matching will affect the characteristics of the device, including its reverse breakdown voltage and current handling ability. In general device designs, the best charge balance is achieved in the alternating P / N thin layers, that is, the P-type thin layer and the N-type thin layer, to obtain the maximum reverse breakdown voltage of the device. Therefore, the super junction device is a MOSFET structure that uses the in-body Resurf technology of PN charge balance to increase the reverse breakdown voltage BV of the device while maintaining a small on-resistance. The Resurf principle utilizes the two-dimensional effect of the electric field distribution in the device. When the electric field near the P-substrate / N-epitaxial junction in the vertical direction has not reached the critical electric field, due to its interaction with the lateral N-epitaxial / P-well junction, that is, by using the interaction between the lateral junction and the vertical junction, the epitaxial layer is completely depleted before the lateral junction reaches the critical avalanche breakdown electric field. By reasonably optimizing the device parameters, the breakdown of the device occurs at the vertical junction, thereby reducing the surface electric field.

[0005] The shielded-gate trench-type power device is a double-trench-gate VDMOS device structure evolved from the trench-gate VDMOS, with a left-right gate structure or an up-down gate structure. In the up-down gate structure, the shielded gate is located directly below the trench gate. The shielded-gate power device has two main advantages: one is to reduce the gate-drain parasitic capacitance Cgd, and the other is to improve the drift region electric field using the field plate effect of the shielded gate and increase the breakdown voltage.

[0006] Due to process limitations, the depth of the gate trench is still relatively small compared to the thickness of the drift region, and the RESURF effect of the shielded gate plays a limited role. Only the superjunction VDMOS can fundamentally improve the device characteristics.

[0007] The shielded-gate trench-type power device has both a low Cgd, a high device breakdown voltage, and a low device on-resistance. However, the current problem is that when the device size is small, the gate trench and the P pillars of the superjunction form a narrow drift region, which easily increases the on-resistance of the device due to the JFET effect. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a shielded-gate trench-type power device with a superjunction, which combines the superjunction and the shielded gate, and has a low gate-drain capacitance, a high breakdown voltage, and a low on-resistance.

[0009] Another technical problem to be solved by the present invention is to provide a process method for the shielded-gate trench-type power device with a superjunction.

[0010] To solve the above problems, the process method for the shielded-gate trench-type power device with a superjunction according to the present invention includes the following process steps:

[0011] Step 1: Provide a semiconductor substrate of a second conductivity type. Perform ion implantation of the second conductivity type on the semiconductor substrate to form a drift region, and then perform ion implantation of the first conductivity type on the surface layer of the semiconductor substrate to form the body region of the shielded-gate trench-type power device.

[0012] Step 2: Etch trenches in the semiconductor substrate through photolithography and etching, deposit a dielectric layer, and deposit polysilicon in the trenches. Back-etch to form a shielded gate; then deposit a dielectric layer again and fill the trenches with polysilicon and back-etch to form the gate of the shielded-gate trench-type power device.

[0013] Step 3: Perform ion implantation on the surface layer of the semiconductor substrate to form the source region of the shielded-gate trench-type power device.

[0014] Step 4: Use the mask of the body region extraction region to perform ion implantation to form the extraction region of the body region; at the same time, use the mask of the body region extraction again to perform ion implantation to form the columnar thin layer of the shielded gate trench-type power device.

[0015] The semiconductor substrate is a silicon substrate, a silicon-germanium substrate, or a gallium arsenide substrate.

[0016] Further, in Step 1, the semiconductor substrate is a heavily doped substrate, and the drift region and the channel region are lightly doped regions.

[0017] Further, in Step 2, the dielectric layer is a silicon oxide layer formed by thermal oxidation; the shielded gate is formed in the lower part of the trench, and the shielded gate is in a floating state; when refilling polysilicon, the trench is filled with polysilicon and then etched back, and the etch-back end point is located on the surface of the semiconductor substrate to form the gate of the shielded gate trench-type power device; perform heavy doping ion implantation of the second conduction type on the gate.

[0018] Further, in Step 3, perform heavy doping ion implantation on both sides of the trench in the semiconductor substrate to form the source region of the shielded gate trench-type power device.

[0019] Further, in Step 4, the ion implantation of the body region extraction region is low-energy heavy doping ion implantation, which is formed in the shallow surface layer of the semiconductor substrate; then use the ion implantation mask of the body region extraction region again to perform ion implantation of the suspended columnar thin layer; the suspended columnar thin layer is in a suspended state where there is a distance between its bottom and the heavily doped substrate in the drift region, and there is also a distance between its top and the body region extraction region, and the columnar thin layer is staggered from the trench of the shielded gate in depth.

[0020] Further, the ion implantation of the columnar thin layer is multiple high-energy ion implantations to form a suspended columnar thin layer directly below the body region extraction region; the ion implantation type of the columnar thin layer is opposite to that of the drift region; for an N-type device, the implanted impurity is boron, and for a P-type device, the implanted impurity is phosphorus.

[0021] Further, the suspended columnar thin layer increases the width of the drift region between the shielded gate trench and the columnar thin layer, avoids the JFET effect between the shielded gate trench and the columnar thin layer, and reduces the on-resistance of the device.

[0022] Further, the subsequent process is also included after the process steps, depositing a dielectric layer, contact holes, and a front metal layer to form a front extraction, and thinning the back and metallizing the back to extract the drain of the device.

[0023] The first conductivity type is P-type, and the second conductivity type is N-type; when the definitions of the first conductivity type and the second conductivity type are exchanged, the formed device is of the opposite type.

[0024] For the shielded-gate trench-type power device of the present invention, a drift region of the second conductivity type is provided in a semiconductor substrate of the second conductivity type, and a channel region of the shielded-gate trench-type power device is above the drift region;

[0025] At the center of the device are the shielded gate and the gate of the shielded-gate trench-type power device of the present invention. The shielded gate and the gate are located in a trench. The shielded gate is located in the lower part of the trench, and the gate is located in the upper part of the trench. Dielectric layers are provided between the shielded gate, the gate, and the substrate material of the drift region;

[0026] Source regions of the shielded-gate trench-type power device are provided on both sides of the trench, and a body region lead-out region is outside the source regions; both the body region lead-out region and the source regions are located in a body region and their depths do not exceed the body region;

[0027] In the drift region below the body region lead-out region, a columnar thin layer of the shielded-gate trench-type power device is provided; the columnar thin layer is of a suspended type, that is, both the top and the bottom of the columnar thin layer do not contact structures outside the drift region and are staggered with the trench;

[0028] The doping type of the columnar thin layer is opposite to that of the drift region, and both the columnar thin layer and the drift region are lightly doped.

[0029] The beneficial effects of the present invention are as follows: To avoid the JFET effect between the shielded gate trench and the columnar thin layer (i.e., the P column), the present invention adopts a suspended-type columnar thin layer. The columnar thin layer and the channel are separated by the drift region, and the columnar thin layer and the shielded gate trench are placed staggeredly to increase the distance between the columnar thin layer and the trench. Through the RESURF effect of the shielded gate and the charge coupling effect of the columnar thin layer, the breakdown voltage BV of the device is maximized, and the on-resistance of the device is reduced by reducing the resistivity of the drift region.

[0030] Therefore, in the medium and low voltage trench gate devices, the structure of the present invention combines the shielded gate and the super junction to simultaneously achieve the effects of reducing the gate-drain capacitance Cgd, increasing the breakdown voltage BV, and reducing the on-resistance.

[0031] In the process method, the suspended-type columnar thin layer in the present invention is formed by multiple high-energy ion implantations. The type of ion-implanted impurities in the columnar thin layer is opposite to that of the drift region. Boron is implanted for N-type devices, and phosphorus is implanted for P-type devices. The mask used for forming the columnar thin layer implantation can be shared with the mask for the implantation of the body region lead-out region of the device, and no additional mask needs to be fabricated. Description of the Drawings

[0032] Figures 1 to 4 Schematic diagram of the process steps of the shielded-gate trench-type power device with a superjunction according to the present invention.

[0033] Figure 5 Process flow chart of the shielded-gate trench-type power device with a superjunction according to the present invention.

[0034] Description of reference numerals

[0035] 1 is the substrate, 2 is the drift region, 3 is the body region (channel region), 4 is the shielded gate, 5 is the gate, 6 is the source region, 7 is the body-region lead-out region, and 8 is the P pillar (columnar thin layer). Detailed implementation manners

[0036] The following provides the detailed implementation manners of the present invention in conjunction with the accompanying drawings, and clearly and completely describes the technical solutions in the present invention. However, the present invention is not limited to the following implementation manners. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. According to the following description and the claims, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise ratios, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention. It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals represent the same elements throughout.

[0037] The structure of the shielded-gate trench-type power device with a superjunction according to the present invention is as Figure 4 shown. Combining the superjunction with the shielded gate, taking the N-type shielded-gate trench-type power device as an example, 1 in the figure is a heavily doped N-type semiconductor substrate, and an N-type drift region 2 is provided in the semiconductor substrate. Above the drift region 2 is the P-type body region 3 of the shielded-gate trench-type power device.

[0038] There is a trench extending into the drift region at the center of the device surface. The trench forms upper and lower regions, which respectively form the gate and the shielded gate. The shielded gate 4 is located in the lower part of the trench, and the gate 5 is located in the upper part of the trench. Dielectric layers are provided between the shielded gate 4, the gate 5, and the drift-region substrate material to achieve electrical isolation. The polysilicon material forming the gate 5 is heavily doped with N+. After being wrapped by the dielectric layer, the shielded gate has no lead-out, forming a floating shielded gate 4, which plays the role of a floating field plate and improves the electric-field distribution in the drift region.

[0039] The shielded gate trench power device has source regions 6 on both sides of the trench, and the outer side of the source region is a body region lead-out region 7; the body region lead-out region and the source region are both located in the body region and their depths do not exceed the depth of the body region.

[0040] In the drift region below the body region lead-out region, there is a P column 8 of the shielded gate trench type power device. The columnar thin layer is of a suspended type, that is, the top and bottom ends of the columnar thin layer are not in contact with the structure outside the drift region, and are staggered with the trench. The suspended P column 8 staggered with the trench increases the spacing between the P column and the drift region of the trench, avoids the formation of a JFET effect between the trench, and can reduce the on-resistance.

[0041] The doping type of the P column 8 is opposite to the doping type of the drift region. The doping concentration of the P column 8 is gradually distributed instead of uniformly distributed. From top to bottom, the doping concentration of the upper part is higher than that of the lower part, and the doping concentration gradually decreases. The shield gate is combined with the super junction to simultaneously play the effect of reducing the gate-drain capacitance Cgd, increasing the breakdown voltage BV and reducing the on-resistance.

[0042] The process method of the shielded gate trench power device of the present invention comprises the following process steps:

[0043] Step 1, such as Figure 1 As shown, N-type ion implantation is performed on an N+ type silicon substrate 1 to form a drift region 2, and then P-type ion implantation is performed on the surface layer of the silicon substrate 1 to form the body region 3 of the shielded gate trench power device.

[0044] Step 2, such as Figure 2 As shown, a groove is etched in the semiconductor substrate by photolithography and etching, a dielectric layer is formed by thermal oxidation process and attached to the inner wall and bottom of the groove, polysilicon is deposited in the groove, and the shield gate 4 is formed by back etching; then the dielectric layer is deposited again and polysilicon is filled in the groove and back etching is performed to form the gate 5 of the shield gate trench type power device. The back etching end point is located on the surface of the semiconductor substrate, forming the gate of the shield gate trench type power device; and the gate is heavily doped with ions of the second conductivity type.

[0045] Step three, photolithography and etching are performed to define the implantation region of the source region, and ion implantation is performed on the surface layer of the semiconductor substrate to form the source region 6 of the shielded gate trench power device, such as Figure 3 The source region is located on both sides of the trench and is a heavily doped N+ region.

[0046] Step 4: Use the mask definition of the body region extraction region to perform low-energy P+-type ion implantation to form the body region extraction region 7; at the same time, use the mask of the body region extraction again to perform P- ion implantation to form the columnar thin layer of the shielded gate trench-type power device, that is, the P column 8. Therefore, the ion implantation of the P column 8 and the body region extraction region 7 can share a set of masks. The P column 8 uses the mask of the body region extraction region to perform multiple high-energy ion implantations to form a suspended P column 8 in the drift region, as Figure 4 shown, the ion implantation type of the P column 8 is opposite to that of the drift region. For N-type devices, the implanted impurity is boron, and for P-type devices, the implanted impurity is phosphorus. The suspended P column refers to a suspended state in the drift region where there is a certain thickness of drift region between its bottom and the heavily doped substrate, and there is also a certain distance between its top and the body region, and the P column and the trench of the shielded gate are staggered in depth.

[0047] The ion implantation of the P column is multiple high-energy ion implantations, and a suspended P column is formed directly below the body region extraction region.

[0048] Subsequent processes also include forming a dielectric layer on the front surface, etching and making contact holes, depositing and etching the front metal, leading the gate, source region, and body region on the front surface to the metal layer, as well as back thinning and depositing back metal to form an extracted drain, etc. These are the same as the existing processes and will not be elaborated here.

[0049] In the present invention, the suspended P column and the channel region are isolated by the drift region, avoiding the JFET effect between the shielded gate trench and the P column, the Resurf effect of the shielded gate, and the charge coupling effect of the P column, maximizing the breakdown voltage of the device, and reducing the on-resistance of the device by reducing the resistivity of the drift region.

[0050] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A process method for a shielded gate trench-type power device with a super junction, characterized in that: it includes the following process steps: Step 1: Provide a semiconductor substrate of a second conductivity type. Perform ion implantation of the second conductivity type on the semiconductor substrate to form a drift region, and then perform ion implantation of a first conductivity type on the surface layer of the semiconductor substrate to form the body region of the shielded gate trench-type power device; Step 2: Etch a trench in the semiconductor substrate through photolithography and etching, deposit a dielectric layer, and deposit polysilicon in the trench, and perform back etching to form a shielded gate; Then deposit the dielectric layer again and fill the trench with polysilicon and perform back etching to form the gate of the shielded gate trench-type power device; Step 3: Perform ion implantation on the surface layer of the semiconductor substrate to form the source region of the shielded gate trench-type power device; Step 4: Use the mask plate of the body region lead-out region to perform ion implantation to form the body region lead-out region of the body region; Then use the mask plate of the body region lead-out region to perform ion implantation again to form the columnar thin layer of the shielded gate trench-type power device; the columnar thin layer is a suspended type, that is, both the top and bottom of the columnar thin layer do not contact the structure outside the drift region, the columnar thin layer is separated from the channel by the drift region, and is offset from the trench.

2. The process method for a shielded gate trench-type power device with a super junction as described in claim 1, characterized in that: In step 1, the semiconductor substrate is a heavily doped substrate, and the drift region and the body region are lightly doped regions; the semiconductor substrate is a silicon substrate, a silicon-germanium substrate or a gallium arsenide substrate.

3. The process method for a shielded gate trench-type power device with a super junction as described in claim 1, characterized in that: In step 2, the dielectric layer is a silicon oxide layer formed by thermal oxidation; the shielded gate is formed in the lower part of the trench, and the shielded gate is in a floating state; when filling the trench with polysilicon again, after the trench is filled with polysilicon, perform back etching, and the back etching end point is located on the surface of the semiconductor substrate to form the gate of the shielded gate trench-type power device; perform heavy doping ion implantation of the second conductivity type on the gate.

4. The process method for a shielded gate trench-type power device with a super junction as described in claim 1, characterized in that: In step 3, in the semiconductor substrate, perform heavy doping ion implantation on both sides of the trench to form the source region of the shielded gate trench-type power device.

5. The process method for a shielded gate trench-type power device with a super junction as described in claim 1, characterized in that: In step 4, the ion implantation of the body region lead-out region is low-energy heavy doping ion implantation, and it is formed in the shallow surface layer of the semiconductor substrate; Then use the ion implantation mask plate of the body region lead-out region to perform ion implantation of the suspended columnar thin layer; the suspended columnar thin layer is in a suspended state where there is a distance between its bottom and the heavily doped substrate in the drift region, and there is also a distance between its top and the body region, and the columnar thin layer is offset from the trench of the shielded gate in depth.

6. The process method of the shielded gate trench-type power device with a super junction as described in claim 5, characterized in that: the ion implantation of the columnar thin layer is high-energy ion implantation carried out in multiple times, and the superposition of multiple ion implantations with different high energies forms a suspended columnar thin layer directly below the body region lead-out region; the ion implantation type of the columnar thin layer is opposite to that of the drift region, and its concentration distribution is a gradually changing distribution from top to bottom, with the concentration gradually decreasing; for N-type devices, the implanted impurity is boron, and for P-type devices, the implanted impurity is phosphorus.

7. The process method of the shielded gate trench-type power device with a super junction as described in claim 5, characterized in that: the suspended columnar thin layer increases the width of the drift region between the shielded gate trench and the columnar thin layer, avoids the JFET effect between the shielded gate trench and the columnar thin layer, and reduces the on-resistance of the device.

8. The process method of the shielded gate trench-type power device with a super junction as described in claim 1, characterized in that: after the process steps, it further includes a back-end process, depositing a dielectric layer, contact holes and a front metal layer to form a front lead-out, and thinning the back and metallizing the back to lead out the drain of the device.

9. The process method of the shielded gate trench-type power device with a super junction as described in any one of claims 1 to 8, characterized in that: the first conductivity type is P-type, and the second conductivity type is N-type; when the definitions of the first conductivity type and the second conductivity type are exchanged, the formed device is of the opposite type.

10. A shielded gate trench-type power device with a super junction formed by using the process method as described in any one of claims 1 to 7, characterized in that: in a semiconductor substrate of the second conductivity type, there is a drift region of the second conductivity type, and above the drift region is the body region of the shielded gate trench-type power device; at the center of the device is the shielded gate and gate of the shielded gate trench-type power device, the shielded gate and gate are located in the trench, the shielded gate is located at the lower part of the trench, the gate is located at the upper part of the trench, and there are dielectric layers between the shielded gate, the gate and the drift region substrate material; on both sides of the trench are the source regions of the shielded gate trench-type power device, and the outside of the source region is the body region lead-out region; both the body region lead-out region and the source region are located in the body region and the depth does not exceed the body region; in the drift region below the body region lead-out region, there is a columnar thin layer of the shielded gate trench-type power device; the columnar thin layer is suspended, that is, the top and bottom of the columnar thin layer do not contact structures outside the drift region and are staggered with the trench; the doping type of the columnar thin layer is opposite to the doping type of the drift region, and both the columnar thin layer and the drift region are lightly doped.

11. A shielded gate trench-type power device with a super junction formed by the process method as described in claim 10, characterized in that: the doping concentration of the columnar thin layer is a gradually changing distribution, and its doping concentration gradually decreases from the top to the bottom of the columnar thin layer.

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