High-voltage ldmos device and method of manufacturing the same

Abstract

The application provides a preparation method of a high-voltage LDMOS device, which comprises the following steps: forming an isolation layer in a second groove of a substrate by using a thermal oxidation furnace tube process; etching to remove part of the thickness of the substrate and the top position of the isolation layer to form a third groove, and defining an active region in the substrate by taking the third groove and the isolation layer as isolation boundaries; and finally forming a dielectric layer in the third groove at the top of the isolation layer. The application also provides a high-voltage LDMOS device. By adjusting the sequence of defining the active region, forming a shallow trench isolation structure and forming a deep trench isolation layer, the isolation layer is first formed in a deep trench (second groove), then the active region in the substrate is defined, and finally the dielectric layer (shallow trench isolation structure) is formed, so that the active region at the junction with the shallow trench isolation structure can be prevented from being misoxidized when the isolation layer is formed by high-temperature thermal oxidation, the isolation withstand voltage performance of the device is improved, and the reliability of the device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of high-voltage LDMOS device manufacturing, in particular to a high-voltage LDMOS device and a preparation method thereof. BACKGROUND

[0002] There are two ways to realize high-voltage devices, namely junction isolation and deep trench isolation (DTI). Generally, in the case of achieving the same withstand voltage, the size of the device of the junction isolation process is larger than that of the device of the DTI process, and accordingly, the production cost is high. However, compared with the junction isolation, the DTI is more difficult in process, especially for the device requiring high breakdown voltage (BV). Therefore, it is urgent to develop a new DTI process to ensure a relatively simple process under the premise of realizing high withstand voltage.

[0003] In addition, for the high-voltage power device, the trench depth needs to reach 10 um or even 20 um, and the size of the trench in width is 1 um to 2 um, and the depth-width ratio of the trench is large, which greatly increases the difficulty of filling the trench.

[0004] At present, the filling mode of the DTI generally adopts pure silicon oxide dielectric layer filling or partial thermal annealing silicon oxide + partial poly combination filling. First, for the structure of the pure silicon oxide dielectric layer filling, in order to facilitate the filling of the trench, the silicon oxide dielectric layer is usually generated by the CVD process, and the film quality of the silicon oxide dielectric layer prepared by the CVD process is relatively poor, which will affect the reliability of the device; second, for the structure of the partial thermal annealing silicon oxide + partial poly combination filling, although the film quality of the thermal annealing silicon oxide is better than that of the silicon oxide generated by the CVD process, but due to the high reaction temperature, the AA (active area) region in the substrate is oxidized, and then the narrow width device is invalid, which is not conducive to practical application.

[0005] Therefore, how to realize high withstand voltage of the device in the DTI process while the AA (active area) region is not oxidized and the preparation process is simpler is the direction of developing new processes at present. SUMMARY

[0006] The present application provides a high-voltage LDMOS device and a preparation method thereof, which can solve the problems of easy oxidation of the AA (active area) region while realizing high withstand voltage of the device in the DTI process, and complex DTI preparation process.

[0007] In one aspect, the present application provides a preparation method of a high-voltage LDMOS device, comprising:

[0008] A substrate is provided, and a pad oxide layer, a silicon nitride layer and a hard mask layer are sequentially stacked on the substrate.

[0009] etching the hard mask layer, the silicon nitride layer and the liner oxide layer to the substrate surface to form a first trench;

[0010] etching the substrate of the first trench bottom wall to form a second trench;

[0011] forming an isolation layer with a certain thickness in the second trench by a hot oxidation furnace tube process, the upper surface of the isolation layer being flush with the upper surface of the substrate;

[0012] etching the hard mask layer, the silicon nitride layer, the liner oxide layer, part of the thickness of the substrate and part of the thickness of the isolation layer to form a third trench and define an active region in the substrate;

[0013] forming a dielectric layer, the dielectric layer filling the third trench; and,

[0014] removing the silicon nitride layer, the liner oxide layer and part of the thickness of the dielectric layer to the substrate surface, the upper surface of the remaining thickness of the dielectric layer being flush with the upper surface of the substrate.

[0015] Optionally, in the preparation method of the high-voltage LDMOS device, in the process of forming the isolation layer with a certain thickness in the second trench by the hot oxidation furnace tube process, oxygen introduced into the furnace tube reacts with the exposed substrate in the second trench to generate the isolation layer.

[0016] Optionally, in the preparation method of the high-voltage LDMOS device, the size of the second trench in width is less than eleven fifths of the size of the isolation layer in width.

[0017] Optionally, in the preparation method of the high-voltage LDMOS device, the hard mask layer, the silicon nitride layer, the liner oxide layer, part of the thickness of the substrate and part of the thickness of the isolation layer are etched by a selective etching process to form the third trench in a bowl shape.

[0018] Optionally, in the preparation method of the high-voltage LDMOS device, the thickness of the substrate removed by etching is the thickness of the isolation layer removed by etching is

[0019] Optionally, in the preparation method of the high-voltage LDMOS device, the thickness of the remaining thickness of the isolation layer is greater than 10 μm.

[0020] Optionally, in the preparation method of the high-voltage LDMOS device, after etching the hard mask layer, the silicon nitride layer, the pad oxide layer, part of the thickness of the substrate and part of the thickness of the isolation layer to form the third groove and define the active region, and before forming the dielectric layer, the preparation method of the high-voltage LDMOS device further comprises:

[0021] removing the remaining hard mask layer.

[0022] Optionally, in the preparation method of the high-voltage LDMOS device, the material of the dielectric layer is silicon oxide.

[0023] Optionally, in the preparation method of the high-voltage LDMOS device, the material of the hard mask layer is silicon oxide.

[0024] In another aspect, the embodiments of the present application also provide a high-voltage LDMOS device, comprising: a substrate, an isolation layer and a dielectric layer, wherein the isolation layer and the dielectric layer are both located in the substrate, the dielectric layer is located at the top end of the isolation layer, and the upper surface of the dielectric layer is flush with the upper surface of the substrate.

[0025] The technical scheme of the present application has at least the following advantages:

[0026] The present application adjusts the sequence of defining the active region, forming the shallow trench isolation structure and forming the isolation layer, first forms the isolation layer in the deep trench (second groove), then defines the active region region in the substrate, and finally forms the dielectric layer (shallow trench isolation structure). The present application realizes high voltage of the device in the DTI process, at the same time, the AA (active region) region at the junction of the shallow trench isolation structure is not misoxidized, improving the isolation voltage performance of the device and improving the reliability of the device.

[0027] Further, the preparation method of the present application adjusts the sequence of multiple process steps, so that the DTI process realizes the purpose of high voltage of the device, without adding additional complex process steps, which indirectly simplifies the preparation process and improves the preparation efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical scheme in the specific embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0029] Figure 1 is the flow chart of the preparation method of the high-voltage LDMOS device of the embodiments of the present application;

[0030] Figures 2-9 This is a semiconductor structure diagram of each process step in the fabrication of a high-voltage LDMOS device according to an embodiment of the present invention;

[0031] The reference numerals in the attached figures are as follows:

[0032] 100 - Substrate, 101 - Active region, 110 - Pad oxide layer, 120 - Silicon nitride layer, 130 - Hard mask layer, 140 - Isolation layer, 150 - Dielectric layer;

[0033] 210 - First groove, 220 - Second groove, 230 - Third groove. Detailed Implementation

[0034] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0036] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0037] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0038] This application provides a method for fabricating a high-voltage LDMOS device. Please refer to [link / reference]. Figure 1 , Figure 1This is a flowchart of a method for fabricating a high-voltage LDMOS device according to an embodiment of the present invention. The method for fabricating the high-voltage LDMOS device includes:

[0039] S10: Provide a substrate on which a pad oxide layer, a silicon nitride layer and a hard mask layer are formed in sequence;

[0040] S20: Etch the hard mask layer, the silicon nitride layer and the pad oxide layer to the substrate surface to form a first trench;

[0041] S30: Etch the substrate at the bottom wall of the first trench to form a second trench;

[0042] S40: An isolation layer of a certain thickness is formed in the second trench using a thermal oxidation furnace tube process, wherein the upper surface of the isolation layer is flush with the upper surface of the substrate;

[0043] S50: Etch the hard mask layer, the silicon nitride layer, the pad oxide layer, a portion of the substrate thickness, and a portion of the isolation layer thickness to form a third trench and define an active region in the substrate;

[0044] S60: Form a dielectric layer, the dielectric layer filling the third trench;

[0045] S70: Remove the silicon nitride layer, the pad oxide layer, and a portion of the dielectric layer down to the substrate surface, with the upper surface of the remaining dielectric layer flush with the upper surface of the substrate.

[0046] For details, please refer to Figures 2-9 , Figures 2-9 This is a semiconductor structure diagram of each process step in the fabrication of a high-voltage LDMOS device according to an embodiment of the present invention.

[0047] First, such as Figure 2 As shown, a substrate 100 is provided, on which a pad oxide layer 110, a silicon nitride layer 120, and a hard mask layer 130 are formed in sequence. Specifically, the substrate 100 is a silicon substrate, and the hard mask layer 130 can be made of silicon oxide.

[0048] Then, as Figure 3 As shown, the hard mask layer 130, the silicon nitride layer 120, and the pad oxide layer 110 are etched to the surface of the substrate 100 to form the first trench 210. Specifically, the hard mask layer 130, the silicon nitride layer 120, and the pad oxide layer 110 are etched to the surface of the substrate 100 using photolithography and dry etching processes.

[0049] Next, as Figure 4As shown, the substrate 100 on the bottom wall of the first trench 210 is etched to form the second trench 220. Specifically, the hard mask layer 130, the silicon nitride layer 120, and the pad oxide layer 110 on the substrate 100 are etched first to form the first trench 210, and then the substrate is etched to form the second trench 220. The second trench 220 (deep trench) is formed in two steps. First, because of the difference in materials, different etching gases are used for the two etching steps. Second, because the depth-to-width ratio of the second trench 220 is large, the two-step etching can ensure the integrity of the morphology of the second trench 220.

[0050] Furthermore, such as Figure 5 As shown, a thermal oxidation furnace tube process is used to form an isolation layer 140 of a certain thickness in the second trench 220. The upper surface of the isolation layer 140 is flush with the upper surface of the substrate 100. Specifically, in the thermal oxidation furnace tube process, oxygen introduced into the furnace tube reacts with the substrate 100 exposed in the second trench 220 to generate the isolation layer 140. Specifically, the width of the isolation layer 140 is greater than the width of the second trench 220. In this embodiment, the width of the second trench 220 is less than five-elevenths of the width of the isolation layer 140, that is, the width of the second trench 220 < the width of the isolation layer 140 ÷ 2.2.

[0051] Furthermore, such as Figure 6 As shown, the hard mask layer 130, the silicon nitride layer 120, the pad oxide layer 110, a portion of the thickness of the substrate 100, and a portion of the thickness of the isolation layer 140 are etched to form a third trench 230 at the top of the isolation layer 140 and define the active region 101 in the substrate 100. Specifically, in this embodiment, a selective etching process can be used to etch the hard mask layer 130, the silicon nitride layer 120, the pad oxide layer 110, a portion of the thickness of the substrate 100, and a portion of the thickness of the isolation layer 140 to form the bowl-shaped third trench 230. The thickness of the substrate 100 removed by etching can be... The thickness of the isolation layer 140 removed by etching can be The remaining thickness of the isolation layer 140 is greater than 10 μm. This application forms the isolation layer (deep trench isolation structure) 140 before defining the active region 101, which avoids accidental oxidation of the exposed active region 101 during the high-temperature thermal oxidation formation of the isolation layer 140, thereby improving the isolation withstand voltage performance and reliability of the device.

[0052] Better, such as Figure 7As shown, after etching the hard mask layer 130, the silicon nitride layer 120, the pad oxide layer 110, a portion of the substrate 100, and a portion of the isolation layer 140 to form the third trench 230 and define the active region 101, the fabrication method of the high-voltage LDMOS device further includes removing the remaining hard mask layer 130. Specifically, the remaining hard mask layer 130 can be removed using dry etching, wet etching, or wet cleaning processes.

[0053] Next, as Figure 8 As shown, a dielectric layer 150 is formed, which fills the third trench 230. Specifically, the dielectric layer 150 can be made of silicon oxide, and the dielectric layer 150 is a shallow trench isolation structure of the device.

[0054] Finally, as Figure 9 As shown, the silicon nitride layer 120, the pad oxide layer 110, and a portion of the dielectric layer 150 are removed to the surface of the substrate 100, with the upper surface of the remaining dielectric layer 150 flush with the upper surface of the substrate 100. Specifically, a stripping process can be used to first remove the silicon nitride layer 120, followed by a dry etching process or a wet cleaning process to remove the pad oxide layer 110 and a portion of the dielectric layer 150; or a chemical mechanical polishing process can be used to directly remove the silicon nitride layer 120, the pad oxide layer 110, and a portion of the dielectric layer 150 to the surface of the substrate 100. The final thickness of the remaining dielectric layer 150 is...

[0055] Based on the same inventive concept, this application also provides a high-voltage LDMOS device, please refer to... Figure 9 , Figure 9 This is a schematic diagram of the structure of the high-voltage LDMOS device in this embodiment. The high-voltage LDMOS device includes a substrate 100, an isolation layer 140, and a dielectric layer 150. The isolation layer 140 and the dielectric layer 150 are both located in the substrate 100. The dielectric layer 150 is located at the top of the isolation layer 140, and the upper surface of the dielectric layer 150 is flush with the upper surface of the substrate 100.

[0056] In summary, the present invention provides a method for fabricating a high-voltage LDMOS device, comprising: providing a substrate 100 having a pad oxide layer 110, a silicon nitride layer 120, and a hard mask layer 130 stacked sequentially; etching the hard mask layer 130, the silicon nitride layer 120, and the pad oxide layer 110 to form a first trench 210; etching the substrate 100 at the bottom wall of the first trench 210 to form a second trench 220; forming an isolation layer 140 of a certain thickness in the second trench 220 using a thermal oxidation furnace tube process; and etching the hard mask layer 130, the silicon nitride layer 120, and the pad oxide layer 110. A mask layer 130, a silicon nitride layer 120, a pad oxide layer 110, a portion of the thickness of the substrate 100, and a portion of the thickness of the isolation layer 140 are used to form a third trench 230 and define an active region 101 in the substrate 100; a dielectric layer 150 is formed to fill the third trench 230; the silicon nitride layer 120, the pad oxide layer 110, and a portion of the thickness of the dielectric layer 150 are removed to the surface of the substrate 100, with the upper surface of the remaining thickness of the dielectric layer 150 flush with the upper surface of the substrate 100. This invention also provides a high-voltage LDMOS device. This application improves the isolation voltage withstand performance and reliability of the device by adjusting the order of defining the active region 101, forming the shallow trench isolation structure (dielectric layer 150), and forming the deep trench isolation layer (isolation layer 140). First, the isolation layer 140 is formed in the deep trench (second trench 220), then the active region 101 in the substrate 100 is defined, and finally the dielectric layer 150 (shallow trench isolation structure) is formed. This avoids the accidental oxidation of the active region 101 at the boundary with the shallow trench isolation structure 150 during the high-temperature thermal oxidation formation of the isolation layer 140, thus improving the device's isolation voltage withstand performance. Furthermore, the fabrication method of this application achieves high voltage withstand performance of the device through the DTI process by adjusting the order of multiple process steps without adding additional complex process steps, thereby simplifying the fabrication process and improving fabrication efficiency.

[0057] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for fabricating a high-voltage LDMOS device, characterized in that, include: A substrate is provided on which a pad oxide layer, a silicon nitride layer and a hard mask layer are formed in sequence. The hard mask layer, the silicon nitride layer, and the pad oxide layer are etched to the substrate surface to form a first trench; The substrate at the bottom wall of the first trench is etched to form the second trench; An isolation layer of a certain thickness is formed in the second trench using a thermal oxidation furnace tube process. The upper surface of the isolation layer is flush with the upper surface of the substrate. During the process of forming the isolation layer of a certain thickness in the second trench using the thermal oxidation furnace tube process, oxygen introduced into the furnace tube reacts with the substrate exposed in the second trench to generate the isolation layer. The width of the second trench is less than five-elevenths of the width of the isolation layer. The hard mask layer, the silicon nitride layer, the pad oxide layer, a portion of the substrate, and a portion of the isolation layer are etched to form a bowl-shaped third trench and define the active region in the substrate; A dielectric layer is formed, the dielectric layer filling the third trench; and, The silicon nitride layer, the pad oxide layer, and a portion of the dielectric layer are removed down to the substrate surface, with the upper surface of the remaining dielectric layer flush with the upper surface of the substrate.

2. The method for fabricating a high-voltage LDMOS device according to claim 1, characterized in that, The hard mask layer, the silicon nitride layer, the pad oxide layer, a portion of the substrate, and a portion of the isolation layer are etched using a selective etching process to form the bowl-shaped third trench.

3. The method for fabricating a high-voltage LDMOS device according to claim 2, characterized in that, Forming the third trench includes: etching away a substrate with a thickness of 3000 Å to 4000 Å; and etching away an isolation layer with a thickness of 3000 Å to 4000 Å.

4. The method for fabricating a high-voltage LDMOS device according to claim 2, characterized in that, The remaining thickness of the isolation layer is greater than 10 μm.

5. The method for fabricating a high-voltage LDMOS device according to claim 1, characterized in that, The fabrication method of the high-voltage LDMOS device further includes, after etching the hard mask layer, the silicon nitride layer, the pad oxide layer, a portion of the substrate thickness, and a portion of the isolation layer to form the third trench and define the active region, and before forming the dielectric layer: Remove the remaining hard mask layer.

6. The method for fabricating a high-voltage LDMOS device according to claim 1, characterized in that, The dielectric layer is made of silicon oxide.

7. The method for fabricating a high-voltage LDMOS device according to claim 1, characterized in that, The hard mask layer is made of silicon oxide.

8. The high-voltage LDMOS device prepared by the method according to any one of claims 1-7, characterized in that, include: The invention comprises a substrate, an isolation layer, and a dielectric layer, wherein the isolation layer and the dielectric layer are both located in the substrate, the dielectric layer is located at the top of the isolation layer, and the upper surface of the dielectric layer is flush with the upper surface of the substrate.

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