Semiconductor package

Abstract

Disclosed are a semiconductor package and a method of manufacturing the same. The semiconductor package includes a first redistribution substrate and a first semiconductor device on the first redistribution substrate. The first redistribution substrate includes a first dielectric layer including a first hole, a lower bump including a first bump portion in the first hole and a second bump portion protruding from the first bump portion to a bottom surface of the first dielectric layer, an external connection terminal on the bottom surface of the first dielectric layer and connected to the lower bump through the first hole, a wetting layer between the external connection terminal and the lower bump, and a first barrier / seed layer between the lower bump and the first dielectric layer and between the lower bump and the wetting layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0115240 filed on September 9, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor package and a method of manufacturing the same. Background Art

[0004] Semiconductor packages are provided to implement integrated circuit chips suitable for use in electronic products. Semiconductor packages are typically constructed such that the semiconductor chip is mounted on a printed circuit board (PCB), and bonding wires or bumps are used to electrically connect the semiconductor chip to the PCB. With the development of the electronics industry, much research has been conducted to improve the reliability and / or durability of semiconductor packages. Summary of the Invention

[0005] Some example embodiments of the inventive concepts provide a semiconductor package having improved reliability.

[0006] Some example embodiments of the present inventive concepts provide a method of manufacturing a semiconductor package, which can improve productivity.

[0007] The objects of the present inventive concept are not limited to the above, and other objects not mentioned above will be clearly understood by those skilled in the art from the following description.

[0008] According to some example embodiments of the present inventive concept, a semiconductor package may include: a first redistribution substrate; and a first semiconductor device located on the first redistribution substrate. The first redistribution substrate may include: a first dielectric layer including a first hole; a lower bump including a first bump portion located in the first hole and a second bump portion protruding from the first bump portion onto the first dielectric layer; an external connection terminal located on a bottom surface of the first dielectric layer and connected to the lower bump through the first hole; a wetting layer located between the external connection terminal and the lower bump; and a first barrier / seed layer located between the lower bump and the first dielectric layer and between the lower bump and the wetting layer.

[0009] According to some example embodiments of the inventive concepts, a semiconductor package can include a first redistribution substrate; and a first semiconductor device on the first redistribution substrate. The first redistribution substrate can include a first dielectric layer including a first hole; a lower bump including a first bump portion in the first hole and a second bump portion protruding from the first bump portion onto the first dielectric layer; and an external connection terminal on a bottom surface of the first dielectric layer and connected to the lower bump through the first hole. An inner sidewall of the first hole can be at a first angle from the bottom surface of the first dielectric layer. The first angle can be in a range of about 45° to about 90°.

[0010] According to some example embodiments of the inventive concepts, a semiconductor package can include a first redistribution substrate; a first semiconductor device on the first redistribution substrate; and a molding layer covering the first semiconductor device and the first redistribution substrate. The first redistribution substrate can include a first dielectric layer including a first hole; a lower bump including a first bump portion in the first hole and a second bump portion protruding from the first bump portion onto the first dielectric layer; an external connection terminal on a bottom surface of the first dielectric layer and connected to the lower bump through the first hole; a wetting layer between the external connection terminal and lower bump; a first barrier / seed layer between the lower bump and the first dielectric layer and between the lower bump and the wetting layer; a second dielectric layer covering the lower bump and the first dielectric layer; and a first redistribution pattern penetrating the second dielectric layer and connected to the lower bump. The external connection terminal can include a first terminal portion in the first hole; and a second terminal portion outwardly protruding from the bottom surface of the first dielectric layer. A sidewall of the first terminal portion can be at a first angle from a top surface of the second terminal portion. The first angle can be in a range of about 45° to about 90°.

[0011] According to some example embodiments of the inventive concept, a method of manufacturing a semiconductor package can include forming a redistribution substrate; mounting a semiconductor device on the redistribution substrate; and bonding external connection terminals to the redistribution substrate. The step of forming the redistribution substrate can include sequentially stacking a release layer and an etch stop layer on a carrier substrate; coating a first dielectric layer on the etch stop layer; exposing and developing the first dielectric layer to form a first hole exposing the etch stop layer; sequentially stacking a sacrificial pattern and a wetting layer in the first hole, the wetting layer exposing an upper portion of an inner sidewall of the first hole; forming a first barrier / seed layer and a lower bump on the wetting layer; and removing the carrier substrate, the release layer, the etch stop layer, and the sacrificial pattern to expose a bottom surface of the wetting layer and the first dielectric layer. The external connection terminals can be bonded to the wetting layer. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 A cross-sectional view showing a semiconductor package according to some example embodiments of the inventive concept is illustrated.

[0013] Figure 2 An enlarged view showing a portion P1 of the semiconductor package according to some example embodiments of the inventive concept is illustrated. Figure 1

[0014] Figures 3A to 3C An enlarged view showing a portion P2 of the semiconductor package according to some example embodiments of the inventive concept is illustrated. Figure 2

[0015] Figure 4 A top view showing a lower bump according to some example embodiments of the inventive concept is illustrated.

[0016] Figures 5A to 5I An enlarged partial cross-sectional view showing a method of manufacturing a semiconductor package according to some example embodiments of the inventive concept is illustrated. Figure 1

[0017] A cross-sectional view showing a semiconductor package according to some example embodiments of the inventive concept is illustrated. Figure 6

[0018] A cross-sectional view showing a semiconductor package according to some example embodiments of the inventive concept is illustrated. Figure 7

[0019] A cross-sectional view showing a semiconductor package according to some example embodiments of the inventive concept is illustrated. Figure 8

[0020] A cross-sectional view showing a semiconductor package according to some example embodiments of the inventive concept is illustrated. Figure 9 ​​Cross-sectional views showing semiconductor packages according to some example embodiments of inventive concepts are shown. DETAILED DESCRIPTION

[0021] Some example embodiments of inventive concepts will now be described in detail by way of reference only to the drawings, to help clarify inventive concepts.

[0022] Figure 1 Cross-sectional views showing semiconductor packages according to some example embodiments of inventive concepts are shown. Figure 2 Cross-sectional views showing semiconductor packages according to some example embodiments of inventive concepts are shown. Figure 1 enlarged view of portion P1 of Figures 3A to 3C enlarged view of portion P2 of Figure 2 enlarged view of portion P2 of Figure 4 Plan views showing under-bumps according to some example embodiments of inventive concepts are shown.

[0023] Referring to Figure 1 and Figure 2 , a semiconductor package 1000 according to the present example embodiment can include a first redistribution substrate RD1 and a first semiconductor device CH1 mounted on the first redistribution substrate RD1. The first semiconductor device CH1 and the first redistribution substrate RD1 can be covered by a first molding layer MD1. In the present specification, the term “redistribution substrate” can be referred to as “redistribution layer” or “wiring structure”.

[0024] The first redistribution substrate RD1 can include a first dielectric layer IL1, a second dielectric layer IL2, a third dielectric layer IL3, and a fourth dielectric layer IL4, which are sequentially stacked. The first dielectric layer IL1, the second dielectric layer IL2, the third dielectric layer IL3, and the fourth dielectric layer IL4 can each include a photoimageable dielectric (PID) layer.

[0025] Referring to Figure 1 , Figure 2 and Figure 3A , the first dielectric layer IL1 can include a plurality of first holes H1. The first holes H1 can have an inclined inner sidewall SS. The inner sidewall SS of the first holes H1 can make a first angle θ1 with a bottom surface IL1B of the first dielectric layer IL1. The first angle θ1 can be, for example, an acute angle. The first angle θ1 can be in a range of, for example, about 45° to about 90°. The inner sidewall SS of the first holes H1 can make a second angle θ2 with a top surface IL1U of the first dielectric layer IL1. The second angle θ2 can be, for example, an obtuse angle. The second angle θ2 can be in a range of, for example, about 90° to about 135°.

[0026] Referring to Figure 3AThe under bump metallurgy (UBM) can be disposed in the first hole H1, respectively. The under bump metallurgy (UBM) can each have a T-shaped cross section. The under bump metallurgy (UBM) can each include a first bump portion PT1 inserted into the first hole H1 and a second bump portion PT2 protruding onto the first dielectric layer IL1. The first bump portion PT1 and the second bump portion PT2 can be integrally connected as a single piece. The first bump portion PT1 can have an inclined first sidewall SW1. An angle between the first sidewall SW1 of the first bump portion PT1 and a bottom surface PT2B of the second bump portion PT2 can be the same as the second angle θ2. An angle between the first sidewall SW1 of the first bump portion PT1 and a bottom surface PT1B of the first bump portion PT1 can be the same as the second angle θ2.

[0027] Still referring to Figure 3A , a bottom surface PT2B of the second bump portion PT2 can be at a third angle θ3 to a second sidewall SW2 of the second bump portion PT2. The third angle θ3 can be greater than the first angle θ1 and less than the second angle θ2. For example, the third angle θ3 can be about 90° or a right angle. As shown in Figure 3A , the second sidewall SW2 of the second bump portion PT2 can be almost perpendicular to a top surface IL1U of the first dielectric layer IL1.

[0028] In example embodiments of the inventive concept, as shown in Figure 3C , the first angle θ1 to the third angle θ3 can each be about 90°.

[0029] Referring to Figure 3B , the first bump portion PT1 can have a first width W1 in a direction. The first width W1 can increase as approaching from a bottom surface IL1B to the top surface IL1U of the first dielectric layer IL1. The second bump portion PT2 can have a second width W2 in the direction. The second width W2 can be greater than the first width W1. The second bump portion PT2 can cover the top surface IL1U of the first dielectric layer IL1. The under bump metallurgy (UBM) can include copper or nickel.

[0030] When viewed in a top view as shown in Figure 4 , the first bump portion PT1 can have a circular shape at a bottom surface PT1B thereof. When viewed in the top view, the first sidewall SW1 of the first bump portion PT1 and the bottom surface PT2B of the second bump portion PT2 can each have a ring shape around the bottom surface PT1B of the first bump portion PT1.

[0031] The first barrier / seed layer SL1 can be interposed between the under bump metallurgy UBM and the first dielectric layer IL1. The first barrier / seed layer SL1 can include a barrier layer and a seed layer sequentially stacked. The barrier layer can include one or more of a titanium layer, a tantalum layer, a titanium nitride layer, and a tantalum nitride layer. The seed layer can include the same material as that of the under bump metallurgy UBM. The first barrier / seed layer SL1 can be in contact with the first sidewall SW1 and the bottom surface PT1B of the first bump portion PT1 and with the bottom surface PT2B of the second bump portion PT2.

[0032] The first barrier / seed layer SL1 (or the barrier layer thereof) can serve to reduce or prevent diffusion of a constituent metal of the under bump metallurgy UBM into the first dielectric layer IL1. Accordingly, the first barrier / seed layer SL1 can reduce or prevent a constituent metal of the under bump metallurgy UBM from reacting with a constituent material of the first dielectric layer IL1. Accordingly, a void can be reduced or prevented from being formed between the under bump metallurgy UBM and the first dielectric layer IL1, and thus the under bump metallurgy UBM can be reduced or prevented from being cracked and / or delaminated from the first dielectric layer IL1.

[0033] The external connection terminal 100 can be joined to the bottom surface IL1B of the first dielectric layer IL1. The external connection terminal 100 can have a circular shape when viewed in a top view. The external connection terminal 100 can be correspondingly connected to the under bump metallurgy UBM through the first hole H1. The external connection terminal 100 can each include a first terminal portion 100a inserted into the first hole H1 and a second terminal portion 100b protruding outward from the bottom surface IL1B of the first dielectric layer IL1. The first terminal portion 100a and the second terminal portion 100b can be integrally connected as a single piece. The external connection terminal 100 can include one or more of tin, lead, and silver. The external connection terminal 100 can be formed of, for example, SnAg.

[0034] Referring back to Figure 3A , the under bump metallurgy UBM can have a first thickness T1 at the second bump portion PT2 thereof. The under bump metallurgy UBM can have a second thickness T2 at the first bump portion PT1 thereof. The external connection terminal 100 can have a third thickness T3 at the first terminal portion 100a thereof. The second thickness T2 can be about 0.8 times to about 1.2 times the third thickness T3. The first thickness T1 can be equal to, greater than, or less than the second thickness T2.

[0035] Referring back to Figure 3A , an angle between the sidewall 100S1 of the first terminal portion 100a and the top surface 100S2 of the second terminal portion 100b can form the same angle as the first angle Θ1. Referring back to Figure 3BThe first terminal portion 100a may have a third width W3 in one direction. The third width W3 may increase as the distance from the bottom surface IL1B of the first dielectric layer IL1 approaches the top surface IL1U. The second terminal portion 100b may have a fourth width W4 in one direction. The fourth width W4 may be greater than the third width W3. The fourth width W4 may be equal to or less than the second width W2.

[0036] The first hole H1 may have a wetting layer 5 interposed therein between the first barrier / seed layer SL1 and the external connection terminal 100. The wetting layer 5 may include, for example, gold. The wetting layer 5 may reduce or prevent oxidation of the underbump UBM and / or the first barrier / seed layer SL1, may have improved wettability to the external connection terminal 100, may reduce or prevent contact failure between the underbump UBM and the external connection terminal 100, and may reduce or prevent delamination of the external connection terminal 100.

[0037] The first barrier / seed layer SL1, the wetting layer 5, and the external connection terminal 100 may all be in contact with the inner sidewall SS of the first hole H1. The first barrier / seed layer SL1, the wetting layer 5, and the first terminal portion 100a of the external connection terminal 100 may have sidewalls aligned with each other. For example, the first barrier / seed layer SL1, the wetting layer 5, and the first terminal portion 100a of the external connection terminal 100 may have sidewalls arranged on a single straight line.

[0038] The first barrier / seed layer SL1 (or its barrier layer) can be used to reduce or prevent the metal constituting the underbump UBM from diffusing into the wetting layer 5 and the external connection terminal 100. Therefore, the first barrier / seed layer SL1 can reduce or prevent the metal constituting the underbump UBM from reacting with the constituent materials of the wetting layer 5 and the constituent materials of the external connection terminal 100. Therefore, the formation of gaps between the underbump UBM and the external connection terminal 100 can be reduced or prevented, thereby reducing or preventing contact failure and / or cracking between the underbump UBM and the external connection terminal 100, as well as delamination of the external connection terminal 100.

[0039] In addition, if Figure 3A As shown, an acute angle or first angle θ1 may be formed between the sidewall 100S1 of the first terminal portion 100a and the top surface 100S2 of the second terminal portion 100b, and thus, the external connection terminal 100 may be difficult to escape from the first hole H1. Therefore, delamination of the external connection terminal 100 may be reduced or prevented.

[0040] In addition, according to some example embodiments of the inventive concept, the first dielectric layer IL1 can partially cover and partially expose the under bump metallurgy UBM, thereby constituting a solder mask defined (SMD) structure, and thus, stress between the under bump metallurgy UBM and the first dielectric layer IL1 can be reduced, and delamination of the under bump metallurgy UBM can be reduced or prevented. As a result, reliability of the semiconductor package 1000 can be improved.

[0041] Referring also to Figure 3A , the second dielectric layer IL2 can cover the under bump metallurgy UBM and the first dielectric layer IL1. The under bump metallurgy UBM can directly contact the second dielectric layer IL2. The first barrier / seed layer SL1 can not be interposed between the second dielectric layer IL2 and the under bump metallurgy UBM. Thus, a constituting metal of the under bump metallurgy UBM can partially diffuse into the second dielectric layer IL2, and thus, the constituting metal of the under bump metallurgy UBM and oxygen inside the second dielectric layer IL2 can react with each other to form a metal oxide layer CO. Figure 3B The metal oxide layer CO can be located between the under bump metallurgy UBM and the second dielectric layer IL2. In addition, because the constituting metal of the under bump metallurgy UBM partially diffuses into the second dielectric layer IL2, as shown in Figure 3B , a void region VD can be formed on a surface of the under bump metallurgy UBM.

[0042] Referring back to Figures 1 to 2 , the first redistribution pattern RP1 can be interposed between the second dielectric layer IL2 and the third dielectric layer IL3. The second barrier / seed layer SL2 can be interposed between the first redistribution pattern RP1 and the second dielectric layer IL2 and between the first redistribution pattern RP1 and the under bump metallurgy UBM.

[0043] The second redistribution pattern RP2 can be interposed between the third dielectric layer IL3 and the fourth dielectric layer IL4. The third barrier / seed layer SL3 can be interposed between the second redistribution pattern RP2 and the third dielectric layer IL3 and between the second redistribution pattern RP2 and the first redistribution pattern RP1.

[0044] The substrate conductive pattern 10 can be disposed on the fourth dielectric layer IL4. A portion of the substrate conductive pattern 10 can penetrate the fourth dielectric layer IL4 and can be connected to the second redistribution pattern RP2. The fourth barrier / seed layer SL4 can be interposed between the substrate conductive pattern 10 and the fourth dielectric layer IL4 and between the substrate conductive pattern 10 and the second redistribution pattern RP2.

[0045] The first redistribution pattern RP1, the second redistribution pattern RP2, and the substrate conductive pattern 10 can include one or more of, for example, copper, nickel, aluminum, and gold. The second barrier / seed layer SL2 to the fourth barrier / seed layer SL4 can have the same material and structure as those of the first barrier / seed layer SL1.

[0046] Each of the first redistribution pattern RP1 and the second redistribution pattern RP2 can include a via portion VP and a line portion LP having a linear shape located on the via portion VP. The via portion VP and the line portion LP can be integrally connected into a single piece. The via portion VP can have a width that decreases in a downward direction. For example, the via portion VP of the first redistribution pattern RP1 can have a fifth width W5 in one direction, as shown in Figure 3B The fifth width W5 can increase in an upward direction. The fifth width W5 can be smaller than the first width W1 to the fourth width W4.

[0047] The first semiconductor device CH1 can be a single semiconductor die or chip, or a semiconductor package including a plurality of semiconductor dies of the same type or different types. The first semiconductor device CH1 can be one selected from among an image sensor chip such as a CMOS image sensor (CIS), a micro electro mechanical system (MEMS) device chip, an application specific integrated circuit (ASIC) chip, and a memory device chip such as a flash memory, a DRAM, an SRAM, an EEPROM, a PRAM, an MRAM, a ReRAM, an HBM (high bandwidth memory), and an HMC (hybrid memory cube).

[0048] The first semiconductor device CH1 can be flip-chip bonded to the first redistribution substrate RD1 through the first internal connection member 110. The first internal connection member 110 can electrically connect the substrate conductive pattern 10 to a chip pad 105 of the first semiconductor device CH1. The first internal connection member 110 can include one or more of a solder ball, a conductive bump, and a conductive pillar. The first internal connection member 110 can include one or more of tin, lead, silver, copper, nickel, and gold.

[0049] The first molding layer MD1 can cover a sidewall of the first semiconductor device CH1, a top surface of the first semiconductor device CH1, and a top surface of the first redistribution substrate RD1. The first molding layer MD1 can include a dielectric resin such as an epoxy molding compound (EMC). The first molding layer MD1 can further include a filler, and the filler can be dispersed in the dielectric resin.

[0050] The first underfill layer UF1 can be interposed between the first semiconductor device CH1 and the first redistribution substrate RD1. The first underfill layer UF1 can include a thermosetting resin or a photocurable resin. In addition, the first underfill layer UF1 can further include an organic filler or an inorganic filler.

[0051] Figures 5A to 5I An enlarged partial cross-sectional view illustrating a method of manufacturing a semiconductor package Figure 1 exhibiting some example embodiments according to inventive concepts is shown.

[0052] Referring to Figure 5A A carrier substrate CB can be prepared. The carrier substrate CB can be, for example, a transparent glass substrate. A release layer RL can be formed on the carrier substrate CB. The release layer RL can include an epoxy resin. The release layer RL can exhibit, for example, photo-degradability or thermal-degradability. An etch stop layer EL can be formed on the release layer RL. The etch stop layer EL can include a conductive material that is etch-selective with respect to the release layer RL. For example, the etch stop layer EL can include a metal such as titanium. A first dielectric layer IL1 can be formed on the etch stop layer EL. The first dielectric layer IL1 can be formed by a coating, exposure, and development process. The exposure and development process can cause the first dielectric layer IL1 to be formed to include a first hole H1 that exposes the etch stop layer EL.

[0053] In addition, the first dielectric layer IL1 can be cured. Thus, the first dielectric layer IL1 can shrink. In some example embodiments, the first dielectric layer IL1 can have a bottom surface IL1B that is in contact with and fixed by the etch stop layer EL, and thus, the first dielectric layer IL1 can be difficult to shrink its lower portion. In contrast, the first dielectric layer IL1 can have a top surface IL1U that is not fixed by the etch stop layer EL, and thus, the first dielectric layer IL1 can be easy to shrink its upper portion. Thus, the first hole H1 can have its inner sidewall SS that is inclined. For example, the inner sidewall SS of the first hole H1 can make a first angle θ1 with the bottom surface IL1B of the first dielectric layer IL1. The inner sidewall SS of the first hole H1 can make a second angle θ2 with the top surface IL1U of the first dielectric layer IL1. The first angle θ1 can be smaller than the second angle θ2.

[0054] Referring to Figure 5BThe sacrificial pattern SP and the wetting layer 5 can be sequentially formed in the first hole H1. The sacrificial pattern SP and the wetting layer 5 can each be formed by electroplating. The sacrificial pattern SP and the wetting layer 5 can not completely fill the first hole H1, and can expose an upper portion of the inner sidewall SS of the first hole H1. The sacrificial pattern SP can include a conductive material that is etch-selective with respect to the etch stop layer EL and the wetting layer 5. The sacrificial pattern SP can include a metal that is different from the metal of the etch stop layer EL and the wetting layer 5. For example, the sacrificial pattern SP can include nickel. The wetting layer 5 can include gold (Au).

[0055] Referring to Figure 5C A first barrier / seed layer SL1 can be conformally formed on the wetting layer 5 and the first dielectric layer IL1. The first barrier / seed layer SL1 can be formed by sequentially stacking a barrier layer and a seed layer. A first mask pattern PR1 can be formed on the first barrier / seed layer SL1. The first mask pattern PR1 can include a first opening OP1 that overlaps the first hole H1. The first opening OP1 can expose the first barrier / seed layer SL1. The first mask pattern PR1 can be, for example, a photoresist pattern. An electroplating process can be performed to form a lower UBM on the first barrier / seed layer SL1. The lower UBM can fill the first hole H1, and can fill at least a portion of the first opening OP1. The lower UBM can expose a top surface of the first mask pattern PR1.

[0056] Referring to Figure 5C and Figure 5D The first mask pattern PR1 can be removed to expose a top surface of the first barrier / seed layer SL1 and a side surface of the lower UBM. When the first mask pattern PR1 is a photoresist pattern, an ashing process can be employed to remove the first mask pattern PR1. The first barrier / seed layer SL1 exposed at the side of the lower UBM can be removed to expose a top surface IL1U of the first dielectric layer IL1.

[0057] Referring also to Figure 5EA second dielectric layer IL2 can be formed on the under bump metallization UBM and the first dielectric layer IL1. The second dielectric layer IL2 can be formed by a coating, exposure, development, and curing process. The second dielectric layer IL2 can be formed to include a second hole H2 that exposes a top surface of the under bump metallization UBM. A second barrier / seed layer SL2 can be conformally formed on the second dielectric layer IL2. A second mask pattern PR2 can be formed on the second barrier / seed layer SL2. The second mask pattern PR2 can be, for example, a photoresist pattern. The second mask pattern PR2 can be formed to include a second opening OP2 that overlaps the second hole H2 and exposes a portion of the second barrier / seed layer SL2. A plating process can be performed to form a first redistribution pattern RP1 in the second hole H2 and the second opening OP2. The first redistribution pattern RP1 can be formed to include a via portion VP that fills the second hole H2 and a line portion LP that is located in the second opening OP2.

[0058] Referring to Figure 5E and Figure 5F The second mask pattern PR2 and the second barrier / seed layer SL2 thereunder can be removed to expose a top surface of the second dielectric layer IL2.

[0059] Referring to Figure 5G A third dielectric layer IL3 can be formed to expose the first redistribution pattern RP1 and the second dielectric layer IL2. The third barrier / seed layer SL3 and a second redistribution pattern RP2 can be formed by using the same methods as discussed with reference to Figure 5E and Figure 5F A fourth dielectric layer IL4 can be formed to cover the second redistribution pattern RP2 and the third dielectric layer IL3. The fourth barrier / seed layer SL4 and a substrate conductive pattern 10 can be formed by using the same methods as discussed with reference to Figure 5E and Figure 5F Thus, a first redistribution substrate RD1 can be formed.

[0060] Referring to Figure 1 , Figure 5G and Figure 5H A first semiconductor device CH1 can be mounted on the first redistribution substrate RD1 using the first internal connection member 110. A first underfill layer UF1 can be formed between the first semiconductor device CH1 and the first redistribution substrate RD1. A first mold layer MD1 can be formed to cover the first redistribution substrate RD1 and the first semiconductor device CH1.

[0061] Referring to Figure 5H and Figure 5IThe carrier substrate CB can be separated from the etching stop layer EL. When the release layer RL is a photo-degradable layer, ultraviolet light UV can be irradiated through the carrier substrate CB to the release layer RL, thereby separating the carrier substrate CB. Or, when the release layer RL is a heat-degradable layer, high-temperature heat can be applied through the carrier substrate CB to the release layer RL, thereby separating the carrier substrate CB. Or, a mechanical force can be provided to the side surface of the release layer RL to physically separate the carrier substrate CB from the etching stop layer EL. After separating the carrier substrate CB, at least a portion of the release layer RL can remain on the etching stop layer EL. A first etching process can be performed in which the release layer RL can be removed to expose a surface of the etching stop layer EL. In some example embodiments, the etching stop layer EL can reduce or prevent the wetting layer 5 from receiving a first etchant for the first etching process. A second etching process can be performed in which the etching stop layer EL can be removed to expose a bottom surface of the first dielectric layer IL1 and a bottom surface of the sacrificial pattern SP. The sacrificial pattern SP can reduce or prevent the wetting layer 5 from receiving a second etchant for the second etching process. A third etching process can be performed in which the sacrificial pattern SP can be removed to expose a surface of the wetting layer 5 and a lower inner sidewall of the first hole H1. Subsequently, return to Figure 2 The external connection terminal 100 can be bonded to the wetting layer 5 exposed through the first hole H1. A separation process can be performed to separate the semiconductor packages from each other. Thus, finally, the semiconductor package 1000 can be manufactured as shown in Figure 1 and Figure 2 .

[0062] In the method of manufacturing a semiconductor package according to some example embodiments of the inventive concept, the etching stop layer EL and the sacrificial pattern SP can be used so that the wetting layer 5, the first barrier / seed layer SL1, and the under bump UBM can be formed without occurrence of failure of the wetting layer 5, the first barrier / seed layer SL1, and the under bump UBM. As a result, the yield can be improved.

[0063] Further, the method of manufacturing a semiconductor package can include an operation of forming the wetting layer 5, and thus oxidation of the under bump UBM and / or the first barrier / seed layer SL1 can be reduced or prevented. Thus, contact failure between the under bump UBM and the external connection terminal 100 can be reduced or prevented. In addition, when the wetting layer 5 is not present, a problem that the external connection terminal 100 is not bonded to the under bump UBM or the first barrier / seed layer SL1 can occur. The inventive concept can include an operation of forming the wetting layer 5, and thus process failure can be reduced or prevented and the yield can be improved.

[0064] Figure 6 A cross-sectional view showing a semiconductor package according to some example embodiments of the inventive concept is illustrated.

[0065] Referring Figure 6 , the semiconductor package 1001 according to the present example embodiment can be configured such that the first semiconductor device CH1 and the second semiconductor device CH2 can be mounted side-by-side on the first redistribution substrate RD1. The first semiconductor device CH1 can be spaced apart from the second semiconductor device CH2. The first underfill layer UF1 can be interposed between the first semiconductor device CH1 and the first redistribution substrate RD1. The second underfill layer UF2 can be interposed between the second semiconductor device CH2 and the first redistribution substrate RD1. The first semiconductor device CH1 and the second semiconductor device CH2 can be of the same type or different types. The first molding layer MD1 can cover the first semiconductor device CH1 and the second semiconductor device CH2. In the present example embodiment, two semiconductor devices CH1 and CH2 are mounted side-by-side, but the number of semiconductor devices CH1 and CH2 can be three or more. Other configurations can be the same as or similar to those discussed with reference to Figures 1 to 4 .

[0066] Figure 7 A cross-sectional view showing a semiconductor package according to some example embodiments of the inventive concepts is illustrated.

[0067] Referring Figure 7 , the semiconductor package 1002 according to the present example embodiment can include a first redistribution substrate RD1 including a first substrate conductive pattern 10a and a second substrate conductive pattern 10b. The first substrate conductive pattern 10a can be connected to the first internal connection member 110. The semiconductor package 1002 can also include a second redistribution substrate RD2 disposed on the first molding layer MD1 and a molding via MV passing through the first molding layer MD1 and connecting the first redistribution substrate RD1 to the second redistribution substrate RD2. The molding via MV can contact the second substrate conductive pattern 10b. The molding via MV can include a conductive material such as copper. The molding via MV can directly contact the first molding layer MD1.

[0068] The second redistribution substrate RD2 can include a fifth dielectric layer IL5, a sixth dielectric layer IL6, and a seventh dielectric layer IL7 stacked in sequence. The fifth dielectric layer IL5 to the seventh dielectric layer IL7 can each include a photoimageable dielectric (PID) layer. A third redistribution pattern RP3 can be interposed between the fifth dielectric layer IL5 and the sixth dielectric layer IL6. A fifth barrier / seed layer SL5 can be interposed between the third redistribution pattern RP3 and the fifth dielectric layer IL5. The third redistribution pattern RP3 can be connected to the molded via MV. A fourth redistribution pattern RP4 can be interposed between the sixth dielectric layer IL6 and the seventh dielectric layer IL7. A sixth barrier / seed layer SL6 can be interposed between the fourth redistribution pattern RP4 and the sixth dielectric layer IL6. The third redistribution pattern RP3 and the fourth redistribution pattern RP4 can each include a via portion VP and a line portion LP. A third substrate conductive pattern 20 can be disposed on the seventh dielectric layer IL7. A seventh barrier / seed layer SL7 can be interposed between the third substrate conductive pattern 20 and the seventh dielectric layer IL7. The third redistribution pattern RP3, the fourth redistribution pattern RP4, and the third substrate conductive pattern 20 can each include one or more of, for example, copper, nickel, aluminum, and gold. The fifth barrier / seed layer SL5 to the seventh barrier / seed layer SL7 can each have the same material and structure as those of the first barrier / seed layer SL1. Other configurations can be the same as or similar to those discussed with reference to Figures 1 to 4

[0069] Figure 8 A cross-sectional view showing a semiconductor package according to some example embodiments of the inventive concepts is illustrated.

[0070] Referring to Figure 8 The semiconductor package 1003 according to the present example embodiments can include a first sub-semiconductor package PK1 and a second sub-semiconductor package PK2 stacked on the first sub-semiconductor package PK1. The first sub-semiconductor package PK1 can have a structure similar to that of the semiconductor package 1001. The second sub-semiconductor package PK2 can have a structure similar to that of the semiconductor package 1002. Figure 7 ​The second sub semiconductor package PK2 can include a first package substrate SB1, a second semiconductor device CH2 mounted on the first package substrate SB1, and a second molding layer MD2 covering the second semiconductor device CH2 and the first package substrate SB1. The second semiconductor device CH2 can be electrically connected to the first package substrate SB1 by, for example, wires 360. The second semiconductor device CH2 can be a single semiconductor die or chip, or a semiconductor package including a plurality of semiconductor dies of the same type or different types. The second semiconductor device CH2 can be one selected from among an image sensor chip such as a CMOS image sensor (CIS), a micro electro mechanical system (MEMS) device chip, an application specific integrated circuit (ASIC) chip, and a memory device chip such as a flash memory, a DRAM, a SRAM, an EEPROM, a PRAM, an MRAM, a ReRAM, an HBM (high bandwidth memory), and an HMC (hybrid memory cube).

[0071] The second molding layer MD2 can include the same material as that of the first molding layer MD1. The wires 360 can include copper or gold. The first package substrate SB1 can be, for example, a double-layer or multi-layer printed circuit board. The first package substrate SB1 can include an upper conductive pattern 380 disposed on a top surface thereof and a lower conductive pattern 382 disposed on a bottom surface thereof. The first package substrate SB1 can have internal wiring (not shown) therein to connect the upper conductive pattern 380 to the lower conductive pattern 382. The upper conductive pattern 380 and the lower conductive pattern 382 can include one or more of, for example, gold, copper, aluminum, and nickel.

[0072] The first sub semiconductor package PK1 can be connected to the second sub semiconductor package PK2 by a second internal connection member 120. The second internal connection member 120 can connect the lower conductive pattern 382 to the third substrate conductive pattern 20. The second internal connection member 120 can include one or more of a solder ball, a conductive bump, and a conductive pillar. The second internal connection member 120 can include one or more of tin, lead, silver, copper, nickel, and gold. Other configurations can be the same as or similar to those discussed with reference to Figure 7

[0073] Figure 9 A cross-sectional view showing a semiconductor package according to some example embodiments of the inventive concepts is illustrated.

[0074] Reference is made to Figure 9 ​According to the present example embodiment, the semiconductor package 1004 can include a first sub semiconductor package PK1 including a first redistribution substrate RD1, a connection substrate 900 and a first semiconductor device CH1 mounted on the first redistribution substrate RD1, a first molding layer MD1 covering the connection substrate 900 and the first semiconductor device CH1, and a second redistribution substrate RD2 on the first molding layer MD1.

[0075] The first underfill layer UF1 can be between the first semiconductor device CH1 and the first redistribution substrate RD1. The connection substrate 900 can include a cavity region CV in a center thereof. The first semiconductor device CH1 can be disposed in the cavity region CV. The connection substrate 900 can include a plurality of base layers 910 and conductive structures 920. The base layers 910 can include a dielectric material. For example, the base layers 910 can include a carbon-based material, a ceramic, or a polymer. The conductive structures 920 can include connection pads 921, first connection vias 922, connection lines 923, and second connection vias 924.

[0076] The connection substrate 900 can be connected to the first redistribution substrate RD1 by the third internal connection member 130. The second underfill layer UF2 can be between the connection substrate 900 and the first redistribution substrate RD1. The first molding layer MD1 can fill a space between the first semiconductor device CH1 and an inner sidewall of the cavity region CV of the connection substrate 900. The second underfill layer UF2 can include the same material as that of the first underfill layer UF1.

[0077] The auxiliary via 30 can penetrate the first molding layer MD1 and can connect the second connection vias 924 of the connection substrate 900 to the third redistribution pattern RP3 of the second redistribution substrate RD2. The third underfill layer UF3 can fill a space between the first sub semiconductor package PK1 and the second sub semiconductor package PK2. The third underfill layer UF3 can include the same material as that of the first underfill layer UF1. Other configurations can be the same as or similar to those discussed with reference to Figure 8 FIGS. 1 to 3.

[0078] According to the semiconductor package of the present inventive concept, the first underfill layer can be between the first semiconductor device and the first redistribution substrate, and the second underfill layer can be between the connection substrate and the first redistribution substrate. The first underfill layer and the second underfill layer can include the same material. The first underfill layer and the second underfill layer can include a carbon-based material, a ceramic, or a polymer.

[0079] In addition, a wetting layer can be between the lower bump and the external connection terminal to reduce or prevent contact failure between the lower bump and the external connection terminal and delamination of the external connection terminal.

[0080] In addition, an acute angle or a first angle can be formed between the sidewall of the first terminal portion of the external connection terminal and the top surface of the second terminal portion of the external connection terminal, so that the external connection terminal can be difficult to be detached from the first hole. Accordingly, delamination of the external connection terminal can be reduced or prevented.

[0081] According to the method of manufacturing a semiconductor package according to the inventive concept, the etch stop layer and the sacrificial pattern can be used, so that the wetting layer, the first barrier / seed layer, and the under bump can be formed without failure of the wetting layer, the first barrier / seed layer, and the under bump. As a result, the yield can be improved.

[0082] Although the inventive concept has been described with reference to some example embodiments of the inventive concept illustrated in the accompanying drawings, those having ordinary skill in the art will appreciate that various modifications and changes can be made thereto without departing from the technical spirit and essential characteristics of the inventive concept. Therefore, the above-disclosed example embodiments should be considered illustrative rather than limiting. Figures 1 to 9 The example embodiments of the inventive concept can be combined with each other.

Claims

1. A semiconductor package, comprising: a first redistribution substrate; and a first semiconductor device, the first semiconductor device being located on the first redistribution substrate; Wherein, the first redistribution substrate comprises: a first dielectric layer comprising a first aperture; a lower bump, the lower bump comprising a first bump portion located in the first hole and a second bump portion protruding from the first bump portion onto the first dielectric layer; an external connection terminal located on a bottom surface of the first dielectric layer and connected to the lower bump through the first hole; a wetting layer, the wetting layer being located between the external connection terminal and the lower bump; a first barrier / seed layer located between the underbump and the first dielectric layer and between the underbump and the wetting layer; a second dielectric layer, the second dielectric layer covering the first dielectric layer and the second bump portion of the lower bump; a metal oxide layer between the second bump portion and the second dielectric layer; and A gap region is located between the second bump portion and the metal oxide layer.

2. The semiconductor package according to claim 1, wherein An inner sidewall of the first hole makes a first angle with the bottom surface of the first dielectric layer, Wherein, the first angle is in the range of 45° to 90°.

3. The semiconductor package according to claim 1, wherein The external connection terminals include: a first terminal portion located in the first hole; and a second terminal portion protruding outwardly from the bottom surface of the first dielectric layer, wherein the side wall of the first terminal portion forms a first angle with the top surface of the second terminal portion, Wherein, the first angle is in the range of 45° to 90°.

4. The semiconductor package according to claim 1, wherein The external connection terminals include: a first terminal portion located in the first hole; and a second terminal portion protruding outwardly from the bottom surface of the first dielectric layer, Wherein, the width of the second terminal portion is greater than the width of the first terminal portion.

5. The semiconductor package according to claim 1, wherein The sidewall of the first bump portion forms a first angle with the bottom surface of the second bump portion, Wherein, the first angle is in the range of 90° to 135°. The semiconductor package according to claim 1 , wherein: A width of the second bump portion is greater than a width of the first bump portion.

7. The semiconductor package according to claim 1, wherein Sidewalls of the external connection terminal, the wetting layer, and the first barrier / seed layer are aligned with each other.

8. The semiconductor package according to claim 1, wherein The first redistribution substrate further includes: a first redistribution pattern penetrating the second dielectric layer and connected to the lower bump; The second bump portion is in direct contact with the second dielectric layer.

9. The semiconductor package according to claim 8, wherein The first redistribution pattern includes a via portion penetrating the second dielectric layer and a line portion protruding onto the second dielectric layer. Wherein, the width of the passage portion is smaller than the width of the first bump portion.

10. A semiconductor package, comprising: a first redistribution substrate; and a first semiconductor device, the first semiconductor device being located on the first redistribution substrate; Wherein, the first redistribution substrate comprises: a first dielectric layer comprising a first aperture; a lower bump, the lower bump comprising a first bump portion located in the first hole and a second bump portion protruding from the first bump portion onto the first dielectric layer; an external connection terminal located on the bottom surface of the first dielectric layer and connected to the lower bump through the first hole; a second dielectric layer, the second dielectric layer covering the first dielectric layer and the second bump portion of the lower bump; a metal oxide layer between the second bump portion and the second dielectric layer; and a gap region, the gap region being located between the second bump portion and the metal oxide layer; wherein the inner sidewall of the first hole forms a first angle with the bottom surface of the first dielectric layer, Wherein, the first angle is in the range of 45° to 90°.

11. The semiconductor package according to claim 10, wherein The first redistribution substrate further includes: a wetting layer located between the external connection terminal and the lower bump; and A first barrier / seed layer is located between the underbump and the first dielectric layer and between the underbump and the wetting layer.

12. The semiconductor package according to claim 10, wherein The sidewall of the first bump portion forms a second angle with the bottom surface of the second bump portion, The second angle is in the range of 90° to 135°.

13. The semiconductor package according to claim 11, wherein Sidewalls of the external connection terminal, the wetting layer, and the first barrier / seed layer are aligned with each other.

14. The semiconductor package according to claim 10, wherein The first redistribution substrate further includes: a first redistribution pattern penetrating the second dielectric layer and connected to the lower bump; The second bump portion is in direct contact with the second dielectric layer.

15. A semiconductor package, comprising: a first redistribution substrate; a first semiconductor device, the first semiconductor device being located on the first redistribution substrate; and a molding layer, the molding layer covering the first semiconductor device and the first redistribution substrate, Wherein, the first redistribution substrate comprises: a first dielectric layer comprising a first aperture; a lower bump, the lower bump comprising a first bump portion located in the first hole and a second bump portion protruding from the first bump portion onto the first dielectric layer; an external connection terminal located on the bottom surface of the first dielectric layer and connected to the lower bump through the first hole; a wetting layer, the wetting layer being located between the external connection terminal and the lower bump; a first barrier / seed layer located between the underbump and the first dielectric layer and between the underbump and the wetting layer; a second dielectric layer covering the lower bump and the first dielectric layer and covering the second bump portion of the lower bump; a first redistribution pattern penetrating the second dielectric layer and connected to the lower bump; a metal oxide layer between the second bump portion and the second dielectric layer; and a gap region, the gap region being located between the second bump portion and the metal oxide layer, Wherein, the external connection terminals include: a first terminal portion located in the first hole; and a second terminal portion protruding outwardly from the bottom surface of the first dielectric layer, wherein the side wall of the first terminal portion forms a first angle with the top surface of the second terminal portion, Wherein, the first angle is in the range of 45° to 90°.

16. The semiconductor package according to claim 15, wherein The sidewall of the first bump portion forms a second angle with the bottom surface of the second bump portion, The second angle is in the range of 90° to 135°.

17. The semiconductor package according to claim 15, wherein Sidewalls of the external connection terminal, the wetting layer, and the first barrier / seed layer are aligned with each other.

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