Semiconductor device and method for forming the same

Abstract

The present invention provides a semiconductor device and a method for forming the same. The method comprises: providing a substrate, forming a dielectric layer on the substrate; etching the dielectric layer, forming a contact hole in the dielectric layer, and exposing the surface of the substrate; forming a metal silicide layer and a barrier layer on the surface of the substrate exposed at the bottom of the contact hole, wherein the barrier layer covers the surface of the metal silicide layer; forming a plug layer located on the surface of the barrier layer, wherein the plug layer fills the contact hole; and separating the metal silicide layer from the plug layer by using the barrier layer to avoid damage to the plug layer caused by the reaction between the metal silicide layer and diffused ions in the plug layer, thereby improving the quality of the formed plug layer, and improving both the electrical performance and the use performance of the formed semiconductor device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. As the most basic semiconductor device, the device is currently being widely used. The control ability of traditional planar devices on channel current has weakened, resulting in short channel effect and leakage current, which ultimately affects the electrical performance of semiconductor devices.

[0003] In the process of manufacturing semiconductor devices, current conduction is usually achieved through metal connection structures, thereby achieving specific functions of semiconductor devices. Generally, metal plugs are connected between different semiconductor devices, respectively connected to the gate and the source and drain regions. However, the formation quality of the metal plugs is currently poor, resulting in poor electrical performance of the formed semiconductor devices.

[0004] How to form high-quality metal plugs to ensure that the formed semiconductor devices have good performance is a problem that urgently needs to be solved. Summary of the invention

[0005] The problem solved by the present invention is to provide a semiconductor device and a method for forming the same, so that the formed metal plug has good forming quality and ensures that the formed semiconductor device has good performance and yield.

[0006] To solve the above problems, the present invention provides a semiconductor device, comprising: a substrate; a dielectric layer located on the substrate; a contact hole located in the dielectric layer, with the bottom exposing the surface of the substrate; a metal silicide layer located on the surface of the substrate at the bottom of the contact hole; a barrier layer located on the surface of the metal silicide layer; and a plug layer located on the barrier layer and filling the contact hole.

[0007] Optionally, the method further includes: an adhesion layer, wherein the adhesion layer is located between the barrier layer and the plug layer.

[0008] Optionally, the thickness of the adhesion layer is to

[0009] Optionally, the material of the barrier layer is titanium-silicon alloy or cobalt-titanium alloy.

[0010] Correspondingly, the present invention also provides a method for forming a semiconductor device, comprising: providing a substrate, forming a dielectric layer on the substrate; etching the dielectric layer, forming a contact hole in the dielectric layer, and exposing the surface of the substrate; forming a metal silicide layer and a barrier layer on the surface of the substrate exposed at the bottom of the contact hole, wherein the barrier layer covers the surface of the metal silicide layer; and forming a plug layer located on the surface of the barrier layer, wherein the plug layer fills the contact hole.

[0011] Optionally, the steps of forming the metal silicide layer and the barrier layer include: forming a metal layer on the surface of the substrate exposed at the bottom of the contact hole; forming a reaction layer on the metal layer; and after forming the plug layer on the reaction layer, performing annealing to form the metal silicide layer on the surface of the substrate and the barrier layer covering the metal silicide layer.

[0012] Optionally, the material of the reaction layer is silane, silicon or cobalt.

[0013] Optionally, when the material of the reaction layer is silane, the process parameters for forming the reaction layer include: using silane gas, the gas flow rate of the silane gas is 100 sccm to 3000 sccm, the reaction temperature is 200° C. to 500° C., and the reaction pressure is 5 torr to 50 torr.

[0014] Optionally, when the material of the reaction layer is silicon or cobalt, the process of forming the reaction layer is a chemical vapor deposition process, an atomic layer deposition process or a physical vapor deposition process.

[0015] Optionally, before forming the plug layer, the method further includes: forming an adhesion layer on the barrier layer and on the sidewalls of the contact hole.

[0016] Optionally, the step of forming the plug layer includes: forming a plug seed layer on the adhesion layer, forming an initial plug layer on the plug seed layer, planarizing the initial plug layer, the plug seed layer and the adhesion layer until the surface of the dielectric layer is exposed, and forming the plug layer in the contact hole.

[0017] Optionally, the thickness of the adhesion layer is to

[0018] Optionally, the thickness of the plug seed layer is less than

[0019] Optionally, after forming the adhesion layer and before forming the plug layer, the substrate is heat treated to form the metal silicide layer on the surface of the substrate.

[0020] Optionally, specific process parameters of the annealing treatment include: the gas used includes nitrogen, the gas flow rate of the nitrogen is 500 sccm to 3000 sccm, and the temperature is 600° C. to 1200° C.

[0021] Optionally, the material of the plug layer includes tungsten.

[0022] Optionally, the material of the metal layer includes titanium.

[0023] Optionally, the material of the barrier layer is titanium-silicon alloy or cobalt-titanium alloy.

[0024] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0025] In the formation method of the present invention, a barrier layer is formed on the metal silicide layer, the barrier layer covers the surface of the metal silicide layer, and a plug layer is formed on the barrier layer, the plug layer fills the contact hole; the barrier layer is used to separate the metal silicide layer from the plug layer, so as to avoid the damage to the plug layer caused by the reaction between the metal silicide layer and the diffused ions in the plug layer, thereby improving the quality of the formed plug layer, so that the electrical performance and use performance of the formed semiconductor device are improved.

[0026] Furthermore, the steps of forming the metal silicide layer and the barrier layer include: forming a metal layer on the surface of the substrate exposed by the contact hole, forming a reaction layer on the metal layer, forming a plug layer on the reaction layer, and performing an annealing treatment after forming the plug layer, thereby ensuring the formation of a high-quality plug layer, so that the electrical performance and performance of the formed semiconductor device are improved. This is because after the metal layer is formed on the surface of the substrate, the metal layer interacts with the substrate to form a metal silicide layer, and at this time there is still a residual metal layer, and the residual metal layer can continue to react with the reaction layer, thereby consuming the residual metal layer, so that the residual metal layer cannot react with the diffused ions in the plug layer, effectively preventing the damage to the plug layer caused by the reaction between the diffused ions and the residual metal layer, thereby improving the quality of the formed plug layer, and the electrical performance and performance of the corresponding semiconductor device are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figures 1 to 5 is a structural schematic diagram of a semiconductor device forming process in one embodiment;

[0028] Figures 6 to 10 It is a structural schematic diagram of a semiconductor device forming process in one embodiment of the present invention. DETAILED DESCRIPTION

[0029] At present, in the process of forming metal plugs using metal layers, the quality of the metal plugs is poor and cracks are easily generated, so that the formed metal plugs have poor quality, which affects the electrical performance and usability of semiconductor devices and limits the use of semiconductor devices. For the specific formation process, please refer to Figures 1 to 5 .

[0030] First reference Figure 1 , providing a substrate 100 , wherein the substrate 100 has a source-drain doped layer 101 , and a dielectric layer 102 located on the substrate 100 and the source-drain doped layer 101 .

[0031] Please refer to Figure 2 , etching the dielectric layer 102 to form a contact hole 103 in the dielectric layer 102 , wherein the bottom of the contact hole 103 exposes the top surface of the source-drain doped layer 101 .

[0032] Please refer to Figure 3 A titanium layer 104 ′ is formed on the top surface of the source / drain doped layer 101 exposed at the bottom of the contact hole 103 .

[0033] Please refer to Figure 4 An adhesion layer 106 is formed on the titanium layer 104 ′ and on the sidewalls of the contact hole 103 .

[0034] After the adhesion layer 106 is formed, an annealing process is performed, and the titanium layer 104 ′ reacts with the substrate 100 and the source-drain doping layer 101 to form a metal silicide layer 105 on the surface of the source-drain doping layer 101 , and there is residual titanium layer 104 .

[0035] Please refer to Figure 5 , a plug layer 107 is formed on the adhesion layer 106 .

[0036] The inventors have found that the semiconductor device formed by this method has poor stability in performance and is prone to failure, which limits the use of the semiconductor device. This is because after the titanium layer 104' is formed on the top surface of the source-drain doping layer 101, the titanium layer 104' reacts with the substrate to form the metal silicide layer 105, and there is still a residual titanium layer 104. After the plug layer 107 is formed, the diffused ions such as F ions in the plug layer 107 can react violently with the residual titanium layer 104, thereby causing the plug layer 107 to explode (i.e., the part pointed by the arrow in the figure), so that the plug layer 107 has poor quality, and the electrical performance and performance of the corresponding semiconductor device are reduced.

[0037] The inventors have found that a barrier layer is formed on the metal silicide layer, the barrier layer covers the surface of the metal silicide layer, a plug layer is formed on the barrier layer, and the plug layer fills the contact hole; the barrier layer is used to separate the metal silicide layer from the plug layer, so as to avoid the metal silicide layer and the diffused ions in the plug layer reacting to damage the plug layer, thereby improving the quality of the formed plug layer, so that the electrical performance and use performance of the formed semiconductor device are improved.

[0038] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figures 6 to 10 It is a structural schematic diagram of a semiconductor device forming process in one embodiment of the present invention.

[0040] First reference Figure 6 , a dielectric layer 203 is formed on the bottom of the substrate 200.

[0041] In this embodiment, the base 200 includes a substrate 201 and a source-drain doped layer 202 located in the substrate 201 .

[0042] In this embodiment, the material of the substrate 201 is silicon; in other embodiments, the material of the substrate 201 may also be semiconductor materials such as polycrystalline silicon, amorphous silicon, germanium, silicon germanium, gallium arsenide, silicon on insulator (SOI), germanium on insulator (GOI), or multi-element semiconductor materials composed of group III-V elements, including: InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0043] In this embodiment, devices such as fins and gate structures may also be formed on the substrate 201 , which are not shown in the figure.

[0044] In this embodiment, the steps of forming the source-drain doped layer 202 include: etching the substrate 201, forming source-drain grooves (not shown in the figure) in the substrate 201, epitaxially growing the material of the source-drain doped layer in the source-drain grooves, and in-situ doping the material of the source-drain doped layer with source and drain ions, thereby forming the source-drain doped layer 202.

[0045] In this embodiment, when the semiconductor device is a P-type device, the material of the source-drain doping layer 202 includes: silicon, germanium or silicon germanium; the source-drain ions are P-type ions, and the source-drain ions include boron ions, BF 2- ions or indium ions;

[0046] When the semiconductor structure is an N-type device, the material of the source-drain doping layer 202 includes: silicon, gallium arsenide or indium gallium arsenic; the source-drain ions are N-type ions, and the source-drain ions include phosphorus ions or arsenic ions.

[0047] In this embodiment, the material of the dielectric layer 203 is silicon carbide; in other embodiments, the material of the dielectric layer 203 may also be insulating materials such as silicon nitride, silicon oxide or silicon oxycarbide.

[0048] In this embodiment, the step of forming the dielectric layer 203 includes: forming an initial dielectric layer on the surfaces of the substrate 201 and the source-drain doped layer 202 , and planarizing the initial dielectric layer to make the surface of the initial dielectric layer flush, thereby forming the dielectric layer 203 .

[0049] In this embodiment, the process for forming the dielectric layer 203 is a chemical vapor deposition process; in other embodiments, one or a combination of atomic layer deposition process, physical vapor deposition process or chemical vapor deposition process may also be used.

[0050] In this embodiment, the process parameters for forming the dielectric layer 203 include: the gases used include hydrogen, HCl gas, SiH2Cl2 and PH3, the flow rate of hydrogen is 2000sccm~20000sccm, the flow rate of HCl gas is 30sccm~150sccm, the flow rate of SiH2Cl2 is 50sccm~1000sccm, the flow rate of PH3 is 10sccm~2000sccm, the chamber pressure is 10torr~600torr, and the temperature is 650 degrees Celsius~850 degrees Celsius.

[0051] Please refer to Figure 7 , etching the dielectric layer 203, forming a contact hole 204 in the dielectric layer 203, and exposing the surface of the substrate 200.

[0052] In this embodiment, the bottom of the contact hole 204 exposes the top surface of the source-drain doped layer 202 .

[0053] In this embodiment, the step of forming the contact hole 204 includes: forming a patterned layer (not shown in the figure) on the dielectric layer 203, the patterned layer having an opening, the opening being aligned with the position of the source-drain doped layer 201, and using the patterned layer as a mask to etch the dielectric layer 203 until the top surface of the source-drain doped layer 202 is exposed.

[0054] In this embodiment, the process of etching the dielectric layer 203 is a dry etching process; in other embodiments, a wet etching process or a process combining a wet etching process and a dry etching process may also be used.

[0055] In this embodiment, the reason why the dry etching process is used to etch the dielectric layer 203 to form the contact hole 204 is that the etching rate of the dry etching in the longitudinal direction is greater than the etching rate in the lateral direction. In this way, the contact hole 204 with good surface quality can be formed in the longitudinal direction without causing damage to other devices in the lateral direction.

[0056] In this embodiment, the specific parameters of the dry etching process include: the gases used include CF4 gas, CH3F gas and O2, the flow rate of CF4 gas is 5sccm~100sccm, the flow rate of CH3F gas is 8sccm~50sccm, the flow rate of O2 is 10sccm~100sccm, the chamber pressure is 10mtorr~2000mtorr, the RF power is 50W~300W, the bias voltage is 30V~100V, and the time is 4 seconds~50 seconds.

[0057] A metal silicide layer and a barrier layer are formed on the surface of the substrate exposed at the bottom of the contact hole, wherein the barrier layer covers the surface of the metal silicide layer. The formation process of the metal silicide layer and the barrier layer can be referred to Figures 8 to 10 .

[0058] Please refer to Figure 8 A metal layer is formed on the surface of the substrate 200 exposed at the bottom of the contact hole 204 , a reaction layer 207 is formed on the metal layer, and an adhesion layer 208 is formed on the reaction layer 207 and on the sidewalls of the contact hole 204 .

[0059] In this embodiment, the purpose of forming the metal layer is to provide a metal source for forming the metal silicide layer.

[0060] In this embodiment, after forming the adhesion layer 208 and before forming the plug layer, the substrate is further heat treated to form a metal silicide layer 205 on the surface of the substrate, that is, on the top surface of the source-drain doping layer 202 .

[0061] In other embodiments, after forming the plug layer, a metal silicide layer 205 may be formed on the top surface of the source / drain doping layer 202 during the annealing process.

[0062] In this embodiment, due to the interaction between the metal layer and the substrate, the metal silicide layer 205 is formed on the exposed top surface of the source-drain doped layer 202 .

[0063] In this embodiment, the step of forming the metal silicide layer 205 includes: forming a metal layer (marked in the figure) on the top surface of the source-drain doping layer 202, and performing rapid thermal annealing (RTA) on the substrate after the metal layer is formed, so as to form the metal silicide layer 205.

[0064] Since the metal layer is not completely consumed during the process of forming the metal silicide layer 205 , a residual metal layer 206 exists.

[0065] In this embodiment, the material of the metal layer includes titanium (Ti); in other embodiments, it may also be cobalt, NiPt, etc.

[0066] The reason why titanium (Ti) is preferred as the material of the metal layer is that titanium as a metal layer can be suitable for the manufacture of semiconductor devices with smaller nodes or smaller feature sizes, and the diffusion direction of titanium in semiconductor devices is deterministic and controllable; while cobalt and NiPt are not suitable for the manufacture of semiconductor devices with small nodes or small feature sizes, and the diffusion of cobalt and NiPt is uncertain and thus difficult to control.

[0067] In this embodiment, the material of the metal layer is single element titanium, that is, the material of the remaining metal layer 206 is titanium.

[0068] In this embodiment, the reaction layer 207 is formed on the remaining metal layer 206 .

[0069] In this embodiment, the material of the reaction layer 207 is silane, silicon or cobalt.

[0070] When the material of the reaction layer 207 is silane (SiH4), the formation process parameters of the reaction layer 207 include: using silane gas, the gas flow rate of the silane gas is 100sccm~3000sccm, the reaction temperature is 200℃~500℃, and the reaction pressure is 5Torr~50Torr.

[0071] In the present embodiment, the silane (SiH4) will be cracked at high temperature to form elemental silicon. In the subsequent annealing process, the formed elemental silicon can chemically react with the residual metal layer 206, thereby consuming the residual metal layer 206. In this way, there is no process of the residual metal layer 206 reacting with the diffused ions (such as F ions) in the subsequently formed plug layer, thereby avoiding damage to the formed plug layer due to the violent reaction between the residual metal layer 206 and the diffused ions, and improving the quality of the subsequently formed plug layer.

[0072] When the material of the reaction layer 207 is silicon or cobalt, the process of forming the reaction layer is a chemical vapor deposition process, an atomic layer deposition process or a physical vapor deposition process.

[0073] When the material of the reaction layer 207 is silicon or cobalt, the preferred formation process is a physical vapor deposition process, and the specific parameters include: using silicon or cobalt as a target material, the reaction gas is argon (Ar), the flow rate of the reaction gas is 50sccm~500sccm, the source RF power is 100W~500W, the bias power is 500W~5000W, and the pressure is 10mTorr~100mTorr.

[0074] In this embodiment, the reason why the reaction layer 207 is formed by physical vapor deposition is that the reaction layer 207 formed by physical vapor deposition is less formed on the dielectric layer 203 and the contact hole 204, and no additional process is required to remove the excess reaction layer 207, which simplifies the process and can reduce damage to the device.

[0075] In this embodiment, in the subsequent annealing process, the deposited silicon can chemically react with the residual metal layer 206 to form a titanium-silicon alloy, thereby consuming the residual metal layer 206, avoiding damage to the formed plug layer due to the violent reaction between the residual metal layer 206 and the diffused ions, and improving the quality of the subsequently formed plug layer.

[0076] In this embodiment, in the subsequent annealing treatment, the deposited cobalt and the residual metal layer 206 are used to form a cobalt-titanium alloy. The cobalt-titanium alloy has a very high density and can isolate the residual metal layer 206 from the diffused ions, preventing the residual metal layer 206 from contacting the diffused ions. This avoids the violent reaction between the residual metal layer 206 and the diffused ions, does not damage the formed plug layer, and can improve the quality of the subsequently formed plug layer.

[0077] In this embodiment, the material of the adhesion layer 208 is titanium nitride (TiN); in other embodiments, the material of the adhesion layer 208 may also be TaN or the like.

[0078] In this embodiment, the adhesion layer 208 has three functions: first, it can serve as a transition layer to provide a better formation interface for the subsequently formed plug layer, thereby improving the quality of the plug layer finally formed; second, it can block the diffusion of ions in the plug layer; and third, it can prevent the metal atoms of the plug layer from diffusing into the dielectric layer.

[0079] In this embodiment, since the reaction layer 207 is formed before the adhesion layer 208 is formed, the reaction layer 207 can consume the residual metal layer 206 or isolate the residual metal layer 206 from the diffused ions in the subsequently formed plug layer, so that the residual metal layer 206 does not react with the diffused ions, which plays a role in blocking the diffused ions in the plug layer. At this time, the thickness of the adhesion layer 208 can be correspondingly thinned, thereby reducing the Rs value and the Rc value of the formed semiconductor device, and improving the electrical performance of the formed semiconductor device.

[0080] In this embodiment, the thickness of the adhesion layer 208 is to When the thickness of the adhesion layer 208 is less than At this time, the thickness of the adhesion layer 208 formed is too thin, and it cannot play a transition role in the process of forming the plug layer, so that the formed plug layer cannot be fully adhered to the surface of the contact hole 204, and there is a gap, resulting in poor quality of the formed plug layer. At the same time, it cannot prevent the metal atoms of the plug layer from diffusing into the dielectric layer, affecting the quality of the semiconductor device finally formed. When the thickness of the adhesion layer 208 is greater than When the thickness of the adhesion layer 208 formed at this time is too thick, although it can play a good transition role and can provide a better interface for the subsequently formed plug layer and block the metal atoms of the plug layer from diffusing into the dielectric layer, the thickness of the adhesion layer 208 formed at this time is too thick, which increases the Rs value and Rc value corresponding to the formed semiconductor device, thereby reducing the electrical performance of the formed semiconductor device.

[0081] Please refer to Fig. 9 , a plug layer 210 is formed on the adhesion layer 208 , and the plug layer 210 fills the contact hole 204 .

[0082] The step of forming the plug layer 210 includes: forming a plug seed layer 209 on the adhesion layer 208, forming an initial plug layer on the plug seed layer 209, planarizing the initial plug layer, the plug seed layer 209 and the adhesion layer 208 until the surface of the dielectric layer 203 is exposed, and forming the plug layer 210 in the contact hole 204.

[0083] In actual process, after the initial plug layer is formed, the plug seed layer 209 is integrated with the initial plug layer and cannot be seen. Fig. 9 In order to clearly show the formation process of the plug layer 210 , the plug seed layer 209 is marked.

[0084] In this embodiment, the thickness of the plug seed layer 209 is less than Due to the existence of the reaction layer 207, the thickness of the plug seed layer 209 can be reduced. This is because the reaction layer 207 has blocked the damage to the plug layer 210 caused by the reaction between the diffused ions in the plug layer 210 and the residual metal layer 206. The plug seed layer 209 also has the function of blocking the diffused ions in the plug layer 210. Because the diffused ions have been blocked before the plug seed layer 209 is formed, the thickness of the plug seed layer 209 can be relatively thinned, thereby providing space for the formed plug layer 210, increasing the volume of the formed plug layer 210, and helping to reduce the values ​​of Rs and Rc. The electrical performance of the semiconductor device is improved.

[0085] In this embodiment, the process for forming the initial plug layer is a chemical vapor deposition process; in other embodiments, one or a combination of a selective growth process, a physical vapor deposition process, an atomic layer deposition process or a chemical vapor deposition process may also be used.

[0086] The plug seed layer 209 is made of the same material as the plug layer 210 .

[0087] In this embodiment, the material of the plug layer 210 includes tungsten.

[0088] In this embodiment, the process parameters for forming the plug layer 210 include: the reaction gas includes WF6 gas and H2, wherein the gas flow rate of the WF6 gas is 50-1000 sccm, and the gas flow rate of the H2 is 500-20000 sccm; the reaction temperature is 100-400° C.; and the chamber pressure is 2-100 Torr.

[0089] Since WF6 gas is used in the process of forming the plug layer 210 , the formed plug layer 210 contains diffused ions, such as F ions.

[0090] In this embodiment, since the thicknesses of the adhesion layer 208 and the plug seed layer 209 are both reduced, the volume of the plug layer 210 is increased, thereby reducing the contact resistance and improving the electrical performance of the formed semiconductor device.

[0091] Please refer to Fig.10 After forming the plug layer 210, an annealing process is performed.

[0092] In this embodiment, arrows indicate annealing treatment.

[0093] In this embodiment, specific process parameters of the annealing treatment include: the gas used includes nitrogen, the gas flow rate of the nitrogen is 500 sccm to 3000 sccm, and the temperature is 600° C. to 1200° C.

[0094] In the present embodiment, during the annealing process, when the material of the reaction layer 207 is silane (SiH4), the silane (SiH4) will be cracked at a high temperature to form elemental silicon, and the formed elemental silicon can chemically react with the residual metal layer 206, thereby consuming the residual metal layer 206. In this way, there is no process of the residual metal layer 206 reacting with the diffused ions (such as F ions) in the plug layer 210, thereby avoiding damage to the plug layer 210 due to the violent reaction between the residual metal layer 206 and the diffused ions, and improving the quality of the subsequently formed plug layer 210, thereby correspondingly improving the performance of the formed semiconductor device.

[0095] In this embodiment, during the annealing process, when the material of the reaction layer 207 is silicon, the elemental silicon can also react chemically with the residual metal layer 206, thereby consuming the residual metal layer 206. In this way, there is no process in which the residual metal layer 206 reacts with the diffused ions (such as F ions) in the plug layer 210, thereby avoiding damage to the plug layer 210 due to the violent reaction between the residual metal layer 206 and the diffused ions.

[0096] In this embodiment, when the material of the reaction layer 207 is cobalt, cobalt can form a cobalt-titanium alloy with the residual metal layer 206. The cobalt-titanium alloy has a very high density and can isolate the residual metal layer 206 from the diffused ions in the plug layer 210, preventing the residual metal layer 206 from contacting the diffused ions. This avoids the violent reaction between the residual metal layer 206 and the diffused ions, and does not cause damage to the formed plug layer 210, thereby improving the quality of the subsequently formed plug layer.

[0097] In this embodiment, after annealing, the barrier layer 211 covering the metal silicide layer 205 is formed, and the barrier layer 211 is located between the metal silicide layer 205 and the adhesion layer 208 .

[0098] The barrier layer 211 is a reaction product of the remaining metal layer 206 and the reaction layer 207 .

[0099] The material of the barrier layer 211 is titanium-silicon alloy or cobalt-titanium alloy.

[0100] Correspondingly, the present invention also provides a semiconductor device, comprising: a substrate 200; a dielectric layer 203, located on the substrate 200; a contact hole 204, located in the dielectric layer 203, with the bottom exposing the surface of the substrate 200; a metal silicide layer 205, located on the surface of the substrate 200 at the bottom of the contact hole 204; a barrier layer 211, located on the surface of the metal silicide layer 205; and a plug layer 210, located on the barrier layer 211 and filling the contact hole 204.

[0101] In this embodiment, the blocking layer 211 is used to isolate the plug layer 210 from the surface of the metal silicide layer 205, and to block the diffused ions in the plug layer 210, thereby preventing the plug layer 210 from being damaged due to the mutual reaction between the diffusion ions and other media, thereby improving the quality of the formed plug layer 210, and correspondingly improving the electrical performance and quality of the formed semiconductor device.

[0102] Optionally, the method further includes: an adhesion layer 208 , wherein the adhesion layer 208 is located between the barrier layer 211 and the plug layer 210 .

[0103] In this embodiment, the adhesion layer 208 has three functions: first, it can serve as a transition layer to provide a better formation interface for the subsequently formed plug layer, thereby improving the quality of the plug layer finally formed; second, it can block the diffusion of ions in the plug layer; and third, it can prevent the metal atoms of the plug layer from diffusing into the dielectric layer.

[0104] The thickness of the adhesion layer 208 is to

[0105] In this embodiment, the thickness of the adhesion layer 208 is to When the thickness of the adhesion layer 208 is less than At this time, the thickness of the adhesion layer 208 formed is too thin, and it cannot play a transition role in the process of forming the plug layer, so that the formed plug layer cannot be fully adhered to the surface of the contact hole 204, and there is a gap, resulting in poor quality of the formed plug layer. At the same time, it cannot prevent the metal atoms of the plug layer from diffusing into the dielectric layer, affecting the quality of the semiconductor device finally formed. When the thickness of the adhesion layer 208 is greater than When the thickness of the adhesion layer 208 formed at this time is too thick, although it can play a good transition role and can provide a better interface for the subsequently formed plug layer and block the metal atoms of the plug layer from diffusing into the dielectric layer, the thickness of the adhesion layer 208 formed at this time is too thick, which increases the Rs value and Rc value corresponding to the formed semiconductor device, thereby reducing the electrical performance of the formed semiconductor device.

[0106] The material of the barrier layer 211 is titanium-silicon alloy or cobalt-titanium alloy.

[0107] In this embodiment, after annealing, a barrier layer 211 is formed between the metal silicide layer 205 and the adhesion layer 208 .

[0108] The barrier layer 211 is a reaction product of the remaining metal layer 206 and the reaction layer 207 .

[0109] The material of the reaction layer 207 is silane, silicon or cobalt, the material of the residual metal layer 206 is titanium, and the material of the barrier layer 211 is titanium-silicon alloy or cobalt-titanium alloy.

[0110] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate, the substrate comprising a source-drain doped layer; A dielectric layer, located on the substrate; A contact hole, located in the dielectric layer, with the bottom exposing the surface of the source-drain doped layer; A metal silicide layer located on the surface of the source-drain doped layer at the bottom of the contact hole, wherein the metal silicide is formed by the interaction between the metal layer located on the surface of the substrate exposed at the bottom of the contact hole and the substrate; a barrier layer, located on the surface of the metal silicide layer, the barrier layer being a reaction product of a residual metal layer and a reaction layer located on the surface of the metal layer, the material of the reaction layer being silane, silicon or cobalt; the material of the barrier layer being a titanium-silicon alloy or a cobalt-titanium alloy; The plug layer is located on the barrier layer and completely fills the contact hole.

2. The semiconductor device according to claim 1, wherein Also includes: An adhesion layer is located between the barrier layer and the plug layer.

3. The semiconductor device according to claim 2, wherein: The thickness of the adhesion layer is 5Å to 15Å.

4. A method for forming a semiconductor device, characterized in that: include: Providing a substrate, and forming a dielectric layer on the substrate; Etching the dielectric layer to form a contact hole in the dielectric layer to expose the substrate surface; forming a metal silicide layer and a barrier layer on the surface of the substrate exposed at the bottom of the contact hole, wherein the barrier layer covers the surface of the metal silicide layer; forming a plug layer located on the surface of the barrier layer, wherein the plug layer completely fills the contact hole; The method for forming the metal silicide comprises: forming a metal layer on the surface of the substrate exposed at the bottom of the contact hole, wherein the metal layer interacts with the substrate to form the metal silicide; The method for forming the barrier layer includes: forming a reaction layer on the metal layer; the barrier layer is a reaction product of the residual metal layer and the reaction layer, and the material of the reaction layer is silane, silicon or cobalt; the material of the barrier layer is titanium-silicon alloy or cobalt-titanium alloy.

5. The forming method according to claim 4, characterized in that: The steps of forming the metal silicide layer and the barrier layer include: forming a metal layer on the surface of the substrate exposed at the bottom of the contact hole; forming a reaction layer on the metal layer; After the plug layer is formed on the reaction layer, an annealing process is performed to form the metal silicide layer and the barrier layer covering the metal silicide layer on the surface of the substrate.

6. The forming method according to claim 5, characterized in that: When the material of the reaction layer is silane, the process parameters for forming the reaction layer include: using silane gas, the gas flow rate of the silane gas is 100 sccm~3000 sccm, the reaction temperature is 200°C~500°C, and the reaction pressure is 5 Torr~50 Torr.

7. The forming method according to claim 5, characterized in that: When the material of the reaction layer is silicon or cobalt, the process of forming the reaction layer is a chemical vapor deposition process, an atomic layer deposition process or a physical vapor deposition process.

8. The forming method according to claim 5, characterized in that: Before forming the plug layer, the method further includes: forming an adhesion layer on the barrier layer and on the sidewalls of the contact hole.

9. The forming method according to claim 8, characterized in that: The step of forming the plug layer includes: forming a plug seed layer on the adhesion layer, forming an initial plug layer on the plug seed layer, planarizing the initial plug layer, the plug seed layer and the adhesion layer until the surface of the dielectric layer is exposed, and forming the plug layer in the contact hole.

10. The forming method according to claim 8, characterized in that: The thickness of the adhesion layer is 5Å to 15Å.

11. The forming method according to claim 9, characterized in that: The plug seed layer has a thickness of less than 15Å.

12. The forming method according to claim 8, characterized in that: After forming the adhesion layer and before forming the plug layer, the substrate is heat-treated to form the metal silicide layer on the surface of the substrate.

13. The forming method according to claim 5, characterized in that: The specific process parameters of the annealing treatment include: the gas used includes nitrogen, the gas flow rate of the nitrogen is 500 sccm to 3000 sccm, and the temperature is 600° C. to 1200° C.

14. The forming method according to claim 4, characterized in that: The material of the plug layer includes tungsten.

15. The forming method according to claim 5, characterized in that: The material of the metal layer includes titanium.

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