Doherty power amplifier integrated circuit, method of manufacturing the same, and apparatus

Abstract

The application discloses a Doherty power amplifier integrated circuit and a preparation method and device thereof, and relates to the technical field of communication.The Doherty power amplifier integrated circuit comprises a power divider, a main power amplifier, a peak power amplifier, a gate bias voltage regulator and a combiner; a first signal output end of the power divider is connected with a signal input end of the main power amplifier, and a signal output end of the main power amplifier is connected with a first signal input end of the combiner; a second signal output end of the power divider is connected with a signal input end of the peak power amplifier, and a signal output end of the peak power amplifier is connected with a second signal input end of the combiner; pinch-off voltage of the peak power amplifier is different from that of the main power amplifier, and an output end of the gate bias voltage regulator is connected with a gate of the main power amplifier and a gate of the peak power amplifier respectively.The Doherty power amplifier integrated circuit can simplify a power supply system.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to a Doherty power amplifier integrated circuit and a preparation method and device thereof. BACKGROUND

[0002] Doherty power amplifier is a kind of high power amplifier technology most widely used in wireless communication system at present, due to the requirement of miniaturization and high efficiency after rollback of microwave rotation, small base station, micro base station and other radio frequency applications, the integrated circuit of Doherty power amplifier has been widely concerned by the industry.

[0003] The traditional Doherty power amplifier includes a main power amplifier, a peak power amplifier and the like, and its basic idea is active load traction, specifically: the main power amplifier works in class B or class AB, and the peak power amplifier works in class C, and the two respectively bear different input signal power, so as to make the two power amplifiers work in their respective saturation regions as much as possible, so as to ensure that the whole power amplifier maintains high efficiency in the largest possible input signal power range, while ensuring a certain linearity. Therefore, the existing Doherty power amplifier needs to provide different gate voltages for the main power amplifier and the peak power amplifier, which makes the power supply system of the Doherty power amplifier complicated. SUMMARY

[0004] The purpose of the present application is to provide a Doherty power amplifier integrated circuit and a preparation method and device thereof, which can realize that only one gate bias voltage regulator is needed to make the main power amplifier work in class B or class AB and the peak power amplifier work in class C, so as to simplify the power supply system.

[0005] The embodiment of the present application is implemented as follows:

[0006] In one aspect of the present application, a Doherty power amplifier integrated circuit is provided, which comprises a power divider, a main power amplifier, a peak power amplifier, a gate bias voltage regulator and a combiner; a first signal output terminal of the power divider is connected to a signal input terminal of the main power amplifier, and a signal output terminal of the main power amplifier is connected to a first signal input terminal of the combiner; a second signal output terminal of the power divider is connected to a signal input terminal of the peak power amplifier, and a signal output terminal of the peak power amplifier is connected to a second signal input terminal of the combiner; wherein the pinch-off voltage of the peak power amplifier is different from the pinch-off voltage of the main power amplifier, and an output terminal of the gate bias voltage regulator is connected to the gate of the main power amplifier and the gate of the peak power amplifier respectively. The Doherty power amplifier integrated circuit can make the main power amplifier work in class B or class AB and the peak power amplifier work in class C only with one gate bias voltage regulator, thereby simplifying the power supply system.

[0007] Optionally, the pinch-off voltage of the peak power amplifier is greater than the pinch-off voltage of the main power amplifier.

[0008] Optionally, the main power amplifier and the peak power amplifier both use high electron mobility transistor devices for signal power amplification.

[0009] Optionally, the high electron mobility transistor device is a gallium nitride-based device.

[0010] Optionally, the main power amplifier is a class AB power amplifier, and the peak power amplifier is a class C power amplifier.

[0011] In another aspect of the present application, a communication device is provided, which comprises the above-mentioned Doherty power amplifier integrated circuit.

[0012] Another aspect of the present application provides a preparation method of a Doherty power amplifier integrated circuit, comprising: sequentially forming a buffer layer, a channel layer, a barrier layer and a passivation layer on a substrate to obtain a first device; forming an isolation region on the first device by an ion implantation process to obtain a first region and a second region which are isolated from each other; forming a source and a drain on the first region and the second region respectively, and the source and the drain are connected to the barrier layer through the passivation layer; forming a first gate slot exposing the barrier layer between the source and the drain of the first region; forming a second gate slot exposing the barrier layer between the source and the drain of the second region, and the thickness of the barrier layer exposed in the second region is less than the thickness of the barrier layer exposed in the first region; forming a gate in the first gate slot and the second gate slot respectively to obtain a main power amplifier in the first region and a peak power amplifier in the second region, and the pinch-off voltage of the peak power amplifier is different from the pinch-off voltage of the main power amplifier; connecting a first signal output end of a power divider to a signal input end of the main power amplifier, and connecting a signal output end of the main power amplifier to a first signal input end of a combiner; connecting a second signal output end of the power divider to a signal input end of the peak power amplifier, and connecting a signal output end of the peak power amplifier to a second signal input end of the combiner; and connecting an output end of a gate bias voltage regulator to the gate of the main power amplifier and the gate of the peak power amplifier respectively.

[0013] Optionally, forming the second gate slot exposing part of the barrier layer between the source and the drain of the second region comprises: etching the passivation layer between the source and the drain of the second region by a dry etching process to form a first sub-slot exposing the barrier layer; and etching the exposed barrier layer by a dry etching process using a chlorine-based gas to form a second sub-slot, the second sub-slot and the first sub-slot being communicated to form the second gate slot, and the depth of the second sub-slot is less than the thickness of the barrier layer.

[0014] Optionally, the thickness of the barrier layer is 22 nm, and the depth of the second sub-slot is 5 nm.

[0015] Optionally, forming the first gate slot exposing the barrier layer between the source and the drain of the first region comprises: etching the passivation layer between the source and the drain of the first region by a dry etching process to form the first gate slot exposing the barrier layer.

[0016] The present application has the following advantages:

[0017] The Doherty power amplifier integrated circuit provided by the application comprises a power divider, a main power amplifier, a peak power amplifier, a gate bias voltage regulator and a combiner; a first signal output end of the power divider is connected with a signal input end of the main power amplifier, and a signal output end of the main power amplifier is connected with a first signal input end of the combiner; a second signal output end of the power divider is connected with a signal input end of the peak power amplifier, and a signal output end of the peak power amplifier is connected with a second signal input end of the combiner; wherein, pinch-off voltage of the peak power amplifier is different from pinch-off voltage of the main power amplifier, and an output end of the gate bias voltage regulator is connected with a gate of the main power amplifier and a gate of the peak power amplifier respectively. By setting the pinch-off voltage of the peak power amplifier and the pinch-off voltage of the main power amplifier to be different, and by using one gate bias voltage regulator to regulate the gate voltage of the main power amplifier and the peak power amplifier, the main power amplifier can work in class B or class AB, and the peak power amplifier can work in class C. Since the application only has one gate bias voltage regulator (the main power amplifier and the peak power amplifier of the prior art are respectively provided with one gate bias voltage regulator), the complexity of the power supply system can be reduced, and the cost of the system can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the application, and therefore should not be regarded as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0019] Figure 1 The structural schematic diagram of the Doherty power amplifier integrated circuit provided by some embodiments of the application;

[0020] Figure 2 The flowchart of the preparation method of the Doherty power amplifier integrated circuit provided by some embodiments of the application;

[0021] Figure 3 The preparation process diagram of the Doherty power amplifier integrated circuit provided by some embodiments of the application;

[0022] Figure 4 The preparation process diagram of the Doherty power amplifier integrated circuit provided by some embodiments of the application;

[0023] Figure 5 The preparation process diagram of the Doherty power amplifier integrated circuit provided by some embodiments of the application;

[0024] Figure 6 Figure 4 is a process flow diagram of a Doherty power amplifier integrated circuit according to some embodiments of the present application;

[0025] Figure 7 Figure 5 is a process flow diagram of a Doherty power amplifier integrated circuit according to some embodiments of the present application;

[0026] Figure 8 Figure 6 is a process flow diagram of a Doherty power amplifier integrated circuit according to some embodiments of the present application;

[0027] Figure 9 Figure 2 is a flow chart of a method of fabricating a Doherty power amplifier integrated circuit according to some embodiments of the present application.

[0028] Legend: 10 - power divider; 20 - main power amplifier; 30 - peak power amplifier; 40 - gate bias voltage regulator; 50 - combiner; 61 - substrate; 62 - buffer layer; 63 - channel layer; 64 - barrier layer; 65 - passivation layer; 70 - first device; 71 - first region; 72 - second region; 73 - isolation region; 74 - passive region; 81 - first gate trench; 82 - second gate trench; 91 - source; 92 - drain; 93 - gate; 94 - interconnect metal; 95 - inductor; 96 - resistor. DETAILED DESCRIPTION

[0029] The implementations set forth below represent the necessary information to enable those skilled in the art to practice the implementations and illustrate best modes of practicing them. Upon reading the following description of the implementations, one skilled in the art will understand how to implement the concepts described herein with appropriate hardware, software, and firmware. The concepts described herein can be implemented with computer-aided design, simulation, fabrication, testing, and so on. The foregoing description is not limiting and has been provided only as an aid to understanding the broader concepts that are encompassed by the present application.

[0030] It should be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] It will be understood that when an element (such as a layer, region, or substrate) is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0032] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" can be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0035] Reference will now be made to Figure 1The embodiment provides a Doherty power amplifier integrated circuit, which comprises a power divider 10, a main power amplifier 20, a peak power amplifier 30, a gate bias voltage regulator 40 and a combiner 50; a first signal output end of the power divider 10 is connected with a signal input end of the main power amplifier 20, and a signal output end of the main power amplifier 20 is connected with a first signal input end of the combiner 50; a second signal output end of the power divider 10 is connected with a signal input end of the peak power amplifier 30, and a signal output end of the peak power amplifier 30 is connected with a second signal input end of the combiner 50; wherein, pinch-off voltage of the peak power amplifier 30 is different from pinch-off voltage of the main power amplifier 20, and an output end of the gate bias voltage regulator 40 is connected with a gate 93 of the main power amplifier 20 and a gate 93 of the peak power amplifier 30 respectively. The Doherty power amplifier integrated circuit can make the main power amplifier 20 work in class B or class AB and the peak power amplifier 30 work in class C only by using one gate bias voltage regulator 40, so that the power supply system is simplified.

[0036] The power divider 10 is used for dividing an input signal into two signals, one of which is input to the main power amplifier 20 through the first signal output end of the power divider 10, and the other of which is output to the peak power amplifier 30 through the second signal output end of the power divider 10.

[0037] The main power amplifier 20 and the peak power amplifier 30 are respectively used for amplifying the signals input by the power divider 10. It should be noted that when power is input, the main power amplifier 20 starts to work to amplify the input signal, and the peak power amplifier 30 does not work when the input power is small, and starts to work only when the main power amplifier 20 approaches saturation. The specific architecture of the Doherty power amplifier integrated circuit is not limited in the application, and a person skilled in the art can select a suitable architecture according to specific needs. For example, a symmetric Doherty architecture can be used, or an asymmetric Doherty architecture can be used. Illustratively, when the symmetric Doherty architecture is used, the sizes of the main power amplifier 20 and the peak power amplifier 30 are the same; when the asymmetric Doherty architecture is used, the sizes of the main power amplifier 20 and the peak power amplifier 30 are different, for example, the size ratio of the main power amplifier 20 to the peak power amplifier 30 can be between 1:1.05 and 1:1.5.

[0038] The gate bias voltage regulator 40 is used to regulate the gate 93 voltage of the main power amplifier 20 and the peak power amplifier 30, so that the main power amplifier 20 is biased between AB class or B class, and the peak power amplifier 30 is biased in C class. Exemplarily, in the embodiment, the main power amplifier 20 is an AB class power amplifier, and the peak power amplifier 30 is a C class power amplifier. In this way, the main power amplifier 20 can be biased in AB class, and the peak power amplifier 30 can be biased in C class.

[0039] Further, in the embodiment, the main power amplifier 20 and the peak power amplifier 30 both use high electron mobility transistor devices for signal power amplification. Alternatively, the high electron mobility transistor device is a gallium nitride-based device.

[0040] The combiner 50 is used to combine the amplified signals output by the main power amplifier 20 and the peak power amplifier 30, and through impedance transformation, the load impedance of the Doherty power amplifier integrated circuit and the impedance after combination are matched. Since the specific structure and function of the combiner 50 are well known to those skilled in the art, the present application will not be described in detail.

[0041] In the embodiment, the pinch-off voltage of the peak power amplifier 30 and the pinch-off voltage of the main power amplifier 20 are different, so that, under the action of one gate bias voltage regulator 40 (i.e. using one gate bias voltage regulator 40 to regulate the gate 93 voltage of the peak power amplifier 30 and the main power amplifier 20), the main power amplifier 20 can work in B class or AB class, and the peak power amplifier 30 can work in C class, thereby simplifying the power supply system.

[0042] In summary, the Doherty power amplifier integrated circuit provided by the application comprises a power divider 10, a main power amplifier 20, a peak power amplifier 30, a gate bias voltage regulator 40, and a combiner 50; a first signal output end of the power divider 10 is connected with a signal input end of the main power amplifier 20, and a signal output end of the main power amplifier 20 is connected with a first signal input end of the combiner 50; a second signal output end of the power divider 10 is connected with a signal input end of the peak power amplifier 30, and a signal output end of the peak power amplifier 30 is connected with a second signal input end of the combiner 50; wherein, the pinch-off voltage of the peak power amplifier 30 is different from the pinch-off voltage of the main power amplifier 20, and an output end of the gate bias voltage regulator 40 is connected with a gate 93 of the main power amplifier 20 and a gate 93 of the peak power amplifier 30 respectively. By setting the pinch-off voltage of the peak power amplifier 30 to be different from the pinch-off voltage of the main power amplifier 20, and by using one gate bias voltage regulator 40 to regulate the gate 93 voltage of the main power amplifier 20 and the peak power amplifier 30, the main power amplifier 20 can work in class B or class AB, and the peak power amplifier 30 can work in class C. Since the application only has one gate bias voltage regulator 40 (the main power amplifier 20 and the peak power amplifier 30 of the prior art are respectively provided with one gate bias voltage regulator 40), the complexity of the power supply system can be reduced, and the cost of the system can be reduced.

[0043] Optionally, the pinch-off voltage of the peak power amplifier 30 is greater than the pinch-off voltage of the main power amplifier 20. The specific value of the pinch-off voltage of the peak power amplifier 30 and the specific value of the pinch-off voltage of the main power amplifier 20 are not limited in the application, and can be determined by the actual circuit application.

[0044] In another aspect of the application, a communication device is provided, which comprises the Doherty power amplifier integrated circuit described above. Since the specific structure of the Doherty power amplifier integrated circuit and its advantages have been described in detail in the foregoing, the application will not be repeated here.

[0045] In another aspect of the application, a preparation method of the Doherty power amplifier integrated circuit is provided, which is shown in Figure 2 The preparation method comprises the following steps:

[0046] S100, sequentially forming a buffer layer 62, a channel layer 63, a barrier layer 64, and a passivation layer 65 on a substrate 61 to obtain a first device 70, as shown in Figure 3 .

[0047] The material of the substrate 61 can be silicon carbide, the material of the buffer layer 62 and the channel layer 63 can be gallium nitride, and the material of the barrier layer 64 can be aluminum gallium nitride. Of course, the above materials are only examples given in the present application, and other suitable materials can be selected by those skilled in the art as needed in other embodiments.

[0048] S200, forming an isolation region 73 on the first device 70 by an ion implantation process to obtain a first region 71 and a second region 72 that are isolated from each other, as shown in Figure 4 .

[0049] The isolation region is provided to form two regions that are electrically isolated from each other, i.e., the first region 71 and the second region 72. Of course, in order to facilitate subsequent metal interconnection of the main power amplifier 20, the peak power amplifier 30, and the capacitor, inductor 95, resistor 96, etc. to form the required integrated circuit, a third region can also be formed in this step, which can be a passive region 74, so that the capacitor, inductor 95, and resistor 96, etc. can be formed on the passive region 74, as shown in Figure 8 .

[0050] S300, forming a source 91 and a drain 92 on the first region 71 and the second region 72, respectively, and the source 91 and the drain 92 are in contact with the barrier layer 64 through the passivation layer 65, as shown in Figure 4 .

[0051] The source 91 and the drain 92 of the first region 71 are arranged in a spaced manner, and the source 91 and the drain 92 of the second region 72 are also arranged in a spaced manner.

[0052] S400, forming a first gate slot 81 exposing the barrier layer 64 between the source 91 and the drain 92 of the first region 71, as shown in Figure 5 .

[0053] The first gate slot 81 is used to form a gate 93 in it subsequently.

[0054] Optionally, the above step S400, forming a first gate slot 81 exposing the barrier layer 64 between the source 91 and the drain 92 of the first region 71, specifically includes the following steps:

[0055] In the first region 71, the passivation layer 65 between the source 91 and the drain 92 is etched by a dry etching process to form a first gate slot 81 exposing the barrier layer 64.

[0056] The first gate slot 81 is located between the source 91 and the drain 92 of the first region 71, and the width of the first gate slot 81 is less than the distance between the source 91 and the drain 92 of the first region 71.

[0057] S500, forming the second gate slot 82 exposing the barrier layer 64 between the source 91 and the drain 92 in the second region 72, the thickness of the barrier layer 64 exposed in the second region 72 is less than the thickness of the barrier layer 64 exposed in the first region 71, as shown in Figure 6

[0058] In this way, the thickness of the barrier layer 64 in the second region 72 is thinned, and thus the concentration of the two-dimensional electron gas corresponding to the second region 72 is reduced, so that the pinch-off voltage of the device (i.e., the peak power amplifier 30) formed in the second region 72 is positively shifted, and thus the pinch-off voltages of the devices obtained in the first region 71 (i.e., the main power amplifier 20) and the second region 72 are different. Specifically, the pinch-off voltage of the peak power amplifier 30 is greater than the pinch-off voltage of the main power amplifier 20.

[0059] In addition, it should be noted that in the present embodiment, the difference in the specific process of forming the gate 93 recess (i.e., the first gate slot 81) in the first region 71 and forming the gate 93 recess (i.e., the second gate slot 82) in the second region 72 is mainly used to obtain different pinch-off voltages (i.e., to obtain different pinch-off voltages of the devices obtained in the first region 71 and the second region 72). Of course, the difference in the pinch-off voltage achieved by the gate 93 recess process is not the only limitation on the way to obtain different pinch-off voltages. In other embodiments, the difference in the pinch-off voltage of the devices obtained in the first region 71 and the second region 72 can also be achieved by fluorine ion implantation.

[0060] Please refer to Figure 9 Optionally, the above step S500, forming the second gate slot 82 exposing part of the barrier layer 64 between the source 91 and the drain 92 in the second region 72, specifically includes the following steps:

[0061] S510, in the second region 72, the passivation layer 65 between the source 91 and the drain 92 is etched by a dry etching process to form a first sub-slot exposing the barrier layer 64.

[0062] The first sub-slot is located between the source 91 and the drain 92 in the second region 72, and the width of the second sub-slot is less than the distance between the source 91 and the drain 92 in the second region 72.

[0063] S520, using a chlorine-based gas to etch the exposed barrier layer 64 by a dry etching process to form a second sub-slot, the second sub-slot and the first sub-slot form a second gate slot 82, and the second sub-slot has a groove depth less than the thickness of the barrier layer 64.

[0064] ​It should be noted that, in the present embodiment, the first region 71 only etches the passivation layer 65 when forming the first gate trench 81, and does not etch the barrier layer 64; the second region 72 not only etches the passivation layer 65 when forming the second gate trench 82, but also etches a part of the barrier layer 64 downwards (i.e. from the passivation layer 65 towards the substrate 61).

[0065] Optionally, the thickness of the barrier layer 64 is 22 nm, and the depth of the second sub-trench is 5 nm. In short, the second region 72 etches the barrier layer 64 downwards by 5 nm when forming the second gate trench 82. In this way, the pinch-off voltage of the device corresponding to the second region 72 has a typical value of -2.5 V, while the pinch-off voltage of the device corresponding to the first region 71 has a typical value of -3.0 V.

[0066] S600, forming a gate 93 in the first gate trench 81 and the second gate trench 82 respectively, so as to obtain the main power amplifier 20 in the first region 71 and the peak power amplifier 30 in the second region 72, the pinch-off voltage of the peak power amplifier 30 being different from that of the main power amplifier 20, as shown in Figure 7 .

[0067] The pinch-off voltage of the peak power amplifier 30 being different from that of the main power amplifier 20 is realized due to the difference between the forming processes of the first gate trench 81 and the second gate trench 82, the specific principle of which has been described in the foregoing, and will not be described herein.

[0068] S700, connecting the first signal output end of the power divider 10 with the signal input end of the main power amplifier 20, and connecting the signal output end of the main power amplifier 20 with the first signal input end of the combiner 50; connecting the second signal output end of the power divider 10 with the signal input end of the peak power amplifier 30, and connecting the signal output end of the peak power amplifier 30 with the second signal input end of the combiner 50; connecting the output end of the gate bias voltage regulator 40 with the gate 93 of the main power amplifier 20 and the gate 93 of the peak power amplifier 30 respectively, as shown in Figure 1 .

[0069] Among them, the specific functions of the power divider 10, the main power amplifier 20, the peak power amplifier 30, the gate bias voltage regulator 40 and the combiner 50 have been described in the structural part of the foregoing, and will not be repeated herein.

[0070] It should be noted that, if it is necessary to apply the Doherty power amplifier integrated circuit provided by the present application to the corresponding actual circuit, the main power amplifier 20 and the peak power amplifier 30 can be metal-interconnected with the corresponding components, for example, the main power amplifier 20 and the peak power amplifier 30 can be metal-interconnected with the capacitors, resistors 96, inductors 95, etc. Please refer to Figure 8As shown, the main power amplifier 20, the peak power amplifier 30 and the resistor 96, the inductor 95 can be interconnected by the interconnection metal 94 to obtain a corresponding circuit structure. Of course, it should be understood that, Figure 8 The connection relationship shown is only an example given in the present application, in other embodiments, other components can also be formed in the passive region 74 to obtain other forms of circuit structure, and the specific connection relationship can be determined by the actual needs of those skilled in the art, and the present application does not limit it.

[0071] The above is only an optional embodiment of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application shall be included in the protection scope of the present application.

[0072] In addition, it should be noted that various specific technical features described in the above specific embodiments can be combined in any appropriate manner without contradiction. In order to avoid unnecessary repetition, various possible combinations are not described again in the present application.

Claims

1. A Doherty power amplifier integrated circuit, characterized in that, It includes a power divider, a main power amplifier, a peak power amplifier, a gate bias voltage regulator, and a combiner; the first signal output terminal of the power divider is connected to the signal input terminal of the main power amplifier, and the signal output terminal of the main power amplifier is connected to the first signal input terminal of the combiner; the second signal output terminal of the power divider is connected to the signal input terminal of the peak power amplifier, and the signal output terminal of the peak power amplifier is connected to the second signal input terminal of the combiner. Wherein, the pinch-off voltage of the peak power amplifier is greater than the pinch-off voltage of the main power amplifier, and the output terminal of the gate bias voltage regulator is connected to the gate of the main power amplifier and the gate of the peak power amplifier respectively. The gate bias voltage regulator is used to adjust the gate voltage of the main power amplifier and the peak power amplifier so that the main power amplifier is biased in a state between class AB and class B, and the peak power amplifier is biased in class C. The Doherty power amplifier integrated circuit includes: a buffer layer, a channel layer, and a barrier layer sequentially formed on a substrate layer; The buffer layer, the channel layer, and the barrier layer form a first region and a second region that are isolated from each other. The main power amplifier is located in the first region, and the peak power amplifier is located in the second region.

2. The Doherty power amplifier integrated circuit according to claim 1, characterized in that, Both the main power amplifier and the peak power amplifier use high electron mobility transistor devices for signal power amplification.

3. The Doherty power amplifier integrated circuit according to claim 2, characterized in that, The high electron mobility transistor device is a gallium nitride-based device.

4. The Doherty power amplifier integrated circuit according to claim 1, characterized in that, The main power amplifier is a Class AB power amplifier, and the peak power amplifier is a Class C power amplifier.

5. A communication device, characterized in that, Includes the Doherty power amplifier integrated circuit as described in any one of claims 1 to 4.

6. A method for fabricating a Doherty power amplifier integrated circuit, characterized in that, include: A buffer layer, a channel layer, a barrier layer, and a passivation layer are sequentially formed on a substrate to obtain a first device; An isolation region is formed on the first device by ion implantation to obtain a first region and a second region that are isolated from each other. A source and a drain are formed in the first region and the second region, respectively, and the source and the drain are respectively connected to the barrier layer through the passivation layer. A first gate trench is formed between the source and drain of the first region to expose the barrier layer; A second gate trench is formed between the source and drain of the second region to expose the barrier layer, and the thickness of the barrier layer exposed in the second region is less than the thickness of the barrier layer exposed in the first region. Gates are formed in the first gate trench and the second gate trench respectively to obtain a main power amplifier in the first region and a peak power amplifier in the second region, wherein the pinch-off voltage of the peak power amplifier is different from that of the main power amplifier. Connect the first signal output terminal of the power divider to the signal input terminal of the main power amplifier, and connect the signal output terminal of the main power amplifier to the first signal input terminal of the combiner; connect the second signal output terminal of the power divider to the signal input terminal of the peak power amplifier, and connect the signal output terminal of the peak power amplifier to the second signal input terminal of the combiner; connect the output terminal of the gate bias voltage regulator to the gate of the main power amplifier and the gate of the peak power amplifier, respectively.

7. The method for fabricating the Doherty power amplifier integrated circuit according to claim 6, characterized in that, A second gate trench is formed between the source and drain of the second region, exposing a portion of the barrier layer, including: In the second region, the passivation layer between the source and the drain is etched using a dry etching process to form a first sub-groove exposing the barrier layer; The exposed barrier layer is etched using a chlorine-based gas through a dry etching process to form a second sub-groove. The second sub-groove and the first sub-groove are connected to form a second gate trench. The depth of the second sub-groove is less than the thickness of the barrier layer.

8. The method for fabricating the Doherty power amplifier integrated circuit according to claim 7, characterized in that, The barrier layer has a thickness of 22 nm, and the second sub-groove has a groove depth of 5 nm.

9. The method for fabricating the Doherty power amplifier integrated circuit according to claim 6, characterized in that, A first gate trench exposing the barrier layer is formed between the source and drain of the first region, including: In the first region, the passivation layer between the source and the drain is etched using a dry etching process to form a first gate trench exposing the barrier layer.

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