Clock frequency conversion system, method, processor, chip and electronic device

Abstract

Embodiments of the present application provide a clock frequency conversion system, method, processor, chip and electronic device, wherein the system comprises: a clock generation circuit, a delay phase-locked loop circuit and a clock selection circuit; the clock generation circuit is configured to generate a source clock signal; the delay phase-locked loop circuit is configured to perform delay processing for multiple iterations based on the source clock signal to obtain multiple delay clock signals with different phases; wherein the last delay clock signal is aligned with the source clock signal, and the phase difference between adjacent delay clock signals is uniformly changed; the source clock signal and part of the delay clock signals form multiple candidate clock signals input to the clock selection circuit; and the clock selection circuit is configured to select a signal edge from the multiple candidate clock signals, and a target clock signal after frequency conversion is formed by the selected signal edge. The embodiments of the present application can improve the frequency change speed of the clock signal and improve the performance of the chip.

Description

Technical Field

[0001] This application relates to the field of processor technology, specifically to a clock frequency conversion system, method, processor, chip, and electronic device. Background Technology

[0002] Clock signals are crucial signals in chips, often requiring different frequencies to operate. For example, processors typically have multiple operating modes, each requiring a different clock frequency. Therefore, the rate of change of the clock signal's frequency significantly impacts chip performance. Consequently, improving the rate of change of the clock signal's frequency has become a critical technical problem for those skilled in the art. Summary of the Invention

[0003] In view of this, embodiments of this application provide a clock frequency conversion system, method, processor, chip, and electronic device to improve the frequency change speed of clock signals and enhance chip performance.

[0004] To achieve the above objectives, the embodiments of this application provide the following technical solutions.

[0005] In a first aspect, embodiments of this application provide a clock frequency conversion system, including: a clock generation circuit, a delay phase-locked loop circuit, and a clock selection circuit;

[0006] The clock generation circuit is used to generate the source clock signal;

[0007] The delay-locked loop circuit is used to perform multiple iterative delay processing based on the source clock signal to obtain multiple delayed clock signals with different phases; wherein, the last delayed clock signal is aligned with the source clock signal, and the phase difference between adjacent delayed clock signals is uniformly varied; the source clock signal and some delayed clock signals form multiple candidate clock signals input to the clock selection circuit.

[0008] The clock selection circuit is used to select a signal edge from the plurality of candidate clock signals, and to form a frequency-converted target clock signal from the selected signal edge.

[0009] Secondly, embodiments of this application provide a clock frequency conversion method, including:

[0010] Generate source clock signal;

[0011] Based on the source clock signal, multiple iterations of delay processing are performed to obtain multiple delayed clock signals with different phases; wherein, the last delayed clock signal is aligned with the source clock signal, and the phase difference between adjacent delayed clock signals varies uniformly; the source clock signal and some delayed clock signals form multiple candidate clock signals;

[0012] Select a signal edge from the plurality of candidate clock signals, and form the frequency-converted target clock signal from the selected signal edge.

[0013] Thirdly, embodiments of this application provide a processor, the processor including the clock conversion system as described in the first aspect above.

[0014] Fourthly, embodiments of this application provide a chip, the chip including the processor as described in the third aspect above.

[0015] Fifthly, embodiments of this application provide an electronic device, which includes the chip described in the fourth aspect above.

[0016] The clock conversion system provided in this application includes a clock generation circuit, a delay phase-locked loop (PLL) circuit, and a clock selection circuit. The clock generation circuit generates a source clock signal. The PLL circuit performs multiple iterative delay processing based on the source clock signal to obtain multiple delayed clock signals with different phases; the last delayed clock signal is aligned with the source clock signal, and the phase difference between adjacent delayed clock signals varies uniformly; the source clock signal and some delayed clock signals form multiple candidate clock signals input to the clock selection circuit. The clock selection circuit selects a signal edge from the multiple candidate clock signals, and the selected signal edge forms the converted target clock signal. In this embodiment, the signal edge forming the target clock signal is selected from multiple candidate clock signals, which are formed from a source clock signal and a portion of delayed clock signals. The last delayed clock signal is aligned with the source clock signal, and the phase difference between adjacent delayed clock signals changes uniformly. Therefore, in this embodiment, by selecting the signal edge from multiple candidate clock signals to form the target clock signal, the signal edge of the target clock signal can be selected from multiple candidate clock signals with different phases. This enables frequency conversion of the target clock signal relative to the source clock signal, achieving a frequency conversion effect for the clock signal. It is evident that this embodiment can rapidly convert the clock signal output by the clock generation circuit without changing the operating state of the internal frequency control device (e.g., VCO) of the clock generation circuit. This allows for rapid response to frequency changes in the clock signal, improving the frequency change speed of the clock signal and consequently enhancing chip performance such as the processor's operating mode switching speed. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the circuit structure of the clock frequency conversion system provided in the embodiments of this application.

[0019] Figure 2A This is another circuit structure diagram of the clock frequency conversion system provided in the embodiments of this application.

[0020] Figure 2B This is a schematic diagram of the output waveform of a delay phase-locked loop circuit.

[0021] Figure 2C This is another circuit structure diagram of the clock frequency conversion system provided in the embodiments of this application.

[0022] Figure 3A This is another circuit structure diagram of the clock frequency conversion system provided in the embodiments of this application.

[0023] Figure 3B A waveform diagram showing the result when the target clock signal is down-frequency.

[0024] Figure 3C A waveform diagram showing the frequency upsampling of the target clock signal.

[0025] Figure 4 This is another circuit structure diagram of the clock frequency conversion system provided in the embodiments of this application.

[0026] Figure 5 This is a timing diagram of a clock frequency conversion system provided in an embodiment of this application.

[0027] Figure 6 A flowchart of a clock frequency conversion method provided in an embodiment of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] In a chip, the clock signal is typically provided by a clock generation circuit, such as a PLL (Phase-Locked Loop). The clock signal provided by the PLL can supply the various circuits within the chip, ensuring their proper operation. Chips sometimes require clock signals of different frequencies. In such cases, the clock generation circuit can adjust the frequency of the generated clock signal to provide different frequencies of clock signals to the circuits within the chip. For example, when the chip's processor needs to switch operating modes, the clock generation circuit can adjust the frequency of the generated clock signal to provide the processor with a clock signal at the frequency corresponding to the switched operating mode.

[0030] Clock generation circuits (such as PLLs) typically include a frequency controller to adjust the clock signal within a specific frequency range. That is, the clock signal generated by the clock generation circuit has a defined frequency range, determined by the design of the internal frequency controller. For example, when a processor needs to switch operating modes, the clock generation circuit can change the frequency of the output clock signal by altering the operating state of its internal frequency controller to meet the requirements of the new operating mode.

[0031] In one example, the frequency control device mentioned above could be a VCO (Voltage Controlled Oscillator). A VCO is a modular circuit whose output clock frequency is controlled by an external input voltage. The amount by which a unit change in input voltage causes a change in the output clock frequency can be called the VCO gain. A PLL can internally configure the VCO and change the frequency of the output clock signal by changing the input control voltage of the VCO.

[0032] However, the clock generation circuit adjusts the clock signal frequency relatively slowly through internal frequency control devices, which limits the chip's performance. For example, when a PLL changes the frequency of its output clock signal by altering the input control voltage of the VCO, the time interval from changing the VCO's input control voltage to the stable clock signal after the frequency change is typically on the order of microseconds. This undoubtedly cannot meet the chip's internal operating requirements at lower time levels (such as nanoseconds), leading to performance limitations such as restricted processor mode switching speed.

[0033] To address the aforementioned problems, this application provides a novel clock signal frequency variation scheme (hereinafter referred to as a clock frequency conversion scheme) to improve the frequency variation speed of the clock signal and enhance chip performance. As an optional implementation, Figure 1 An exemplary circuit structure diagram of a clock frequency conversion system provided in an embodiment of this application is shown. This clock frequency conversion system can be the internal circuit system of an integrated circuit such as a chip. Figure 1As shown, the clock frequency conversion system may include: a clock generation circuit 110, a delay phase-locked loop circuit 120, and a clock selection circuit 130.

[0034] Clock generation circuit 110 is used to generate source clock signal clkin0. Source clock signal clkin0 can be considered as the clock signal before frequency conversion. In this embodiment, when it is necessary to convert the clock signal, this embodiment does not achieve it by adjusting the working state of the frequency control device inside the clock generation circuit 110, but by processing the clock signal generated and output by the clock generation circuit 110 through delay phase-locked loop circuit 120 and clock selection circuit 130 to achieve clock frequency conversion.

[0035] The delay phase-locked loop circuit 120 is used to perform multiple iterations of delay processing based on the source clock signal clkin0 to obtain multiple delayed clock signals clkin1 to clkinN with different phases; wherein, the last delayed clock signal clkinN is aligned with the source clock signal clkin0, and the phase difference between adjacent delayed clock signals is uniformly varied.

[0036] To achieve frequency conversion of the clock signal, this embodiment further includes a clock selection circuit 130. The source clock signal and a portion of the delayed clock signal obtained from the delay phase-locked loop circuit 120 can be used as the clock signal input to the clock selection circuit 130. This allows the clock selection circuit 130 to select signal edges (rising and falling edges) from the input clock signal, thereby forming the frequency-converted clock signal from the selected signal edges. For ease of explanation, this embodiment refers to the clock signal input to the clock selection circuit 130 as the candidate clock signal, and the frequency-converted clock signal of the clock selection circuit 130 as the target clock signal clkout.

[0037] In some embodiments, there may be multiple candidate clock signals, which may be formed by the source clock signal clkin0 and the first delayed clock signal clkin1 to the last second delayed clock signal clkinN-1. That is, the multiple candidate clock signals may include: the source clock signal clkin0, and the N clock signals from the first delayed clock signal clkin1 to the last second delayed clock signal clkinN-1.

[0038] Based on multiple candidate clock signals of the input clock selection circuit 130, the clock selection circuit 130 can be used to select a signal edge from the multiple candidate clock signals, and form a frequency-converted target clock signal from the selected signal edge.

[0039] In some embodiments, multiple candidate clock signals can be arranged in a predetermined order. This predetermined order can refer to the order in which the phase difference between adjacent candidate clock signals changes uniformly. For example, the order from the source clock signal clkin0 to the second-to-last delayed clock signal clkinN-1 can form a positive sequence of multiple candidate clock signals, i.e., clkin0, clkin1, clkin2, and so on up to clkinN-1. This positive sequence can be used as a predetermined order of multiple candidate clock signals. Here, clkin0 and clkinN are aligned, and the phase difference between adjacent delayed clock signals changes uniformly. Therefore, among the multiple candidate clock signals from clkin0 to clkinN-1, the phase difference between adjacent candidate clock signals changes uniformly, and this positive sequence can be used as a predetermined order of multiple candidate clock signals.

[0040] For example, starting with the source clock signal clkin0 and then proceeding to clkinN-1 and clkin1, another possible setting order for multiple candidate clock signals can be formed. This setting order starts with clkin0 and proceeds to clkinN-1 and clkin1. Since clkin0 and clkinN are aligned and the phase difference between adjacent delayed clock signals changes uniformly, the phase difference between adjacent candidate clock signals changes uniformly in the order starting with clkin0 and proceeding to clkinN-1 and clkin1. Therefore, this order can be used as another possible setting order for multiple candidate clock signals.

[0041] Based on the set order of multiple candidate clock signals, the clock selection circuit 130 can cyclically select signal edges from each candidate clock signal according to the set order, and select one signal edge from each candidate clock signal at a time, thereby obtaining the signal edges selected from multiple candidate clock signals to form the target clock signal clkinout.

[0042] As an optional implementation, when the clock signal needs to be down-clocked, the clock selection circuit 130 can cyclically select signal edges from each candidate clock signal in ascending order from clkin0 to clkinN-1, and select one signal edge from each candidate clock signal at a time to obtain the signal edge that forms the target clock signal clkinout; when the clock signal needs to be up-clocked, the clock selection circuit 130 can start from clkin0 and cyclically select signal edges from each candidate clock signal in order from clkinN-1 to clkin1 to form the signal edge of the target clock signal clkinout.

[0043] The above describes a possible way for the clock selection circuit 130 to select signal edges. Of course, the embodiments of this application are not limited to the above description. As long as the clock selection circuit 130 can select rising and falling edges from multiple candidate clock signals in a certain set order, and the set order is the order in which the phase difference between adjacent candidate clock signals changes uniformly, the embodiments of this application can select multiple signal edges with different phases and uniform phase differences in a set order. After these multiple signal edges are combined, the frequency-converted target clock signal clkinout can be obtained, thereby realizing the frequency conversion of the clock signal.

[0044] In some further embodiments, combined with Figure 1 As shown, the source clock signal clkin0 generated by the clock generation circuit 110 can be input to the delay phase-locked loop circuit 120 after passing through the buffer 140. It should be noted that setting the buffer 140 is not a necessary measure, and the buffer 140 may not be set in this embodiment.

[0045] The clock conversion system provided in this application includes a clock generation circuit, a delay phase-locked loop (PLL) circuit, and a clock selection circuit. The clock generation circuit generates a source clock signal. The PLL circuit performs multiple iterative delay processing based on the source clock signal to obtain multiple delayed clock signals with different phases; the last delayed clock signal is aligned with the source clock signal, and the phase difference between adjacent delayed clock signals varies uniformly; the source clock signal and some delayed clock signals form multiple candidate clock signals input to the clock selection circuit. The clock selection circuit selects a signal edge from the multiple candidate clock signals, and the selected signal edge forms the converted target clock signal. In this embodiment, the signal edge forming the target clock signal is selected from multiple candidate clock signals, which are formed from a source clock signal and a portion of delayed clock signals. The last delayed clock signal is aligned with the source clock signal, and the phase difference between adjacent delayed clock signals changes uniformly. Therefore, in this embodiment, by selecting the signal edge from multiple candidate clock signals to form the target clock signal, the signal edge of the target clock signal can be selected from multiple candidate clock signals with different phases. This enables frequency conversion of the target clock signal relative to the source clock signal, achieving a frequency conversion effect for the clock signal. It is evident that this embodiment can rapidly convert the clock signal output by the clock generation circuit without changing the operating state of the internal frequency control device (e.g., VCO) of the clock generation circuit. This allows for rapid response to frequency changes in the clock signal, improving the frequency change speed of the clock signal and consequently enhancing chip performance such as the processor's operating mode switching speed.

[0046] Figure 2AAn exemplary schematic diagram of another circuit structure of the clock frequency conversion system provided in an embodiment of this application is shown. Figure 2A The clock frequency conversion system shown is in Figure 1 Based on this, the circuit structure of the delay phase-locked loop circuit 120 was refined. Combined with... Figure 1 and Figure 2A As shown, in Figure 2A In the clock frequency conversion system shown, the delay phase-locked circuit 120 may include: multiple delay units 211 to 21N, the specific value of N can be set according to the actual situation, a phase comparator 220, and a delay control circuit 230.

[0047] When the source clock signal clkin0 is input to the delay phase-locked loop circuit 120, multiple delay units 211 to 21N are used to iteratively adjust the delay of the clock signal, starting from the source clock signal clkin0, to obtain multiple delayed clock signals clkin1 to clkinN with different phases. The last delayed clock signal clkinN is aligned with the source clock signal clkin0. For example, the delay between the last delayed clock signal clkinN and the source clock signal clkin0 is one clock cycle, which can be the period of one clock signal.

[0048] In this embodiment, a delay unit can adjust the delay of the input clock signal and output a delayed clock signal with a phase change accordingly. The clock signal input to the next delay unit is the delayed clock signal output by the previous delay unit. For the first delay unit 211, the clock signal input to the first delay unit 211 is the source clock signal clkin0. It should be noted that phase refers to the delay time between the clock signal and the ideal signal at the corresponding effective instant (generally the rising edge or falling edge). In some cases, phase can be regarded as a delay.

[0049] Assuming the source clock signal clkin0 generated by clock generation circuit 110 has a phase of phase 0, the source clock signal clkin0 can be input to the first delay unit 211. The first delay unit 211 adjusts the delay of the source clock signal clkin0 by the delay size, and outputs a first delayed clock signal clkin1 with a phase of phase 1. The phase difference between phase 1 and phase 0 is the delay size of the delay unit. The first delayed clock signal clkin1 output by the first delay unit 211 is input to the second delay unit 212. The second delay unit 212 adjusts the delay of the first delayed clock signal clkin1 by the delay size, and outputs a second delayed clock signal clkin2 with a phase of phase 2. The phase difference of phase 1 is the delay size of the delay unit; the third delay unit 213 adjusts the delay of clkin2 by the delay size and outputs the third delayed clock signal clkin3 with phase 3. The phase difference between phase 3 and phase 2 is the delay size of the delay unit; and so on, the (N-1)th delay unit 21N-1 outputs the delayed clock signal clkinN-1 with phase N-1 and inputs it to the Nth delay unit 21N. The Nth delay unit 21N adjusts the delay of clkinN-1 by the delay size and outputs the Nth delayed clock signal clkinN with phase N (i.e., the last delayed clock signal clkinN). The phase difference between phase N and phase N-1 is the delay size of the delay unit.

[0050] In some embodiments, the delay magnitude of each delay unit can be the same, and the delay control circuit 230 can control the delay magnitude of the delay unit based on the phase relationship between the last delayed clock signal clkinN and the source clock signal clkin0. Figure 2A As shown, the last delayed clock signal clkinN and the source clock signal clkin0 can be input to the phase comparator 220, so that the phase comparator 220 compares the phase relationship between the last delayed clock signal clkinN and the source clock signal clkin0, and outputs control information for controlling the delay control circuit 230 based on the compared phase relationship.

[0051] In some embodiments, phase comparator 220 can compare whether the phase of clkinN leads or lags clkin0 (i.e., compare whether phaseN leads or lags phase0). If phase comparator 220 finds that the phase of clkinN leads clkin0 (i.e., phaseN leads phase0), then phase comparator 220 can output first control information, which can be used to control delay control circuit 230 to increase the delay size of delay unit; if phase comparator 220 finds that the phase of clkinN lags clkin0 (i.e., phaseN lags phase0), then phase comparator 220 can output second control information, which can be used to control delay control circuit 230 to decrease the delay size of delay unit. Optionally, the first and second control information can be numerical information, such as the first control information being a first value and the second control information being a second value. In one example, the first value can be 0 and the second value can be 1; of course, in this embodiment, the first value can also be set to 1 and the second value to 0.

[0052] In this embodiment, the delay control circuit 230 can be used to control the delay size of each delay unit. In some embodiments, as described above, the delay control circuit 230 can increase the delay size of the delay unit based on the first control information output by the phase comparator 220, and decrease the delay size of the delay unit based on the second control information output by the phase comparator 220. Alternatively, the delay control circuit 230 can output a delay control signal (delay code) to each delay unit to increase or decrease the delay size of the delay unit. For example, the delay control circuit 230 can transmit a delay control signal to each delay unit to increase the delay size based on the first control information output by the phase comparator 220 (such as the first value where the phase comparator 220 outputs a value of 0), thereby increasing the delay size of each delay unit; the delay control circuit 230 can also transmit a delay control signal to each delay unit to decrease the delay size based on the second control information output by the phase comparator 220 (such as the second value where the phase comparator 220 outputs a value of 1), thereby decreasing the delay size of each delay unit.

[0053] Understandably, phase comparator 220 can output control information of 0 or 1 based on the phase relationship between clkinN and clkin0, indicating whether phase N of clkinN leads or lags phase 0 of clkin0. If phase N leads phase 0, phase comparator 220 can output control information of 0, allowing delay control circuit 230 to increase the delay size of the delay unit through delay control signal, thus increasing the total delay between phase N and phase 0. Phase comparator 220 can continuously adjust the delay of clkinN and continuously judge the phase relationship between clkinN and clkin0. When the delay size of the delay unit increases to the point that phase N lags phase 0, phase comparator 220 can output control information of 1, allowing delay control circuit 230 to decrease the delay size of the delay unit through delay control signal, thus reducing the delay of clkinN. Through the above repeated processing, the output of phase comparator 220 jumps between 0 and 1, so that phase N is located in a position close to phase 0, achieving the effect that clkinN is approximately aligned with clkin0.

[0054] It should be noted that aligning clkinN with clkin0 can be considered as aligning clkinN with the source clock signal clkin0 by a delay of one clock cycle. This clock cycle can be the period of the clock signal from the clock generation circuit. Since clkin0 is iteratively delayed through multiple delay units 211 to 21N to obtain delayed clock signals clkin1 to clkinN, and the delay magnitude of each delay unit is the same, the phases of clkin0 to clkinN change uniformly. That is, when phaseN is aligned with phase0, the delay between phaseN and phase0 is one clock cycle, and this one clock cycle delay is evenly divided by the clock signals with phases from phase0 to phaseN-1. For example, the phase difference between adjacent clock signals among the N clock signals clkin0 to clkinN-1 is one clock cycle divided by N, and the delay of one clock cycle is evenly divided by these N clock signals.

[0055] For ease of understanding, Figure 2B An exemplary schematic diagram of the output waveform of the delay-locked loop circuit 120 is shown. Figure 2BIt can be seen that the delayed clock signals clkin1 to clkinN output by the delay phase-locked loop circuit 120 are all the same source clock signals clkin0 output by the clock generation circuit 110 (e.g., PLL). The delayed clock signals clkin1 to clkinN have a total of N phases phase1 to phaseN. PhaseN is aligned with the phase phase0 of the source clock signal clkin0, and there is a fixed delay size (i.e., the delay size of the delay unit) between two adjacent phases. This delay size is the clock period divided by N.

[0056] From the connection relationship of the delay-locked loop circuit 120, the source clock signal clkin0 is input to the first delay unit 211 among multiple delay units; thus, each delay unit can adjust the delay of the input clock signal and output a corresponding delayed clock signal. Among the multiple delay units, except for the last delay unit 21N, the delayed clock signals clkin1 to clkinN-1 output by the other delay units, as well as the source clock signal clkin0, can be input to the phase selection circuit 130. Simultaneously, the source clock signal clkin0 can be input to the phase comparator 220, and the output of the last delay unit 21N among the multiple delay units can be connected to the input of the phase comparator 220, so that the phase comparator 220 can compare the phase relationship between clkinN and clkin0. The output of the phase comparator 220 can be connected to the input of the delay control circuit 230; the output of the delay control circuit 230 can be connected to the control terminal of each delay unit, so that the delay control circuit 230 can set the delay size of each delay unit.

[0057] exist Figure 2A In one optional implementation of the delay-locked loop (DLL) 120 shown, the DLL can be a delay-locked loop (DLL). A DLL is an improvement on PLL technology. The DLL inherits the phase-locking technology of the PLL but removes the oscillator section from the PLL circuit, replacing it with a delay unit whose delay size can be controlled. When the DLL is locked, the output clock signal and the input clock signal are phase-aligned, but the delay is one clock cycle. Based on the DLL, Figure 2C An exemplary circuit structure diagram of the clock conversion system provided in this application embodiment is shown below. Figure 2C The clock frequency conversion system shown is in Figure 2A Based on this, an optional circuit implementation of the delay-locked loop circuit 120 is shown. Combined with... Figure 2A and Figure 2C As shown, Figure 2A The clock generation circuit 110 shown can be Figure 2C The PLL111 shown, Figure 2AThe delay-locked loop circuit 120 shown can be Figure 2C DLL121 shown, Figure 2A The phase comparator 220 shown can be Figure 2C The phase detector 221 shown, Figure 2A The delay control circuit 230 shown can be Figure 2C The DLL control circuit 231 is shown. The functions of the phase detector 221 and the DLL control circuit 231 can be found in [reference needed]. Figure 2A As shown in the diagram, further explanation is not provided here.

[0058] Figure 3A An exemplary circuit structure diagram of the clock conversion system provided in this application embodiment is shown below. Figure 3A The clock frequency conversion system shown is in Figure 2C Based on this, the circuit structure of the clock selection circuit 130 was refined. Combined with... Figure 2C and Figure 3A As shown, in Figure 3A In the clock frequency conversion system shown, the clock selection circuit 130 may include: a phase enable circuit 310, multiple AND gates 320 to 32N-1, and an OR gate 330.

[0059] The phase enable circuit 310 can input multiple candidate clock signals. For example, the phase enable circuit 310 can input a source clock signal clkin0, and a first delayed clock signal clkin1 to a last delayed clock signal clkinN-1. Thus, the phase enable circuit 310 can determine the enable signal en0 of the source clock signal clkin0 based on the phase 0 of the source clock signal clkin0, and determine the enable signals en1 to enN-1 of clkin1 to clkinN-1 based on the phases phase1 to phaseN-1 of the first delayed clock signal clkin1 to the last delayed clock signal clkinN-1, respectively. For example, the phase enable circuit 310 can obtain the enable signal en1 of clkin1 based on the phase 1 of clkin1, the enable signal en2 of clkin2 based on the phase 2 of clkin2, and so on, until the enable signal enN-1 of clkinN-1 is obtained based on the phase N-1 of clkinN-1. The phase enable circuit 310 can transmit en0 to enN-1 in ascending order to multiple AND gates 320 to 32N-1.

[0060] Multiple AND gates 320 to 32N-1 can be sequentially input with the source clock signal clkin0 and the corresponding enable signal en0, the first delayed clock signal clkin1 to the last second delayed clock signal clkinN-1 and the corresponding enable signals en0 to enN-1. For example, AND gate 320 can input the source clock signal clkin0 and the enable signal en0, AND gate 321 can input the first delayed clock signal clkin1 and the enable signal en1, AND gate 322 can input the second delayed clock signal clkin2 and the enable signal en2, and so on. AND gate 32N-1 can input the last second delayed clock signal clkinN-1 and the enable signal enN-1.

[0061] Each AND gate can select the signal edge of the input clock signal based on the input enable signal. For example, AND gate 320 can select the signal edge of the input source clock signal clkin0 based on the input enable signal en0; AND gate 321 can select the signal edge of the first delayed clock signal clkin1 based on the input enable signal en1; AND gate 322 can select the signal edge of the second delayed clock signal clkin2 based on the input enable signal en2; and so on, AND gate 32N-1 can select the signal edge of the second-to-last delayed clock signal clkinN-1 based on the input enable signal enN-1.

[0062] Each signal edge selected by the AND gate can pass through the OR gate 330 to form the target clock signal clkout after frequency conversion.

[0063] In some embodiments, in scenarios where clock signal down-frequency reduction is required, multiple AND gates 320 to 32N-1 can cyclically select signal edges from the candidate clock signals input to each AND gate in a predetermined order. Each AND gate selects one signal edge at a time, thus obtaining the signal edges selected by each AND gate. Alternatively, in this embodiment, based on the principle that if the previous candidate clock signal selected a rising edge, the next candidate clock signal will select a falling edge, multiple AND gates 320 to 32N-1 can cyclically select signal edges from the input candidate clock signals in ascending order, corresponding to the current signal edge sequence number of the target clock signal, thus obtaining the signal edges selected by each AND gate.

[0064] For example, AND gate 320, as the first AND gate, can select the rising edge starting from the selected rising edge, and the current sequence number of the rising edge is 1. Then, AND gate 320 can select the first rising edge from the input source clock signal clkin0 as the first rising edge of the target clock signal clkout. Following the ascending order of the multiple AND gates, AND gate 321, as the second AND gate selecting the signal edge, can select the falling edge while AND gate 320, which selected the rising edge in the previous selection, is doing so. And the current sequence number of the falling edge is 1. Then, AND gate 321 can select the first falling edge from the input first delayed clock signal clkin1 as the first falling edge of the target clock signal clkout. Falling edge; AND gate 322 acts as the third AND gate for selecting the signal edge. After AND gate 321 selects the falling edge in the previous selection signal edge, AND gate 322 can select the rising edge. If the current sequence number of the rising edge is 2, then AND gate 322 can select the second rising edge from the second delayed clock signal clkin2 as the second rising edge of the target clock signal clkout. And so on. After multiple AND gates 320 to 32N-1 complete one cycle, the next cycle can be entered. Starting from the first AND gate 320, the signal edges are selected in the ascending order of multiple AND gates. This cycle is repeated to obtain the signal edge of the target clock signal clkout.

[0065] For ease of understanding, Figure 3B A waveform diagram is shown when the target clock signal is down-frequency. For example... Figure 3B As shown, the first rising edge of clkin0 is selected as the first rising edge of clkout, the first falling edge of clkin1 is selected as the first falling edge of clkout, the second rising edge of clkin2 is selected as the second rising edge of clkout, the second falling edge of clkin3 is selected as the second falling edge of clkout, and so on. After AND gates 320 to 32N-1 complete a cycle of signal edge selection for clkin0 to clkinN-1, this embodiment of the application can enter the next cycle, thereby returning to AND gate 320, selecting the rising edge corresponding to the current ordinal number of the rising edge of clkout from clkin0, and repeating this process to determine each rising and falling edge of clkout.

[0066] In scenarios requiring clock signal down-clocking, the target clock signal clkout can be generated by OR gate 330 based on the signal edges selected by each AND gate. It can be understood that since the phase difference between adjacent clock signals from clkin0 to clkinN-1 is 1 / N of a clock period, in clock signal down-clocking scenarios, when the target clock signal clkout is sequentially generated by the signal edges selected by each AND gate, the period of the target clock signal clkout is 1+2 / N times the period of the source clock signal clkin0. Therefore, the frequency of the target clock signal clkout is reduced by 1 / (1+2 / N) times, achieving a fractional-fold down-clocking.

[0067] It should be noted that in the scenario of clock signal downclocking, the above-described AND gate selects the signal edge in ascending order based on the principle that the next candidate clock signal selects the falling edge when the previous candidate clock signal selects the rising edge. The method of selecting the signal edge in ascending order by multiple AND gates in a loop is only one optional implementation. In the embodiments of this application, the signal edge can also be selected according to the principle of selecting the falling edge and rising edge by AND gate interval. Multiple AND gates can also select the signal edge in reverse order or in other order, and it is not necessarily in ascending order.

[0068] In some embodiments, in scenarios where clock signals need to be upscaled, multiple AND gates 320 to 32N-1 can cyclically select signal edges from the candidate clock signals input to each AND gate, starting from the first AND gate 320 and proceeding in the order from the last AND gate 32N-1 to the second AND gate 321. Each AND gate selects one signal edge at a time, thus obtaining the signal edges selected by each AND gate. Alternatively, embodiments of this application can, based on the principle that if the previous candidate clock signal selected a rising edge, the next candidate clock signal will select a falling edge, starting from the first AND gate and proceeding in the order from the last AND gate to the second AND gate, cyclically select the signal edge corresponding to the current signal edge sequence from the candidate clock signals input to each AND gate, thus obtaining the signal edges selected by each AND gate.

[0069] For example, AND gate 320, as the first AND gate, can select the rising edge starting from the selected rising edge, and the current sequence number of the rising edge is 1. Then, AND gate 320 can select the first rising edge from the input source clock signal clkin0 as the first rising edge of the target clock signal clkout. Following the order of the last AND gate 32N-1 to the second AND gate 321, the last AND gate 32N-1, as the second AND gate selecting the signal edge, can select the falling edge while the previous AND gate 320 selects the rising edge, and the current sequence number of the falling edge is 1. Then, AND gate 32N-1 can select the first falling edge from the (N-1)th delayed clock signal clkinN-1 as the first falling edge of the target clock signal clkout. Following the order of the last AND gate 32... The sequence from N-1 to the second AND gate 321 is followed by the last AND gate 32N-2, which acts as the third AND gate for selecting the signal edge. After the falling edge is selected by the previous AND gate 32N-1, AND gate 32N-2 selects the rising edge. Since the current sequence number of the rising edge is 2, AND gate 32N-2 can select the second rising edge from the (N-2)th delayed clock signal clkinN-2 as the second rising edge of the target clock signal clkout. This process continues until multiple AND gates 320 to 32N-1 complete one cycle. Then, the next cycle begins, starting from the first AND gate 320 and selecting the signal edge in the order from the last AND gate 32N-1 to the second AND gate 321. This cycle is repeated to obtain the signal edge of the target clock signal clkout.

[0070] For ease of understanding, Figure 3C A waveform diagram is shown when the target clock signal is frequency-upgraded. (Example) Figure 3C As shown, the first rising edge of clkin0 is selected as the first rising edge of clkout, the first falling edge of clkinN-1 is selected as the first falling edge of clkout, the second rising edge of clkinN-2 is selected as the second rising edge of clkout, the second falling edge of clkinN-3 is selected as the second falling edge of clkout, and so on. After AND gates 320 to 32N-1 complete a cycle of signal edge selection for clkin0 to clkinN-1, this embodiment of the application can enter the next cycle. Starting from AND gate 320, the signal edges are selected again in the order of the second AND gate 321 to the last AND gate 32N-1, and so on, thereby realizing the determination of each rising edge and falling edge of clkout.

[0071] In the clock signal upsampling scenario, based on the signal edges selected by each AND gate, OR gate 330 can form the upsampling target clock signal clkout. It can be understood that since the phase difference between adjacent clock signals from clkin0 to clkinN-1 is 1 / N of a clock period, in the clock signal upsampling scenario, the period of the target clock signal clkout is 1-2 / N times that of the source clock signal clkin0, meaning the frequency is increased by 1 / (1-2 / N) times, achieving a fractional-fold upsampling.

[0072] It should be noted that the embodiments of this application can realize frequency conversion of the clock signal by any fractional factor, such as frequency reduction or increase of the clock signal by any fractional factor. In some embodiments, when increasing the frequency, the frequency increase factor is determined based on 1 / (1-2 / N), and when reducing the frequency, the frequency reduction factor is determined based on 1 / (1+2 / N). Therefore, the frequency conversion factor of the clock signal can depend on the number of delayed clock signals obtained by the delay phase-locked circuit (e.g., DLL), for example, based on the number of delay units of the delay phase-locked circuit. In some embodiments, N can be an even number. For example, the delay phase-locked circuit sets an even number of delay units to obtain an even number of delayed clock signals; the clock selection circuit sets an even number of AND gates to select the signal edge of the target clock signal clkout from an even number of clock signals from clkin0 to clkinN-1. In addition, whether the clock signal is increased or decreased depends on whether the actual application requires the clock signal to be decreased or increased, and the required frequency reduction and increase ratios of the clock signal in the actual application. The embodiments of this application do not impose any limitations on this.

[0073] It should be noted that, Figure 3A The clock selection circuit 130 shown uses an AND gate to select a signal edge from multiple candidate clock signals; this is merely one possible implementation of the clock selection circuit 130's signal edge selection. In some embodiments, based on the concept of the clock selection circuit 130's signal edge selection provided in this application, the clock selection circuit 130 can also select a signal edge using other circuit devices, and does not necessarily have to use an AND gate. That is, the clock selection circuit 130 can cyclically select a signal edge from each candidate clock signal according to a set order, and select one signal edge from each candidate clock signal at a time, wherein the set order is the order in which the phase difference between adjacent candidate clock signals changes uniformly. Under this concept, this application embodiment can set various circuit structures of the clock selection circuit 130 to achieve signal edge selection.

[0074] In one alternative implementation of the above approach, when the clock signal needs to be down-clocked, the clock selection circuit 130 can, based on the principle that if the previous candidate clock signal is selected on its rising edge, then the next candidate clock signal is selected on its falling edge, and so on, cyclically select the signal edge corresponding to the current signal edge number of the target clock signal from among the multiple candidate clock signals in ascending order. The ascending order of the multiple candidate clock signals can be from the source clock signal clkin0 to the second-to-last delayed clock signal clkinN-1.

[0075] For example, when using AND gates to implement signal edge selection, if the clock signal needs to be down-clocked, multiple AND gates can select the signal edge corresponding to the current signal edge number of the target clock signal from the candidate clock signals input by each AND gate in ascending order from the first AND gate 320 to the last AND gate 32N-1, based on the principle that the previous candidate clock signal selects the rising edge and the next candidate clock signal selects the falling edge.

[0076] In another alternative implementation of the above approach, when the clock signal needs to be upscaled, the clock selection circuit 130 can select the signal edge corresponding to the current signal edge number of the target clock signal from each candidate clock signal in a cyclical manner, starting from the source clock signal and following the order from the second-to-last delayed clock signal to the first delayed clock signal.

[0077] For example, when using AND gates to implement signal edge selection, if the clock signal needs to be upscaled, multiple AND gates can select the signal edge corresponding to the current signal edge number of the target clock signal from the candidate clock signals input by each AND gate in a cyclical manner, starting from the first AND gate and proceeding in the order from the last AND gate to the second AND gate.

[0078] exist Figure 3A In one alternative implementation of the clock selection circuit 130 shown, the clock selection circuit 130 can be a clock picker. Figure 4 An exemplary schematic diagram of another circuit structure of the clock frequency conversion system provided in this application embodiment is shown. Figure 4 The clock frequency conversion system shown is in Figure 3A Based on the above, an exemplary circuit implementation of the clock selection circuit 130 is shown. Combined with... Figure 3A and Figure 4 As shown, Figure 3A The clock selection circuit 130 shown can be Figure 4 The clock picker 131 shown is... Figure 3AThe phase enable circuit 310 shown can be Figure 4 The phase enable generator 311 is shown. The clock picker works as follows: the phase enable generator generates enable signals en0 to enN-1 corresponding to each AND gate based on the phases phase0 to phaseN-1 of clkin0 to clkinN-1; these enable signals en0 to enN-1 and clkin0 to clkinN-1 are then sequentially input into each AND gate, and selected by the AND gates to the signal edge of clkout; the signal edges selected by each AND gate are then output as clkout by OR gates. The specific implementation process of the above working principle can be referred to the description in the corresponding section above, and will not be repeated here.

[0079] In some embodiments, from the perspective of the overall clock frequency conversion system, the working principle of the clock frequency conversion system can be as follows: The source clock signal clkin0 generated by the clock generation circuit (e.g., PLL) is transmitted to the delay phase-locked circuit (e.g., DLL) after passing through a buffer; the delay phase-locked circuit, based on clkin0, divides the delay between adjacent clock signals into N equal parts of the clock period, and outputs clkin0 to clkinN-1 to the clock selection circuit (e.g., clock picker). The clock selection circuit selects the signal edge of the target clock signal clkout from clkin0 to clkinN-1, and forms the target clock signal clkout from the selected signal edge. The formed target clock signal clkout can be a clock signal that is down-clocked or up-clocked relative to the source clock signal clkin0. As an optional implementation, the target clock signal clkout can be provided to the circuitry of the chip. For example, clkout can be provided to the processor for switching the processor's operating mode.

[0080] Figure 5An exemplary timing diagram of the clock conversion system provided in this application embodiment is shown, wherein clkin0 is the clock signal output by the PLL (an optional form of clock generation circuit), and clockpicker enable is the enable signal of the clockpicker (an optional form of clock selection circuit). The clockpicker enable can be externally input to control the timing of frequency changes in the clock signal. When clockpicker enable changes from 0 to 1, the clockpicker is turned on. enable_sync is the synchronization signal of the clockpicker. enable_sync is triggered on the first falling edge of clkin0 after clockpicker enable is 1, at which time enable_sync changes from 0 to 1, thus the clockpicker begins to select the signal edge of the target clock signal clkout from clkin0 to clkinN-1. Figure 5 As shown, the time from clockpicker enable to clkout starting frequency conversion is at most 1.5 clock cycles. That is, the embodiment of this application can complete the frequency change of the clock signal within 1.5 clock cycles. Since 1.5 clock cycles of a chip system's clock signal are typically at the nanosecond level, this embodiment of the application can quickly convert the clock signal output by the clock generation circuit without changing the operating state of the internal frequency control device (e.g., VCO) of the clock generation circuit. This allows for rapid response to the frequency change requirements of the clock signal, improving the frequency conversion speed of the clock signal.

[0081] This application also provides a clock frequency conversion method, which, as an optional implementation, can be implemented based on the clock frequency conversion system described above. Figure 6 An exemplary flowchart of a clock frequency conversion method provided in an embodiment of this application is shown. (Refer to...) Figure 6 The process may include the following steps.

[0082] In step S610, a source clock signal is generated.

[0083] In some embodiments, step S610 may be performed by clock generation circuit 110.

[0084] In step S611, based on the source clock signal, multiple iterations of delay processing are performed to obtain multiple delayed clock signals with different phases; wherein, the last delayed clock signal is aligned with the source clock signal, and the phase difference between adjacent delayed clock signals changes uniformly; the source clock signal and some delayed clock signals form multiple candidate clock signals input to the clock selection circuit.

[0085] In some embodiments, step S611 may be performed by the delay phase-locked loop circuit 120.

[0086] In step S612, a signal edge is selected from the plurality of candidate clock signals, and the selected signal edge is used to form the frequency-converted target clock signal.

[0087] In some embodiments, step S612 may be performed by clock selection circuit 130.

[0088] In some embodiments, the process of selecting a signal edge from the plurality of candidate clock signals may include:

[0089] The signal edge is selected from each candidate clock signal in a cyclical manner according to the set order of the candidate clock signals, and one signal edge is selected from each candidate clock signal at a time; wherein the set order is the order in which the phase difference between adjacent candidate clock signals changes uniformly.

[0090] In some embodiments, the plurality of candidate clock signals include: a source clock signal, and a first delayed clock signal to a last second delayed clock signal; the forward order of the plurality of candidate clock signals is the order of the source clock signal to the last second delayed clock signal.

[0091] In some embodiments, the process of cyclically selecting signal edges from each candidate clock signal according to a set order, and selecting one signal edge from each candidate clock signal at a time, may include:

[0092] When the clock signal needs to be down-clocked, based on the principle that the rising edge of the previous candidate clock signal is selected and the falling edge of the next candidate clock signal is selected, the signal edge corresponding to the current signal edge number of the target clock signal is selected from the candidate clock signals in the ascending order of the multiple candidate clock signals.

[0093] And / or,

[0094] When the clock signal needs to be up-frequencyed, based on the principle that the rising edge of the previous candidate clock signal is selected and the falling edge of the next candidate clock signal is selected, starting from the source clock signal, the signal edge corresponding to the current signal edge number of the target clock signal is selected from each candidate clock signal in the order of the second-to-last delayed clock signal to the first delayed clock signal.

[0095] In some embodiments, when the clock signal needs to be down-clocked, the frequency of the target clock signal is reduced by 1 / (1+2 / N) times relative to the source clock signal, where N is the number of the plurality of delayed clock signals; when the clock signal needs to be up-clocked, the frequency of the target clock signal is increased by 1 / (1-2 / N) times relative to the source clock signal.

[0096] In some embodiments, the delay between the last delayed clock signal and the source clock signal is one clock cycle, and the phase difference between adjacent delayed clock signals is one clock cycle divided by N, where N is the number of the plurality of delayed clock signals.

[0097] The clock frequency conversion method provided in this application embodiment can quickly convert the clock signal output by the clock generation circuit, which can quickly respond to the frequency change requirements of the clock signal and improve the frequency change speed of the clock signal.

[0098] This application also provides a processor, which may include the clock conversion system provided in this application. The processor may be, for example, a central processing unit (CPU), various complex instruction set computing (CISC) processors, various reduced instruction set computing (RISC) processors, various very long instruction word (VLIW) processors, etc.

[0099] This application also provides a chip, which may include the processor provided in this application.

[0100] This application also provides an electronic device that may include the chip provided in this application. This electronic device may be, for example, a terminal device or a server device.

[0101] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0102] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A clock frequency conversion system, characterized in that, include: Clock generation circuit, delay phase-locked loop circuit, and clock selection circuit; The clock generation circuit is used to generate the source clock signal; The delay-locked loop circuit is used to perform multiple iterative delay processing based on the source clock signal to obtain multiple delayed clock signals with different phases; wherein, the last delayed clock signal is aligned with the source clock signal, and the phase difference between adjacent delayed clock signals varies uniformly; the source clock signal and some delayed clock signals form multiple candidate clock signals input to the clock selection circuit; the multiple candidate clock signals include: the source clock signal, and N clock signals from the first delayed clock signal to the last second delayed clock signal; The clock selection circuit is used to select a signal edge from the plurality of candidate clock signals, and to form a frequency-converted target clock signal from the selected signal edge; the clock selection circuit is used to select a signal edge from the plurality of candidate clock signals including: The signal edge is selected from each candidate clock signal in a cyclical manner according to the set order of the candidate clock signals, and one signal edge is selected from each candidate clock signal at a time; wherein, the set order is the order in which the phase difference between adjacent candidate clock signals changes uniformly; The clock selection circuit includes: Multiple AND gates; wherein the multiple candidate clock signals are sequentially input into the multiple AND gates in ascending order, and each AND gate outputs a signal edge selected from the input candidate clock signals; A phase enable circuit and an OR gate; the phase enable circuit is used to output multiple enable signals according to the phase of the multiple candidate clock signals respectively; the multiple enable signals are sequentially input into the multiple AND gates in ascending order, so that each AND gate selects a signal edge based on the input enable signal and the candidate clock signal; the OR gate is used to obtain the signal edge selected by each AND gate, and the signal edge selected by each AND gate forms the frequency-converted target clock signal.

2. The clock frequency conversion system according to claim 1, characterized in that, The plurality of candidate clock signals include: a source clock signal, and a first delayed clock signal to the last second delayed clock signal; the forward order of the plurality of candidate clock signals is the order of the source clock signal to the last second delayed clock signal.

3. The clock frequency conversion system according to claim 2, characterized in that, The clock selection circuit is used to cyclically select signal edges from each candidate clock signal according to a set order, and selecting a signal edge from each candidate clock signal at a time includes: When the clock signal needs to be down-clocked, based on the principle that the rising edge of the previous candidate clock signal is selected and the falling edge of the next candidate clock signal is selected, the signal edge corresponding to the current signal edge number of the target clock signal is selected from the candidate clock signals in the ascending order of the multiple candidate clock signals. And / or, When the clock signal needs to be up-frequencyed, based on the principle that the rising edge of the previous candidate clock signal is selected and the falling edge of the next candidate clock signal is selected, starting from the source clock signal, the signal edge corresponding to the current signal edge number of the target clock signal is selected from each candidate clock signal in the order of the second-to-last delayed clock signal to the first delayed clock signal.

4. The clock frequency conversion system according to claim 3, characterized in that, The plurality of AND gates are used for: When the clock signal needs to be down-clocked, based on the principle that the rising edge of the previous candidate clock signal is selected and the falling edge of the next candidate clock signal is selected, the clock signal is selected cyclically from the first AND gate to the last AND gate in order, and the signal edge corresponding to the current signal edge number of the target clock signal is selected from the candidate clock signals input by each AND gate. And / or, when the clock signal needs to be up-frequencyed, based on the principle that the rising edge of the previous candidate clock signal is selected and the falling edge of the next candidate clock signal is selected, starting from the first AND gate, in the order from the last AND gate to the second AND gate, the signal edge corresponding to the current signal edge number of the target clock signal is selected from the candidate clock signals input to each AND gate in a cyclical manner.

5. The clock frequency conversion system according to claim 3 or 4, characterized in that, When it is necessary to reduce the frequency of the clock signal, the frequency of the target clock signal is reduced by 1 / (1+2 / N) times relative to the source clock signal, where N is the number of the plurality of delayed clock signals; When it is necessary to upscale the clock signal, the frequency of the target clock signal is increased by 1 / (1-2 / N) times relative to the source clock signal.

6. The clock frequency conversion system according to claim 1, characterized in that, The delay-locked loop circuit includes: multiple delay units, a phase comparator, and a delay control circuit; The multiple delay units are used to iteratively adjust the delay of the clock signal starting from the source clock signal to obtain multiple delayed clock signals with different phases. The phase comparator is used to input a source clock signal and a last delayed clock signal, compare the phase relationship between the last delayed clock signal and the source clock signal, and output control information based on the compared phase relationship. The delay control circuit is used to control the delay size of the delay unit based on the control information output by the phase comparator.

7. The clock frequency conversion system according to claim 6, characterized in that, The phase comparator is used to output control information based on the compared phase relationship, including: If the phase of the last delayed clock signal leads the phase of the source clock signal, output the first control information; if the phase of the last delayed clock signal lags the phase of the source clock signal, output the second control information. The delay control circuit is used to control the delay size of the delay unit based on the control information output by the phase comparator, including: Based on the first control information, the delay size of the delay unit is increased; and based on the second control information, the delay size of the delay unit is decreased.

8. The clock frequency conversion system according to any one of claims 6-7, characterized in that, A delay unit adjusts the delay of the input clock signal and outputs a phase-changing delayed clock signal accordingly. The clock signal input to the next delay unit is the delayed clock signal output by the previous delay unit, and the clock signal input to the first delay unit is the source clock signal.

9. The clock frequency conversion system according to claim 1, characterized in that, The delay between the last delayed clock signal and the source clock signal is one clock cycle, and the phase difference between adjacent delayed clock signals is one clock cycle divided by N, where N is the number of the multiple delayed clock signals.

10. A clock frequency conversion method, characterized in that, Applied to the clock frequency conversion system as described in any one of claims 1-9, comprising: Generate source clock signal; Based on the source clock signal, multiple iterations of delay processing are performed to obtain multiple delayed clock signals with different phases; wherein, the last delayed clock signal is aligned with the source clock signal, and the phase difference between adjacent delayed clock signals varies uniformly; the source clock signal and some delayed clock signals form multiple candidate clock signals; the multiple candidate clock signals include: the source clock signal, and N clock signals from the first delayed clock signal to the second-to-last delayed clock signal; The clock selection circuit selects a signal edge from the plurality of candidate clock signals, and forms a frequency-converted target clock signal from the selected signal edge; the clock selection circuit, used to select a signal edge from the plurality of candidate clock signals, includes: The signal edge is selected from each candidate clock signal in a cyclical manner according to the set order of the candidate clock signals, and one signal edge is selected from each candidate clock signal at a time; wherein the set order is the order in which the phase difference between adjacent candidate clock signals changes uniformly.

11. A processor, characterized in that, The processor includes the clock conversion system as described in any one of claims 1-9.

12. A chip, characterized in that, The chip includes the processor as described in claim 11.

13. An electronic device, characterized in that, The electronic device includes the chip as described in claim 12.

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