Image sensor and method of operating the same

Abstract

An image sensor and an operating method thereof are disclosed. The image sensor includes a pixel array including a plurality of pixels arranged in a matrix, each pixel including a microlens, a first photoelectric conversion element, and a second photoelectric conversion element, the first photoelectric conversion element and the second photoelectric conversion element being arranged in parallel with each other in a first direction under the microlens; and a row decoder configured to control sequential output of a first image signal generated by the first photoelectric conversion element and a sum image signal generated by the first photoelectric conversion element and the second photoelectric conversion element from a first pixel in a first row of the pixel array during a first readout period, and to control sequential output of a second image signal generated by the second photoelectric conversion element and the sum image signal from a second pixel in a second row of the pixel array during a second readout period.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0115654, filed on September 9, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to an image sensor, and more specifically, to an image sensor that performs an autofocus function and a method for reading the image sensor. Background Technology

[0004] Recently, autofocus (AF), which automatically detects the focus of an image sensor, has been widely used.

[0005] Due to its fast focus detection speed, phase difference autofocus (PAF) technology has been extensively researched and developed. PAF technology separates the light passing through the photographic lens, detects the light at different positions, and controls the focal length by automatically driving the focusing lens, ensuring that the detected signals have the same intensity in one phase. Typically, autofocus settings are performed using an AF sensor much smaller than the image sensor, or by incorporating focus detection pixels (in addition to image detection pixels) within a portion of the image sensor using an AF module within the image sensor. Recently, research has been conducted on improving focus detection speed by forming a pair of photoelectric conversion elements using focus detection pixels or entirely using image detection pixels. Focus detection speed and accuracy can be improved by performing PAF detection on each pixel or specific neighboring pixels. Summary of the Invention

[0006] One or more example embodiments provide an image sensor for providing high frame rate and high-speed autofocus capabilities, as well as a method of operating the image sensor.

[0007] According to an aspect of example embodiments, there is provided an image sensor including: a pixel array including a plurality of pixels arranged in a matrix, each of the plurality of pixels including a microlens, a first photoelectric conversion element, and a second photoelectric conversion element, the first photoelectric conversion element and the second photoelectric conversion element being arranged in parallel with each other in a first direction below the microlens; and a row decoder configured to control sequential output of a first image signal and a first sum image signal from a first pixel in a first row of the pixel array during a first readout period, the first image signal being generated by the first photoelectric conversion element of the first pixel, and the first sum image signal being generated by the first photoelectric conversion element and the second photoelectric conversion element of the first pixel, and control sequential output of a second image signal and a second sum image signal from a second pixel in a second row of the pixel array during a second readout period, the second image signal being generated by the second photoelectric conversion element of the second pixel, and the second sum image signal being generated by the first photoelectric conversion element and the second photoelectric conversion element of the second pixel.

[0008] According to an aspect of example embodiments, there is provided an image sensor including: a pixel array including a plurality of rows extending in a first direction, a plurality of columns extending in a second direction perpendicular to the first direction, and a plurality of pixels connected to the plurality of rows and the plurality of columns and arranged in a matrix, each of the plurality of pixels including a first sub-pixel and a second sub-pixel arranged in parallel with each other in a third direction; and a row decoder configured to provide a plurality of first control signals to a first pixel in a first row of the pixel array, and provide a plurality of second control signals to a second pixel in a second row of the pixel array, wherein the pixel array is configured to: during a first readout period, in response to the plurality of first control signals, output, through a first column, a first image signal from the first sub-pixel of the first pixel, and output a first sum image signal from the first sub-pixel and the second sub-pixel of the first pixel; and during a second readout period, in response to the plurality of second control signals, output, through the first column, a second image signal from the second sub-pixel of the second pixel, and output a second sum image signal from the first sub-pixel and the second sub-pixel of the second pixel.

[0009] According to an aspect of the example embodiments, there is provided an image sensor, comprising: a pixel array comprising a plurality of first pixels in a first row and a plurality of second pixels in a second row, each of the plurality of first pixels and each of the plurality of second pixels comprising first and second photoelectric conversion elements arranged in parallel with each other in a first direction; a row decoder configured to provide a plurality of first control signals to the plurality of first pixels through a plurality of first row lines and to provide a plurality of second control signals to the plurality of second pixels through a plurality of second row lines; and a readout circuit configured to receive a plurality of pixel signals from the pixel array through a plurality of column lines to perform analog-to-digital conversion on the plurality of pixel signals, wherein each of the plurality of first pixels is configured to sequentially output, during a first readout period, a first reset signal from the first photoelectric conversion element of each first pixel, a first image signal, and a first sum image signal from the first and second photoelectric conversion elements of each first pixel to the readout circuit as first pixel signals, and wherein each of the plurality of second pixels is configured to sequentially output, during a second readout period, a second reset signal from the second photoelectric conversion element of each second pixel, a second image signal, and a second sum image signal from the first and second photoelectric conversion elements of each second pixel to the readout circuit as second pixel signals.

[0010] According to an aspect of the example embodiments, there is provided a method of operating an image sensor comprising a pixel array, the method comprising: outputting a first image signal from a first photoelectric conversion element of a first pixel in a first row of the pixel array, the first pixel comprising first and second photoelectric conversion elements arranged in parallel with each other in a first direction; outputting a first sum image signal from the first and second photoelectric conversion elements of the first pixel; outputting a second image signal from a second photoelectric conversion element of a second pixel in a second row of the pixel array, the second pixel comprising first and second photoelectric conversion elements arranged in parallel with each other in the first direction; outputting a second sum image signal from the first and second photoelectric conversion elements of the second pixel; and generating autofocus data based on the first and second image signals. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and / or other aspects will be more apparent by describing certain example embodiments, by reference to the accompanying drawings, in which:

[0012] Figure 1 is a block diagram of a digital imaging device according to an example embodiment;

[0013] Figure 2 is a block diagram of an image sensor according to an example embodiment;

[0014] Figure 3 is a diagram of a pixel array according to an example embodiment;

[0015] Figure 4A and Figure 4B are respectively Figure 3 a front view and a vertical sectional view of a pixel of the pixel array of

[0016] Figure 5 is an equivalent circuit diagram of a pixel of the pixel array of Figure 3

[0017] Figure 6 is a timing diagram of an image sensor reading a pixel signal from a pixel of Figure 5

[0018] Figure 7 shows a method of outputting an image signal for generating auto focus data from a pixel array according to an example embodiment;

[0019] Figure 8 is a timing diagram of an image sensor reading a pixel signal from a pixel according to an example embodiment;

[0020] Figure 9 shows transfer of photo charges in a pixel according to a transfer control signal in Figure 8

[0021] Figure 10A and Figure 10B are respectively a schematic block diagram and a schematic timing diagram of a row decoder according to an example embodiment;

[0022] Figure 11A shows a pixel array according to an example embodiment, Figure 11B is a front view of a pixel of the pixel array of Figure 11A

[0023] Figure 12 shows a pixel array according to an example embodiment;

[0024] Figure 13A shows a pixel array according to an example embodiment, Figure 13B is a front view of a pixel of the pixel array of Figure 13A

[0025] Figure 14 is an equivalent circuit diagram of a pixel in Figure 13A

[0026] Figure 15 is a timing diagram of a transfer control signal applied to a pixel array of Figure 13A

[0027] ​​​​​​​Figure 16 is a flowchart of a method of operating an image sensor according to an example embodiment;

[0028] Figure 17 and Figure 18 are block diagrams of an electronic device including a multi-camera module according to example embodiments, respectively; and

[0029] Figure 19 is Figure 17 a detailed block diagram of the camera module in DETAILED DESCRIPTION

[0030] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings.

[0031] Figure 1 is a block diagram of a digital imaging device 1000 according to an example embodiment.

[0032] The digital imaging device 1000 can include an imaging unit 1100, an image sensor 1200, and a processor 1300. The digital imaging device 1000 can have an auto focus function (hereinafter, referred to as an AF function).

[0033] The operation of the digital imaging device 1000 can be controlled by the processor 1300. The processor 1300 can provide each of the lens driver 1120, the aperture driver 1140, and the controller 1220 with a control signal for the operation of each corresponding element.

[0034] The imaging unit 1100 receives light and can include a lens 1110, a lens driver 1120, an aperture 1130, and an aperture driver 1140. The lens 1110 can include a plurality of lenses.

[0035] The lens driver 1120 can exchange information about focus detection with the processor 1300 and can control the position of the lens 1110 according to a control signal from the processor 1300. The lens driver 1120 can control the position of the lens 1110 by moving the lens 1110. For example, the lens driver 1120 can move the lens 1110 in a direction away from or toward the object 5000, thereby controlling the distance between the lens 1110 and the object 5000. According to the position of the lens 1110, the object 5000 can be in focus or out of focus.

[0036] The image sensor 1200 can convert incident light into an image signal. The image sensor 1200 can include a pixel array 1210, a controller 1220, and a signal processor 1230. When a light signal that has passed through the lens 1110 and the aperture 1130 reaches a light-receiving surface of the pixel array 1210, the light signal can form an image of the object 5000.

[0037] The pixel array 1210 can include a complementary metal-oxide semiconductor (CMOS) image sensor (CIS) that converts a light signal into an electrical signal. The sensitivity of the pixel array 1210, etc. can be controlled by the controller 1220. The pixel array 1210 can include a plurality of pixels in a matrix. Each pixel can include a micro lens and at least two photoelectric conversion elements arranged in parallel with each other under the micro lens. Each pixel can include at least one first photoelectric conversion element and at least one second photoelectric conversion element in parallel with each other. The pixel can output a first image signal generated by the first photoelectric conversion element or a second image signal generated by the second photoelectric conversion element. The pixel can output a sum image signal generated by the first photoelectric conversion element and the second photoelectric conversion element.

[0038] The signal processor 1230 can generate a pair of phase detection signals used in phase difference calculation based on the first image signal and the second image signal output from at least two pixels located in different adjacent rows and a column. In the case of defocus, the phase of the first image signal can be different from the phase of the second image signal. For example, the intensity of the first image signal can be different from the intensity of the second image signal. In the case of focus, the phase of the first image signal can be the same as the phase of the second image signal.

[0039] The signal processor 1230 can generate a plurality of pairs of phase detection signals based on a plurality of first image signals and a plurality of second image signals output from the pixel array 1210. The pair of phase detection signals or first and second images generated based on the pair of phase detection signals can be provided to the processor 1300 as auto focus data.

[0040] The processor 1300 can receive image data from the image sensor 1200. The image data can include images in units of frames and / or auto focus data. The processor 1300 can perform phase difference calculation for AF function using the auto focus data. In an example embodiment, the processor 1300 can perform phase difference calculation based on a plurality of pairs of phase detection signals included in the auto focus data. For example, the processor 1300 can generate a first image based on a plurality of first phase detection signals among the pair of phase detection signals and generate a second image based on a plurality of second phase detection signals among the pair of phase detection signals, and can calculate a phase difference between the first image and the second image.

[0041] Through the phase difference calculation, the processor 1300 can obtain a position of a focus point at which intensities of two phase detection signals included in the pair of phase detection signals are the same as each other (i.e., the phase of the first image is the same as the phase of the second image), a direction of the focus point, and / or a distance between the object 5000 and the image sensor 1200.

[0042] The processor 1300 can generate a control signal for controlling the lens driver 1120 to move the lens 1110 based on the phase difference calculation result, and can output the control signal to the lens driver 1120.

[0043] Figure 2 is a block diagram of an image sensor 100 according to an example embodiment.

[0044] The image sensor 100 can be mounted on an electronic device having an image or optical sensing function, and in particular, can be mounted on an electronic device having an AF function. For example, the image sensor 100 can be mounted on an electronic device such as a camera, a smart phone, a wearable device, an Internet of Things (IoT) device, a tablet personal computer (PC), a personal digital assistant (PDA), a portable multimedia player (PMP), or a navigation device. The image sensor 100 can also be mounted on an electronic device serving as a component of a vehicle, furniture, a manufacturing facility, a door, or various measuring equipment.

[0045] The image sensor 100 can include a pixel array 110, a row decoder 120, a ramp signal generator 130, a comparator circuit 140, a clock signal generator 150, a counter circuit 160, a timing controller 170, a column decoder 180, and a signal processor 190. The comparator circuit 140 and the counter circuit 160 can be referred to as a readout circuit (or an analog-to-digital converter circuit).

[0046] The pixel array 110 can include a plurality of row lines RL, a plurality of column lines CL, and a plurality of pixels PX connected to the row lines RL and the column lines CL and arranged in a matrix.

[0047] The pixel PX can sense incident light and output an image signal, i.e., an electrical signal corresponding to the sensed light, using a photoelectric conversion element. The pixel PX can include a red pixel, a green pixel, and a blue pixel. The red pixel can generate an image signal (or charge) corresponding to a red signal in response to a wavelength in a red range of a visible light spectrum. The green pixel can generate an image signal (or charge) corresponding to a green signal in response to a wavelength in a green range of the visible light spectrum. The blue pixel can generate an image signal (or charge) corresponding to a blue signal in response to a wavelength in a blue range of the visible light spectrum. However, embodiments are not limited thereto, and the pixel PX can also include a white pixel. For example, the pixel PX can include a cyan pixel, a yellow pixel, a magenta pixel, or a white pixel.

[0048] A microlens and a color filter can be disposed (e.g., stacked) over each pixel PX. The plurality of color filters of a pixel PX can form a color filter array. The color filter can pass light of a specific color (i.e., a wavelength in a specific color range) among light incident through the microlens. The color sensed by the pixel PX can be determined according to the color filter provided in correspondence with the pixel PX. However, embodiments are not limited thereto. According to an example embodiment, light corresponding to a wavelength in a color range can be converted into an electrical signal according to a level (e.g., a voltage level) of an electrical signal applied to a photoelectric conversion element of the pixel PX, and thus, the color sensed by the pixel PX can be determined according to the level of the electrical signal applied to the photoelectric conversion element.

[0049] Each pixel PX can include at least two photoelectric conversion elements (referred to as a photosensitive element). For example, the photoelectric conversion element can include a photodiode, a phototransistor, a photogate, or a pinned photodiode. The at least two photoelectric conversion elements can independently generate photocharges, and thus, independent image signals.

[0050] Each pixel PX can include a first photoelectric conversion element positioned to the left (or above) of an optical axis of the microlens and a second photoelectric conversion element positioned to the right (or below) of the optical axis of the microlens. Each pixel PX can output a first image signal generated by the first photoelectric conversion element or a second image signal generated by the second photoelectric conversion element. In two pixels PX in one column and two adjacent rows, one pixel PX can output a first image signal generated by a first photoelectric conversion element, and the other pixel PX can output a second image signal generated by a second photoelectric conversion element. At this time, the two pixels PX can sense the same color. Automatic focus data used in phase difference calculation for an AF function, for example, a pair of phase detection signals, can be generated based on the first image signal and the second image signal respectively output from the two pixels PX.

[0051] The pixel PX can output a sum image signal generated by the at least one first photoelectric conversion element and the at least one second photoelectric conversion element. The sum image signal can generate an image for each frame.

[0052] The row decoder 120 can generate a plurality of control signals controlling the operation of the pixels PX in each row under the control of the timing controller 170. The row decoder 120 can provide the control signals to the pixels PX of the pixel array 110 through the row lines RL. The pixel array 110 can be driven row by row in response to the control signals from the row decoder 120. In other words, the pixels PX of the pixel array 110 can sequentially output pixel signals row by row. At this time, the pixel signals can include a reset signal indicating a reset level of the pixel PX and an image signal generated by a photoelectric conversion element.

[0053] The ramp signal generator 130 can generate a ramp signal RAMP (e.g., a ramp voltage) whose level increases or decreases at a certain slope under the control of the timing controller 170. The ramp signal RAMP can be provided to each of the plurality of comparators 141 of the comparator circuit 140.

[0054] The comparator circuit 140 can include comparators 141 and can convert a plurality of pixel signals received from the pixel array 110 through the column line CL into a plurality of digital signals. Each of the comparators 141 can convert a pixel signal into a digital signal based on the ramp signal RAMP. When the level of the ramp signal RAMP is the same as the level of the pixel signal, each of the comparators 141 can output a comparison signal that transitions from a first level (e.g., a logic high) to a second level (e.g., a logic low). The level transition time of the comparison signal can be determined according to the level of the pixel signal.

[0055] The comparator 141 can include a circuit using correlated double sampling (CDS), e.g., a CDS circuit. The comparator 141 can sample or hold a pixel signal from the pixel PX, can double sample the level of a certain noise (e.g., a reset signal) and the level of an image signal, and can generate a comparison signal based on the difference between the double-sampled levels. For example, the comparator 141 can include at least one operational transconductance amplifier (OTA) (or a differential amplifier), two sample-and-hold capacitors connected to two input terminals of the OTA, respectively, and two switches that connect the two input terminals of the OTA to two output terminals of the OTA, respectively, in an auto-zero operation. Here, the reset noise of the pixel signal and the offset of the comparator 141 can be removed by the auto-zero operation.

[0056] The clock signal generator 150 can generate a count clock signal CCLK to be provided to the counter circuit 160. The generation timing and frequency of the count clock signal CCLK can be controlled by the timing controller 170. In an example embodiment, the clock signal generator 150 can include a Gray code generator. The clock signal generator 150 can generate a plurality of code values as the count clock signal CCLK, the plurality of code values having resolution according to a set number of bits. For example, when a 10-bit code is set, the clock signal generator 150 can generate a count clock signal CCLK including 1024 code values. When an 11-bit code is set, the clock signal generator 150 can generate a count clock signal CCLK including 2048 code values.

[0057] The counter circuit 160 can include a plurality of counters (CNTR) 161. Each counter 161 can count a level transition time of a comparison signal output from the corresponding comparator 141 based on a count clock signal CCLK, and can output a count value. In an example embodiment, each counter 161 can include a latch circuit and an operation circuit. The latch circuit can latch a code value received as the count clock signal CCLK at a level transition time of a comparison signal of the comparator 141. The latch circuit can latch a code value of a reset value corresponding to a reset signal and a code value of an image signal value corresponding to an image signal, for example. The operation circuit can perform an operation on the reset value and the image signal value, and thus generate an image signal value from which a reset level of the pixel PX is removed. The counter 161 can output the image signal value from which the reset level is removed as a pixel value. However, embodiments are not limited thereto. The counter 161 can include an operation circuit and an up counter that increases a count value based on the count clock signal CCLK, or can include an up / down counter, or a bit-wise inverting counter.

[0058] In an example embodiment, the counter circuit 160 can include a plurality of memories 162. The memories 162 can store pixel values output from the counters 161, respectively. The memories 162 can include static random access memories (SRAMs), latches, flip-flops, or a combination thereof, but are not limited thereto.

[0059] The column decoder 180 can control an output timing of the pixel values stored in each memory 162 under the control of the timing controller 170. In an example embodiment, the memory 162 can sequentially output the pixel values under the control of the column decoder 180. The pixel values can be output to the outside of the image sensor 100 or to the signal processor 190.

[0060] The timing controller 170 can generate a control signal for controlling operations of the row decoder 120, the ramp signal generator 130, the comparator circuit 140, the clock signal generator 150, the counter circuit 160, and the column decoder 180. The timing controller 170 can be implemented as Figure 1 a controller 1220 in FIG. 12B or a part of the controller 1220.

[0061] The signal processor 190 can perform signal processing on image data (e.g., a plurality of pixel values) received from the counter circuit 160. The signal processor 190 can generate auto focus data based on a plurality of first pixel values (e.g., a plurality of first image signal values) corresponding to a plurality of first image signals and a plurality of second pixel values (e.g., a plurality of second image signal values) corresponding to a plurality of second image signals.

[0062] The signal processor 190 can perform noise reduction, gain tuning, wave shaping, interpolation, white balancing, gamma processing, edge enhancement, binning, etc. on the image data. In an example embodiment, the signal processor 190 can be provided in a processor 1300 outside the image sensor 100. Figure 1 ).

[0063] Figure 3 is a diagram of a pixel array according to an example embodiment.

[0064] Referring to Figure 3 , the pixel array 110a includes a plurality of pixels PXa in a matrix. For example, the pixels PXa can include a plurality of green pixels G, a plurality of blue pixels B, and a plurality of red pixels R. Two green pixels G, one blue pixel B, and one red pixel R can be arranged in a 2x2 matrix, and the two green pixels G can be arranged in a diagonal direction. This pixel pattern can be repeated in the pixel array 110a. Although 16 pixels PXa are arranged in the first row ROW1, the second row ROW2, the third row ROW3, and the fourth row ROW4 and the first column COL1, the second column COL2, the third column COL3, and the fourth column COL4 in Figure 3 , this is merely an example for convenience of description. The number of pixels PXa can be determined according to the resolution of the pixel array 110a.

[0065] Each of the pixels PXa can include a microlens ML and two sub-pixels, e.g., a first sub-pixel SPX1 and a second sub-pixel SPX2. A sub-pixel, e.g., the first sub-pixel SPX1 or the second sub-pixel SPX2, can refer to a single photoelectric conversion element or a structure (or circuit) involving a single photoelectric conversion element and another element connected to the single photoelectric conversion element one on top of the other. The first sub-pixel SPX1 and the second sub-pixel SPX2 can be parallel to each other in a row direction (e.g., an X-axis direction (e.g., a first direction)). For example, the first sub-pixel SPX1 can be located at the left side of each pixel PXa, and the second sub-pixel SPX2 can be located at the right side of each pixel PXa.

[0066] The first sub-pixel SPX1 of the corresponding pixel PXa can operate in response to a plurality of first transfer control signals TG11, TG21, TG31, and TG41. The second sub-pixel SPX2 of the corresponding pixel PXa can operate in response to a plurality of second transfer control signals TG12, TG22, TG32, and TG42. Each of the operations in the first sub-pixel SPX1 and the second sub-pixel SPX2 indicates that photocharges generated by a photoelectric conversion element (e.g., a first photodiode PD1 or a second photodiode PD2 in Figure 4A the first sub-pixel SPX1 or the second sub-pixel SPX2) are transferred to a floating diffusion node FD of the pixel PXa.Figure 4B ).

[0067] The first transfer control signals TG11, TG21, TG31, and TG41 and the second transfer control signals TG12, TG22, TG32, and TG42 can be respectively supplied from the row decoder 120 (see FIG. 1) through corresponding row lines RL. Figure 2 The first sub-pixel SPX1 of the pixel PXa in a row can receive one of the first transfer control signals TG11, TG21, TG31, and TG41 through one row line RL, and the second sub-pixel SPX2 of the pixel PXa in the row can receive one of the second transfer control signals TG12, TG22, TG32, and TG42 through one row line RL. The connection relationship between the row line RL and the sub-pixel (e.g., the first sub-pixel SPX1 or the second sub-pixel SPX2) is indicated by the connection CNT in FIG. 1. Figure 3

[0068] During a plurality of readout periods (referred to as horizontal periods), a plurality of rows (e.g., the first row ROW1 to the fourth row ROW4) of the pixel array 110a can be sequentially read out. In other words, a plurality of signals can be read out row by row from the plurality of pixels PXa arranged in the first row ROW1 to the fourth row ROW4. For example, a pixel signal can be output from the pixels PXa in the first row ROW1 during a first readout period, a pixel signal can be output from the pixels PXa in the second row ROW2 during a second readout period, a pixel signal can be output from the pixels PXa in the third row ROW3 during a third readout period, and a pixel signal can be output from the pixels PXa in the fourth row ROW4 during a fourth readout period. However, embodiments are not limited thereto. The order of reading out the plurality of rows can be changed.

[0069] The pixel array 110a can be divided into a plurality of pixel groups PG. Each pixel group PG can include at least two 2x2 matrixes of pixel patterns adjacent to each other in the Y-axis direction (e.g., the second direction). For example, the pixel group PG can include the pixels PXa in the 2x4 matrix shown in FIG. 2. Each pixel group PG can be a pixel unit for generating auto-focus data. For example, the auto-focus data, such as a pair of phase detection signals for phase difference calculation for adjusting a focus in left and right directions, can be generated based on a first image signal (e.g., a left image signal) and a second image signal (e.g., a right image signal) generated by the pixels PXa of each pixel group PG. At this time, the first image signal generated by the first sub-pixel SPX1 can be output from the pixels PXa in a certain row among the plurality of rows (e.g., the first row ROW1 to the fourth row ROW4), and the second image signal generated by the second sub-pixel SPX2 can be output from the pixels PXa in another certain row among the plurality of rows. Figure 3

[0070] Figure 4A ​​and Figure 4B are Figure 3 front view and vertical sectional view of a pixel of a pixel array. Figure 4B is a vertical sectional view taken along Figure 4A line A-A' in

[0071] Referring to Figure 4A and Figure 4B , a color filter CF and a microlens ML can be located on or above the first photodiode PD1 and the second photodiode PD2. The first sub-pixel SPX1 can include the first photodiode PD1, and the second sub-pixel SPX2 can include the second photodiode PD2.

[0072] The pixel PXa can include a first layer L1 and a second layer L2 stacked in a Z-axis direction (e.g., a third direction). The first layer L1 can be referred to as a photoelectric conversion layer, and can include the color filter CF and the microlens ML located on the substrate SUB and two photoelectric conversion elements (e.g., the first photodiode PD1 and the second photodiode PD2) located in the substrate SUB. The second layer L2 can be referred to as a wiring layer. A plurality of wirings WS can be formed in the second layer L2.

[0073] The substrate SUB can include a silicon wafer, a silicon-on-insulator (SOI) substrate, or a semiconductor epitaxial layer. The substrate SUB can include a first surface Sf and a second surface Sb facing each other. For example, the first surface Sf can be a front surface of the substrate SUB, and the second surface Sb can be a back surface of the substrate SUB. Light can be incident on the second surface Sb.

[0074] A plurality of pixel separation films (e.g., deep trench isolation (DTI) or P-type ion implantation regions) are formed in the substrate SUB to extend from the second surface Sb of the substrate SUB toward the first surface Sf of the substrate SUB. A pixel region APX in which the pixel PXa is formed is defined by a plurality of first pixel separation films SEP1 that are relatively long among the pixel separation films. The pixel region APX is divided into a first region A1 and a second region A2 by a second pixel separation film SEP2 that is relatively short among the pixel separation films, and the first sub-pixel SPX1 and the second sub-pixel SPX2 are respectively formed in the first region A1 and the second region A2. In an example embodiment, the first region A1 and the second region A2 can be doped with a first conductivity type (e.g., P-type) impurity. The first photodiode PD1 and the second photodiode PD2 can be respectively formed in the first region A1 and the second region A2. For example, a well region doped with a second conductivity type (e.g., N-type) impurity can be formed as the first photodiode PD1 and the second photodiode PD2.

[0075] As Figure 4BAs shown, the first photodiode PD1 and the second photodiode PD2 can be parallel to each other in a first direction (e.g., an X-axis direction) or a second direction (e.g., a Y-axis direction) with respect to an optical axis MLX of the microlens ML.

[0076] A floating diffusion node FD can be formed between the first photodiode PD1 and the second photodiode PD2. In an example embodiment, gate terminals and source terminals (not shown) of transistors (e.g., TX1, TX2, RX, DX, and SX in Figure 5 The gate terminals and the source terminals (not shown) of the transistors (e.g., TX1, TX2, RX, DX, and SX in Figure 5 The gate terminals and the source terminals (not shown) of the transistors (e.g., TX1, TX2, RX, DX, and SX in Figure 5 The gate terminals and the source terminals (not shown) of the transistors (e.g., TX1, TX2, RX, DX, and SX in

[0077] Figure 5 is an equivalent circuit diagram of the pixel of Figure 3

[0078] Referring to Figure 5 The pixel PXa can include a first photodiode PD1, a second photodiode PD2, a first transfer transistor TX1, a second transfer transistor TX2, a reset transistor RX, a drive transistor DX, and a selection transistor SX.

[0079] A floating diffusion node FD (referred to as a floating diffusion region) can be shared by the first photodiode PD1, the second photodiode PD2, the first transfer transistor TX1, and the second transfer transistor TX2. The first photodiode PD1 and the first transfer transistor TX1 can be referred to as a first sub-pixel SPX1, and the second photodiode PD2 and the second transfer transistor TX2 can be referred to as a second sub-pixel SPX2.

[0080] Each of the first photodiode PD1 and the second photodiode PD2 can generate photocharges whose amount varies with intensity of light. For example, each of the first photodiode PD1 and the second photodiode PD2 can include a P-N junction diode and can generate charges that are proportional to an amount of incident light, i.e., electrons corresponding to negative charges and holes corresponding to positive charges. Each of the first photodiode PD1 and the second photodiode PD2 is an example of a photoelectric conversion element and can include at least one selected from among a phototransistor, a photogate, a pinned photodiode (PPD), and combinations thereof.

[0081] ​The floating diffusion node FD can operate as a capacitor. When the first transfer transistor TX1 is turned on in response to a first transfer control signal TG1 applied to its gate, the charge (e.g., photocharge) generated by the first photodiode PD1 can be transferred to and stored in the floating diffusion node FD. The second transfer transistor TX2 can be turned on in response to a second transfer control signal TG2 applied to its gate, and can thus transfer the charge generated by the second photodiode PD2 to the floating diffusion node FD. The first transfer control signal TG1 and the second transfer control signal TG2 can be separate signals, and therefore, the turn-on timing of the first transfer transistor TX1 and the second transfer transistor TX2 can be independently controlled by the first transfer control signal TG1 and the second transfer control signal TG2, respectively.

[0082] The reset transistor RX can periodically reset the charge accumulated in the floating diffusion node FD. The source electrode of the reset transistor RX can be connected to the floating diffusion node FD, and its drain electrode can be connected to the supply voltage VPIX. When the reset transistor RX is turned on in response to a reset control signal RS applied to its gate, the supply voltage VPIX connected to the drain electrode of the reset transistor RX is transferred to the floating diffusion node FD. When the reset transistor RX is turned on, the charge accumulated in the floating diffusion node FD is discharged, thereby resetting the floating diffusion node FD.

[0083] The driving transistor DX can operate as a source follower. The driving transistor DX can receive a signal corresponding to the amount of charge in the floating diffusion node FD (i.e., the potential of the floating diffusion node FD) through its gate, and can buffer and output the received signal. The selection transistor SX can be turned on in response to a selection signal SEL applied to its gate. When the selection transistor SX is turned on, the buffered signal output from the driving transistor DX can be output as the pixel signal VOUT through the column line CL.

[0084] Figure 6 According to the example embodiment, from Figure 5 Timing diagram of image sensor 100 that reads pixel signals.

[0085] During the readout period (also known as the horizontal period), it is possible to read from ( Figure 3 In the pixel array 110a, multiple pixel signals VOUT are read from multiple pixels PXa in a row. In other words, pixel signals VOUT can be output from pixels PXa in a row, and the pixel signals VOUT can be read from the readout circuit (e.g., ...). Figure 2 The pixel value (as a digital value) is generated based on the pixel signal VOUT by the comparator circuit 140 and the counter circuit 160 in the circuit.

[0086] Referring to Figure 6 , the readout period can be divided into a first sub-period SP1, a second sub-period SP2, and a third sub-period SP3 according to signals output from the pixel PXa and undergoing analog-digital conversion. During the first sub-period SP1, a reset signal RST (e.g., a reset voltage) corresponding to a reset level can be output as a pixel signal VOUT. During the second sub-period SP2, a first image signal IMG1 (e.g., a first signal voltage) generated by the first photodiode PD1 of the pixel PXa or a second image signal IMG2 (e.g., a second signal voltage) generated by the second photodiode PD2 of the pixel PXa can be output as the pixel signal VOUT. During the third sub-period SP3, a sum image signal SIMG (e.g., a sum signal voltage) generated by the first photodiode PD1 and the second photodiode PD2 of the pixel PXa can be output as the pixel signal VOUT.

[0087] The reset level can be different between the plurality of pixels PXa and can vary with time even in one pixel PXa. Accordingly, the reset signal RST can be first read out from the pixel PXa during the readout period, and then the reset signal RST can be subtracted from (or added to) the image signals (e.g., the first image signal IMG1 (or the second image signal IMG2) and the sum image signal SIMG read out subsequently). As a result, the actual image signals can be obtained, and variations between the image signals output from the plurality of pixels PXa can be reduced.

[0088] As described above, the reset signal RST, the first image signal IMG1 (or the second image signal IMG2), and the sum image signal SIMG generated by the pixel PXa can be sequentially read out during the readout period. This readout method can be referred to as a reset-signal-signal (RSS) readout method.

[0089] In detail, referring to Figure 5 and Figure 6 , the selection signal SEL can be at an active level, e.g., a logic high, during the readout period. The selection transistor SX can be turned on in response to the selection signal SEL and can be connected to the column line CL of the pixel PXa. At this time, the active level of a signal can refer to a level that enables a transistor to which the signal is applied to be turned on. In an example embodiment, it is assumed that the logic high is the active level and the logic low is the deactive level.

[0090] When the readout period starts, the reset control signal RS transitions from logic low to logic high, and thus the reset transistor RX is turned on so that the floating diffusion node FD can be reset. During the first sub-period SP1, the reset signal RST corresponding to the reset level of the floating diffusion node FD can be output as the pixel signal VOUT through the column line CL, and the comparator 141 connected to the column line CL in the readout circuit 140 can compare the ramp signal RAMP with the pixel signal VOUT and output the comparison result as the comparison signal. The level of the ramp signal RAMP decreases at a certain slope. When the level of the ramp signal RAMP is less than the level of the pixel signal VOUT, the level of the comparison signal can flip. During the first sub-period SP1, the comparator 141 can compare the ramp signal RAMP with the reset signal RST received as the pixel signal VOUT and output the comparison signal. Figure 2

[0091] The counter 161 in the readout circuit 140 can count the pixel signal VOUT based on the count clock signal CCLK. In detail, the counter 161 can count the reset signal RST by counting the comparison signal from when the level of the ramp signal RAMP starts to decrease to when the level of the comparison signal flips, i.e., when the level of the ramp signal RAMP is the same as the level of the pixel signal VOUT. In an example embodiment, the counter 161 can receive a Gray code having sequentially increasing code values as the count clock signal CCLK, and can output a code value corresponding to the time when the level of the comparison signal flips as a count value. Figure 2

[0092] During the first sub-period SP1, the reset signal RST can be counted, and a count value corresponding to the level of the reset signal RST (hereinafter, referred to as a reset value) can be stored in an internal latch (or a memory) of the counter 161 in the readout circuit 140 or in the memory 162 in the readout circuit 140. Thus, the reset signal RST can be read during the first sub-period SP1 Figure 2 Figure 2

[0093] During the second sub-period SP2, as the first transfer control signal TG1 transitions to the active level, the charge generated by the first photodiode PD1 can be transferred to the floating diffusion node FD and stored in the floating diffusion node FD. Based on the potential of the floating diffusion node FD according to the amount of charge received from the first photodiode PD1, the drive transistor DX can output the first image signal IMG1, and the first image signal IMG1 can be output as the pixel signal VOUT through the column line CL.

[0094] ​​​​The comparator 141 can compare the first image signal IMG1 with the ramp signal RAMP. The counter 161 can count the first image signal IMG1 by counting the comparison signal output from the comparator 141 based on the count clock signal CCLK. The first image signal IMG1 can be read out by generating a count value (hereinafter, referred to as a first image signal value) corresponding to the level of the first image signal IMG1.

[0095] During the third sub-period SP3, as the first transfer control signal TG1 and the second transfer control signal TG2 transition to the active level, the charges generated by the first photodiode PD1 and the second photodiode PD2 can be transferred to the floating diffusion node FD and stored in the floating diffusion node FD. Based on the potential of the floating diffusion node FD according to the amount of charge, the drive transistor DX can output the sum image signal SIMG, and the sum image signal SIMG can be output through the column line CL as the pixel signal VOUT.

[0096] The comparator 141 can compare the sum image signal SIMG with the ramp signal RAMP. The counter 161 can count the sum image signal SIMG by counting the comparison signal output from the comparator 141 based on the count clock signal CCLK. The sum image signal SIMG can be read out by generating a count value (hereinafter, referred to as a sum image signal value) corresponding to the level of the sum image signal SIMG.

[0097] Because the first image signal IMG1 is generated by one photodiode (e.g., the first photodiode PD1), and the sum image signal SIMG is generated by two photodiodes (e.g., the first photodiode PD1 and the second photodiode PD2), the signal range (e.g., voltage range) of the sum image signal SIMG can be wider than the signal range of the first image signal IMG1. For example, the signal range of the sum image signal SIMG can double the signal range of the first image signal IMG1. Accordingly, the range of code values (i.e., the number of toggled clocks) of the count clock signal CCLK provided during the third sub-period SP3 can be wider than the range of code values provided during the second sub-period SP2. For example, the comparator 141 can count the comparison signal based on N code values CDV during the second sub-period SP2, and can count the comparison signal based on 2N code values CDV during the third sub-period SP3.

[0098] Figure 7 A method of outputting an image signal for generating auto focus data from a pixel array according to an example embodiment is shown.

[0099] Reference is made to Figure 7The first image signal (e.g., an image signal corresponding to the photocharge generated by the first photodiode PD1) can be read out from the first sub-pixel SPX1 located on the left side of each pixel PXa in a particular row among the multiple rows (e.g., the first row ROW1 to the fourth row ROW4). The second image signal (e.g., an image signal corresponding to the photocharge generated by the second photodiode PD2) can be read out from the second sub-pixel SPX2 located on the right side of each pixel PXa in each of the other particular rows among the multiple rows. The autofocus data can be generated based on the first image signal and the second image signal (i.e., the first image signal value and the second image signal value).

[0100] In the example embodiment, in each pixel PXa in the first row ROW1 and the fourth row ROW4, the first image signal can be output from the first sub-pixel SPX1 in response to the first transfer control signal TG11 or TG41. In each pixel PXa in the second row ROW2 and the third row ROW3, the second image signal can be output from the second sub-pixel SPX2 in response to the second transfer control signal TG22 or TG32.

[0101] In the example embodiment, in each pixel PXa in the first row ROW1 and the second row ROW2, the first image signal can be output from the first sub-pixel SPX1 in response to the first transfer control signal TG11 or TG21. In each pixel PXa in the third row ROW3 and the fourth row ROW4, the second image signal can be output from the second sub-pixel SPX2 in response to the second transfer control signal TG32 or TG42.

[0102] For example, the first image signal (e.g., a first red image signal) can be output from the first sub-pixel SPX1 of the red pixel R in the first row ROW1, and the second image signal (e.g., a second red image signal) can be output from the second sub-pixel SPX2 of the red pixel R in the third row ROW3. The pair of phase detection signals corresponding to the red pixels R of the pixel group PG can be generated based on the first red image signal and the second red image signal.

[0103] The second image signal (e.g., a second blue image signal) can be output from the second sub-pixel SPX2 of the blue pixel B in the second row ROW2, and the first image signal (e.g., a first blue image signal) can be output from the first sub-pixel SPX1 of the blue pixel B in the fourth row ROW4. The pair of phase detection signals corresponding to the blue pixels B of the pixel group PG can be generated based on the first blue image signal and the second blue image signal.

[0104] In this way, the autofocus data can be generated based on the plurality of first image signals and the plurality of second image signals output from the plurality of pixel groups PG of the pixel array 110a.

[0105] Figure 8 is a timing chart of an image sensor according to an example embodiment that reads out a pixel signal from a pixel. Figure 9 The transfer of photocharges in a pixel according to an example embodiment is shown. Figure 8 For ease of description, the pixel is assumed to be a pixel PXa in a first row ROW1 of a pixel array 110a. Figure 8 The reset control signal RS, the first and second transfer control signals TG11, TG12, TG21 and TG22, the ramp signal RAMP, the pixel signal VOUT and the count clock signal CCLK during two readout periods (e.g., a first readout period 1H and a second readout period 2H) are shown. As already described above with reference to Figure 6 The method of reading out an image signal from a pixel PXa described above can be applied to an example embodiment.

[0106] With reference to Figure 3 , Figure 5 and Figure 8 , a pixel PXa (hereinafter, referred to as a first pixel) in a row (e.g., a first row ROW1) of the pixel array 110a can output a pixel signal VOUT during a first readout period 1H, and a pixel PXa (hereinafter, referred to as a second pixel) in another row (e.g., a second row ROW2) of the pixel array 110a can output a pixel signal VOUT during a second readout period 2H.

[0107] During respective first sub-periods SP1 of the first readout period 1H and the second readout period 2H, respective reset transistors RX of the first pixel and the second pixel can be turned on in response to a reset signal RST, and thus can each reset a floating diffusion node FD, as shown in Figure 9 The first pixel and the second pixel can each output a reset signal in accordance with the floating diffusion node FD that has been reset. The reset signals of the first pixel and the second pixel and can be counted as the pixel signal VOUT.

[0108] During a second sub-period SP2 of the first readout period 1H, as a first transfer transistor TX1 of the first pixel is turned on in response to a first transfer control signal TG11, charges (or photocharges) generated by the first photodiode PD1 can be transferred to the floating diffusion node FD. The first pixel can output a first image signal IMG1, e.g., a left image signal, corresponding to the charges stored in the floating diffusion node FD. Thus, the first image signal IMG1 can be output from the first photodiode PD1 (or a first sub-pixel SPX1) of the first pixel and counted.

[0109] During the third sub-period SP3 of the first readout period 1H, the first transfer transistor TX1 and the second transfer transistor TX2 of the first pixel can be turned on in response to the first transfer control signal TG11 and the second transfer control signal TG12, respectively, and the charge generated by the second photodiode PD2 (and the charge remaining in the first photodiode PD1) can be transferred to the floating diffusion node FD and stored in the floating diffusion node FD. The charge transferred from the first photodiode PD1 during the second sub-period SP2 and the charge transferred from the second photodiode PD2 during the third sub-period SP3 can be stored in the floating diffusion node FD. The first pixel can output a sum image signal corresponding to the charge stored in the floating diffusion node FD, e.g., a first sum image signal SIMG1. Thus, the first sum image signal SIMG1 can be output from the first pixel and counted. Although Figure 9 Although it is shown that the charge transferred from the second photodiode PD2 during the third sub-period SP3 is stored in the floating diffusion node FD, this is only for ease of description, and the charge remaining in the first photodiode PD1 during the third sub-period SP3 can also be transferred to the floating diffusion node FD and stored in the floating diffusion node FD.

[0110] During the second sub-period SP2 of the second readout period 2H, as the second transfer transistor TX2 of the second pixel is turned on in response to the second transfer control signal TG22, the charge (or photocharge) generated by the second photodiode PD2 can be transferred to the floating diffusion node FD. The second pixel can output a second image signal IMG2 corresponding to the charge stored in the floating diffusion node FD, e.g., a right image signal. Thus, the second image signal IMG2 can be output from the second photodiode PD2 (or the second sub-pixel SPX2) of the second pixel and counted.

[0111] During the third sub-period SP3 of the second readout period 2H, the first transfer transistor TX1 and the second transfer transistor TX2 of the second pixel can be turned on in response to the first transfer control signal TG21 and the second transfer control signal TG22, respectively, and the charge generated by the first photodiode PD1 and the charge generated by the second photodiode PD2 can be transferred to the floating diffusion node FD and stored in the floating diffusion node FD. The second pixel can output a sum image signal corresponding to the charge stored in the floating diffusion node FD, e.g., a second sum image signal SIMG2. Thus, the second sum image signal SIMG2 can be output from the second pixel and counted.

[0112] As described above, during the second sub-period SP2 of the first readout period 1H, the pixel PXa (e.g., the first pixel) in the first row ROW1 can output the first image signal IMG1 (e.g., the left image signal) in response to the first transfer control signal TG11; and during the second sub-period SP2 of the second readout period 2H, the pixel PXa (e.g., the second pixel) in the second row ROW2 can output the second image signal IMG2 (e.g., the right image signal) in response to the second transfer control signal TG22.

[0113] An example in which the pixel signal VOUT is read out from the first row ROW1 during the first readout period 1H and the pixel signal VOUT is read out from the second row ROW2 during the second readout period 2H has been described with reference to Figure 8 However, embodiments are not limited thereto. For example, the pixel signal VOUT can be read out from the first row ROW1 or the fourth row ROW4 in the first readout period 1H, and the pixel signal VOUT can be read out from the second row ROW2 or the third row ROW3 in the second readout period 2H. Figure 3 Alternatively, the pixel signal VOUT can be read out from the first row ROW1 or the second row ROW2 in the first readout period 1H, and the pixel signal VOUT can be read out from the third row ROW3 or the fourth row ROW4 in the second readout period 2H. Figure 3

[0114] As described above, according to example embodiments, in the image sensor 100 and the method of operating the same, each of the plurality of pixels PX of the pixel array 110 can include at least two photoelectric conversion elements, e.g., the first photodiode PD1 and the second photodiode PD2, which are parallel to each other. Each pixel in a certain row can output a first image signal generated from the first photoelectric conversion element, and each pixel of another certain row can output a second image signal generated from the second photoelectric conversion element. Auto focus data for an AF function can be generated based on a first image signal value and a second image signal value obtained by respectively converting digital values of the first image signal and the second image signal.

[0115] In the comparative example, the pixel PX outputs the first image signal (e.g., the left image signal) and the sum image signal, and the second image signal value is calculated by subtracting the first image signal value corresponding to the first image signal from the sum image signal value corresponding to the sum image signal. In this case, in order to avoid signal distortion from occurring in the second image signal value, the sum image signal can be counted during readout of the sum image signal based on a greater number of code values than the number of code values required to count the sum image signal. The increase in the number of code values can indicate an increase in readout time, and thus the time taken to convert the image signal output from the pixel to a digital value can increase.​

[0116] However, according to the example embodiments, in the operation method of the image sensor 100, the first image signal and the second image signal can be read out from at least two adjacent pixels of the same color, and the autofocus data for the AF function can be generated based on the read first image signal and the read second image signal (i.e., the first image signal value and the second image signal value). Thus, the time taken to convert each of the first image signal and the second image signal to a digital value can be reduced without signal distortion, and thus, the frame rate of the image sensor 100 can be increased. In addition, because a plurality of pixels PX of the pixel array 110 (e.g., all of the pixels PX of the pixel array 110) can be used to generate the autofocus data, high-precision autofocus data can be generated. Thus, the imaging apparatus (e.g., the digital imaging apparatus 1000) including the image sensor 100 can perform high-speed autofocus. Figure 1

[0117] Figure 10A and Figure 10B are a schematic block diagram and a schematic timing diagram of the row decoder 120 according to the example embodiments, respectively.

[0118] Referring to Figure 10A , the row decoder 120 can include a pre-decoder 121, a logic circuit 122, and a driver 123.

[0119] The pre-decoder 121 can generate a control signal, e.g., a reset control signal, a transfer control signal, and a selection signal, provided to the pixel array 110( Figure 2 ). The pre-decoder 121 can generate a first reference control signal TGR1 and a second reference control signal TGR2, and can generate a first transfer control signal TG1 and a second transfer control signal TG2 based on the first reference control signal TGR1 and the second reference control signal TGR2.

[0120] ​The predecoder 121 can include a first multiplexer 121-1 and a second multiplexer 121-2. The first multiplexer 121-1 can receive the first reference control signal TGR1 and the second reference control signal TGR2, and can select one of the first reference control signal TGR1 and the second reference control signal TGR2 as the first transfer control signal TG1 based on a toggle enable signal SEN. The second multiplexer 121-2 can select one of the first reference control signal TGR1 and the second reference control signal TGR2 as the second transfer control signal TG2 based on a toggle enable inhibit signal SENB. The toggle enable inhibit signal SENB can have an opposite phase from the toggle enable signal SEN. Thus, one of the first reference control signal TGR1 and the second reference control signal TGR2 can be selected by the first multiplexer 121-1 as the first transfer control signal TG1 and the other of the first reference control signal TGR1 and the second reference control signal TGR2 can be selected by the second multiplexer 121-2 as the second transfer control signal TG2.

[0121] Referring to Figure 10B During a readout period (e.g., the first readout period 1H or the second readout period 2H), the first reference control signal TGR1 and the second reference control signal TGR2 can be toggled from a first level (e.g., logic low) to a second level (e.g., logic high) at least once. The first reference control signal TGR1 can toggle earlier than the second reference control signal TGR2. For example, the first reference control signal TGR1 can toggle during the second sub-period SP2. The second reference control signal TGR2 can toggle during the third sub-period SP3. In an example embodiment, the first reference control signal TGR1 can also toggle during the third sub-period SP3.

[0122] The toggle enable signal SEN can be at the first level (e.g., logic low) during the first readout period 1H. The first multiplexer 121-1 can output the first reference control signal TGR1 as the first transfer control signal TG1 in response to the toggle enable signal SEN, and the second multiplexer 121-2 can output the second reference control signal TGR2 as the second transfer control signal TG2 in response to the toggle enable inhibit signal SENB.

[0123] The toggle enable signal SEN can be at the second level (e.g., logic high) during the second readout period 2H. The first multiplexer 121-1 can output the second reference control signal TGR2 as the first transfer control signal TG1 in response to the toggle enable signal SEN, and the second multiplexer 121-2 can output the first reference control signal TGR1 as the second transfer control signal TG2 in response to the toggle enable inhibit signal SENB.

[0124] The logic circuit 122 can generate the reset control signal, the transfer control signal, and the selection signal for each row in the pixel array 110a based on the control signals (e.g., the reset control signal, the transfer control signal, and the selection signal) received from the pre-decoder 121. For example, the logic circuit 122 can generate the first transfer control signal TG11 and the second transfer control signal TG12 applied to the first row ROW1 during the first readout period 1H and the first transfer control signal TG21 and the second transfer control signal TG22 applied to the second row ROW2 during the second readout period 2H based on the first transfer control signal TG1 and the second transfer control signal TG2 received from the pre-decoder 121. Figure 3 The logic circuit 122 can generate the reset control signal, the transfer control signal, and the selection signal for each row in the pixel array 110a based on the control signals (e.g., the reset control signal, the transfer control signal, and the selection signal) received from the pre-decoder 121. For example, the logic circuit 122 can generate the first transfer control signal TG11 and the second transfer control signal TG12 applied to the first row ROW1 during the first readout period 1H and the first transfer control signal TG21 and the second transfer control signal TG22 applied to the second row ROW2 during the second readout period 2H based on the first transfer control signal TG1 and the second transfer control signal TG2 received from the pre-decoder 121.

[0125] The driver 123 can level-shift the control signals (e.g., the reset control signal, the transfer control signal, and the selection signal) for each row received from the logic circuit 122 based on the power supply voltage corresponding to the activation level or the deactivation level, and can output the level-shifted control signals to the pixel array 110a.

[0126] Figure 11A A pixel array 110b according to an example embodiment is shown. Figure 11B is a front view of a pixel of the pixel array Figure 11A Figure 11A The pixel array 110b of FIG. 10 can be a modified form of the pixel array 110a of FIG. 9. Thus, the pixel array 110b will be described focusing on the differences from the pixel array 110a. Figure 3 Referring to FIG. 10,

[0127] and Figure 11A Each of the plurality of pixels PXb can include a microlens ML and two sub-pixels, e.g., a first sub-pixel SPX1 and a second sub-pixel SPX2. The first sub-pixel SPX1 and the second sub-pixel SPX2 can be parallel to each other in a column direction (e.g., a Y-axis direction (e.g., the second direction)). For example, the first sub-pixel SPX1 can be located at a top of each pixel PXb, and the second sub-pixel SPX2 can be located at a bottom of each pixel PXb. The first sub-pixel SPX1 and the second sub-pixel SPX2 can include a first photodiode PD1 and a second photodiode PD2, respectively. Figure 11B The first sub-pixel SPX1 of the corresponding pixel PXb can operate in response to the plurality of first transfer control signals TG11, TG21, TG31, and TG41. The second sub-pixel SPX2 of the corresponding pixel PXb can operate in response to the plurality of second transfer control signals TG12, TG22, TG32, and TG42.

[0128] As described above with reference to

[0129] Figure 3 to Figure 9 ​​The pixel array 110b can be modified from the pixel array 110a. Thus, the pixel array 110b will be described with emphasis on the differences from the pixel array 110a.

[0130] Figure 12 A pixel array according to an example embodiment is shown. Figure 12 The pixel array 110c can be a modified form of the pixel array 110b. Figure 3 The pixel array 110a and Figure 11A The pixel array 110b. Thus, the pixel array 110c will be described with emphasis on the differences from the pixel array 110a and 110b.

[0131] Referring to Figure 12 The pixel array 110c can include a plurality of first type pixels PXa each including a first sub-pixel SPX1 and a second sub-pixel SPX2 parallel to each other in a row direction (e.g., an X-axis direction (e.g., a first direction)) and a plurality of second type pixels PXb each including a first sub-pixel SPX1 and a second sub-pixel SPX2 parallel to each other in a column direction (e.g., a Y-axis direction (e.g., a second direction)). The first type pixels PXa and the second type pixels PXb can be arranged in a row. The first type pixels PXa and the second type pixels PXb in a row (e.g., a first row ROW1) can receive a first transfer control signal TG11 through a same row line RL and a second transfer control signal TG12 through the same row line RL.

[0132] The pixel array 110c can be divided into a plurality of first pixel groups PG1 and a plurality of second pixel groups PG2. The first pixel groups PG1 can include a 2x4 matrix of the first type pixels PXa and the second pixel groups PG2 can include a 2x4 matrix of the second type pixels PXb.

[0133] Pixel signals can be read from pixel array 110c. A first image signal generated by a first sub-pixel SPX1 can be output from a first type pixel PXa in a specific row from the first row ROW1 to the fourth row ROW4, and a third image signal generated by the first sub-pixel SPX1 can be output from a second type pixel PXb in the same specific row. A second image signal generated by a second sub-pixel SPX2 can be output from a first type pixel PXa in another specific row from the first row ROW1 to the fourth row ROW4, and a fourth image signal generated by the second sub-pixel SPX2 can be output from a second type pixel PXb in the same other specific row. The first and second image signals can correspond to the left and right image signals, respectively, and the third and fourth image signals can correspond to the top and bottom image signals, respectively.

[0134] A phase detection signal pair for calculating the phase difference in adjusting the focus in the left and right directions can be generated based on a first image signal and a second image signal generated from a first type pixel PXa of the first pixel group PG1. A phase detection signal pair for calculating the phase difference in adjusting the focus in the vertical direction can be generated based on a third image signal and a fourth image signal generated from a second type pixel PXb of the second pixel group PG2.

[0135] Although Figure 12 The document describes a pixel array 110c comprising a first type of pixel PXa in which first sub-pixels SPX1 and second sub-pixels SPX2 are parallel to each other in the row direction, and a second type of pixel PXb in which first sub-pixels SPX1 and second sub-pixels SPX2 are parallel to each other in the column direction; however, embodiments are not limited thereto. In an example embodiment, pixel array 110c may include a third type of pixel in which first sub-pixels SPX1 and second sub-pixels SPX2 are arranged in the upper-left direction (or lower-right direction), and a fourth type of pixel in which first sub-pixels SPX1 and second sub-pixels SPX2 are arranged in the upper-right direction (or lower-left direction).

[0136] Figure 13A A pixel array according to an example embodiment is shown. Figure 13B yes Figure 13A The front view of the pixels of the pixel array.

[0137] Reference Figure 13A and Figure 13BEach of the plurality of pixels PXc can include a microlens ML and four sub-pixels, e.g., a first sub-pixel SPX1, a second sub-pixel SPX2, a third sub-pixel SPX3, and a fourth sub-pixel SPX4. The first sub-pixel SPX1 can be located at a left top of each pixel PXc, the second sub-pixel SPX2 can be located at a right top of the pixel PXc, the third sub-pixel SPX3 can be located at a left bottom of the pixel PXc, and the fourth sub-pixel SPX4 can be located at a right bottom of the pixel PXc. In other words, the first sub-pixel SPX1 and the third sub-pixel SPX3 can be parallel to the second sub-pixel SPX2 and the fourth sub-pixel SPX4, respectively, in a row direction (e.g., an X-axis direction (or a first direction)), and the first sub-pixel SPX1 and the second sub-pixel SPX2 can be parallel to the third sub-pixel SPX3 and the fourth sub-pixel SPX4, respectively, in a column direction (e.g., a Y-axis direction (or a second direction)).

[0138] Each of the first sub-pixel SPX1, the second sub-pixel SPX2, the third sub-pixel SPX3, and the fourth sub-pixel SPX4 can include a single photoelectric conversion element, e.g., a first photodiode PD1, a second photodiode PD2, a third photodiode PD3, or a fourth photodiode PD4.

[0139] Each of the plurality of first sub-pixels SPX1 of the corresponding pixel PXc can operate in response to one of a plurality of first transfer control signals TG11, TG21, TG31, and TG41. Each of the plurality of second sub-pixels SPX2 of the corresponding pixel PXc can operate in response to one of a plurality of second transfer control signals TG12, TG22, TG32, and TG42. Each of the plurality of third sub-pixels SPX3 of the corresponding pixel PXc can operate in response to one of a plurality of third transfer control signals TG13, TG23, TG33, and TG43. Each of the plurality of fourth sub-pixels SPX4 of the corresponding pixel PXc can operate in response to one of a plurality of fourth transfer control signals TG14, TG24, TG34, and TG44.

[0140] The first transfer control signals TG11, TG21, TG31, and TG41, the second transfer control signals TG12, TG22, TG32, and TG42, the third transfer control signals TG13, TG23, TG33, and TG43, and the fourth transfer control signals TG14, TG24, TG34, and TG44 can be respectively from different row lines RL. Figure 2The row decoder 120 in the pixel array 110c provides separate signals. In a pixel PXc in a row, a first sub-pixel SPX1 can receive a corresponding first transfer control signal TG11, TG21, TG31, or TG41 through a row line RL; a second sub-pixel SPX2 can receive a corresponding second transfer control signal TG12, TG22, TG32, or TG42 through a row line RL; a third sub-pixel SPX3 can receive a corresponding third transfer control signal TG13, TG23, TG33, or TG43 through a row line RL; and a fourth sub-pixel SPX4 can receive a corresponding fourth transfer control signal TG14, TG24, TG34, or TG44 through a row line RL.

[0141] The pixel array 110d can be divided into a plurality of pixel groups PG. For example, each of the pixel groups PG can include a 2x4 matrix of pixels PXc.

[0142] Figure 14 is Figure 13A An equivalent circuit diagram of a pixel in the pixel array 110c.

[0143] Referring to Figure 14 The pixel PXc can include a first photodiode PD1, a second photodiode PD2, a third photodiode PD3, a fourth photodiode PD4, a first transfer transistor TX1, a second transfer transistor TX2, a third transfer transistor TX3, a fourth transfer transistor TX4, a reset transistor RX, a drive transistor DX, and a selection transistor SX.

[0144] A floating diffusion node FD (or a floating diffusion region) can be shared by the first photodiode PD1, the second photodiode PD2, the third photodiode PD3, the fourth photodiode PD4, the first transfer transistor TX1, the second transfer transistor TX2, the third transfer transistor TX3, and the fourth transfer transistor TX4.

[0145] Each of the first transfer transistor TX1, the second transfer transistor TX2, the third transfer transistor TX3, and the fourth transfer transistor TX4 can be independently turned on or turned off in response to a transfer control signal of the first transfer control signal TG1, the second transfer control signal TG2, the third transfer control signal TG3, and the fourth transfer control signal TG4 applied to a gate terminal thereof. When the first transfer transistor TX1, the second transfer transistor TX2, the third transfer transistor TX3, or the fourth transfer transistor TX4 is turned on, photocharges generated by a corresponding photodiode can be transferred to the floating diffusion node FD and stored in the floating diffusion node FD.

[0146] Reference has been made above Figure 5The control signals applied to each of the reset transistor, the driving transistor DX, and the selection transistor SX and their operations are described.

[0147] Figure 15 is a timing chart of the transfer control signals applied to the pixel array according to an example embodiment. Figure 13A

[0148] Referring to Figure 13A , Figure 14 and Figure 15 , a pixel PXc (hereinafter, referred to as a first pixel) in a row (e.g., a first row ROW1) of the pixel array 110d can output a pixel signal VOUT during a first readout period 1H, and a pixel PXc (hereinafter, referred to as a second pixel) in another row (e.g., a second row ROW2) of the pixel array 110d can output a pixel signal VOUT during a second readout period 2H.

[0149] During respective first sub-periods SP1 of the first readout period 1H and the second readout period 2H, the first pixel and the second pixel can each output a reset signal.

[0150] During a second sub-period SP2 of the first readout period 1H, the first transfer control signal TG11 and the third transfer control signal TG13 can be switched. As the first transfer transistor TX1 and the third transfer transistor TX3 of the first pixel are turned on in response to the first transfer control signal TG11 and the third transfer control signal TG13, respectively, charges (or photocharges) generated by the first photodiode PD1 and the third photodiode PD3 can be transferred to and stored in the floating diffusion node FD. The first pixel can output a first image signal, e.g., a left image signal, corresponding to the charges stored in the floating diffusion node FD. Thus, the first pixel can output the first image signal generated by the first photodiode PD1 and the third photodiode PD3 (or the first sub-pixel SPX1 and the third sub-pixel SPX3).

[0151] ​During the third sub-period SP3 of the first readout period 1H, the first to fourth transfer control signals TG11, TG12, TG13, and TG14 can be switched. The first to fourth transfer transistors TX1 to TX4 of the first pixel can be turned on in response to the first to fourth transfer control signals TG11 to TG14, respectively, and the charges generated by the first to fourth photodiodes PD1 to PD4 can be transferred to and stored in the floating diffusion node FD. The first pixel can output a sum image signal corresponding to the charges stored in the floating diffusion node FD, for example, a first sum image signal of the first pixel. Thus, the first sum image signal can be output from the first pixel and counted.

[0152] During the second sub-period SP2 of the second readout period 2H, as the second and fourth transfer transistors TX2 and TX4 of the second pixel are turned on in response to the second and fourth transfer control signals TG22 and TG24, respectively, the charges generated by the second and fourth photodiodes PD2 and PD4 can be transferred to and stored in the floating diffusion node FD. The second pixel can output a second image signal corresponding to the charges stored in the floating diffusion node FD, for example, a right image signal. Thus, the second pixel can output the second image signal generated by the second and fourth photodiodes PD2 and PD4 (or the second and fourth sub-pixels SPX2 and SPX4).

[0153] During the third sub-period SP3 of the second readout period 2H, the first to fourth transfer control signals TG21, TG22, TG23, and TG24 can be switched. The first to fourth transfer transistors TX1 to TX4 of the second pixel can be turned on in response to the first to fourth transfer control signals TG21 to TG24, respectively, and the charges generated by the first to fourth photodiodes PD1 to PD4 can be transferred to and stored in the floating diffusion node FD. The second pixel can output a sum image signal corresponding to the charges stored in the floating diffusion node FD, for example, a second sum image signal of the second pixel. Thus, the second sum image signal can be output from the second pixel and counted.

[0154] As described above, during the second sub-period SP2 of the first readout period 1H, the pixel PXc (e.g., the first pixel) in the first row ROW1 can output a first image signal, e.g., a left image signal, in response to the first transfer control signal TG11 and the third transfer control signal TG13; and during the second sub-period SP2 of the second readout period 2H, the pixel PXc (e.g., the second pixel) in the second row ROW2 can output a second image signal (e.g., a right image signal) in response to the second transfer control signal TG22 and the fourth transfer control signal TG24.

[0155] In an example embodiment, the first transfer control signals TG11 and TG21 can be identical to the fourth transfer control signals TG14 and TG24, respectively, and the second transfer control signals TG12 and TG22 can be identical to the third transfer control signals TG13 and TG23, respectively. Thus, during the second sub-period SP2 of the first readout period 1H, the pixel PXc (e.g., the first pixel) in the first row ROW1 can output a third image signal (e.g., a top image signal) generated by the first photodiode PD1 and the fourth photodiode PD4 in response to the first transfer control signal TG11 and the fourth transfer control signal TG14; and during the second sub-period SP2 of the second readout period 2H, the pixel PXc (e.g., the second pixel) in the second row ROW2 can output a fourth image signal (e.g., a bottom image signal) generated by the second photodiode PD2 and the third photodiode PD3 in response to the second transfer control signal TG22 and the third transfer control signal TG23.

[0156] Figure 16 is a flowchart of an operation method of an image sensor according to an example embodiment. The operation method of the image sensor 100 can be performed by Figure 2 the image sensor 100. Figure 16 the operation method of the image sensor 100.

[0157] Referring to Figure 16 In operations S110, S120, and S130, each first pixel in a first row of the pixel array 110 can sequentially output a reset signal, a first image signal, and a sum image signal according to the RSS readout method. Then, in operations S140, S150, and S160, each second pixel in a second row of the pixel array 110 can sequentially output a reset signal, a second image signal, and a sum image signal according to the RSS readout method. The first pixels and the second pixels can be arranged in the same column and have the same color.

[0158] In operation S110, the first pixel in the first row can output a first reset signal. The first pixel can output the first reset signal in response to a transfer control signal from the row decoder 120.

[0159] The first pixel in the first row can output a first image signal from the first photoelectric conversion element in operation S120, and then output a first sum image signal from the first photoelectric conversion element and the second photoelectric conversion element in operation S130.

[0160] Then, the second pixel in the second row can output a second reset signal in operation S140, output a second image signal from the second photoelectric conversion element in operation S150, and then output a second sum image signal from the first photoelectric conversion element and the second photoelectric conversion element in operation S160.

[0161] When operations S110 to S160 are performed, the signals (e.g., the first reset signal, the first image signal, the first sum image signal, the second reset signal, the second image signal, and the second sum image signal) output from the first pixel and the second pixel can be converted into digital values, e.g., count values, by the comparator circuit 140 and the counter circuit 160. The first image signal value, the second image signal value, the first sum image signal value, and the second sum image signal value (each of which removes a reset level) can be generated based on the first reset signal value and the second reset signal value.

[0162] The signal processor 190 can generate autofocus data based on the first image signal and the second image signal in operation S170. The signal processor 190 can generate a pair of phase detection signals based on the first image signal value and the second image signal value from which the reset level has been removed. A plurality of pairs of phase detection signals can be generated based on a plurality of first image signals and a plurality of second image signals output from the pixel array 110.

[0163] Figure 17 and Figure 18 are block diagrams of electronic devices including a multi-camera module according to example embodiments. Figure 19 isa detailed block diagram of the camera module in Figure 17

[0164] Referring to Figure 17 , the electronic device 2000 can include a camera module group 2100, an application processor 2200, a power management integrated circuit (PMIC) 2300, and an external memory 2400.

[0165] The camera module group 2100 can include a plurality of camera modules 2100a, 2100b, and 2100c. Although Figure 17 three camera modules 2100a, 2100b, and 2100c are shown, embodiments are not limited thereto. In some embodiments, the camera module group 2100 can be modified to include only two camera modules, or to include "n" camera modules, where "n" is a natural number of 4 or more.

[0166] Reference will be made toFigure 19 A detailed configuration of the camera module 2100b is described. The following description can also be applied to the other camera modules 2100a and 2100c.

[0167] Referring to Figure 19 The camera module 2100b can include a prism 2105, an optical path folding element (OPFE) 2110, an actuator 2130, an image sensing device 2140, and a reservoir 2150.

[0168] The prism 2105 can include a reflective surface 2107 of a light-reflecting material, and can change a path of light L incident from the outside.

[0169] In some embodiments, the prism 2105 can change a path of light L incident in a first direction X to a second direction Y perpendicular to the first direction X. The prism 2105 can rotate the reflective surface 2107 of the light-reflecting material in a direction A about a central axis 2106, or can rotate the central axis 2106 in a direction B, so that the path of the light L incident in the first direction X is changed to the second direction Y perpendicular to the first direction X. At this time, the OPFE 2110 can move in a third direction Z perpendicular to the first direction X and the second direction Y.

[0170] In some embodiments, a maximum rotation angle of the prism 2105 in the A direction can be less than or equal to 15 degrees in the positive (+) A direction, and can be greater than 15 degrees in the negative (-) A direction, but embodiments are not limited thereto.

[0171] In some embodiments, the prism 2105 can move about 20 degrees between the (+) B direction or the (-) B direction, or can move in the range of about 10 degrees to about 20 degrees in the (+) B direction or the (-) B direction, or can move from about 15 degrees to about 20 degrees in the (+) B direction or the (-) B direction. The angle at which the prism 2105 moves in the (+) B direction can be the same as or similar to the angle at which the prism 2105 moves in the (-) B direction within a deviation of about 1 degree.

[0172] In some embodiments, the prism 2105 can move the reflective surface 2107 of the light-reflecting material in a third direction Z parallel to an extension direction parallel to the central axis 2106.

[0173] In some embodiments, the camera module 2100b can include at least two prisms, and can differently change a path of light L incident in a first direction X to, for example, a second direction Y perpendicular to the first direction X, then to the first direction X or a third direction Z, and then to the second direction Y, and so on.

[0174] The OPFE 2110 can include, for example, “m” optical lenses, where “m” is a natural number. The “m” lenses can be moved in the second direction Y and can change the optical zoom ratio of the camera module 2100b. For example, when the default optical zoom ratio of the camera module 2100b is Z, the optical zoom ratio of the camera module 2100b can be changed to 3Z, 5Z, or more by moving the “m” optical lenses included in the OPFE 2110.

[0175] The actuator 2130 can move the OPFE 2110 or the optical lens to a specific position. For example, the actuator 2130 can adjust the position of the optical lens so that the image sensor 2142 is located at the focal distance of the optical lens for accurate sensing.

[0176] The image sensing device 2140 can include an image sensor 2142, control logic 2144, and a memory 2146. The image sensor 2142 can sense an image of an object using light L provided through the optical lens. Referring to Figure 2 to Figure 16 The described image sensor 100 can be used as the image sensor 2142. Each of the plurality of pixels PX of the pixel array 110 can include at least one first photoelectric conversion element and at least one second photoelectric conversion element under the microlenses in parallel with each other. A first image signal (e.g., a left image signal (or a top image signal)) can be output from the first photoelectric conversion element of each of the pixels PX in a specific row among the pixels PX. A second image signal (e.g., a right image signal (or a bottom image signal)) can be output from the second photoelectric conversion element of each of the pixels PX in another specific row among the pixels PX. Auto focus data (e.g., a phase detection signal pair) for an AF function can be generated based on the first and second image signals respectively output from two pixels PX respectively located in two adjacent rows and one column.

[0177] The control logic 2144 can generally control the operation of the camera module 2100b and can process the sensed image. For example, the control logic 2144 can control the operation of the camera module 2100b according to a control signal provided through a control signal line CSLb. For example, the control logic 2144 can control the actuator 2130 so that the optical lens is located at the focal distance according to AF based on a focus signal received from the application processor 2200. The control logic 2144 can extract image data corresponding to a specific image (e.g., a face of a person, an arm, a leg, etc.) from the sensed image.

[0178] In some embodiments, the control logic 2144 can perform image processing, such as encoding or noise reduction, on the sensed image.

[0179] The memory 2146 can store information such as correction data 2147 to be used in the operation of the camera module 2100b. The correction data 2147 can include information used when the camera module 2100b generates image data using light L provided from the outside. For example, the correction data 2147 can include information on a rotation angle, information on a focal length, information on an optical axis, etc. When the camera module 2100b is implemented as a multi-state camera having a focal length that changes as the position of the optical lens changes, the correction data 2147 can include values of the focal length for each position (or state) of the optical lens and information on auto focus. In some embodiments, two chips can be stacked, in which the image sensor 2142 can be formed in one of the two chips, and the control logic 2144, the buffer 2150, and the memory 2146 can be formed in the other of the two chips.

[0180] The buffer 2150 can store image data sensed by the image sensor 2142. The buffer 2150 can be disposed outside the image sensing device 2140, and can form a stack with the sensor chip of the image sensing device 2140. In some embodiments, the buffer 2150 can include an electrically erasable programmable read-only memory (EEPROM), but embodiments are not limited thereto. In some embodiments, the image sensor 2142 can include a pixel array, and the control logic 2144 can include an analog-to-digital converter and an image signal processor that processes a sensed image.

[0181] Referring to Figure 17 and Figure 19 In some embodiments, each of the camera modules 2100a, 2100b, and 2100c can include the actuator 2130. Accordingly, according to the operation of the actuator 2130 included in each of the camera modules 2100a, 2100b, and 2100c, the camera modules 2100a, 2100b, and 2100c can include the same or different correction data 2147 between the camera modules 2100a, 2100b, and 2100c.

[0182] In some embodiments, one of the camera modules 2100a, 2100b, and 2100c (for example, the camera module 2100b) can be a folded lens type including the prism 2105 and the OPFE 2110, and the other camera modules (for example, the camera modules 2100a and 2100c) can be vertical types not including the prism 2105 and the OPFE 2110. However, embodiments are not limited thereto.

[0183] In some embodiments, one of the camera modules 2100a, 2100b, and 2100c (e.g., the camera module 2100c) can include a vertical depth camera that extracts depth information using infrared (IR). In this case, the application processor 2200 can generate a three-dimensional (3D) depth image by merging image data provided by the depth camera with image data provided by another camera module (e.g., the camera module 2100a or 2100b).

[0184] In some embodiments, at least two of the camera modules 2100a, 2100b, and 2100c (e.g., 2100a and 2100b) can have different fields of view. In this case, two of the camera modules 2100a, 2100b, and 2100c (e.g., 2100a and 2100b) can respectively have different optical lenses, although embodiments are not limited thereto.

[0185] In some embodiments, the camera modules 2100a, 2100b, and 2100c can have different fields of view from each other. For example, the camera module 2100a can include an ultra-wide camera, the camera module 2100b can include a wide camera, and the camera module 2100c can include a tele camera, although embodiments are not limited thereto. In this case, the camera modules 2100a, 2100b, and 2100c can respectively have different optical lenses, although embodiments are not limited thereto.

[0186] In some embodiments, the camera modules 2100a, 2100b, and 2100c can be physically separated from each other. In other words, the sensing area of the image sensor 2142 is not divided for use by the camera modules 2100a, 2100b, and 2100c, although the image sensor 2142 can be independently included in each of the camera modules 2100a, 2100b, and 2100c.

[0187] Referring back to Figure 17 , the application processor 2200 can include an image processing unit 2210, a memory controller 2220, and an internal memory 2230. The application processor 2200 can be implemented separately from the camera modules 2100a, 2100b, and 2100c. For example, the application processor 2200 and the camera modules 2100a, 2100b, and 2100c can be implemented in different semiconductor chips.

[0188] The image processing unit 2210 can include a plurality of sub-image processors 2212a, 2212b, and 2212c, an image generator 2214, and a camera module controller 2216.

[0189] The image processing unit 2210 can include a number of sub-image processors 2212a, 2212b, and 2212c as the camera modules 2100a, 2100b, and 2100c.

[0190] Image data generated by the camera module 2100a can be provided to the sub-image processor 2212a through an image signal line ISLa, image data generated by the camera module 2100b can be provided to the sub-image processor 2212b through an image signal line ISLb, and image data generated by the camera module 2100c can be provided to the sub-image processor 2212c through an image signal line ISLc. The image data transmission can be performed using, for example, a camera serial interface (CSI) based on a mobile industry processor interface (MIPI), but embodiments are not limited thereto.

[0191] In some embodiments, a single sub-image processor can be provided for a plurality of camera modules. For example, unlike the sub-image processors 2212a and 2212c, the sub-image processor 2212b can not be separated but can be integrated into a single sub-image processor, and image data provided from the camera module 2100b can be selected by a selection element (e.g., a multiplexer) and then provided to the integrated sub-image processor. At this time, the sub-image processors 2212a and 2212c can not be integrated but can receive image data from the camera module 2100a or the camera module 2100c. Figure 17 Differently, the sub-image processors 2212a and 2212c can not be separated but can be integrated into a single sub-image processor, and image data provided from the camera module 2100a or the camera module 2100c can be selected by a selection element (e.g., a multiplexer) and then provided to the integrated sub-image processor. At this time, the sub-image processor 2212b can not be integrated but can receive image data from the camera module 2100b.

[0192] In some embodiments, image data generated by the camera module 2100a can be provided to the sub-image processor 2212a through an image signal line ISLa, image data generated by the camera module 2100b can be provided to the sub-image processor 2212b through an image signal line ISLb, and image data generated by the camera module 2100c can be provided to the sub-image processor 2212c through an image signal line ISLc. In addition, while image data processed by the sub-image processor 2212b can be directly provided to the image generator 2214, one of image data processed by the sub-image processor 2212a and image data processed by the sub-image processor 2212c can be selected by a selection element (e.g., a multiplexer) and then provided to the image generator 2214.

[0193] Each of the sub-image processors 2212a, 2212b, and 2212c can perform image processing, such as bad pixel correction, 3A adjustment (i.e., auto focus correction, auto white balance, and auto exposure), noise reduction, sharpening, gamma control, or remosaic, on image data provided from a corresponding one of the camera modules 2100a, 2100b, and 2100c.

[0194] In some embodiments, re-stitching signal processing can be performed by each of the camera modules 2100a, 2100b, and 2100c, and the processing results can be provided to each of the sub-image processors 2212a, 2212b, and 2212c.

[0195] Image data processed by each of the sub-image processors 2212a, 2212b, and 2212c can be provided to an image generator 2214. The image generator 2214 can generate an output image using the image data provided from each of the sub-image processors 2212a, 2212b, and 2212c according to image generation information or a mode signal.

[0196] In detail, the image generator 2214 can generate an output image by merging at least some portions of corresponding pieces of image data respectively generated from the camera modules 2100a, 2100b, and 2100c having different fields of view according to the image generation information or the mode signal. Alternatively, the image generator 2214 can generate an output image by selecting one of the pieces of image data respectively generated from the camera modules 2100a, 2100b, and 2100c having different fields of view according to the image generation information or the mode signal.

[0197] In some embodiments, the image generation information can include a zoom signal or a zoom factor. In some embodiments, the mode signal can be based on a mode selected by a user.

[0198] When the image generation information includes a zoom signal or a zoom factor and the camera modules 2100a, 2100b, and 2100c have different fields of view, the image generator 2214 can perform different operations according to different types of zoom signals. For example, when the zoom signal is a first signal, the image generator 2214 can generate an output image using image data output from the sub-image processor 2212a between image data output from the sub-image processor 2212a and image data output from the sub-image processor 2212c and using image data output from the sub-image processor 2212b. When the zoom signal is a second signal different from the first signal, the image generator 2214 can generate an output image using image data output from the sub-image processor 2212c between image data output from the sub-image processor 2212a and image data output from the sub-image processor 2212c and image data output from the sub-image processor 2212b. When the zoom signal is a third signal different from the first and second signals, the image generator 2214 can generate an output image by selecting one of the pieces of image data output from the sub-image processors 2212a, 2212b, and 2212c, respectively, instead of performing a merge of the pieces of image data output from the sub-image processors 2212a, 2212b, and 2212c, respectively. However, embodiments are not limited thereto, and the method of processing image data can be variously changed.

[0199] Referring to Figure 18 In some embodiments, the image processing unit 2210 can further include a selector 2213 that selects outputs of the sub-image processors 2212a, 2212b, and 2212c and transmits the same to the image generator 2214.

[0200] In this case, the selector 2213 can perform different operations according to a zoom signal or a zoom factor. For example, when the zoom signal is a fourth signal (e.g., when a zoom ratio is a first ratio), the selector 2213 can select and transmit one of the outputs of the sub-image processors 2212a, 2212b, and 2212c.

[0201] When the scaling signal is a fifth signal different from the fourth signal (for example, when the scaling ratio is the second ratio), the selector 2213 can sequentially transmit "p" (where "p" is a natural number of 2 or more) of the outputs among the outputs of the sub-image processors 2212a, 2212b, and 2212c. For example, the selector 2213 can sequentially transmit the output of the sub-image processor 2212b and the output of the sub-image processor 2212c to the image generator 2214. For example, the selector 2213 can sequentially transmit the output of the sub-image processor 2212a and the output of the sub-image processor 2212b to the image generator 2214. The image generator 2214 can merge the "p" outputs sequentially received with each other, and generate a single output image.

[0202] Here, image processing such as demosaicing, downscaling to a video / preview resolution, gamma correction, and high dynamic range (HDR) processing can be performed by the sub-image processors 2212a, 2212b, and 2212c, and the processed image data can be transmitted to the image generator 2214. Accordingly, although the processed image is provided from the selector 2213 to the image generator 2214 through a single signal line, the image merging operation of the image generator 2214 can be performed at a high speed.

[0203] In some embodiments, the image generator 2214 can receive a plurality of pieces of image data having different exposure times from at least one of the sub-image processors 2212a, 2212b, and 2212c, and perform HDR processing on the plurality of pieces of image data, thereby generating merged image data having an increased dynamic range.

[0204] The camera module controller 2216 can provide a control signal to each of the camera modules 2100a, 2100b, and 2100c. The control signal generated by the camera module controller 2216 can be provided to a corresponding one of the camera modules 2100a, 2100b, and 2100c through a corresponding one of the control signal lines CSLa, CSLb, and CSLc, which are separate from each other.

[0205] One of the camera modules 2100a, 2100b, and 2100c (for example, the camera module 2100b) can be designated as a master camera and the other camera modules (for example, 2100a and 2100c) can be designated as slave cameras according to the mode signal or the image generation signal including the scaling signal. Such designation information can be included in the control signal and provided to each of the camera modules 2100a, 2100b, and 2100c through a corresponding one of the control signal lines CSLa, CSLb, and CSLc, which are separate from each other.

[0206] The camera module operating as a master camera or a slave camera can be changed according to a zoom factor or an operation mode signal. For example, when a field of view of the camera module 2100a is greater than that of the camera module 2100b and the zoom factor indicates a low zoom ratio, the camera module 2100a can operate as a master camera and the camera module 2100b can operate as a slave camera. On the other hand, when the zoom factor indicates a high zoom ratio, the camera module 2100b can operate as a master camera and the camera module 2100a can operate as a slave camera.

[0207] In some embodiments, the control signal provided from the camera module controller 2216 to each of the camera modules 2100a, 2100b, and 2100c can include a synchronization enable signal. For example, when the camera module 2100b is a master camera and the camera module 2100a is a slave camera, the camera module controller 2216 can transmit a synchronization enable signal to the camera module 2100b. The camera module 2100b provided with the synchronization enable signal can generate a synchronization signal based on the synchronization enable signal, and can provide the synchronization signal to the camera modules 2100a and 2100c through a synchronization signal line SSL. The camera modules 2100a, 2100b, and 2100c can synchronize with the synchronization signal, and can transmit image data to the application processor 2200.

[0208] In some embodiments, the control signal provided from the camera module controller 2216 to each of the camera modules 2100a, 2100b, and 2100c can include mode information according to a mode signal. The camera modules 2100a, 2100b, and 2100c can operate in a first operation mode or a second operation mode related to a sensing speed based on the mode information.

[0209] In the first operation mode, the camera modules 2100a, 2100b, and 2100c can generate an image signal at a first speed (e.g., a first frame rate), encode the image signal at a second speed (e.g., at a second frame rate higher than the first frame rate) higher than the first speed, and transmit the encoded image signal to the application processor 2200. For example, the second speed can be about 30 times or less of the first speed.

[0210] The application processor 2200 can store the received image signal, i.e., the encoded image signal, in an internal memory 2230 inside the application processor 2200 or in an external memory 2400 outside the application processor 2200. Then, the application processor 2200 can read the encoded image signal from the internal memory 2230 or the external memory 2400, decode the encoded image signal, and display image data generated based on the decoded image signal. For example, a corresponding one of sub image processors 2212a, 2212b, and 2212c of the image processing unit 2210 can perform decoding, and can also perform image processing on the decoded image signal.

[0211] In the second operation mode, the camera modules 2100a, 2100b, and 2100c can generate image signals at a third speed (e.g., at a third frame rate) lower than the first speed and transmit the image signals to the application processor 2200. The image signals provided to the application processor 2200 can not be encoded. The application processor 2200 can perform image processing on the image signals or store the image signals in the internal memory 2230 or the external memory 2400.

[0212] The PMIC 2300 can provide power (e.g., a power voltage) to each of the camera modules 2100a, 2100b, and 2100c. For example, under the control of the application processor 2200, the PMIC 2300 can provide first power to the camera module 2100a through a power signal line PSLa, second power to the camera module 2100b through a power signal line PSLb, and third power to the camera module 2100c through a power signal line PSLc.

[0213] The PMIC 2300 can generate power corresponding to each of the camera modules 2100a, 2100b, and 2100c in response to a power control signal PCON from the application processor 2200 and adjust the level of the power. The power control signal PCON can include a power adjustment signal for each operation mode of the camera modules 2100a, 2100b, and 2100c. For example, the operation mode can include a low power mode. The power control signal PCON can include information about the camera modules operating in the low power mode and the power level to be set. The same or different levels of power can be provided to the camera modules 2100a, 2100b, and 2100c, respectively. The level of the power can be dynamically changed.

[0214] While the disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An image sensor, comprising: A pixel array comprising a plurality of pixels arranged in a matrix, each of the plurality of pixels comprising a microlens, a first photoelectric conversion element and a second photoelectric conversion element, the first photoelectric conversion element and the second photoelectric conversion element being arranged parallel to each other in a first direction below the microlens; The line decoder is configured as follows: During the first readout period, a first image signal and a first summed image signal are sequentially output from the first pixel in the first row of the pixel array. The first image signal is generated by the first photoelectric conversion element of the first pixel, and the first summed image signal is generated by the first photoelectric conversion element and the second photoelectric conversion element of the first pixel. During the second readout period, the second image signal and the second summed image signal are controlled to be sequentially output from the second pixel in the second row of the pixel array. The second image signal is generated by the second photoelectric conversion element of the second pixel, and the second summed image signal is generated by the first photoelectric conversion element and the second photoelectric conversion element of the second pixel. as well as A signal processor configured to generate a pair of phase detection signals for autofocus based on the first image signal and the second image signal.

2. The image sensor according to claim 1, wherein, The line decoder is also configured to: Multiple first control signals are provided to the first pixel, which control a first reset signal, a first image signal, and a first summed image signal to be sequentially output from the first pixel during the first readout period. The first reset signal represents the reset level of the first pixel. A plurality of second control signals are provided to the second pixel, wherein the plurality of second control signals control a second reset signal, a second image signal and a second summed image signal to be sequentially output from the second pixel during the second readout period, and the second reset signal represents the reset level of the second pixel.

3. The image sensor according to claim 1, wherein, Each of the plurality of pixels also includes: Floating diffusion nodes; A first transfer transistor is configured to be turned on to transfer photocharge generated by the first photoelectric conversion element to the floating diffusion node; The second transfer transistor is configured to be turned on to transfer the photocharge generated by the second photoelectric conversion element to the floating diffusion node; A reset transistor, configured to be turned on, to reset the floating diffusion node to the supply voltage; and A driving transistor is configured to output a pixel signal corresponding to the potential of the floating diffusion node. During the first readout period, the second transfer transistor of the first pixel is turned on at a later time than when the first transfer transistor of the first pixel is first turned on, and During the second readout period, the first transfer transistor of the second pixel is turned on at a later time than when the second transfer transistor of the second pixel is first turned on.

4. The image sensor according to claim 3, wherein, The line decoder is also configured to: During the first readout period, a first transfer control signal and a second transfer control signal are respectively provided to the first transfer transistor and the second transfer transistor of the first pixel, and During the second readout period, a third transfer control signal and a fourth transfer control signal are respectively provided to the first transfer transistor and the second transfer transistor of the second pixel, and Wherein, the first transfer control signal is the same as the fourth transfer control signal, and the second transfer control signal is the same as the third transfer control signal.

5. The image sensor according to claim 4, wherein, The line decoder includes a pre-decoder, which is configured to: During the first readout period, the first reference control signal is selected from the first reference control signal and the second reference control signal as the first transfer control signal, and the second reference control signal is selected as the second transfer control signal. During the second readout period, the second reference control signal is selected as the third transfer control signal, and the first reference control signal is selected as the fourth transfer control signal.

6. The image sensor of claim 1 further includes a readout circuit configured to convert the first image signal and the second image signal into digital signals based on N counting clock pulses, and to convert the first summed image signal and the second summed image signal into digital signals based on 2N counting clock pulses, where N is a positive integer of 2 or greater.

7. The image sensor according to claim 1, wherein, The first pixel and the second pixel are respectively configured to convert optical signals of the same wavelength into electrical signals.

8. The image sensor according to claim 1, wherein, The first pixel and the second pixel are located in the same column of the pixel array.

9. The image sensor according to claim 1, wherein, Each of the plurality of pixels further includes a third photoelectric conversion element and a fourth photoelectric conversion element arranged parallel to the first photoelectric conversion element and the second photoelectric conversion element respectively in a second direction perpendicular to the first direction, and The line decoder is also configured as follows: During the first readout period, a third image signal and a third summed image signal are sequentially output from the first pixel. The third image signal is generated by the first and third photoelectric conversion elements of the first pixel, and the third summed image signal is generated by the first, second, third, and fourth photoelectric conversion elements of the first pixel. During the second readout period, a fourth image signal and a fourth summed image signal are controlled to be output sequentially from the second pixel. The fourth image signal is generated by the second photoelectric conversion element and the fourth photoelectric conversion element of the second pixel, and the fourth summed image signal is generated by the first photoelectric conversion element, the second photoelectric conversion element, the third photoelectric conversion element, and the fourth photoelectric conversion element of the second pixel.

10. An image sensor, comprising: A pixel array comprising multiple row lines extending in a first direction, multiple column lines extending in a second direction perpendicular to the first direction, and multiple pixels connected to the multiple row lines and the multiple column lines and arranged in a matrix, each of the multiple pixels comprising a first sub-pixel and a second sub-pixel arranged parallel to each other in a third direction. as well as A row decoder is configured to provide a plurality of first control signals to a first pixel in a first row of the pixel array, and a plurality of second control signals to a second pixel in a second row of the pixel array. The pixel array is configured as follows: During the first readout period, in response to the plurality of first control signals, a first image signal is output from a first sub-pixel of the first pixel and a first summed image signal is output from a first sub-pixel of the first pixel via a first column line; and During the second readout period, in response to the plurality of second control signals, a second image signal is output from the second sub-pixel of the second pixel and a second summed image signal is output from the first sub-pixel and the second sub-pixel of the second pixel via the first column line. The image sensor further includes a signal processor configured to generate a pair of phase detection signals based on the first image signal and the second image signal, and to perform phase difference calculations for autofocus based on the pair of phase detection signals.

11. The image sensor according to claim 10, wherein, Each of the first sub-pixel and the second sub-pixel includes a photoelectric conversion element, and The first sub-pixel and the second sub-pixel share a microlens.

12. The image sensor according to claim 10, wherein, The third direction is the same as the first direction.

13. The image sensor according to claim 10, wherein, The third direction is the same as the second direction.

14. A method of operating an image sensor comprising a pixel array, the method comprising: A first image signal is output from a first photoelectric conversion element of a first pixel in the first row of the pixel array, wherein the first pixel includes a first photoelectric conversion element and a second photoelectric conversion element arranged parallel to each other in a first direction; A first summed image signal is output from the first photoelectric conversion element and the second photoelectric conversion element of the first pixel; A second image signal is output from a second photoelectric conversion element of a second pixel in the second row of the pixel array, wherein the second pixel includes a first photoelectric conversion element and a second photoelectric conversion element arranged parallel to each other in the first direction; A second summed image signal is output from the first photoelectric conversion element and the second photoelectric conversion element of the second pixel; as well as Autofocus data is generated based on the first image signal and the second image signal.

15. The method of claim 14, further comprising: A first reset signal is output from the first pixel, wherein the first reset signal represents the reset level of the first pixel; as well as A second reset signal is output from the second pixel, the second reset signal representing the reset level of the second pixel.

16. The method of claim 14, wherein, The first pixel and the second pixel are respectively configured to convert optical signals in the same wavelength band into electrical signals.

17. The method of claim 14, wherein, The first pixel and the second pixel are located in the same column of the pixel array of the image sensor.

18. The method according to claim 14, wherein, The steps for generating the autofocus data include: A pair of phase detection signals will be generated based on the first image signal and the second image signal, which will be used for phase difference calculation.

Images